Preparation method for GAN HEMT device, and GAN HEMT device

Abstract

A preparation method for a GaN HEMT device, and a GaN HEMT device. The preparation method comprises the following steps: forming a substrate (10) of an SIC material of a second doping type; forming a separate SIC epitaxial wafer (12-0) of a first doping type grown along a C axis; forming an electric field stop layer (11) of the first doping type on the front surface of the SIC epitaxial wafer, wherein the doping concentration of the electric field stop layer is greater than the doping concentration of the substrate; forming a lift-off layer (13) at the position in the SIC epitaxial wafer located below the electric field stop layer, wherein the portion of the SIC epitaxial wafer located between the electric field stop layer and the lift-off layer serves as an electric field pressure-bearing layer (12); bonding the front surface of the electric field stop layer and the front surface of the substrate together; and performing lift-off at the lift-off layer, the electric field stop layer being located on the substrate, and the electric field pressure-bearing layer being located on the electric field stop layer.

Description

A method for fabricating a GaN HEMT device and the GaN HEMT device Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for fabricating a GaN HEMT device and the GaN HEMT device itself. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are an emerging type of semiconductor device that has found widespread application in various fields due to their superior performance. Compared to traditional silicon-based devices, GaN HEMTs offer higher switching speeds and higher breakdown voltages, enabling them to perform exceptionally well in high-frequency, high-power, and high-temperature environments.

[0003] In recent years, GaN HEMT device technology has developed rapidly. Many semiconductor companies and research institutions have increased their investment in GaN material research and production. Compared with earlier technologies, today's GaN HEMT devices have made significant progress in cost, stability, and manufacturing processes. With the maturity of manufacturing processes, GaN HEMT devices are finding increasingly wider market applications, and their prices are gradually decreasing, driving their widespread adoption in various fields.

[0004] GaN on SiC HEMT devices: Specifically refers to GaN HEMT devices fabricated on silicon carbide (SiC) substrates. GaN on SiC HEMT devices typically use a high-resistivity SiC substrate, on which the epitaxial structure of the GaN HEMT device is placed.

[0005] Figure 1 is a schematic diagram of a GaN on SiC HEMT device in the prior art. Figure 1 is from the literature "A Review of GaN on SiC High Electron-Mobility Power Transistors and MMICs". As shown in Figure 1, the substrate via (i.e., substrate via 1-1) extends from the back side of the device to the front side to achieve grounding.

[0006] While GaN on SiC HEMTs are under development, they also face the problem of high cost of silicon carbide substrates. Epitaxial gallium nitride (GaN) materials grown on silicon carbide substrates have lower defect density and higher crystal quality than those grown on silicon or sapphire substrates. Therefore, high-performance GaN HEMT devices often use SiC materials as substrates. Current industry technology for manufacturing GaN HEMT devices typically uses high-resistivity SiC substrates grown along the C-axis. GaN epitaxial layers grown on C-axis high-resistivity SiC substrates have lower defect and dislocation rates, resulting in better material quality.

[0007] Conventionally, substrates used in large-scale power devices are relatively inexpensive, low-resistivity single-crystal SiC substrates grown at a 4-degree angle off the C-axis, D-grade wafers (test wafers), or polycrystalline SiC substrates. However, the price of high-resistivity SiC substrates grown along the C-axis is significantly higher than that of low-resistivity substrates grown at a 4-degree angle off the C-axis. This results in substrate cost accounting for a major portion of the overall cost of GaN HEMT devices. Furthermore, because GaN HEMT devices often undergo back-side thinning and back-gold bonding, the hundreds of micrometers-thick SiC high-resistivity substrates grown along the C-axis are often thinned to tens to a few micrometers. The excess SiC substrate is removed using CMP technology and is not utilized, resulting in a waste of expensive substrate material.

[0008] Therefore, the high cost of traditional GaN HEMT devices limits their application scenarios, which is a technical problem that urgently needs to be solved by those skilled in the art.

[0009] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0010] This application provides a method for fabricating a GaN HEMT device and a GaN HEMT device, in order to solve the technical problem that the high cost of traditional GaN HEMT devices limits their application scenarios.

[0011] This application provides a method for fabricating a GaN HEMT device, comprising the following steps:

[0012] Substrate for forming SiC material of the second doping type;

[0013] Forming a single, first-doped SiC epitaxial wafer grown along the C-axis;

[0014] An electric field termination layer of a first doping type is formed on the front side of the SiC epitaxial wafer; wherein the doping concentration of the electric field termination layer is greater than the doping concentration of the substrate;

[0015] A release layer is formed in the SiC epitaxial wafer at a position below the electric field termination layer; wherein, the portion of the SiC epitaxial wafer located between the electric field termination layer and the release layer serves as an electric field bearing layer;

[0016] The front side of the electric field termination layer and the front side of the substrate are bonded together;

[0017] Peeling is performed at the peeling layer; wherein, the electric field terminating layer is above the substrate, and the electric field bearing layer is above the electric field terminating layer;

[0018] The electric field bearing layer is above the epitaxial structure of the GaN HEMT device.

[0019] This application also provides a GaN HEMT device, comprising:

[0020] Substrates of SiC materials with the second doping type;

[0021] An electric field termination layer of SiC of the first doped type grown along the C-axis is formed on the substrate;

[0022] An electric field bearing layer of SiC of the first doped type, grown along the C-axis, is formed on the electric field termination layer 11.

[0023] This application, by adopting the above technical solution, has the following technical effects:

[0024] The substrate in this application is relatively thick, and after the entire GaN HEMT device is completed, the back side of the substrate needs to be thinned. The lower-cost substrate used in this application serves both as a support base and as the target for thinning.

[0025] Compared to the thickness loss in existing thinning processes, the GaN HEMT device fabrication method of this application results in a very small loss of the release layer thickness. The electric field termination layer and electric field bearing layer in this application serve to bear pressure and terminate the electric field; therefore, the substrate, electric field termination layer, and electric field bearing layer as a whole can correspond to the high-resistivity SiC substrates in the prior art.

[0026] The growth of SiC epitaxial wafers along the C-axis is a costly and complex process. SiC epitaxial wafers grown in a single step along the C-axis can be reused multiple times, each time to fabricate one or a batch of GaN HEMT devices, thus reducing the fabrication cost of GaN HEMT devices and simplifying the fabrication method. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0028] Figure 1 is a schematic diagram of a GaN on SiC HEMT device in the prior art;

[0029] Figure 2-A is a flowchart of the fabrication method of the GaN HEMT device of this application;

[0030] Figure 2-B is a schematic diagram of step S1 in the fabrication method of the GaN HEMT device of this application;

[0031] Figure 2-C is a schematic diagram of step S3 in the fabrication method of the GaN HEMT device of this application;

[0032] Figure 2-D is a schematic diagram of step S4 in the fabrication method of the GaN HEMT device of this application;

[0033] Figure 2-E is a schematic diagram of step S5 in the fabrication method of the GaN HEMT device of this application;

[0034] Figure 2-F is a schematic diagram of step S6 in the fabrication method of the GaN HEMT device of this application;

[0035] Figure 2-G is a schematic diagram of step S6 in the fabrication method of the GaN HEMT device of this application;

[0036] Figure 3 is a schematic diagram of one implementation of the GaN HEMT device of this application;

[0037] Figure 4 is a schematic diagram of another implementation of the GaN HEMT device of this application;

[0038] Figure 5 is a schematic diagram of another implementation of the GaN HEMT device of this application;

[0039] Figure 6 is a schematic diagram of step S7 in the fabrication method of the GaN HEMT device of this application;

[0040] Figure 7 is a schematic diagram illustrating step S8 of the GaN HEMT device fabrication method of this application;

[0041] Figure 8 is a schematic diagram of step S9 in the fabrication method of the GaN HEMT device of this application;

[0042] Figure 9 is a schematic diagram of step S10 of the fabrication method of the GaN HEMT device of this application;

[0043] Figure 10 is a schematic diagram of step S11 of the fabrication method of the GaN HEMT device of this application;

[0044] Figure 11 is a schematic diagram of step S12 in the fabrication method of the GaN HEMT device of this application;

[0045] Figure 12 is a schematic diagram of step S13 of the fabrication method of the GaN HEMT device of this application;

[0046] Figure 13 is a schematic diagram of step S14 in the fabrication method of the GaN HEMT device of this application.

[0047] Figure label:

[0048] In the background art: Through-hole 1-1 in the substrate;

[0049] In this application: Substrate 10, SiC epitaxial wafer 12-0, electric field termination layer 11, electric field bearing layer 12, release layer 13; SiC connection region 20, first connection region 21, AlN layer 22, AlN layer base 220, GaN buffer layer 23, GaN buffer layer base 230, GaN layer 24, GaN layer base 240, AlGaN layer 25, AlGaN layer base 250, gate metal 26, SiN layer 27, SiN layer base 270, drain 28-1, source 28-2, metal silicide layer 29, source metal 31, backside ground metal 32, second connection region 33. Detailed Implementation

[0050] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0051] Example 1

[0052] As shown in Figure 2-A, a method for fabricating a GaN HEMT device according to this application includes the following steps:

[0053] As shown in Figure 2-B, step S1: forming a substrate 10 of SiC material of the second doping type;

[0054] Step S2: Form a separate first-doped SiC epitaxial wafer 12-0 grown along the C-axis;

[0055] As shown in Figure 2-C, step S3: forming a first doped electric field termination layer 11 on the front side of the SiC epitaxial wafer 12-0; wherein, the doping concentration of the electric field termination layer 11 is greater than the doping concentration of the substrate 10.

[0056] As shown in Figure 2-D, step S4: a release layer 13 is formed in the SiC epitaxial wafer 12-0 at a position below the electric field termination layer 11; wherein, the portion of the SiC epitaxial wafer 12-0 located between the electric field termination layer 11 and the release layer 13 serves as the electric field bearing layer 12.

[0057] As shown in Figure 2-E, step S5: bond the front side of the electric field termination layer 11 and the front side of the substrate 10 together;

[0058] As shown in Figure 2-F, step S6: peeling is performed at the peeling layer 13; wherein, as shown in Figure 2-G, the electric field termination layer 11 is above the substrate 10, and the electric field bearing layer 12 is above the electric field termination layer 11.

[0059] The electric field bearing layer 12 is above the epitaxial structure of the GaN HEMT device.

[0060] The method for fabricating the GaN HEMT device of this application includes the following steps:

[0061] Step S1: Form a substrate 10 of the second-doped SiC material. Specifically, this can be done by forming a separate substrate 10 of the second-doped SiC material grown at an angle of 4 degrees off the C-axis. The cost of the second-doped substrate 10 grown at an angle of 4 degrees off the C-axis is lower.

[0062] Step S2: Form a separate C-axis-grown first-doped SiC epitaxial wafer 12-0. Note that the C-axis-grown SiC epitaxial wafer 12-0 is not formed directly on the substrate 10 which is grown at an angle of 4 degrees away from the C-axis, because a SiC epitaxial wafer grown along the C-axis cannot be grown on the substrate 10 which is grown at an angle of 4 degrees away from the C-axis.

[0063] Step S3: Form a first doped electric field termination layer 11 on the front side of the SiC epitaxial wafer 12-0; wherein the doping concentration of the electric field termination layer 11 is greater than the doping concentration of the substrate 10.

[0064] Step S4: A release layer 13 is formed in the SiC epitaxial wafer 12-0 at a position below the electric field termination layer 11; wherein, the portion of the SiC epitaxial wafer 12-0 located between the electric field termination layer 11 and the release layer 13 serves as the electric field bearing layer 12.

[0065] Step S5: Turn the entire SiC epitaxial wafer 12-0 upside down and bond the front side of the electric field termination layer 11 to the front side of the substrate 10.

[0066] Step S6: Peeling is performed at the release layer 13; wherein, the electric field termination layer 11 is above the substrate 10, and the electric field bearing layer 12 is above the electric field termination layer 11. At this time, the portion of the SiC epitaxial wafer 12-0 located at and above the release layer 13 is peeled off, and the electric field termination layer 11 and the electric field bearing layer 12 are sequentially arranged from bottom to top on the substrate 10.

[0067] From this point on, the substrate 10, the electric field termination layer 11, and the electric field bearing layer 12 together form the basis of the epitaxial structure of the GaN HEMT device. That is, the substrate 10, the electric field termination layer 11, and the electric field bearing layer 12 together correspond to the high-resistivity SiC substrate in the prior art.

[0068] The substrate 10 grown at a 4-degree angle off the C-axis in this application has a relatively large thickness, and the back side of the substrate 10 needs to be thinned after the entire GaN HEMT device is completed. The substrate 10 grown at a 4-degree angle off the C-axis in this application, which has a lower cost, serves as both a support base and a target for thinning.

[0069] Due to its inherent characteristics, the SiC substrate 10, which is grown at a 4-degree angle off the C-axis, cannot be directly used as the basis for the epitaxial structure of a GaN HEMT device. Direct growth on the substrate 10 at this angle will only result in an epitaxial layer that is also off the C-axis, and this epitaxial layer cannot be directly used as the basis for the epitaxial structure of a GaN HEMT device.

[0070] Therefore, this application achieves the electric field termination layer 11 and electric field bearing layer 12 on the substrate 10 through SiC epitaxial wafers, electric field termination layer 11, electric field bearing layer 12, reverse bonding, front bonding, and peeling. While the electric field termination layer 11 and electric field bearing layer 12 are relatively expensive, their thickness in the GaN HEMT device of this application is small, and thinning of the electric field termination layer 11 and electric field bearing layer 12 is not required during the entire GaN HEMT device fabrication process, thus avoiding any loss of the expensive electric field termination layer 11 and electric field bearing layer 12. Only one peeling layer 13 is lost throughout the entire process. Compared to the thickness loss in existing thinning processes, the thickness of the peeling layer 13 lost in the GaN HEMT device fabrication method of this application is very small. In this application, the electric field termination layer 11 and the electric field bearing layer 12 serve to bear pressure and terminate the electric field. Therefore, the substrate 10, the electric field termination layer 11, and the electric field bearing layer 12 as a whole can correspond to the high-resistivity SiC substrate in the prior art.

[0071] Furthermore, the first-doped SiC epitaxial wafer 12-0 grown along the C-axis can be grown to a relatively large thickness in a single operation. The release layer 13, electric field termination layer 11, and electric field bearing layer 12 used in the fabrication of a single GaN HEMT device consume a certain thickness of the SiC epitaxial wafer 12-0, leaving the remaining portion that can still be used to fabricate other GaN HEMT devices. This allows for multiple uses of the first-doped SiC epitaxial wafer 12-0 grown along the C-axis from a single growth. The growth of the SiC epitaxial wafer 12-0 along the C-axis is a costly and complex process. The ability to reuse the SiC epitaxial wafer 12-0 grown along the C-axis in a single operation, fabricating one or a batch of GaN HEMT devices each time, reduces the fabrication cost and complexity of the GaN HEMT device fabrication method.

[0072] In practice, the step of forming a first-doped electric field termination layer 11 on the front side of the SiC epitaxial wafer 12-0 specifically includes:

[0073] An electric field termination layer 11 of the first doping type is formed on the front side of the SiC epitaxial wafer 12-0 by ion implantation;

[0074] Alternatively, an electric field termination layer 11 of the first doping type can be formed on the front side of the SiC epitaxial wafer 12-0 by epitaxial growth.

[0075] In practice, the step of forming a release layer 13 in the SiC epitaxial wafer 12-0 below the electric field termination layer 11 specifically includes:

[0076] In the SiC epitaxial wafer 12-0, a release layer 13 is formed below the electric field termination layer 11 by hydrogen ion implantation.

[0077] In practice, the step of bonding the front side of the electric field termination layer 11 and the front side of the substrate 10 together is specifically as follows:

[0078] The front side of the electric field termination layer 11 and the front side of the substrate 10 are connected together by low-temperature bonding.

[0079] The bonding method can be Smartcut bonding.

[0080] In practice, the step of bonding the front side of the electric field termination layer 11 and the front side of the substrate 10 together is specifically as follows:

[0081] The front side of the electric field termination layer 11 and the front side of the substrate 10 are connected together by low-temperature bonding;

[0082] The step of peeling the SiC epitaxial wafer 12-0 off at the position of the release layer 13 is as follows:

[0083] The peeling is performed at the peeling layer 13 by thermal reaction, and the surface of the newly peeled electric field bearing layer 12 is reinforced by high-temperature thermal annealing and smoothed by CMP (chemical mechanical polishing) process.

[0084] The GaN HEMT device fabrication method of this application uses ion implantation, bonding, stripping, high-temperature annealing to strengthen bonding, and CMP processes, all of which are common and mature processes that do not require additional process development costs. This makes the fabrication method of the GaN HEMT device of this application more convenient and less difficult to implement.

[0085] In practice, the substrate 10 is a substrate of single-crystal or polycrystalline SiC material;

[0086] Or a D-grade wafer (test wafer grade) on a SiC substrate.

[0087] In practice, the substrate 10 is a high-resistivity substrate or a low-resistivity substrate.

[0088] Specifically, the GaN HEMT device of this application also includes steps for fabricating other structures.

[0089] Specifically, the first doping type is P-type, and the second doping type is N-type.

[0090] In practice, the substrate 10 is a low-resistivity substrate;

[0091] The upper surface of the electric field bearing layer 12 is divided into a first electric field bearing layer region and a second electric field bearing layer region; the preparation method also includes the following steps:

[0092] A grounded back-side metal 32 is formed on the back side of the substrate 10;

[0093] A first connection region base of a first doped type is formed downward in the first region of the electric field bearing layer. A first through hole is formed downward from the upper surface of the first connection region base by etching. The first through hole is filled with SiC of a second doped type to form a SiC connection region 20 of the second doped type. The unetched portion of the first connection region base forms a first connection region 21.

[0094] The back-side ground metal 32, the substrate 10, and the SiC connection region 20 are connected to a position on the upper surface of the SiC connection region 20 within the GaN HEMT device, where zero potential is connected.

[0095] The implementation also includes the following steps:

[0096] A second connection region 33 is formed by injection into the inner wall of the first through hole. The second connection region 33 is as follows:

[0097] In the vertical direction, the second connection area 33 is connected below the first connection area 21, and the bottom end of the SiC connection area 20 enters into the electric field termination layer 11 or the bottom end of the SiC connection area 20 is connected to the upper surface of the substrate 10.

[0098] In the lateral direction, the second connection area 33 is formed on the outer peripheral surface of the SIC connection area 20;

[0099] The doping concentration of the second connection region 33 is greater than the doping concentration of the electric field termination layer 11.

[0100] The electric field termination layer 11 and the electric field bearing layer 12 formed on the substrate 10 are essential structures for GaN HEMT devices. The upper surface of the electric field bearing layer is divided into a first electric field bearing layer region and a second electric field bearing layer region, and the GaN HEMT front structure is formed on the first electric field bearing layer region.

[0101] The first via is formed by etching downwards from the second region of the electric field bearing layer, with the bottom end of the first via penetrating into the substrate 10. That is, the etching for forming the first via begins in the second region of the electric field bearing layer and ends within the substrate 10. The etching for forming the first via only needs to penetrate the thickness of the SiC material's electric field termination layer 11 and the electric field bearing layer 12, and then slightly deeper into the substrate 10. The total thickness of the electric field termination layer 11 and the electric field bearing layer 12 is generally only a few micrometers; therefore, the etching depth for forming the first via is very small.

[0102] The N-type SiC connection region 20 is formed by filling the first via with N-type polycrystalline SiC, and the lower end of the SiC connection region 20 extends into the substrate 10. In this way, the back ground metal 32, the N-type substrate 10, and the N-type SiC connection region 20 are connected.

[0103] The GaN HEMT front-side structure is formed above the first electric field-bearing pressure region. The distance between the back-side ground metal 32 and the upper surface of the GaN HEMT front-side structure is the full thickness of the GaN HEMT device of this application. Therefore, the etching to form the first via is performed on the SiC material, which is difficult to etch, and the etching depth is relatively small, and much smaller than the thickness of the GaN HEMT device of this application. Therefore, the etching to form the first via does not require a TSV via process, but only a semi-via etching process is needed, which is simple and has low implementation difficulty.

[0104] The first through hole has a smaller depth, and correspondingly, the diameter of the first through hole is also smaller, which in turn makes the area occupied by the first through hole smaller.

[0105] The back-side grounded metal 32 is grounded, and its conductive charge carriers are electrons. The substrate is an N-type low-resistivity substrate 10, meaning that the majority charge carriers of substrate 10 are electrons, and substrate 10 has a relatively large number of electrons. Since both the back-side grounded metal 32 and the N-type low-resistivity substrate 10 have a relatively large number of electrons as conductive charge carriers, the connection between the N-type low-resistivity substrate 10 and the back-side grounded metal 32 has a good electrical connection and low resistance.

[0106] Both the N-type substrate 10 and the N-type SiC connection region 20 are N-type, and the majority carriers are electrons. Thus, by controlling the doping concentration of the N-type substrate 10 and the N-type SiC connection region 20, it is possible to achieve a better electrical connection and lower resistance at the connection point of the N-type substrate 10 and the N-type SiC connection region 20.

[0107] This allows for a good electrical connection between the back-side ground metal 32, the N-type substrate 10, and the N-type SiC connection region 20, resulting in low resistance. Since the back-side ground metal 32 is grounded, the connection between the back-side ground metal 32, the N-type substrate 10, and the N-type SiC connection region 20 connects the zero potential of the grounded back-side ground metal 32 to the upper surface of the SiC connection region 20 (corresponding to the height of the upper surface of the second region of the epitaxial layer). In other words, the zero potential is connected to the interior of the GaN HEMT device of this application and is located in the middle of the thickness direction, providing the conditions for front-side grounding of the GaN HEMT device of this application. Thus, the structure of the GaN HEMT device of this application eliminates the need for front-side grounding to penetrate the entire thickness of the device, and consequently, eliminates the need for TSV via technology.

[0108] The fabrication process of the GaN HEMT device in this application, based on Figures 2A-6 in chronological order, also includes the following steps:

[0109] Step S7: As shown in Figure 6, a back-ground metal 32 is formed on the back side of the N-type low-resistivity substrate 10, and a P-type SiC material epitaxial layer is formed from the upper surface of the substrate 10. The epitaxial layer consists of a P-type electric field termination layer 11 and an electric field bearing layer 12 from bottom to top.

[0110] Step S8: As shown in Figure 7, a P-type first connection region base is formed by implantation. A first through-hole is formed by etching from the upper surface of the first connection region base downwards. An N-type polycrystalline SiC is filled in the first through-hole to form an N-type SiC connection region 20. At this time, the first connection region 21 is formed.

[0111] Step S9: As shown in Figure 8, AlN layer foundation 220, GaN buffer layer foundation 230, GaN layer foundation 240, AlGaN layer foundation 250 and SiN layer foundation 270 are formed sequentially from bottom to top above the electric field bearing layer 12, the N-type SiC connection region 20 and the first connection region 21.

[0112] Step S10: As shown in Figure 9, the first interconnect region 21 and the N-type SiC interconnect region 20 are exposed by etching downward from the upper surface of the SiN layer base 270.

[0113] Step S11: As shown in Figure 10, a metal silicide layer 29 is formed on the first connection region 21 and the N-type SiC connection region 20;

[0114] Step S12: As shown in Figure 11, a gate metal 26 is formed on the SiN layer base 270;

[0115] Step S13: As shown in Figure 12, a first contact hole 30 is formed on the metal silicide layer 29 to form a source electrode 28-1 and a drain electrode 28-2; thus, an AlN layer 22, a GaN buffer layer 23, a GaN layer 24, an AlGaN layer 25, and a SiN layer 27 are formed.

[0116] Step S14: As shown in Figure 13, source metal 31 and drain metal are formed.

[0117] Example 2

[0118] The GaN HEMT device of this application includes:

[0119] Substrate 10 of SiC material of the second doping type;

[0120] An electric field termination layer 11 of a first doped type of SiC grown along the C-axis is formed on the substrate 10.

[0121] An electric field bearing layer 12 of a first doped type of SiC grown along the C-axis is formed on the electric field termination layer 11.

[0122] The substrate 10 can specifically be a substrate 10 grown at an angle of 4 degrees off the C-axis with the second doping type.

[0123] The GaN HEMT device of this application, comprising a substrate 10, an electric field termination layer 11, and an electric field bearing layer 12, serves as the basis for the epitaxial structure of the GaN HEMT device. The overall cost is low, and the fabrication process is relatively simple. The substrate 10, electric field termination layer 11, and electric field bearing layer 12 correspond to the high-resistivity SiC substrates in the prior art.

[0124] The substrate 10 grown at a 4-degree angle off the C-axis in this application has a relatively large thickness, and the back side of the substrate 10 needs to be thinned after the entire GaN HEMT device is completed. The substrate 10 grown at a 4-degree angle off the C-axis in this application, which has a lower cost, serves as both a support base and a target for thinning.

[0125] The electric field termination layer 11 and the electric field bearing layer 12 are relatively expensive, but their thickness in the GaN HEMT device of this application is small, and the electric field termination layer 11 and the electric field bearing layer 12 do not need to be thinned during the entire fabrication process of the GaN HEMT device, so the expensive electric field termination layer 11 and the electric field bearing layer 12 are not lost. The electric field termination layer 11 and the electric field bearing layer 12 in this application serve the functions of bearing pressure and terminating the electric field. Therefore, the substrate 10, the electric field termination layer 11, and the electric field bearing layer 12 as a whole can correspond to the high-resistivity SiC substrate in the prior art.

[0126] In practice, the substrate 10 is a low-resistivity substrate 10;

[0127] The upper surface of the electric field pressure-bearing layer 12 is divided into a first region of the electric field pressure-bearing layer and a second region of the electric field pressure-bearing layer.

[0128] GaN HEMT devices also include:

[0129] A grounded back-side grounding metal 32 is formed on the back side of the substrate 10;

[0130] The first through hole is formed downward from the first region of the electric field bearing layer, and the bottom end of the first through hole enters into the substrate 10;

[0131] The N-type SiC connection region 20 is formed by filling the first via with N-type polycrystalline SiC, and the lower end of the SiC connection region 20 extends into the substrate 10.

[0132] The GaN HEMT front structure is formed on the second region of the electric field bearing layer;

[0133] The back-side ground metal 32, the N-type substrate 10, and the N-type SiC connection region 20 are connected to the position of the upper surface of the SiC connection region 20, which connects to the zero potential within the GaN HEMT device.

[0134] Patent application CN118016691A discloses a gallium nitride heterostructure based on a large-size silicon-based composite substrate and its fabrication method.

[0135] This application differs from patent application with publication number CN118016691A in the following ways:

[0136] Patent application CN118016691A discloses a silicon-based composite substrate, employing Si and SiC substrate bonding. These two heterogeneous materials have different thermal conductivity and lattice constants, inevitably leading to thermal and lattice mismatch issues during bonding. Stress is generated at the bonding interface, and to relax this stress, dislocations form at the interface, potentially extending upwards and affecting the SiC material, subsequently impacting the performance of gallium nitride (GaN) materials and devices. Achieving a good interface necessitates strict control over the bonding process and quality, increasing costs. Furthermore, silicon's thermal conductivity is significantly lower than that of SiC and GaN, resulting in slow heat dissipation and severely limiting the high-temperature and high-power applications of power devices.

[0137] Furthermore, silicon-based composite substrates cannot be used in the structure of connecting SiC interconnects to the substrate in this application. Due to the heterojunction structure formed by SiC and Si materials, there may be defects, dangling bonds, and interface states at the interface, which affect the transport of electrons from the SiC interconnect to the Si material, thereby affecting the performance of GaN devices.

[0138] This application uses SiC epitaxial wafers bonded to SiC substrates. Since they are homogeneous materials, there are no thermal mismatch or lattice mismatch issues at the bonding interface. There are no special requirements for the bonding process, so it will not increase costs. At the same time, since the SiC interconnect layer and the substrate are made of the same material, the device performance will not be affected.

[0139] In practice, the depth at which the lower end of the N-type SiC interconnect region 20 penetrates into the substrate 10 is greater than or equal to 0.1 μm. This ensures a good connection between the N-type SiC interconnect region 20 and the substrate 10.

[0140] In practice, the thickness of the substrate 10 is in the range of 5 μm less than or equal to 300 μm;

[0141] The resistivity of the substrate 10 is greater than or equal to 0.1 mol / cm and less than or equal to 1000 ohm / cm.

[0142] The logic behind choosing the substrate resistivity is that the device needs to conduct electricity to the back side through the substrate. With current technology, the back substrate thickness is approximately 100 μm. To achieve lower resistance to ground, for a 10 mm² device, based on a resistivity of 100 ohms*cm, the resistance to ground is 10 ohms. Values ​​greater than this will result in poor device performance. The substrate thickness and resistivity together determine the parasitic resistance.

[0143] In practice, as shown in Figures 3, 4, and 5, the GaN HEMT device of this application also includes:

[0144] A metal silicide layer 29 is formed on an N-type SiC interconnect region 20;

[0145] A first contact hole 30 is formed on the metal silicide layer 29; the upper end of the first contact hole 30 is connected to the source metal 31 of the GaN HEMT front structure.

[0146] The GaN HEMT front structure includes a source metal 31, a first contact hole 30, a metal silicide layer 29, an N-type SiC interconnect region 20, an N-type substrate 10, and a grounded back metal 32.

[0147] In this way, the source metal 31 of the GaN HEMT front structure is grounded from the front of the GaN HEMT device of this application through the first contact hole 30, the metal silicide layer 29, the N-type SiC interconnect region 20, the N-type substrate 10, and the grounded back ground metal 32. That is, the source of the GaN HEMT device of this application is grounded through the front ground structure.

[0148] The first contact hole 30 is formed using a contact hole process, and the first contact hole 30 is made of tungsten metal. Therefore, the fabrication process of the first contact hole 30 is simple and has low cost.

[0149] Thus, the front-side grounding structure of the GaN HEMT device in this application includes:

[0150] The components include source metal 31, first contact hole 30, metal silicide layer 29, N-type SiC interconnect region 20 (filled in the first via), N-type substrate 10, grounded back-side ground metal 32, and first interconnect region 21.

[0151] The adopted two-end structure consists of one section consisting of the metal silicide layer 29 and the structure below it (the N-type SiC connection area 20 (filled in the first via), the N-type substrate 10, the grounded back-side ground metal 32, and the first connection area 21), and another section consisting of the structure above the metal silicide layer 29 (the source metal 31 and the first contact hole 30). Both the first contact hole 30 and the first via are relatively short, much shorter than the overall thickness of the GaN HEMT device of this application. Moreover, the first contact hole 30 uses a contact hole process, and the first via uses a semi-through-hole process. That is, the fabrication process of the front-side ground structure of the GaN HEMT device of this application does not require the TSV process, and the shortcomings of the TSV process are also absent in this application.

[0152] In practice, as shown in Figures 3, 4, and 5, the GaN HEMT device of this application also includes:

[0153] A P-type interconnect region is formed downward from the first region of the epitaxial layer within the epitaxial layer, and the P-type interconnect region is connected to the outer peripheral surface of the N-type SiC interconnect region 20; and the metal silicide layer 29 is formed on the N-type SiC interconnect region 20 and the P-type interconnect region.

[0154] The metal silicide layer 29 connects the N-type SiC connection region 20 and the P-type connection region, respectively.

[0155] This achieves the connection of the back ground metal 32, the N-type substrate 10, the N-type SiC connection region 20, and the metal silicide layer 29; as well as the connection of the P-type epitaxial layer, the P-type connection region, and the metal silicide layer 29.

[0156] The zero potential of the grounded back-side grounding metal 32 is connected to the metal silicide layer 29 via the back-side grounding metal 32, the N-type substrate 10, the N-type SiC interconnect region 20, and the metal silicide layer 29. The P-type epitaxial layer is connected to zero potential via the metal silicide layer 29 (which is already connected to zero potential), the P-type interconnect region, and the P-type epitaxial layer.

[0157] Regarding the structure of the epitaxial layer:

[0158] As a first alternative, the epitaxial layer includes:

[0159] A P-type electric field termination layer 11 is formed on the substrate 10.

[0160] As a second alternative approach, in implementation, as shown in Figures 3, 4, and 5, the epitaxial layer includes:

[0161] A P-type electric field termination layer 11 is formed on the substrate 10;

[0162] A P-type electric field bearing layer 12 is formed on the electric field termination layer 11.

[0163] Simultaneously providing a P-type electric field termination layer 11 and a P-type electric field bearing layer 12 is a preferred implementation. In this way, the parameters of the lower-doped P-type electric field bearing layer 12 are used to meet the voltage withstand requirements of the GaN HEMT device, while the parameters of the higher-doped P-type electric field termination layer 11 are used to meet the electric field cutoff requirements of the GaN HEMT device. Therefore, the GaN HEMT device of this application can meet the voltage withstand requirements, while also ensuring that the electric field is cut off within the electric field termination layer 11, and the overall thickness of the GaN HEMT device remains relatively small.

[0164] In practice, as shown in Figures 3, 4, and 5, the GaN HEMT device also includes:

[0165] The first connection region 21 of type P is formed downward from the upper surface of the epitaxial layer and connected to the outer peripheral surface of the SiC connection region 20 of type N. The first connection region 21 occupies a part of the epitaxial layer in the lateral direction.

[0166] The metal silicide layer 29 is also formed on the first connection region 21, and the metal silicide layer 29 connects the first connection region 21 and the N-type SiC connection region 20 respectively.

[0167] The epitaxial layer of P-type SiC material, the first P-type connection region 21, and the metal silicide layer 29 are connected and electrically well. Since the zero potential has been connected to the metal silicide layer 29, the epitaxial layer is thus connected to zero potential.

[0168] In implementation, as shown in Figures 3, 4, and 5, the P-type connection area includes a P-type first connection area 21, wherein the first connection area 21:

[0169] In the vertical direction, the first connection area 21 is formed downward from the upper surface of the electric field bearing layer 12, and the lower surface of the first connection area 21 is higher than the lower surface of the electric field bearing layer 12.

[0170] In the lateral direction, the first connection area 21 is connected to the outer peripheral surface of the N-type SiC connection area 20, occupying a portion of the electric field bearing layer 12;

[0171] The doping concentration of the first connection region 21 is greater than the doping concentration of the electric field bearing layer 12;

[0172] The metal silicide layer 29 is also formed on the first connection region 21, and the metal silicide layer 29 connects the first connection region 21 and the N-type SiC connection region 20 respectively.

[0173] The doping concentration of the first connection region 21 of the P-type is greater than the doping concentration of the electric field bearing layer 12 of the P-type. Thus, the electric field bearing layer 12 of the P-type and the first connection region 21 of the P-type are electrically connected to the metal silicide layer 29 with zero potential, thereby realizing that the electric field bearing layer 12 of the P-type is connected to zero potential.

[0174] The metal silicide layer 29 is connected to the first connection region 21 and the N-type SiC connection region 20, respectively. The zero potential of the grounded back-side metal 32 is connected to the metal silicide layer 29 via the back-side ground metal 32, the N-type substrate 10, the N-type SiC connection region 20, and the metal silicide layer 29. The P-type electric field bearing layer 12, the P-type first connection region 21, and the metal silicide layer 29 connected to zero potential are electrically connected, thus connecting the P-type electric field bearing layer 12 to zero potential.

[0175] The first region of the epitaxial layer corresponds to the first region of the electric field bearing layer, and the second region of the epitaxial layer corresponds to the second region of the electric field bearing layer.

[0176] As an alternative approach, as shown in Figure 4, the first connection region 21 is located below the first region of the electric field bearing layer and partially below the second region of the electric field bearing layer. That is, the first connection region 21 extends laterally beneath the GaN HEMT front structure.

[0177] Since the doping concentration of the first connection region 21 is greater than that of the electric field bearing layer 12, the electric field generated by the GaN HEMT front structure is rapidly reduced at the location of the first connection region 21, which plays a role in balancing the electric field.

[0178] As an alternative approach, as shown in Figure 5, the P-type connection region further includes a P-type second connection region 33:

[0179] In the vertical direction, the second connection area 33 is connected below the first connection area 21, and the bottom end of the N-type SiC connection area 20 enters into the electric field termination layer 11 or the bottom end of the N-type SiC connection area 20 is connected to the upper surface of the substrate 10.

[0180] In the lateral direction, the second connection region 33 is formed on the outer peripheral surface of the N-type SiC connection region 20;

[0181] The doping concentration of the second connection region 33 is greater than the doping concentration of the electric field termination layer 11.

[0182] Because the doping concentration of the second connection region 33 is greater than that of the electric field termination layer 11 and the doping concentration of the first connection region 21 is greater than that of the electric field bearing layer 12, the connection of the electric field termination layer 11, the second connection region 33, the first connection region 21 and the metal silicide layer 29 of the P-type is better, and the connection of the electric field bearing layer 12, the second connection region 33, the first connection region 21 and the metal silicide layer 29 of the N-type is also better.

[0183] The epitaxial layer of the P-type SiC material, the P-type second connection region 33, and the metal silicide layer 29 are connected and electrically connected, which is also to better connect the epitaxial layer to zero potential.

[0184] The reason why the first connection region 21 and the second connection region 33 are formed using two separate processes is that, due to limitations in the implantation process, the depth of the first connection region 21 cannot be reached too deeply, and the first connection region 21 cannot directly enter the electric field termination layer 11. Therefore, the second connection region 33 is formed by ion implantation on the sidewall of the via once.

[0185] The higher the doping concentration of the first connection region 21 and the second connection region 33, the better. In actual fabrication, the doping concentration of the first connection region 21 and the second connection region 33 is limited by the ion implantation process.

[0186] In practice, the doping concentration of the first connection region 21 ranges from greater than or equal to 1 × 10⁻⁶. 17 cm -3 Less than or equal to 1×10 22 cm -3 Furthermore, the doping concentration of the first connection region 21 is at least two orders of magnitude higher than the doping concentration of the electric field bearing layer 12;

[0187] The doping concentration of the second connection region 33 ranges from 1×10⁻⁶. 17 cm -3 Less than or equal to 1×10 22 cm -3 Furthermore, the doping concentration of the second connection region 33 is at least two orders of magnitude higher than the doping concentration of the electric field termination layer 11.

[0188] Specifically, as shown in Figures 3, 4, and 5, the GaN HEMT front-side structure includes:

[0189] AlN layer 22 is formed on the second region of the electric field bearing layer;

[0190] GaN buffer layer 23 is formed on top of AlN layer 22;

[0191] GaN layer 24 is formed on top of GaN buffer layer 23;

[0192] AlGaN layer 25 is formed on top of GaN layer 24;

[0193] SiN layer 27 is formed on top of AlGaN layer 25;

[0194] Gate metal 26 is formed on SiN layer 27 and is connected to AlGaN layer 25 through contact hole through SiN layer 27.

[0195] The source electrode 28-1 and the drain electrode 28-2 each penetrate through the SiN layer 27 and the AlGaN layer 25 into the GaN layer 24, and are respectively connected to the two ends of the GaN layer 24;

[0196] Source metal 31 is connected to source metal 28-1.

[0197] AlN stands for aluminum nitride; GaN for gallium nitride; AlGaN for aluminum gallium nitride; and SiN for silicon nitride.

[0198] AlGaN / GaN form a heterojunction, and the two-dimensional electron gas (2DEG) generated by the heterojunction is the basis for the operation of all GaN HEMT devices. AlGaN layer 25 and GaN layer 24 form a heterojunction, and the two-dimensional electron gas 2DEG generated by the heterojunction is controlled to be turned on and off by gate metal 26.

[0199] The electric field termination layer 11 and the electric field bearing layer 12 are required to grow along the C-axis because this results in better performance of the GaN HEMT front structure.

[0200] Although some optional embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including some optional embodiments as well as all changes and modifications falling within the scope of this application.

[0201] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for fabricating a GaN HEMT device, characterized in that, include: A substrate (10) for forming a second type of SiC material; Form a separate first-doped SiC epitaxial wafer (12-0) grown along the C-axis; An electric field termination layer (11) of the first doping type is formed on the front side of the SiC epitaxial wafer (12-0); wherein the doping concentration of the electric field termination layer (11) is greater than the doping concentration of the substrate (10); A release layer (13) is formed in the SiC epitaxial wafer (12-0) below the electric field termination layer (11); wherein, the portion of the SiC epitaxial wafer (12-0) between the electric field termination layer (11) and the release layer (13) serves as an electric field bearing layer (12); The front side of the electric field termination layer (11) and the front side of the substrate (10) are bonded together; Peeling is performed at the location of the peeling layer (13); wherein, the electric field termination layer (11) and the electric field bearing layer (12) are sequentially located on the substrate (10).

2. The method for fabricating a GaN HEMT device according to claim 1, characterized in that, The step of forming a first-doped electric field termination layer (11) on the front side of the SiC epitaxial wafer (12-0) specifically includes: An electric field termination layer (11) of the first doping type is formed on the front side of the SiC epitaxial wafer (12-0) by ion implantation; Alternatively, an electric field termination layer (11) of the first doping type can be formed by epitaxial growth on the front side of the SiC epitaxial wafer (12-0).

3. The method for fabricating a GaN HEMT device according to claim 2, characterized in that, The step of forming a release layer (13) in the SiC epitaxial wafer (12-0) below the electric field termination layer (11) is as follows: A release layer (13) is formed by hydrogen ion implantation at a position below the electric field termination layer (11) in the SiC epitaxial wafer (12-0).

4. The method for fabricating a GaN HEMT device according to claim 3, characterized in that, The step of bonding the front side of the electric field termination layer (11) and the front side of the substrate (10) together is specifically as follows: The front side of the electric field termination layer (11) and the front side of the substrate (10) are connected together by low-temperature bonding; The step of peeling the SiC epitaxial wafer (12-0) from the release layer (13) is as follows: The peeling is performed at the peeling layer (13) by thermal reaction, and the bond is strengthened by high temperature heat annealing, and the surface of the electric field bearing layer (12) that has just been peeled off is smoothed by CMP.

5. The method for fabricating a GaN HEMT device according to any one of claims 1 to 4, characterized in that, The substrate (10) is a single crystal or a polycrystalline substrate, and the substrate is a high-resistivity substrate or a low-resistivity substrate. The specific steps for forming the substrate (10) of the second doped SiC material are as follows: A substrate (10) of a second-doped SiC material grown at an angle of 4 degrees off the C-axis is formed.

6. The method for fabricating a GaN HEMT device according to any one of claims 1 to 4, characterized in that, The substrate (10) is a low-resistivity substrate; The upper surface of the electric field bearing layer (12) is divided into a first region of the electric field bearing layer and a second region of the electric field bearing layer; the preparation method also includes the following steps: A grounded back-side metal (32) is formed on the back side of the substrate (10); A first connection region base of the first doped type is formed downward in the second region of the electric field bearing layer. A first through hole is formed downward from the upper surface of the first connection region base by etching. The first through hole is filled with SiC of the second doped type to form a SiC connection region of the second doped type (20). The unetched part of the first connection region base forms the first connection region (21).

7. The method for fabricating a GaN HEMT device according to claim 6, characterized in that, It also includes the following steps: A second connection region (33) is formed by injection into the inner wall of the first through hole. The second connection region (33) is as follows: In the vertical direction, the second connection area (33) is connected below the first connection area (21), and the bottom end of the SIC connection area (20) enters into the electric field termination layer (11) or the bottom end of the SIC connection area (20) is connected to the upper surface of the substrate (10). In the lateral direction, the second connection area (33) is formed on the outer peripheral surface of the SIC connection area (20).

8. A GaN HEMT device, characterized in that, include: Substrate (10) of SiC material of the second doping type; An electric field termination layer (11) of a first doped type of SiC grown along the C-axis is formed on the substrate (10); An electric field bearing layer (12) of a first doped type of SiC grown along the C-axis is formed on the electric field termination layer (11).

9. The GaN HEMT device according to claim 8, characterized in that, The substrate (10) is a low-resistivity substrate; The upper surface of the electric field bearing layer (12) is divided into a first region of the electric field bearing layer and a second region of the electric field bearing layer; GaN HEMT devices also include: A grounded back-side grounding metal (32) is formed on the back side of the substrate (10); The first through hole is formed downward from the first region of the electric field bearing layer, and the bottom end of the first through hole enters into the substrate (10); The N-type SiC connection region (20) is formed by filling the first via with N-type polycrystalline SiC, and the lower end of the SiC connection region (20) extends into the substrate (10). The GaN HEMT front structure is formed on the second region of the electric field bearing layer; The back-side ground metal (32), the N-type substrate (10), and the N-type SiC connection area (20) are connected and attached to the GaN HEMT device.

10. The GaN HEMT device of claim 9, wherein, Also includes: A metal silicide layer (29) is formed on an N-type SiC interconnect region (20); A first contact hole (30) is formed on the metal silicide layer (29); the upper end of the first contact hole (30) is connected to the source metal (31) of the GaN HEMT front structure; The source metal (31), the first contact hole (30), and the metal silicide layer (29) of the GaN HEMT front structure are connected.

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