Display substrate and preparation method therefor, and display panel

Abstract

The present disclosure belongs to the technical field of display. Provided is a display substrate, by means of which the problem of the light utilization rate of a display substrate being low can be solved. The display substrate in the present disclosure comprises a base substrate, and a plurality of pixel units arranged on the base substrate, wherein each pixel unit comprises a pixel driving circuit and a light-emitting device connected to the pixel driving circuit; a planarization layer is provided on the side of the pixel driving circuit facing away from the base substrate, and the planarization layer is provided with a plurality of first grooves, with a first electrode of a light-emitting device covering a first groove; a pixel defining layer is provided on the side, which faces away from the base substrate, of a layer where first electrodes of light-emitting devices are located; the pixel defining layer is provided with a plurality of pixel openings; and an orthographic projection of a pixel opening on the base substrate is located within a range defined by an orthographic projection of a first groove on the base substrate.

Description

Display substrate and its preparation method, display panel Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display substrate and its preparation method, and a display panel. Background Technology

[0002] Organic light-emitting displays (OLEDs) offer advantages over liquid crystal displays, including self-illumination, fast response, wide viewing angles, high brightness, vibrant colors, and thinness, and are considered the next generation of display technology. The self-emissive element of an OLED device mainly consists of an anode layer, an organic material functional layer (typically including an electron transport layer, an emissive layer, and a hole transport layer), and a cathode layer, arranged sequentially away from the substrate. However, existing OLED devices suffer from low light utilization efficiency. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a display substrate, including a substrate and a plurality of pixel units disposed on the substrate; the pixel unit includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit; wherein,

[0004] A planarization layer is provided on the side of the pixel driving circuit away from the substrate, and the planarization layer has a plurality of first grooves, and a first electrode of the light-emitting device covers the first groove; the first electrode of the light-emitting device is provided on the side of the planarization layer away from the substrate, and the first electrode of the light-emitting device covers the bottom and sidewall of the first groove.

[0005] A pixel defining layer is provided on the side of the layer where the first electrode of each of the light-emitting devices is located, away from the substrate; the pixel defining layer has a plurality of pixel openings; the orthogonal projection of one of the pixel openings on the substrate is located within the defined range of the orthogonal projection of the first groove on the substrate.

[0006] In some embodiments, the light-emitting layer of the light-emitting device is disposed on the side of the first electrode away from the substrate, and the light-emitting layer is located at the pixel opening; the shape of the light-emitting layer and the orthographic projection of the pixel opening on the substrate are different.

[0007] In some embodiments, the distance between the light-emitting layer and the sidewall of the first groove is not equal at at least some locations.

[0008] In some embodiments, the pixel defining layer includes a pixel barrier defining the plurality of pixel openings; the first electrode includes an electrically connected first sub-electrode and a second sub-electrode; the first sub-electrode covers the bottom of the first groove, and the second sub-electrode covers at least the sidewall of the first groove;

[0009] The orthographic projection of the pixel barrier on the substrate covers the orthographic projection of the second sub-electrode on the substrate, and at least partially overlaps with the orthographic projection of the first sub-electrode on the substrate.

[0010] In some embodiments, the planarization layer includes a first sub-planarization layer and a second sub-planarization layer stacked in a direction away from the substrate.

[0011] The surface of the first sub-planarization layer facing away from the substrate is the first surface; the second sub-planarization layer includes a plurality of planar portions; the sidewalls of the four adjacent planar portions together with the first surface define the first groove.

[0012] In some embodiments, the dihedral angle formed by the sidewall of the flat portion and the first surface is θ, where 20°≤θ≤80°.

[0013] In some embodiments, the pixel defining layer is in contact with at least a portion of the first electrode; the maximum distance between the orthographic projection of the pixel defining layer on the first surface and the orthographic projection of the flat portion on the first surface is w, where 0µm < w ≤ 3µm.

[0014] In some embodiments, the display substrate further includes an interlayer insulating layer disposed between the layer containing the pixel driving circuit and the first sub-planarization layer, and a first conductive layer disposed between the interlayer insulating layer and the first sub-planarization layer;

[0015] The first conductive layer includes a first transition electrode; the pixel driving circuit includes at least a driving thin film transistor; the first transition electrode is connected to the drain of the driving thin film transistor through a first via penetrating the interlayer insulating layer; the first electrode is connected to the first transition electrode through a second via penetrating the planarization portion and the first sub-planarization layer in sequence.

[0016] In some embodiments, the first conductive layer further includes an auxiliary electrode; the orthographic projection of the auxiliary electrode on the substrate is located within the defined range of the orthographic projection of the light-emitting layer on the substrate.

[0017] In some embodiments, a support layer is further provided on the side of the pixel defining layer opposite to the substrate; the orthographic projection of the support layer on the substrate is located within the defined range of the orthographic projection of the pixel defining layer on the substrate.

[0018] In some embodiments, the plurality of pixel units include a first color pixel unit, a second color pixel unit, and a third color pixel unit that emit different colors;

[0019] The plurality of pixel units are divided into alternating first pixel groups and second pixel groups along a first direction, with adjacent second pixel groups staggered; the plurality of pixel units are divided into alternating third pixel groups and fourth pixel groups along a second direction, with adjacent fourth pixel groups staggered; the first direction intersects the second direction;

[0020] The first pixel group includes a plurality of first color pixel units spaced apart along the second direction; the second pixel group includes a plurality of second color pixel units and the third color pixel units arranged alternately along the second direction; the third pixel group includes a plurality of first color pixel units spaced apart along the first direction; and the fourth pixel group includes a plurality of second color pixel units and the third color pixel units arranged alternately along the first direction.

[0021] In some embodiments, the spacing between two adjacent first color pixel units in the first pixel group, the spacing between adjacent second color pixel units and third color pixel units in the second pixel group, the spacing between two adjacent first color pixel units in the third pixel group, and the spacing between adjacent second color pixel units and third color pixel units in the fourth pixel group are all equal.

[0022] In some embodiments, the size of the first color pixel unit, the second color pixel unit, and the third color pixel unit are all 2µm to 60nm;

[0023] The distance between the first color pixel unit and the nearest first color pixel unit is 5µm to 30nm; the distance between the first color pixel unit and the nearest third color pixel unit is 5µm to 30nm; the distance between the second color pixel unit and the nearest third color pixel unit is 5µm to 30nm.

[0024] In some embodiments, the orthographic projection of the first groove on the substrate includes any one of a square, rectangle, circle, triangle, or irregular shape; the orthographic projection of the light-emitting unit on the substrate includes any one of a square, rectangle, circle, triangle, or irregular shape.

[0025] This disclosure also provides a method for preparing the above-mentioned display substrate, comprising:

[0026] A substrate is provided on which a plurality of pixel driving circuits are formed;

[0027] A planarization layer is formed on the side of the layer where the pixel driving circuit is located that is away from the substrate, and a plurality of first grooves are formed on the planarization layer;

[0028] A plurality of first electrodes for light-emitting devices are formed on the side of the planarization layer opposite to the substrate; one of the first electrodes for light-emitting devices covers the bottom and sidewalls of the first groove;

[0029] A pixel defining layer is formed on the side of the layer where the first electrode of each of the light-emitting devices is located, away from the substrate; the pixel defining layer has a plurality of pixel openings; the orthogonal projection of one of the pixel openings on the substrate is located within the defined range of the orthogonal projection of the first groove on the substrate.

[0030] This disclosure also provides a display panel, including the display substrate in the above embodiments. Attached Figure Description

[0031] Figure 1 is a schematic diagram of the structure of an existing display substrate.

[0032] Figure 2 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure.

[0033] Figure 3 is a partial structural schematic diagram of a display substrate provided in an embodiment of this disclosure.

[0034] Figure 4 is a partial structural schematic diagram of a display substrate provided in an embodiment of this disclosure.

[0035] Figure 5 is a graph showing the relationship between the dihedral angle θ and the light intensity on the light-emitting side of the display substrate, according to an embodiment of this disclosure.

[0036] Figure 6 is a partial structural schematic diagram of an actual display substrate provided in an embodiment of this disclosure.

[0037] Figure 7 is a partial structural schematic diagram of another actual display substrate provided in an embodiment of this disclosure.

[0038] Figure 8 is a top view of the first groove and the light-emitting layer provided in an embodiment of this disclosure.

[0039] Figure 9 is a schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure.

[0040] Figure 10 is a partial structural schematic diagram of a display substrate provided in an embodiment of this disclosure.

[0041] Figure 11 is a schematic diagram of the arrangement of pixel units in a display substrate provided in this disclosure.

[0042] Figure 12a is a schematic diagram of the intermediate product structure in step S1 of the process of preparing a display substrate provided in the embodiments of this disclosure.

[0043] Figure 12b is a schematic diagram of the intermediate product structure in step S2 of the process of preparing a display substrate provided in the embodiments of this disclosure.

[0044] Figure 12c is a schematic diagram of the intermediate product structure in step S3 of the process of preparing a display substrate provided in the embodiments of this disclosure.

[0045] Figure 12d is a schematic diagram of the intermediate product structure in step S4 of the process of preparing a display substrate provided in the embodiments of this disclosure.

[0046] Figure 12e is a schematic diagram of the intermediate product structure in step S5 of the process of preparing a display substrate provided in the embodiments of this disclosure.

[0047] Figure 12f is a schematic diagram of the intermediate product structure in step S6 of the process of preparing a display substrate provided in the embodiments of this disclosure.

[0048] Figure 12g is a schematic diagram of the intermediate product structure in step S7 of the process of preparing a display substrate provided in the embodiments of this disclosure.

[0049] Figure 12h is a schematic diagram of the intermediate product structure in step S8 of the process of preparing a display substrate provided in the embodiments of this disclosure.

[0050] Figure 12i is a schematic diagram of the intermediate product structure in step S9 of the process of preparing a display substrate according to an embodiment of this disclosure. Detailed Implementation

[0051] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0053] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0054] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate. Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] In related technologies, referring to Figure 1, to achieve surface planarization of the device, the planarization layer PLN of the display substrate completely covers the underlying driving circuit layer DL, which includes multiple driving circuits PC, and the thickness of the planarization layer PLN is equal at all locations. The anode of the light-emitting device is disposed above the planarization layer PLN, and the pixel limiting layer PDL is disposed above the layer where the anode is located. The pixel openings in the pixel limiting layer PDL allow at least a portion of the anode to contact the light-emitting layer EL of the light-emitting device to drive the light-emitting device to emit light. However, the light emitted by the light-emitting device is directed in all directions. Among them, the light emitted to the left and right sides will be transmitted laterally along the light-emitting layer EL and cannot be reflected to the light-emitting side of the display substrate for effective utilization, resulting in a reduction in light utilization.

[0056] To address the aforementioned issues, this disclosure provides a display substrate, as shown in Figure 2, which includes a substrate SUB and a plurality of pixel units disposed on the substrate SUB. Each pixel unit includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. The light-emitting device includes, but is not limited to, an organic light-emitting diode (OLED). The OLED includes a first electrode, a light-emitting layer EL, and a second electrode stacked sequentially along a direction away from the substrate SUB. The first electrode can be an anode, and the second electrode can be a cathode. The pixel driving circuit includes at least a driving thin-film transistor (TFT) Td, the drain D of which is electrically connected to the anode of the light-emitting device. After a driving voltage is applied to the anode by the pixel driving circuit, the light-emitting layer EL can emit light. The pixel driving circuit can employ a 2T1C, 7T1C, or similar pixel driving circuit.

[0057] Specifically, referring to Figures 2-4, the display substrate includes a substrate SUB, and a driving circuit layer DL (specifically including the driving thin-film transistor TFT Td, storage capacitor Cst, first gate insulating layer G11 and second gate insulating layer G12 in Figure 2), a planarization layer, a first electrode layer, and a pixel defining layer PDL stacked sequentially along a direction away from the substrate SUB. The driving circuit layer DL includes pixel driving circuits for each pixel unit. The planarization layer has multiple first grooves GRV, each corresponding to a pixel unit. The first electrode layer includes the anode of the light-emitting device in each pixel unit, and the anode covers the first groove GRV. It should be noted that the first groove GRV includes sidewalls and a bottom, and the anode includes an electrically connected first sub-electrode 31 and a second sub-electrode 32, wherein the first sub-electrode 31 covers the bottom of the first groove GRV, and the second sub-electrode 32 at least covers the sidewalls of the first groove GRV. The pixel defining layer PDL has multiple pixel openings OP and pixel barriers DQ defining the multiple pixel openings OP. The pixel openings OP are used to house the light-emitting layer EL of the light-emitting device. In some embodiments, the orthographic projection of the pixel barrier DQ onto the substrate SUB covers the orthographic projection of the second sub-electrode 32 onto the substrate SUB, and the orthographic projection of the pixel barrier DQ onto the substrate SUB at least partially overlaps with the orthographic projection of the first sub-electrode 31 onto the substrate SUB. In this case, the orthographic projection of a pixel opening OP onto the substrate SUB is located within the defined range of the orthographic projection of a first recess GRV onto the substrate SUB. In this situation, the light-emitting layer EL located within the pixel opening OP is also located within the first recess GRV. The anode on the sidewall of the first recess GRV can act as a reflector, reflecting the light emitted by the light-emitting layer EL to the left and right sides, ultimately allowing most of the light emitted by the light-emitting layer EL to exit from the light-emitting side of the display substrate, effectively improving light utilization.

[0058] Further, referring to FIGS. 2 and 3, the first planarization layer includes a stacked first sub-planarization layer PLN1 and second sub-planarization layer PLN2. The first sub-planarization layer PLN1 is closer to the substrate SUB than the second sub-planarization layer PLN2. Among them, the thickness of the first sub-planarization layer PLN1 is equal everywhere, and the second sub-planarization layer PLN2 includes a plurality of flat portions PLN2-1 that are discontinuously arranged. In some examples, the value range of the thickness h of the flat portion PLN2-1 is 1um < h ≤ 3um. When viewed from the light-emitting side of the display substrate, the extending directions of some flat portions PLN2-1 are in the row direction, and the extending directions of some flat portions PLN2-1 are in the column direction. The plurality of flat portions PLN2-1 arranged crosswise form the second sub-planarization layer PLN2 in a grid-like structure. One side of the first sub-planarization layer PLN1 facing away from the substrate SUB is the first surface O1. The first surface O1 and the side walls of four adjacent flat portions PLN2-1 together form the first groove GRV. When viewed from the light-emitting side of the display substrate, four adjacent flat portions PLN2-1 form a "square" structure, that is, one grid of the grid-like structure. The area in the middle of the grid is the first groove GRV, and the first groove GRV is used to arrange light-emitting devices.

[0059] In some examples, still referring to FIGS. 2-4, the dihedral angle formed by the side wall of the flat portion PLN2-1 and the first surface O1 is θ, and the value range of θ is 20° ≤ θ ≤ 80°. Preferably, θ is 40° - 60°. More preferably, θ is 5°. FIG. 5 is a relationship diagram of the value of θ and the light intensity on the light-emitting side of the display panel. Referring to FIG. 5, under the same power, assuming the light intensity of the traditional display substrate is 100% (at this time θ is 0°), when θ is 40°, the light intensity is 104.2%, that is, the light intensity is 1.042 times that of the traditional display substrate; when θ is 50°, the light intensity is 111.1%, that is, the light intensity is 1. times that of the traditional display substrate; when θ is 60°, the light intensity is 105.1%, that is, the light intensity is 1.051 times that of the traditional display substrate. Therefore, using the display substrate of the present application can reflect the light emitted from the light-emitting layer EL to the left and right sides and covered by the side wall of the flat portion PLN2-1 to the light-emitting side of the display panel, effectively improving the light utilization rate.

[0060] The size of the dihedral angle θ depends on the shape of the mask used when forming the first groove GRV. It is understood that during the formation of the first groove GRV, the mask is used to block part of the photoresist, preventing this blocked portion from being exposed and undergoing a chemical reaction. This blocked portion of the photoresist is then washed away in subsequent processes, forming the shape of the first groove GRV. Therefore, the shape of the mask is the same as the shape of the orthographic projection of the first groove GRV onto the substrate SUB. The shape of the orthographic projection of the first groove GRV onto the substrate SUB can include any one of a square, rectangle, circle, triangle, regular polygon, or irregular shape. Figures 6 and 7 exemplarily provide partial cross-sectional views of two actual display substrates. Referring to Figure 6, when the orthographic projection of the first groove GRV onto the substrate SUB is square, the resulting dihedral angle θ is 51.5°. Referring to Figure 7, when the orthographic projection of the first groove GRV onto the substrate SUB is circular, the resulting dihedral angle θ is 60.4°. Using masks of different shapes can create flat regions PLN2-1 with different morphologies and dihedral angles θ with different angle values.

[0061] In some examples, the shapes of the first groove GRV and the orthographic projection of the light-emitting layer EL onto the substrate SUB are different. The shape of the orthographic projection of the light-emitting layer EL onto the substrate SUB can include any of the following: square, rectangle, circle, triangle, regular polygon, or irregular shape. For example, the orthographic projection of the first groove GRV onto the substrate SUB is square, and the orthographic projection of the light-emitting layer EL onto the substrate SUB is triangular, as shown in Figure 8. Another example is that the orthographic projection of the first groove GRV onto the substrate SUB is semi-circular, and the orthographic projection of the light-emitting layer EL onto the substrate SUB is rectangular. In this case, the distance between the sidewall of the first groove GRV and the light-emitting layer EL is unequal at at least some locations. For example, when the orthographic projection of the first groove GRV onto the substrate SUB is square and the orthographic projection of the light-emitting layer EL onto the substrate SUB is circular, referring to Figure 8, the distance between the sidewall of the first groove GRV and the light-emitting layer EL first monotonically decreases and then monotonically increases along the column direction. This arrangement is designed to ensure that light emitted from different positions of the EL layer can be reflected to the light-emitting side by the anode on the sidewall, and that the distance between the sidewall of the first groove GRV and the EL layer is not equal at at least some positions, which can avoid excessive local light intensity and thus improve light uniformity.

[0062] In some examples, the pixel defining layer PDL not only covers the orthographic projection of the second sub-electrode 32 onto the substrate SUB, but also at least partially overlaps with the orthographic projection of the first sub-electrode 31 onto the substrate SUB. Referring again to Figures 2 and 3, the light-emitting layer EL disposed in the pixel opening OP has a certain preset distance between it and the first groove GRV. This preset distance ensures that the light emitted from the left and right sides of the light-emitting layer EL has sufficient space for reflection, further improving light utilization. For example, the maximum distance between the orthographic projection of the flat portion PLN2-1 onto the first surface O1 and the orthographic projection of the pixel defining layer PDL onto the first surface O1 is set to w, where w ranges from 0µm < w ≤ 3µm.

[0063] In some examples, the display substrate further includes a support layer disposed on the side of the pixel defining layer PDL facing away from the substrate SUB. The support layer includes a plurality of spaced support blocks PS, and the orthographic projection of the support blocks PS onto the substrate SUB is within the defined range of the orthographic projection of the planar portion PLN2-1 onto the substrate SUB. The support layer may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.

[0064] In some examples, the display substrate also includes an encapsulation layer disposed on the side of the support layer facing away from the substrate SUB. The encapsulation layer EPL covers the organic light-emitting diodes (OLEDs) and the pixel definition pattern to seal the OLEDs, thereby reducing or preventing degradation of the OLEDs caused by moisture and / or oxygen present in the environment. The encapsulation layer EPL can be a single-layer structure or a multi-layer structure comprising stacked inorganic and organic layers. For example, the encapsulation layer EPL may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer disposed sequentially.

[0065] Next, we will introduce the specific structure of each film layer between the first sub-planarization layer PLN1 and the substrate SUB.

[0066] Taking the 2T1C circuit as an example, referring to Figure 9, the pixel driving circuit PC in the driving circuit layer DL includes a driving thin-film transistor (TFT) Td, a switching thin-film transistor (TFT) Ts, and a storage capacitor Cst. The switching TFT Ts is connected to the gate line GL and the data line DL, and is configured to transmit a data signal received via the data line DL to the driving TFT Td according to a scan signal received via the gate line GL. The storage capacitor Cst is connected to the switching TFT Ts and the driving voltage line PL, and is configured to store a voltage corresponding to the difference between the voltage received from the switching TFT Ts and the driving voltage ELVDD supplied to the driving voltage line PL. The driving TFT Td is connected to the driving voltage line PL and the storage capacitor Cst, and can be used to control the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) based on the voltage value stored in the storage capacitor Cst. The OLED can emit light with a desired brightness using the driving current. The OLED can emit, for example, red, green, blue, or white light. In this configuration, the drain of the driving thin-film transistor (TFT) Td is connected to the anode (i.e., the first electrode) of the organic light-emitting diode (OLED).

[0067] In some examples, referring to FIG10, the driving circuit layer DL may include a semiconductor layer 10, a first gate insulating layer G11, a gate electrode layer G1, a second gate insulating layer G12, and a source / drain conductive layer SD1 disposed sequentially along the direction away from the substrate SUB.

[0068] The semiconductor layer 10 includes an active layer for driving thin-film transistors (TFTs) Td and switching thin-film transistors (TFTs) Ts. The active layer may include, for example, inorganic semiconductor materials (e.g., polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials.

[0069] The first gate insulating layer GI1 may cover the active layer. For example, the first gate insulating layer GI1 may fully cover the thickness of the active layer. The first gate insulating layer GI1 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first gate insulating layer GI1 may be formed as a single layer or multiple layers.

[0070] The gate electrode layer G1 includes the gate for driving the thin-film transistor TFT Td and switching the thin-film transistor TFT Ts, and the first plate of the storage capacitor Cst. The gate electrode layer can include, for example, metals, metal alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, the gate electrode layer can include gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The gate electrode can have a single layer or multiple layers.

[0071] The second gate insulating layer GI2 can cover the gate electrode and the first plate of the storage capacitor Cst. The second gate insulating layer GI2 can include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The second gate insulating layer GI2 can be formed as a single layer or multiple layers.

[0072] The source / drain conductive layer SD1 may include the source and drain electrodes of the driving thin-film transistor TFT Td and the switching thin-film transistor TFT Ts, as well as the first electrode of the storage capacitor Cst. The source / drain conductive layer SD1 may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, the source / drain conductive layer SD1 may be a single layer or multiple layers made of metal, such as Mo / Al / Mo or Ti / Al / Ti.

[0073] In some embodiments, continuing to refer to FIG10, the display substrate further includes an interlayer insulating layer ILD disposed between the source / drain conductive layer SD1 and the first sub-planarization layer PLN1, and a first conductive layer 20 disposed between the interlayer insulating layers ILD. The first conductive layer 20 includes a first transition electrode RX, which is connected to the drain of the driving thin-film transistor TFT Ts through a first via VIA1 penetrating the interlayer insulating layer ILD. The second sub-electrode 32 is connected to the first transition electrode RX through a second via VIA2 penetrating the planarization portion PLN2-1 and the first sub-planarization layer PLN1 in sequence. In this way, the driving thin-film transistor TFT Ts and the anode are electrically connected through the first transition electrode RX.

[0074] In some embodiments, continuing to refer to FIG10, the first conductive layer 20 further includes an auxiliary electrode FX, the orthographic projection of which lies on the substrate SUB within the defined range of the orthographic projection of the light-emitting layer EL on the substrate SUB. The auxiliary electrode FX can be a signal line connected to the source of a driving thin-film transistor (TFT) Ts, such as a driving voltage line PL. The auxiliary electrode FX can also be a signal line connected to the source of a switching thin-film transistor (TFT) Ts, such as a data line DL.

[0075] In some examples, the display substrate also includes a buffer layer (BFL) disposed between the semiconductor layer and the substrate SUB. The buffer layer BFL can prevent or reduce the diffusion of metal atoms and / or impurities from the substrate SUB into the semiconductor layer. For example, the buffer layer BFL may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.

[0076] Figure 11 is a top view of a display substrate provided in this disclosure. The display substrate includes multiple pixel units, each pixel unit comprising a first color pixel unit, a second color pixel unit, and a third color pixel unit, each emitting a different color. For example, the pixel arrangement of the display substrate of this disclosure will be described below using a green pixel unit G as the first color pixel unit, a red pixel unit R as the second color pixel unit, and a blue pixel unit B as the third color pixel unit.

[0077] Referring to Figure 11, a first pixel group PG1 and a second pixel group PG2 are arranged alternately along a first direction, containing multiple pixel units. The first pixel group PG1 includes multiple green pixel units G spaced apart along a second direction, and the second pixel group PG2 includes multiple red pixel units R and blue pixel units B arranged alternately along the second direction, with adjacent second pixel groups PG2 staggered. That is, the pixel unit arrangement of the first second pixel group PG2 is blue→red→blue→red→…, the pixel unit arrangement of the second second pixel group PG2 is red→blue→red→blue…, and so on. This arrangement ensures that the blue pixel units B and red pixel units R are evenly distributed, improving light uniformity.

[0078] Referring again to Figure 11, a third pixel group PG3 and a fourth pixel group PG4 are arranged alternately along a second direction, consisting of multiple pixel units. The third pixel group PG3 includes multiple green pixel units G spaced apart along a first direction, and the fourth pixel group PG4 includes multiple red pixel units R and blue pixel units B arranged alternately along the first direction, with adjacent fourth pixel groups PG4 staggered. That is, the pixel units of the first fourth pixel group PG4 are arranged in the order blue → red → blue → red → ..., the pixel units of the second fourth pixel group PG4 are arranged in the order red → blue → red → blue, ..., and so on. Here, the first direction can be a row direction, and the second direction can be a column direction.

[0079] In some examples, the distance between any two adjacent pixel units in the aforementioned pixel unit array is equal. That is, the distances between two adjacent green pixel units G in the first pixel group PG1, between two adjacent green pixel units G in the third pixel group PG3, between two adjacent blue pixel units B and red pixel unit R in the second pixel group PG2, and between two adjacent blue pixel units B and red pixel unit R in the fourth pixel group PG4 are all equal. This ensures a neat and aesthetically pleasing layout of the display substrate and facilitates uniform image display. Of course, the distance between pixel units can be designed differently based on the actual display effect and various display requirements. Specifically, the distance between a green pixel unit G and its nearest red pixel unit R can be 5µm to 30nm, the distance between a green pixel unit G and its nearest blue pixel unit B can be 5µm to 30nm, and the distance between a red pixel unit R and its nearest blue pixel unit B can also be 5µm to 30nm.

[0080] In some examples, the sizes of the green pixel unit G, red pixel unit R, and blue pixel unit B can all range from 2µm to 60nm. When the orthographic projection of the pixel unit onto the substrate SUB is square, this size refers to the side length of the square pixel unit. When the orthographic projection of the pixel unit onto the substrate SUB is circular, this size refers to the diameter of the circular pixel unit.

[0081] Based on the specific structure of the display substrate described above, this disclosure also provides a method for fabricating a display substrate, which includes steps S1 to S9. Referring to Figures 12a-12i, the fabrication method includes:

[0082] S1. Provide a substrate SUB, as shown in Figure 12a.

[0083] In some examples, step S1 may specifically include cleaning the substrate SUB using a standard cleaning process. The cleaning methods for the substrate SUB may include: alkaline cleaning, which involves immersing the substrate SUB in a solution containing sodium hydroxide or ammonium hydroxide, with a commonly used solution concentration of 5%–10%, to remove organic matter and metal ions from the substrate SUB surface; acidic cleaning, which involves immersing the substrate SUB in a solution containing hydrofluoric acid or hydrochloric acid, with a commonly used solution concentration of 10%–30%, to remove oxides and silica gel impurities from the substrate SUB surface; oxidative cleaning, which involves immersing the substrate SUB in a solution containing potassium hydroxide or hydrogen peroxide, with a commonly used solution concentration of 5%–10%, to remove carbon and metal elements from the substrate SUB surface; and ultrapure water cleaning, which involves immersing or spraying the substrate SUB in ultrapure water to remove fine particles from the substrate SUB surface.

[0084] S2. A driving circuit layer DL is formed on the substrate SUB1. The driving circuit layer DL may include a semiconductor layer, a first gate insulating layer G11, a gate electrode layer G1, a second gate insulating layer G12 and a source / drain conductive layer SD1 arranged sequentially along the direction away from the substrate SUB, as shown in FIG12b.

[0085] The semiconductor layer includes an active layer for driving thin-film transistors (TFTs) Td and switching thin-film transistors (TFTs). A first gate insulating layer GI1 covers the active layer. The gate electrode layer G1 includes the gate of the driving TFT Td and the switching TFT Ts, and the first electrode of the storage capacitor Cst. A second gate insulating layer GI2 covers the gate electrode and the first electrode of the storage capacitor Cst. The source-drain conductive layer SD1 may include the source and drain of the driving TFT Td and the switching TFT Ts, and the second electrode of the storage capacitor Cst.

[0086] S3. An interlayer insulating layer ILD is formed on the side of the source / drain conductive layer SD1 away from the substrate SUB, and a first through-hole VIA1 is formed on the interlayer insulating layer ILD, as shown in Figure 12c.

[0087] Specifically, an interlayer insulating layer (ILD) and a metal layer can be deposited sequentially using sputtering, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECRCVD). The metal layer is then patterned to form a pattern including a first transition electrode RX and an auxiliary electrode FX.

[0088] The patterning process can include forming a pattern, including a first transition electrode RX and an auxiliary electrode FX, on a metal layer using an etching process. The etching process can be either dry etching or wet etching. Dry etching involves exposing the metal layer surface to plasma generated in a gaseous state. The plasma then reacts physically or chemically with the metal layer through windows created in the photoresist, removing the exposed surface material. Dry etching can specifically include ion milling, plasma etching, and reactive ion etching. Wet etching involves immersing the metal layer in a chemical reagent or solution, allowing the portion of the film surface not masked by the resist to react chemically with the reagent and be removed. Compared to dry etching, wet etching is simpler to operate, requires less equipment, and is easier to mass-produce. However, dry etching significantly improves the anisotropy of the etching process, ensuring the accuracy of the pattern.

[0089] S4. A planarization layer is formed on the side of the layer where the first transfer electrode RX and the auxiliary electrode FX are located that is away from the substrate SUB, as shown in Figure 12d.

[0090] In some examples, the planarization layer includes a first sub-planarization layer PLN1 and a second sub-planarization layer PLN2 stacked together. The second sub-planarization layer PLN2 includes a plurality of planarization portions PLN2-1. The sidewalls of the planarization portions PLN2-1 form a first groove GRV with the surface of the first sub-planarization layer PLN1 on the side opposite to the substrate SUB.

[0091] In some examples, the first sub-planarization layer PLN1 and the second sub-planarization layer PLN2 can be deposited sequentially using the above deposition process, and then the second sub-planarization layer PLN2 can be processed by photolithography to form multiple planar portions PLN2-1. Alternatively, a thicker planarization layer can be deposited using the above deposition process, and then a first groove GRV that at least partially penetrates can be formed by photolithography. In other examples, the first sub-planarization layer PLN1 and the second sub-planarization layer PLN2 can be directly formed by 3D printing.

[0092] Taking the example of sequentially depositing two planarization layers and then forming a planarization portion PLN2-1 through photolithography, step S4 may include: sequentially forming a first planarization film and a second planarization film on the side of the layer where the first transition electrode RX and the auxiliary electrode FX are located away from the substrate SUB through a deposition process; then coating a layer of photoresist on the second planarization film; exposing the photoresist after masking it with a mask, causing the unmasked photoresist to undergo a chemical reaction; then washing away the unexposed photoresist with a chemical reagent, so that the photoresist has a pattern of the first groove GRV; and then etching the second planarization film through the above etching process to form a second sub-planarization layer PLN2 with the first groove.

[0093] S5. A second via VIA2 is formed through the planarization portion PLN2-1 and the first sub-planarization layer PLN1, so that the drain of the driving thin film transistor TFT Ts is exposed, and an anode is formed in the first groove GRV. The anode extends to the second via VIA2 and is electrically connected to the first transition electrode RX through the second via VIA2, as shown in FIG12e.

[0094] S6. A pixel defining layer PDL is formed on the side of the layer containing the first electrode away from the substrate SUB. The pixel defining layer PDL has multiple pixel openings OP, which expose at least a portion of the first electrode located within the first groove GRV, as shown in FIG12f.

[0095] In some examples, the pixel definition layer (PDL) may include organic or inorganic materials. Specifically, it may include organic insulating materials such as polyimide, polyphthalamide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic insulating materials such as silicon oxide or silicon nitride.

[0096] S7. An organic functional layer is formed on the side of the first electrode away from the substrate SUB. The organic functional layer may include a light-emitting layer EL, as shown in Figure 12g.

[0097] In some examples, the luminescent layer (EL) may include small molecule organic materials or polymeric organic materials, and may be fluorescent or phosphorescent materials, emitting red, green, blue, or white light. Furthermore, as needed, the organic functional layer may also include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, etc.

[0098] S8. A support layer is formed on the side of the flat portion PLN2-1 away from the substrate SUB. The support layer includes a plurality of support blocks PS, as shown in FIG12h. The orthogonal projection of the support block PS on the substrate SUB is within the defined range of the orthogonal projection of the flat portion PLN2-1 on the substrate SUB.

[0099] In some examples, the material of the support layer may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.

[0100] S9. An encapsulation layer EPL is formed on the side of the support layer that is away from the substrate SUB, as shown in Figure 12i.

[0101] In some examples, the material of the encapsulation layer EPL may include insulating materials such as silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), and polymer resins. Inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx) have high density, preventing the intrusion of water, oxygen, etc. The material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that blocks moisture, such as polymer resins, to planarize the surface of the display substrate and relieve stress in the first and second inorganic encapsulation layers. It may also include water-absorbing materials such as desiccants to absorb water, oxygen, and other substances that intrude into the interior.

[0102] This disclosure also provides a display panel, which includes the display substrate described in the above embodiments. The display panel can be used in a display device, which can be any device such as a mobile phone, tablet computer, laptop computer, e-book reader, game console, television, digital photo frame, navigator, etc., or any combination of electronic devices and hardware. The embodiments of this disclosure do not limit this.

[0103] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, comprising a substrate and a plurality of pixel units disposed on the substrate; each pixel unit comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit; wherein, A planarization layer is provided on the side of the pixel driving circuit away from the substrate, and the planarization layer has a plurality of first grooves; the first electrode of the light-emitting device is provided on the side of the planarization layer away from the substrate, and one first electrode of the light-emitting device covers the bottom and sidewall of the first groove. A pixel defining layer is provided on the side of the layer where the first electrode of each of the light-emitting devices is located, away from the substrate. The pixel defining layer has multiple pixel openings; The orthographic projection of one of the pixel openings onto the substrate lies within the defined range of the orthographic projection of the first groove onto the substrate.

2. The display substrate according to claim 1, wherein, The light-emitting layer of the light-emitting device is disposed on the side of the first electrode away from the substrate, and the light-emitting layer is located at the pixel opening; the shape of the light-emitting layer is different from the orthographic projection of the first groove on the substrate.

3. The display substrate according to claim 2, wherein, The distance between the light-emitting layer and the sidewall of the first groove is not equal at at least some locations.

4. The display substrate according to claim 1, wherein, The pixel defining layer includes a pixel barrier defining the plurality of pixel openings; the first electrode includes a first sub-electrode and a second sub-electrode that are electrically connected; the first sub-electrode covers the bottom of the first groove, and the second sub-electrode covers at least the sidewall of the first groove; The orthographic projection of the pixel barrier on the substrate covers the orthographic projection of the second sub-electrode on the substrate, and at least partially overlaps with the orthographic projection of the first sub-electrode on the substrate.

5. The display substrate according to claim 1, wherein, The planarization layer includes a first sub-planarization layer and a second sub-planarization layer stacked along a direction away from the substrate. The surface of the first sub-planarization layer facing away from the substrate is the first surface; the second sub-planarization layer includes a plurality of planar portions; the sidewalls of the four adjacent planar portions together with the first surface define the first groove.

6. The display substrate according to claim 5, wherein, The dihedral angle formed by the sidewall of the flat portion and the first surface is θ, where 20°≤θ≤80°.

7. The display substrate according to claim 5, wherein, The pixel defining layer is in contact with at least a portion of the first electrode; the maximum distance between the orthographic projection of the pixel defining layer on the first surface and the orthographic projection of the flat portion on the first surface is w, where 0um < w ≤ 3um.

8. The display substrate according to claim 5, wherein, The display substrate further includes an interlayer insulating layer disposed between the layer where the pixel driving circuit is located and the first sub-planarization layer, and a first conductive layer disposed between the interlayer insulating layer and the first sub-planarization layer. The first conductive layer includes a first transition electrode; The pixel driving circuit includes at least a driving thin-film transistor; the first transition electrode is connected to the drain of the driving thin-film transistor through a first via penetrating the interlayer insulating layer; the first electrode is connected to the first transition electrode through a second via penetrating the planarization portion and the first sub-planarization layer in sequence.

9. The display substrate according to claim 8, wherein, The first conductive layer further includes an auxiliary electrode; the orthogonal projection of the auxiliary electrode on the substrate is located within the defined range of the orthogonal projection of the light-emitting layer on the substrate.

10. The display substrate according to claim 1, wherein, It also includes a support layer disposed on the side of the pixel defining layer opposite to the substrate; the orthogonal projection of the support layer on the substrate is located within the defined range of the orthogonal projection of the pixel defining layer on the substrate.

11. The display substrate according to claim 1, wherein, The plurality of pixel units include a first color pixel unit, a second color pixel unit, and a third color pixel unit with different emission colors; The plurality of pixel units are divided into alternating first pixel groups and second pixel groups along a first direction, with adjacent second pixel groups staggered; the plurality of pixel units are divided into alternating third pixel groups and fourth pixel groups along a second direction, with adjacent fourth pixel groups staggered; the first direction intersects the second direction; The first pixel group includes a plurality of first color pixel units spaced apart along the second direction; the second pixel group includes a plurality of second color pixel units and the third color pixel units arranged alternately along the second direction; the third pixel group includes a plurality of first color pixel units spaced apart along the first direction; and the fourth pixel group includes a plurality of second color pixel units and the third color pixel units arranged alternately along the first direction.

12. The display panel according to claim 11, wherein, The spacing between two adjacent first color pixel units in the first pixel group, the spacing between adjacent second color pixel units and third color pixel units in the second pixel group, the spacing between two adjacent first color pixel units in the third pixel group, and the spacing between adjacent second color pixel units and third color pixel units in the fourth pixel group are all equal.

13. The display panel according to claim 11, wherein, The size of the first color pixel unit, the second color pixel unit, and the third color pixel unit are all 2µm to 60nm; The distance between the first color pixel unit and the nearest first color pixel unit is 5µm to 30nm; the distance between the first color pixel unit and the nearest third color pixel unit is 5µm to 30nm; the distance between the second color pixel unit and the nearest third color pixel unit is 5µm to 30nm.

14. The display substrate according to claim 2, wherein, The orthographic projection of the first groove on the substrate includes any one of square, rectangular, circular, triangular, or irregular shapes; the orthographic projection of the light-emitting unit on the substrate includes any one of square, rectangular, circular, triangular, or irregular shapes.

15. A method for preparing a display substrate as described in any one of claims 1-14, comprising: A substrate is provided on which a plurality of pixel driving circuits are formed; A planarization layer is formed on the side of the layer where the pixel driving circuit is located that is away from the substrate, and a plurality of first grooves are formed on the planarization layer; A first electrode for a plurality of light-emitting devices is formed on the side of the planarization layer opposite to the substrate. A first electrode of the light-emitting device covers the bottom and sidewalls of the first groove; A pixel defining layer is formed on the side of the layer where the first electrode of each of the light-emitting devices is located, away from the substrate. The pixel defining layer has multiple pixel openings; The orthographic projection of one of the pixel openings onto the substrate lies within the defined range of the orthographic projection of the first groove onto the substrate.

16. A display panel comprising a display substrate as claimed in any one of claims 1-14.

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