Method and apparatus for detecting stack overflow using physical memory protection function

Abstract

The present disclosure relates to a stack overflow detection method performed by a processor including a memory protection address register and a memory protection configuration register, and the method may comprise the steps of: detecting access to a first memory access address value located outside a stack area of a first execution unit on the basis of a first memory protection address register value of the first execution unit recorded in the memory protection address register; comparing the first memory access address value with a first memory protection address value of the first execution unit; and performing stack overflow detection on the basis of a result of comparing the first memory access address value with the first memory protection address value of the first execution unit.

Description

Method and device for detecting stack overflow using physical memory protection function

[0001] The present disclosure relates to a technique for efficiently detecting stack overflow in a memory-constrained environment.

[0002] The present invention is derived from research conducted as part of the Ministry of Science and ICT’s Artificial Intelligence Semiconductor SW Integrated Platform Technology Development (Project Unique No.: 1711198587, Project No.: RS-2023-00277060, Project Management Agency: Korea Institute of Information & Communication Technology Planning & Evaluation, Research Project Title: Open Edge AI Semiconductor Design and SW Platform Technology Development, Project Performing Agency: Altist Co., Ltd., Research Period: June 1, 2023 – December 31, 2027). Meanwhile, the Korean government has no proprietary interest in any aspect of the present invention.

[0003]

[0004] During the execution of a process, a specific memory area is allocated for each process, which includes a stack memory area. The stack memory area generally has a fixed size, and if access exceeds the pre-allocated stack area during process execution, a stack overflow occurs.

[0005] Conventionally, the use of guard pages has been widely employed to prevent stack overflows. However, in environments with limited memory capacity (e.g., embedded devices), utilizing guard pages requires the configuration of page table entries, which presents a problem in that it is difficult to prevent stack overflows in a memory-efficient manner.

[0006] Therefore, there is a demand in the industry for techniques to prevent stack overflow in memory-constrained environments.

[0007]

[0008] The present disclosure aims to provide a method for efficiently detecting stack overflow in environments where memory utilization is limited, such as embedded devices.

[0009] The problems that this disclosure aims to solve are not limited to those described above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below.

[0010]

[0011] A stack overflow detection method performed by a processor comprising a memory protection address register and a memory protection configuration register according to one embodiment of the present disclosure, the method may include: a step of detecting access to a first memory access address value outside the stack area of ​​the first execution unit based on a first memory protection address register value of the first execution unit recorded in the memory protection address register; a step of comparing the first memory access address value with the first memory protection address value of the first execution unit; and a step of performing stack overflow detection based on the result of comparison between the first memory access address value and the first memory protection address value of the first execution unit.

[0012] In addition, the first memory protection address register value of the first execution unit and the first memory protection address value may be characterized as being the stack end address value of the first execution unit.

[0013] Additionally, the step of comparing the first memory access address value and the first memory protection address value may be characterized by including the step of verifying the first memory protection address value recorded in the control block of the first execution unit.

[0014] In addition, the control block of the first execution unit may be characterized by including a plurality of memory protection address values.

[0015] In addition, the first memory protection address value may be characterized as being recorded with the highest priority within the control block of the first execution unit.

[0016] Additionally, the stack overflow detection method may further include the step of performing context switching from the first execution unit to the second execution unit; wherein the step of performing context switching comprises: the step of releasing the memory protection address register and the memory protection configuration register; the step of writing a first memory protection address value written in the control block of the second execution unit to the memory protection address register; and the step of writing a first memory protection configuration value written in the control block of the second execution unit to the memory protection configuration register.

[0017] In addition, the first memory protection configuration value of the second execution unit may be characterized by restricting read, write, and execute permissions for a memory address corresponding to the memory protection address value of the second execution unit.

[0018]

[0019] The stack overflow detection technique according to the present disclosure can efficiently detect the occurrence of a stack overflow by utilizing a Physical Memory Protection (PMP) function.

[0020] The effects according to the present disclosure are not limited to those described above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below.

[0021]

[0022] FIG. 1 is a conceptual diagram showing the configuration of a processor according to some embodiments of the present disclosure.

[0023] FIG. 2 is a block diagram showing the configuration of a memory protection entry according to some embodiments of the present disclosure.

[0024] FIG. 3 is a conceptual diagram showing memory protection configuration register values ​​for preventing stack overflow according to some embodiments of the present disclosure.

[0025] FIG. 4 is a flowchart illustrating the process of handling context switching in a stack overflow detection method according to some embodiments of the present disclosure.

[0026] FIG. 5 is a flowchart illustrating the process of a stack overflow detection device detecting a stack overflow according to some embodiments of the present disclosure.

[0027] FIG. 6 is a block diagram showing a stack overflow detection device of the present disclosure.

[0028]

[0029] Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the contents described in the attached drawings. However, the present invention is not limited or restricted by exemplary embodiments. Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall be used in a meaning that is commonly understood by those skilled in the art to which this disclosure belongs, but this may vary depending on the intent of those skilled in the art, case law, the emergence of new technology, etc.

[0030] Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise. In certain cases, terms have been selected at the applicant's discretion, and in such cases, their meanings will be described in detail in the relevant explanatory sections. Accordingly, terms used in this disclosure should be defined not merely by their names, but based on their meanings and the content throughout this disclosure.

[0031] Throughout this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Furthermore, the singular form used in this specification includes the plural form unless specifically stated otherwise. Additionally, the expression "at least one of a, b, and / or c" as used throughout this specification may encompass 'a alone', 'b alone', 'c alone', 'a and b', 'a and c', 'b and c', or 'a, b, and c all'.

[0032] Meanwhile, terms such as "first and / or second" used in this specification may be used to describe various components, but they are used solely for the purpose of distinguishing one component from another and are not intended to limit the scope to the components referred to by such terms. For example, without departing from the scope of the present invention, the first component may be named the second component, and the second component may also be named the first component.

[0033] Additionally, terms such as “…part,” “…module,” etc., as described in this specification refer to a unit that processes at least one function or operation, which may be implemented in hardware or software, or a combination of hardware and software. Furthermore, embodiments of this disclosure may be represented in this specification by functional block configurations and various processing steps. These functional blocks may be implemented by various numbers of hardware and / or software configurations that execute specific functions. For example, embodiments of this disclosure may employ integrated circuit configurations such as memory, processing, logic, look-up tables, etc., which can execute various functions under the control of one or more microprocessors or other control devices.

[0034] Similar to how the components disclosed herein may be executed as software programs or software elements, embodiments of the present disclosure may be implemented in programming or scripting languages ​​such as C, C++, Java, assembler, etc., including various algorithms implemented as combinations of data structures, processes, routines, or other programming configurations. Functional aspects may be implemented as algorithms executed on one or more processors. Additionally, the present embodiments may employ prior art for at least one of electronic configuration, signal processing, and data processing. Terms such as “mechanism,” “element,” “means,” and “configuration” may be used broadly and are not limited to mechanical and physical configurations. The above terms may include the meaning of a series of software processes (routines) in conjunction with a processor, etc.

[0035] Each block of the process flow diagrams attached to this specification and combinations of the flow diagrams may be executed by computer program instructions. Since these computer program instructions may be loaded into the processor of a general-purpose computer, a computer for special purposes, or other programmable data processing equipment, the instructions executed through the processor of the computer or other programmable data processing equipment create means for performing the functions described in the flow diagram block(s).

[0036] These computer program instructions may be stored in computer-available or computer-readable memory that can be directed toward a computer or other programmable data processing equipment to implement a function in a specific way, and the instructions stored in said computer-available or computer-readable memory may also produce a manufactured item containing instruction means that performs the function described in the flowchart block(s).

[0037] Since computer program instructions can be loaded onto a computer or other programmable data processing equipment, instructions that perform a series of operation steps on the computer or other programmable data processing equipment to create a process executed by the computer can also provide steps for executing the functions described in the flowchart block(s).

[0038] Additionally, each block may represent a module, segment, or part of code containing one or more executable instructions for executing a specified logical function(s). Furthermore, in some alternative execution examples, the functions mentioned in the blocks may occur out of order. For instance, two blocks described in succession may actually be executed substantially simultaneously, or the blocks may be executed in reverse order according to their corresponding functions.

[0039] The “electronic device” or “terminal” mentioned in this specification may be implemented as a computer or portable terminal capable of connecting to a server or other terminal via a network. Here, the computer includes, for example, a notebook, desktop, or laptop equipped with a web browser, and the portable terminal may include, for example, any type of handheld wireless communication device that ensures portability and mobility, such as a communication-based terminal like IMT (International Mobile Telecommunication), CDMA (Code Division Multiple Access), W-CDMA (W-Code Division Multiple Access), or LTE (Long Term Evolution), as well as a smartphone or tablet PC. Additionally, the “electronic device” or “terminal” mentioned in this specification may also include a processor, memory for storing and executing program data, permanent storage such as a disk drive, a communication port for communicating with an external device, and user interface devices such as a touch panel, a key, or a button.

[0040] In the present disclosure, methods implemented as software modules or algorithms may be stored on a computer-readable recording medium as computer-readable code or program instructions executable on a processor. The computer-readable recording medium may include magnetic storage media (e.g., ROM (read-only memory), RAM (random-access memory), floppy disks, hard disks, etc.) and optical reading media (e.g., CD-ROM, DVD (Digital Versatile Disc)). The computer-readable recording medium may be distributed and executed across networked computer systems.

[0041] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In describing the embodiments, technical details that are well known in the art to which the present invention pertains and are not directly related to the present invention will be omitted. This is to ensure that the essence of the present invention is conveyed more clearly without obscuring it by omitting unnecessary explanations. For the same reason, some components in the accompanying drawings may be exaggerated, omitted, or schematically depicted. Furthermore, the size of each component does not entirely reflect its actual size. Throughout this specification, the same reference numerals may refer to the same or corresponding components.

[0042]

[0043] FIG. 1 is a conceptual diagram showing the configuration of a processor according to some embodiments of the present disclosure.

[0044] Referring to FIG. 1, a processor (820) according to some embodiments of the present disclosure may include a register set (100).

[0045] In some embodiments, the register set (100) may be configured through one or more registers. Although only the memory protection configuration register (110) and / or memory protection address register (120) are shown in FIG. 1 within the register set (100), the register set (100) may include additional registers for performing functions of the processor (820).

[0046] In some embodiments, the register set (100) may enable the processor (820) to perform processing for the execution of a program, process, and / or thread by exchanging data and control commands with an arithmetic unit (821) and / or a control unit (822) included within the processor (820).

[0047] In some embodiments of the present disclosure, the memory protection configuration register (110) may be at least one register included in the register set (100). In one embodiment, the memory protection configuration register (110) may be a register for storing one or more authorization information for a memory address indicated by address information stored in the memory protection address register (120).

[0048] In one embodiment, the memory protection configuration register (110) may be composed of a plurality of bits representing information regarding read permission, write permission, execute permission, permission setting address range, and / or modification permission for a memory address indicated by the memory protection address register (120).

[0049] Referring again to FIG. 1, a register set (100) according to some embodiments of the present disclosure may include a memory protection address register (120).

[0050] In some embodiments, the memory protection address register (120) may be a register for storing data to represent a memory area that must be protected from a program, process and / or thread to prevent stack overflow.

[0051] In some embodiments, the memory protection address register (120) may store the starting address value of a memory region to be protected. For example, the memory protection address register (120) may store the ending address value of a stack region of a process and / or thread. In one embodiment, the memory protection address register (120) may store a value obtained by performing a pre-set operation on the memory address value according to the configuration of a specific microarchitecture. For example, the memory protection address register (120) may store a value obtained by shifting the end address of the process and / or thread stack region to the right by a pre-set value (e.g., 2).

[0052] Referring again to FIG. 1, the memory protection configuration register (110) and the memory protection address register (120) included in the register set (100) work together to control memory access rights, thereby detecting whether a process and / or thread accesses a memory area beyond the stack end area of ​​the process and / or thread, and thereby preventing a stack overflow.

[0053]

[0054] FIG. 2 is a block diagram showing the configuration of a memory protection entry according to some embodiments of the present disclosure.

[0055] Referring to FIG. 2, a control block (200) according to some embodiments of the present disclosure may include one or more memory protection entries. In one embodiment, the control block (200) shown in FIG. 2 may be a Process Control Block (PCB) or a Thread Control Block (TCB).

[0056] In some embodiments, one or more memory protection entries included in the control block (200) may have an order. For example, referring to FIG. 2, the first memory protection entry (210) may be a memory protection entry having a higher priority than the second memory protection entry (220). In one embodiment, the memory protection entry having a higher priority may be applied first during the execution of a process and / or thread. Preferably, the memory protection entry for preventing stack overflow according to the present disclosure (e.g., the memory protection configuration register value for preventing stack overflow and the memory protection address register value corresponding to the end of the stack) may be applied first.

[0057] Referring to FIG. 2, one or more memory protection entries may be sequentially written within the control block (200). In one embodiment, the first memory protection entry (210) may include a first memory protection configuration value (211) and a first memory protection address value (212), and the second memory protection entry (220) may include a second memory protection configuration value (221) and a second memory protection address value (222). In this case, the memory protection configuration value and the memory protection address value may be written to the memory protection configuration register and the memory protection address register within the processor of the process and / or thread associated with the control block.

[0058] In one embodiment, if the first memory protection entry (210) is a memory protection entry written with the highest priority within the control block (200), the first memory protection entry (210) may include a configuration value and an address value to prevent stack overflow.

[0059] Specific examples of configuration values ​​to prevent stack overflow are described later through Fig. 3.

[0060]

[0061] FIG. 3 is a conceptual diagram showing memory protection configuration register values ​​for preventing stack overflow according to some embodiments of the present disclosure.

[0062] Referring to FIG. 3, a memory protection configuration register (110) according to some embodiments of the present disclosure may include a read permission value (111), a write permission value (112), an execute permission value (113), an address usage information value (114), an unused value (115) and / or a modification permission value (116).

[0063] In some embodiments, the memory protection configuration register value (211a) according to the present disclosure can control the process and / or thread from accessing the memory area and detect a stack overflow by setting other values ​​to 0 in addition to the address usage information value (114), thereby restricting all read, write, and execute permissions for the memory area stored in the memory protection address register.

[0064] In some embodiments, the address usage information value (114) according to the present disclosure may be a value representing an address range where access rights are controlled from a memory address specified in a memory protection register. In one example, if the address usage information value (114) is 0, the memory protection according to the present disclosure may not be enabled. In another example, if the address usage information value (114) is binary 10, this may cause access rights restrictions to be applied up to a range of 4 bytes (2^2) from an address specified in a memory protection address register.

[0065]

[0066] FIG. 4 is a flowchart illustrating the process of handling context switching in a stack overflow detection method according to some embodiments of the present disclosure.

[0067] Referring to FIG. 4, a step (S110) in which thread context switching occurs from the first thread to the second thread can be performed.

[0068] In some embodiments, the processor may perform the step (S120) of disabling a memory protection entry of the first thread upon the occurrence of a thread context switch. In one embodiment, the step (S120) of disabling a memory protection entry may include releasing the values ​​of a memory protection configuration register and a memory protection address register written for the execution of the first thread.

[0069] In some embodiments, when the memory protection entry of the first thread is disabled through step (S120), the processor may perform step (S130) of checking the memory protection address of the second thread. As described above in FIGS. 1 to 3, the memory protection address of the second thread may include the end of the stack address. In this case, the memory protection address of the second thread may be a memory address value included in the memory protection address register value recorded at the very beginning and / or highest priority of the thread control block.

[0070] In some embodiments, the processor may perform the step (S140) of inputting the memory protection address of the second thread, identified through step (S130), into a memory protection address register. After the memory protection address register is input, the processor may perform the step (S150) of setting the memory protection configuration register of the second thread, and then perform the step (S160) of executing the second thread.

[0071] Although the context switching step is described based on threads throughout Fig. 4, the above description can also be performed based on processes, and obvious variations arising from technical differences between threads and processes should also be interpreted as being included in the description of Fig. 4.

[0072]

[0073] FIG. 5 is a flowchart illustrating the process of a stack overflow detection device detecting a stack overflow according to some embodiments of the present disclosure.

[0074] Referring to FIG. 5, a processor according to some embodiments of the present disclosure may perform the step (S210) of detecting a first memory access address access that extends beyond a stack area allocated to a first thread, based on a memory protection configuration register and a memory protection address register. For example, the first memory access address may include an address value greater than or equal to the stack end address value recorded in the memory protection address register.

[0075] When the processor detects access to the first memory access address in step (S210), it may perform step (S220) of causing a page fault for the first memory access address to occur in the Memory Management Unit (MMU). When a page fault for the first memory access address occurs in the Memory Management Unit through step (S220), the processor may perform an exception handling procedure through the operating system. For example, such an exception handling procedure may include the execution of a routine following the occurrence of an interrupt and / or trap.

[0076] In some embodiments, the processor may check the memory protection address of the first thread in the thread control block of the first thread after the exception handling procedure is performed through step (S230). In one example, the memory protection address of the first thread may include the end-of-stack address of the first thread. In another example, the memory protection address of the first thread may be written in the thread block with the highest priority.

[0077] In some embodiments, the processor may include a step (S250) of checking whether the first memory access address and the first thread memory protection address match after checking the first thread memory protection address through step (S240). In some embodiments, if the first memory access address and the first thread memory protection address do not match in step (S250) (S250, No), the processor may perform a step (S260) of performing a page fault handling operation because a stack overflow has not occurred. In another embodiment, if the first memory access address and the first thread memory protection address match in step (S250) (S250, Yes), the processor may determine that a stack overflow has occurred and perform a stack overflow detection operation (S270).

[0078] Although the stack overflow detection step based on threads has been described throughout Fig. 5, the above description can also be performed based on processes, and obvious variations arising from technical differences between threads and processes should also be interpreted as being included in the description of Fig. 5.

[0079]

[0080] FIG. 6 is a block diagram showing the configuration of a stack overflow detection device of the present disclosure.

[0081] The computing device (800) may include a memory (810), a processor (820), a communication unit (830), and an input / output interface (840), and as shown in FIG. 6, the computing device (800) may be configured to communicate information and / or data through a network using the communication unit (830).

[0082] The memory (810) may include any non-transient computer-readable recording medium. According to one embodiment, the memory (810) may include a permanent mass storage device such as random access memory (RAM), read-only memory (ROM), disk drive, solid state drive (SSD), flash memory, etc. As another example, a permanent mass storage device such as ROM, SSD, flash memory, disk drive, etc. may be included in the computing device (800) as a separate permanent storage device distinct from the memory. Additionally, an operating system and at least one program code may be stored in the memory (810).

[0083] These software components may be loaded from a computer-readable recording medium separate from the memory (810). This separate computer-readable recording medium may include a recording medium that can be directly connected to the computing device (800), for example, a computer-readable recording medium such as a floppy drive, disk, tape, DVD / CD-ROM drive, or memory card. As another example, the software components may be loaded into the memory (810) via a communication unit (830) rather than a computer-readable recording medium. For example, at least one program may be loaded into the memory (810) based on a computer program installed by files provided through the communication unit (830) by developers or a file distribution system that distributes installation files for applications.

[0084] The program described herein may include program instructions, data files, and data structures, either individually or in combination. The program may be designed and created using machine code or high-level language code. The program may be specifically designed to implement the invention described above, or it may be implemented using various functions or definitions that are known and available to those skilled in the art in the field of computer software. A program for implementing the invention described above may be recorded on a recording medium readable by a processor.

[0085] Memory can store a program that performs the aforementioned operation and the operation described below, and the processor can execute the program stored in memory. When there are multiple processors and memory, it is possible for them to be integrated on a single chip or to be provided in physically separate locations. Memory may include volatile memory such as S-RAM (Static Random Access Memory, S-RAM) and D-RAM (Dynamic Random Access Memory) for temporarily storing data. Additionally, memory may include non-volatile memory such as ROM (Read Only Memory), EPROM (Erasable Programmable Read Only Memory), and EEPROM (Electrically Erasable Programmable Read Only Memory) for long-term storage of control programs and control data.

[0086]

[0087] The processor (820) may be configured to process instructions of a computer program by performing basic arithmetic, logic, and input / output operations. Instructions may be provided to another user terminal (not shown) or another external system by memory (810) or communication unit (830).

[0088] The processor may include various logic circuits and arithmetic circuits, process data according to a program provided from memory, and generate control signals based on the processing results. In this case, the memory and the processor may each be implemented as separate chips. Alternatively, the memory and the processor may be implemented as a single chip.

[0089] The processor (820) may include one or more processors. In this case, the one or more processors may be homogeneous or heterogeneous processors. For example, the processor (820) may include heterogeneous processors such as a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU) and / or a neural processing unit (NPU). For convenience of explanation, one or more homogeneous or heterogeneous processors may be referred to as 'processors' within this specification.

[0090] The communication unit (830) may provide a configuration or function for a user terminal (not shown) and a computing device (800) to communicate with each other via a network, and may provide a configuration or function for the computing device (800) to communicate with an external system (e.g., a separate cloud system). For example, control signals, commands, data, etc. provided under the control of the processor (820) of the computing device (800) may be transmitted to the user terminal and / or the external system through the communication unit (830) and the network, and through the communication unit of the user terminal and / or the external system.

[0091] The wired communication unit may include various wired communication units such as a Local Area Network (LAN) module, a Wide Area Network (WAN) module, or a Value Added Network (VAN) module, as well as various cable communication units such as USB (Universal Serial Bus), HDMI (High Definition Multimedia Interface), DVI (Digital Visual Interface), RS-232 (recommended standard 232), power line communication, or POTS (plain old telephone service).

[0092] In addition to Wi-Fi modules and WiBro (Wireless broadband) modules, the wireless communication unit may include a wireless communication unit that supports various wireless communication methods such as GSM (global System for Mobile Communication), CDMA (Code Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), UMTS (universal mobile telecommunications system), TDMA (Time Division Multiple Access), LTE (Long Term Evolution), 4G, 5G, and 6G.

[0093] The wireless communication unit may include a wireless communication interface comprising an antenna and a transmitter that transmit a Wi-Fi signal. Additionally, the wireless communication unit may further include a Wi-Fi signal conversion module that modulates a digital control signal output from the control unit through the wireless communication interface into an analog wireless signal under the control of the control unit.

[0094] The wireless communication unit may include a wireless communication interface comprising an antenna and a receiver for receiving a Wi-Fi signal. Additionally, the wireless communication unit may further include a Wi-Fi signal conversion module for demodulating an analog wireless signal received through the wireless communication interface into a digital control signal.

[0095] The short-range communication unit is for short-range communication and can support short-range communication by using at least one of Bluetooth, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, and Wireless USB (Wireless Universal Serial Bus) technologies.

[0096] Additionally, the input / output interface (840) of the computing device (800) may be a means for interfacing with a device (not shown) for input or output that is connected to the computing device (800) or that the computing device (800) may include.

[0097] The input unit is for receiving information and data, including audio information (or signals), text, etc., from a network or a user, and may include at least one microphone and at least one of a user input unit. Data collected from the input unit may be analyzed and processed into a user control command.

[0098] The user input unit is intended to receive information from a user, and when information is input through the user input unit, the control unit can control the operation of the device to correspond to the input information. Such a user input unit may include a hardware physical key (e.g., a button, dome switch, jog wheel, jog switch, etc. located on at least one of the front, rear, and side of the device) and a software touch key. As an example, the touch key may consist of a virtual key, soft key, or visual key displayed on a touchscreen-type display unit through software processing, or may consist of a touch key placed on a part other than the touchscreen. Meanwhile, the virtual key or visual key may have various forms and may be displayed on the touchscreen, for example, as a graphic, text, icon, video, or a combination thereof.

[0099] In FIG. 6, the input / output interface (840) is shown as an element configured separately from the processor (820), but is not limited thereto, and the input / output interface (840) may be configured to be included in the processor (820). The computing device (800) may include more components than those in FIG. 6. However, there is no need to clearly illustrate most of the prior art components.

[0100] The processor (820) of the computing device (800) may be configured to manage, process, and / or store information and / or data received from a plurality of user terminals and / or a plurality of external systems.

[0101] The methods and / or various embodiments described above may be realized in digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the present disclosure may be executed by a data processing device, for example, one or more programmable processors and / or one or more computing devices, or may be implemented as a computer program stored on a computer-readable recording medium and / or a computer program stored on a computer-readable recording medium. The computer program described above may be written in any form of programming language, including a compiled language or an interpreted language, and may be distributed in any form, such as a standalone program, a module, a subroutine, etc. The computer program may be distributed through a single computing device, a plurality of computing devices connected through the same network, and / or a plurality of computing devices distributed to be connected through a plurality of different networks.

[0102] The methods and / or various embodiments described above may be performed by one or more processors configured to execute one or more computer programs that process, store, and / or manage any functions, functions, etc. by operating based on raw samples or generating output data. For example, the methods and / or various embodiments of the present disclosure may be performed by special-purpose logic circuits such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and an apparatus and / or system for performing the methods and / or embodiments of the present disclosure may be implemented as a special-purpose logic circuit such as an FPGA or an ASIC.

[0103] One or more processors executing a computer program may include one or more processors of a general-purpose or special-purpose microprocessor and / or any type of digital computing device. The processor may receive instructions and / or data from each of read-only memory and random access memory, or receive instructions and / or data from read-only memory and random access memory. In the present invention, components of a computing device performing the methods and / or embodiments may include one or more processors for executing instructions and one or more memory devices for storing instructions and / or data.

[0104] According to one embodiment, a computing device may exchange data with one or more mass storage devices for storing data. For example, the computing device may receive and / or receive data from a magnetic disc or an optical disc, and may transfer data to a magnetic disc or an optical disc. A computer-readable storage medium suitable for storing instructions and / or data associated with a computer program may include, but is not limited to, any form of non-volatile memory including semiconductor memory devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable PROM), and flash memory devices. For example, a computer-readable storage medium may include magnetic discs such as internal hard disks or removable disks, optical magnetic discs, CD-ROMs, and DVD-ROMs.

[0105] To provide interaction with a user, the computing device may include, but is not limited to, a display device for providing or displaying information to the user (e.g., CRT (Cathode Ray Tube), LCD (Liquid Crystal Display), etc.) and a pointing device (e.g., keyboard, mouse, trackball, etc.) on which the user can provide input and / or commands, etc. on the computing device. That is, the computing device may further include any other type of device for providing interaction with the user. For example, the computing device may provide any form of sensory feedback to the user for interaction with the user, including visual feedback, auditory feedback and / or tactile feedback. In this regard, the user may provide input to the computing device through various gestures such as visual, vocal, and motion.

[0106] In the present invention, various embodiments may be implemented in a computing system comprising backend components (e.g., data servers), middleware components (e.g., application servers), and / or frontend components. In this case, the components may be interconnected by any form or medium of digital data communication, such as a communication network. For example, the communication network may include a Local Area Network (LAN), a Wide Area Network (WAN), etc.

[0107] A computing device based on the exemplary embodiments described herein may be implemented using hardware and / or software configured to interact with a user, including a user device, a user interface (UI) device, a user terminal, or a client device. For example, the computing device may include a portable computing device such as a laptop computer. Additionally or alternatively, the computing device may include, but is not limited to, Personal Digital Assistants (PDAs), tablet PCs, game consoles, wearable devices, Internet of Things (IoT) devices, Virtual Reality (VR) devices, Augmented Reality (AR) devices, etc. The computing device may further include other types of devices configured to interact with a user. Additionally, the computing device may include a portable communication device suitable for wireless communication over a network such as a mobile communication network (e.g., a mobile phone, a smartphone, a wireless cellular phone, etc.). A computing device may be configured to communicate wirelessly with a network server using wireless communication technologies and / or protocols such as radio frequency (RF), microwave frequency (MWF) and / or infrared frequency (IRF).

[0108] In an embodiment according to the present disclosure, functions related to artificial intelligence may be implemented through a processor and memory. In this case, the processor may be any one of a general-purpose processor such as a CPU (Center Processing Unit), AP (Application Processor), DSP (Digital Signal Processor), a graphics-dedicated processor such as a GPU (Graphic Processing Unit) or VPU (Vision Processing Unit), and an artificial intelligence-dedicated processor such as an NPU (Neural Network Processing Unit). The processor may process raw samples according to predefined operation rules or artificial intelligence models stored in memory. Alternatively, if the processor is an artificial intelligence-dedicated processor, the artificial intelligence-dedicated processor may be designed with a hardware structure specialized for processing a specific artificial intelligence model. In some embodiments according to the present disclosure, functions related to artificial intelligence may be implemented through a plurality of processors.

[0109]

[0110] The above descriptions are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present disclosure will include technologies that can be easily modified and implemented using the embodiments described above. Accordingly, the scope of the present disclosure should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of the present disclosure.

Claims

1. A stack overflow detection method performed by a processor comprising: a memory protection address register; and a memory protection configuration register; wherein A step of detecting access to a first memory access address value outside the stack area of ​​the first execution unit based on the value of the first memory protection address register of the first execution unit recorded in the memory protection address register; A step of comparing the first memory access address value and the first memory protection address value of the first execution unit; and A step of performing stack overflow detection based on the result of comparing the first memory access address value and the first memory protection address value of the first execution unit; Stack Overflow Detection Method 2. In Paragraph 1, The first memory protection address register value of the first execution unit and the first memory protection address value are Characterized by being the stack end address value of the first execution unit, Stack Overflow Detection Method 3. In Paragraph 2, The step of comparing the first memory access address value and the first memory protection address value is Characterized by including the step of verifying the first memory protection address value recorded in the control block of the first execution unit. Stack Overflow Detection Method 4. In Paragraph 3, The control block of the first execution unit above is, Characterized by including multiple memory protection address values, Stack Overflow Detection Method 5. In Paragraph 4, The above first memory protection address value is, Characterized by being recorded with the highest priority within the control block of the first execution unit, Stack Overflow Detection Method 6. In Paragraph 1, The above stack overflow detection method is, The method further includes the step of performing context switching from the first execution unit to the second execution unit. The step of performing the above context switching is, A step of releasing the memory protection address register and the memory protection configuration register; A step of writing a first memory protection address value recorded in the control block of the second execution unit to the memory protection address register; and Characterized by including the step of recording a first memory protection configuration value recorded in the control block of the second execution unit into the memory protection configuration register. Stack Overflow Detection Method 7. In Paragraph 6, The first memory protection configuration value of the second execution unit above is, Characterized by restricting read, write, and execute permissions for a memory address corresponding to the memory protection address value of the second execution unit. Stack Overflow Detection Method 8. A computing device comprising a processor that performs a stack overflow detection method according to any one of claims 1 to 7.

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