Array substrate, display panel and near-eye display device
Patent Information
- Application Number
- PCT/CN2025/078890
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-08-27
Smart Images
Figure CN2025078890_27082026_PF_FP_ABST
Abstract
Description
Array substrate, display panel and near-eye display device Technical Field
[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate, a display panel, and a near-eye display device. Background Technology
[0002] With the continuous development of display technology, display panels have been widely used, and people's requirements for display panels are getting higher and higher. Among them, high pixel density (Pixels Per Inch; PPI) is an important development direction for display panels. Common display panels can include liquid crystal display panels (LCD) and organic light-emitting diode display panels (OLED). Thanks to the simpler pixel circuit structure of liquid crystal display panels (which can contain fewer thin-film transistors and capacitors), liquid crystal display panels have an advantage in ultra-high pixel density (such as greater than or equal to 1000 PPI). Summary of the Invention
[0003] On one hand, an array substrate is provided. The array substrate includes a substrate, a first light-shielding layer, a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a second light-shielding layer, and a first via. The first light-shielding layer is disposed on one side of the substrate and includes a first light-shielding portion. The semiconductor layer is disposed on the side of the first light-shielding layer away from the substrate and includes a semiconductor pattern. The semiconductor pattern includes a channel region and two conductor regions located on both sides of the channel region. The first insulating layer is disposed on the side of the semiconductor layer away from the substrate. The first conductive layer is disposed on the side of the first insulating layer away from the substrate and includes multiple gate lines. The second insulating layer is disposed on the side of the first conductive layer away from the substrate. The first via at least penetrates the second insulating layer and exposes the conductor regions. The second conductive layer is disposed on the side of the second insulating layer away from the substrate and includes multiple data lines, the data lines being electrically connected to the conductor regions through the first via. The second light-shielding layer is disposed on the side of the second conductive layer away from the substrate and includes a second light-shielding portion. The multiple gate lines and the multiple data lines intersect to define multiple pixel regions. In the orthographic projection of the first light-shielding portion, the second light-shielding portion, and the first via on the substrate, the first light-shielding portion and the first via at least partially overlap, the second light-shielding portion and the first via at least partially overlap, the first light-shielding portion and the second light-shielding portion together form a first region, the first region covers the first via; the second light-shielding portion covers at least one convex corner of the first light-shielding portion, and the number of convex corners formed in the first region within a pixel area is less than 4.
[0004] In some embodiments, in the orthographic projections of the first light-shielding portion, the second light-shielding portion, and the first via on the substrate, the center lines of the first light-shielding portion and the second light-shielding portion in the first direction are respectively located on both sides of the center line of the first via in the first direction. The first direction is the extension direction of the gate line. The first light-shielding portion includes a first edge and a second edge disposed opposite to each other along the first direction. The orthographic projection of the second light-shielding portion on the substrate at least partially coincides with the orthographic projection of the first edge on the substrate, covers the orthographic projection of the convex corner connected to the first edge on the substrate, and does not coincide with the orthographic projection of the second edge on the substrate.
[0005] In some embodiments, the first light-shielding layer further includes a plurality of third light-shielding portions, which extend along the first direction and are spaced apart along a second direction. The second direction intersects the first direction. The first light-shielding portion is located between two adjacent third light-shielding portions, and a first end of the first light-shielding portion along the second direction is connected to the third light-shielding portion, while the second end is a free end.
[0006] In some embodiments, the second light-shielding layer further includes a plurality of fourth light-shielding portions, which extend along the first direction and are spaced apart along the second direction. The second light-shielding portion is located between two adjacent fourth light-shielding portions, and a third end of the second light-shielding portion along the second direction is connected to a fourth light-shielding portion, with the fourth end being a free end. The orthographic projections of the first end and the third end onto the substrate are respectively located on opposite sides along the second direction of the orthographic projection of the first via onto the substrate.
[0007] In some embodiments, the first light-shielding layer further includes a plurality of third light-shielding portions, which extend along the first direction and are spaced apart along a second direction; the second direction intersects the first direction. The first light-shielding portion is located between two adjacent second light-shielding portions, and both ends of the first light-shielding portion along the second direction are spaced apart from the third light-shielding portions. The orthographic projection of the second light-shielding portion on the substrate covers the orthographic projection of the first edge on the substrate.
[0008] In some embodiments, the second light-shielding layer further includes a plurality of fourth light-shielding portions, which extend along the first direction and are spaced apart along the second direction. The second light-shielding portions are located between two adjacent fourth light-shielding portions, and their two ends along the second direction are respectively connected to the fourth light-shielding portions.
[0009] In some embodiments, the radial dimension of the first via is greater than the line width of the data line. In the orthographic projection of the first light-shielding portion and the first via onto the substrate, one end of the first via along the first direction is located within the range of the first light-shielding portion and has a first gap with the second edge, while the other end is located outside the range of the first light-shielding portion.
[0010] In some embodiments, at least one end of the first light-shielding portion along the second direction is a free end, and the orthographic projection of the free end of the first light-shielding portion on the substrate has a second interval with the orthographic projection of the first via on the substrate, the second interval being equal to the first interval.
[0011] In some embodiments, the first interval is D1, and D1 satisfies: Wherein, A1 is the alignment deviation between the first via and the first light-shielding layer, A2 is the single-sided dimensional process fluctuation of the first light-shielding layer, and B is the single-sided dimensional process fluctuation of the first via.
[0012] In some embodiments, the radial dimension of the first via is greater than the line width of the data line. The second light-shielding portion includes a third edge and a fourth edge disposed opposite to each other along the first direction, the third edge being located on the side of the fourth edge away from the second edge. In the orthographic projection of the second light-shielding portion and the first via onto the substrate, one end of the first via along the first direction is located within the range of the second light-shielding portion and has a third gap with the third edge, while the other end is located outside the range of the second light-shielding portion.
[0013] In some embodiments, one end of the second light-shielding portion along the second direction is a free end, and the orthographic projection of the free end of the second light-shielding portion on the substrate has a fourth interval between it and the orthographic projection of the first via on the substrate; the fourth interval is equal to the third interval.
[0014] In some embodiments, the third interval is D2, where D2 satisfies: Wherein, C1 is the alignment deviation between the first via and the second light-shielding layer, C2 is the single-sided dimensional process fluctuation of the second light-shielding layer, and B is the single-sided dimensional process fluctuation of the first via.
[0015] In some embodiments, the dimension of the first light-shielding portion along the first direction is equal to the dimension of the second light-shielding portion along the first direction.
[0016] In some embodiments, the data line includes a plurality of alternately connected first extension segments and a plurality of second extension segments; the plurality of first extension segments all extend along a first direction and are spaced apart along a second direction; the plurality of second extension segments all extend along the second direction and are alternately connected to the two ends of the first extension segments along the first direction. The first region covers the orthographic projection of the second extension segments onto the substrate.
[0017] In some embodiments, the extending direction of the semiconductor pattern forms an angle with the first direction, and the orthographic projection of the semiconductor pattern on the substrate passes through the orthographic projection of the gate line on the substrate; the two conductor regions of the semiconductor pattern are respectively located in two different pixel regions. The orthographic projection of the channel region on the substrate at least partially coincides with the orthographic projections of the gate line, the data line, the first light-shielding layer, and the second light-shielding layer on the substrate.
[0018] In some embodiments, the first light-shielding layer further includes a third light-shielding portion; the orthographic projection of the channel region on the substrate at least partially coincides with the orthographic projection of the third light-shielding portion on the substrate. The second light-shielding layer further includes a fourth light-shielding portion; the orthographic projection of the channel region on the substrate at least partially coincides with the orthographic projection of the fourth light-shielding portion on the substrate.
[0019] In some embodiments, the array substrate further includes a common electrode layer. The common electrode layer is disposed on the side of the second light-shielding layer near the substrate and in contact with the second light-shielding layer. The common electrode layer includes a plurality of openings. Each pixel region includes at least one of the openings, the openings at least partially overlapping with the fourth light-shielding portion, and the orthographic projection of the openings onto the substrate at least partially overlapping with the third light-shielding portion.
[0020] On the other hand, a display panel is provided. The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate as described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is disposed between the array substrate and the color filter substrate.
[0021] In another aspect, a near-eye display device is provided. The near-eye display device includes the aforementioned display panel and driving circuit board. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0023] Figure 1 is a structural diagram of a display device according to some embodiments;
[0024] Figure 2 is a structural diagram of a display device according to some embodiments;
[0025] Figure 3A is a cross-sectional structural diagram of an array substrate according to some embodiments;
[0026] Figure 3B is another cross-sectional view of the array substrate according to some embodiments;
[0027] Figure 4A is a plan view of the first light-shielding layer according to some embodiments;
[0028] Figure 4B is a planar structural diagram of a semiconductor layer according to some embodiments;
[0029] Figure 4C is a planar structural diagram of the first conductive layer according to some embodiments;
[0030] Figure 4D is a planar structural diagram of the second conductive layer according to some embodiments;
[0031] Figure 4E is a partial structural diagram of the first light-shielding layer to the second conductive layer according to some embodiments;
[0032] Figure 4F is a planar structural diagram of the first electrode layer according to some embodiments;
[0033] Figure 4G is a planar structural diagram of the second electrode layer according to some embodiments;
[0034] Figure 4H is a planar structural diagram of the third electrode layer according to some embodiments;
[0035] Figure 4I is a planar structural diagram of the common electrode layer according to some embodiments;
[0036] Figure 4J is a plan view of the second light-shielding layer according to some embodiments;
[0037] Figure 4K is a planar structural diagram of an array substrate according to some embodiments;
[0038] Figure 5 is a scanning electron microscope (SEM) image of the second signal line and the first via according to some embodiments;
[0039] Figure 6 is a structural diagram of the first light-shielding layer and data lines of the array substrate in the related technology;
[0040] Figure 7 is a scanning electron microscope (SEM) image of a rectangular light-shielding block according to some embodiments;
[0041] Figure 8 is a structural diagram of a first light-shielding layer, a second conductive layer, and a third light-shielding layer according to some embodiments;
[0042] Figure 9 is another structural diagram of the first light-shielding layer, the second conductive layer, and the third light-shielding layer according to some embodiments;
[0043] Figure 10A is a structural diagram of the first light-shielding layer and the semiconductor layer according to some embodiments;
[0044] Figure 10B is a structural diagram of the second light-shielding layer and the semiconductor layer according to some embodiments;
[0045] Figure 10C is a structural diagram of a first light-shielding layer, a second light-shielding layer, and a common electrode layer according to some embodiments. Detailed Implementation
[0046] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0048] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.
[0049] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
[0050] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.
[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0052] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.
[0053] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
[0054] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0055] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.
[0056] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0057] As used herein, “approximately” or “about” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0058] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
[0059] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0060] Referring to FIG1, an embodiment of the present disclosure provides a display device, the display device 1000 being a product having image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.
[0061] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.
[0062] For example, the aforementioned display device can be a near-eye display device, which can include, but is not limited to, AR devices, VR devices, and MR devices. Near-eye display devices, in particular, have higher requirements for pixel density; for instance, their pixel density is typically greater than 1000 PPI.
[0063] In some embodiments, the display device 1000 includes a display panel 1100 and a driving circuit board. The driving circuit board may include, for example, a timing controller (TCON), a DC / DC power management chip, and an adjustable resistor voltage divider circuit (generating Vcom), etc. The driving circuit board may also include other circuit structures, which will not be listed here. The driving circuit board is electrically connected to the display panel 1100 and is used to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to display images. In addition, the display device 1000 may also include a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to perform various functions such as touch control, photography, video recording, or fingerprint recognition; specific limitations are not specified here.
[0064] In some embodiments, the display device 1000 described above may be a liquid crystal display (LCD). Referring to FIG2, the display device 1000 may further include a backlight module 1200 disposed on the backlight side of the display panel 1100. Exemplarily, the backlight module 1200 may be a direct-lit backlight module or an edge-lit backlight module, etc., and the backlight module 1200 is used to provide a light source for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, and the display panel 1100 can adjust the amount of light passing through each sub-pixel, thereby enabling the plurality of sub-pixels to display the same or different gray levels to achieve the purpose of image display.
[0065] Referring again to Figure 2, when the display panel 1100 is a liquid crystal display panel, the display panel 1100 may include an array substrate 100 and a color filter substrate 200 disposed opposite each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 can filter the light passing through it. One sub-pixel can emit light of one color (such as red, green, or blue), and multiple sub-pixels can emit light of the same or different colors, thereby enabling the display panel 1100 to achieve color display. Of course, the structure of the display panel 1100 is not limited to this. The display panel 1100 may also include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 200 near the liquid crystal layer 300, etc.
[0066] In some embodiments, referring to Figures 3A and 3B, the array substrate 100 may include a substrate 101, a first light-shielding layer 10, a semiconductor layer 20, a first insulating layer GI, a first conductive layer 30, a second insulating layer ILD, a second conductive layer 40, and a second light-shielding layer 50. The first light-shielding layer 10 is disposed on one side of the substrate 101, the semiconductor layer 20 is disposed on the side of the first light-shielding layer 10 away from the substrate 101, the first insulating layer GI is disposed on the side of the semiconductor layer 20 away from the substrate 101, the first conductive layer 30 is disposed on the side of the first insulating layer GI away from the substrate 101, the second insulating layer ILD is disposed on the side of the second conductive layer 40 away from the substrate 101, and the second light-shielding layer 50 is disposed on the side of the second conductive layer 40 away from the substrate 101. That is, the first light-shielding layer 10, the semiconductor layer 20, the first insulating layer GI, the first conductive layer 30, the second insulating layer ILD, the second conductive layer 40, and the second light-shielding layer 50 are arranged sequentially in a direction away from the substrate 101.
[0067] In some embodiments, referring to FIG4B, the semiconductor layer 20 includes a semiconductor pattern 21, which includes a channel region 211 and a conductor region 212. The conductor region 212 may include, for example, a source contact region and a drain contact region located on both sides of the channel region 211 and separated by the channel region 211.
[0068] Exemplarily, the material of the semiconductor layer 20 may include metal oxide materials and / or metal oxide nitride materials. Metal oxide materials include, but are not limited to, indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. Metal oxide nitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. The material of the semiconductor layer 20 can be amorphous, partially crystalline, single-crystal or polycrystalline, and can also be a single-layer or multi-layer structure.
[0069] In this design, both the channel region and the conductor region can be made of the same semiconductor material. The conductor region differs from the channel region in that it undergoes a process to make it more conductive (a conductorization process), which includes, but is not limited to, doping and annealing processes. The conductivity of the conductor region differs from that of the channel region. For example, the channel region can comprise a semiconductor material, and the conductor region can comprise a doped semiconductor material. Thus, the conductor region can form a conductor, and the channel region can form a semiconductor.
[0070] As shown in Figure 4C, the first conductive layer 30 includes a plurality of gate lines 31. For example, the plurality of gate lines 31 extend along a first direction X and are spaced apart along a second direction Y.
[0071] In some embodiments, as shown in FIG3A, the first conductive layer 30 may consist only of a metallic material. Alternatively, referring to FIG3B, in other embodiments, the first conductive layer 30 may include a first material layer 301 and a second material layer 302 stacked together. The material of the first material layer 301 may include a transparent conductive material, and the material of the second material layer 302 may include a metallic material. For example, the transparent conductive material may include, for instance, indium tin oxide (ITO). The metallic material may include a single metallic material or may include a stack of metals, such as one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys. Metallic multilayer structures can include titanium-aluminum-titanium (Ti / Al / Ti) multilayer structures, molybdenum-aluminum (Mo / Al) multilayer structures, molybdenum-aluminum-molybdenum (Mo / Al / Mo) multilayer structures, molybdenum-niobium-titanium (MoNb / Ti) multilayer structures, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) multilayer structures, molybdenum-niobium-copper (MoNb / Cu) multilayer structures, molybdenum-nickel-titanium-copper (MTD / Cu) multilayer structures, and molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / C) multilayer structures. The following are some of the following stacked structures, or combinations thereof: molybdenum-nickel-titanium (Mo / MTD) stacked structure, molybdenum-titanium-copper (MoTi / Cu / MTD) stacked structure, molybdenum-titanium-copper (MoTi / Cu / MTD) stacked structure, molybdenum-titanium-copper-molybdenum-titanium (MoTi / Cu / MoTi) stacked structure, molybdenum-neodymium-copper stacked structure, MoNb-copper-MoNb stacked structure, and AlNb-molybdenum-AlNd stacked structure.
[0072] Referring to Figure 4D, the second conductive layer 40 includes multiple data lines 41. The multiple data lines 41 extend generally along the second direction Y and are spaced apart along the first direction X.
[0073] In some embodiments, the data line 41 can be a broken line, as shown in FIG4D. The data line 41 includes a plurality of alternating first extension segments 43 and a plurality of second extension segments 44. The plurality of first extension segments 43 extend along a first direction X and are spaced apart along a second direction Y; the plurality of second extension segments 44 extend along the second direction Y and are alternately connected to the two ends of the first extension segments 43 along the first direction X. For example, two second extension segments 44 are respectively connected to the two ends of the same first extension segment 43 along the first direction X. Alternatively, in some embodiments, the data line 41 can also be a straight line, extending along the second direction Y. This disclosure uses a broken line as an example for illustrative purposes, but the embodiments of this disclosure are not limited thereto.
[0074] Referring to Figure 4E, multiple gate lines 31 and multiple data lines 41 intersect to define multiple pixel areas 102. The orthographic projections of the multiple gate lines 31 on the substrate 101 and the orthographic projections of the multiple data lines 41 on the substrate 101 intersect to form a grid structure, and one grid defines one pixel area 102.
[0075] As shown in Figure 3A, the array substrate 100 also includes a first via V1, which penetrates at least the second insulating layer ILD and exposes the conductor region of the semiconductor pattern 21. The data line DL can be electrically connected to the conductor region of the semiconductor pattern 21 through the first via V1.
[0076] Exemplarily, the first insulating layer GI can extend substantially across the entire array substrate, in which case the first insulating layer GI covers at least a portion of the conductive region of the semiconductor pattern, and the first via V1 also penetrates the first insulating layer GI (as shown in FIG3A). Alternatively, in other examples, the orthographic projection of the first insulating layer GI onto the substrate 101 can substantially coincide with the orthographic projection of the first conductive layer 30 onto the substrate 101. For example, the fabrication process of the array substrate may include: after the formation of the first conductive layer 30, etching the first insulating layer GI using the first conductive layer 30 as a mask; in this case, the first insulating layer GI does not cover the conductive region of the semiconductor pattern 21, and the first via V1 only penetrates the second insulating layer ILD. Referring to FIG4D and FIG5, the data line 41 is conformal at the first via V1, that is, the shape of the data line 41 is the same as the shape of the first via V1, for example, the data line 41 will cover at least a portion of the sidewall of the first via V1. As the pixel density of the array substrate increases, the size of each structure on the array substrate (including but not limited to data lines, gate lines, and the second light-shielding part) becomes smaller and smaller. Part of the first via V1 is located within the pixel area 102, or the edge of the first via V1 is adjacent to the edge of the pixel area 102. As a result, the light leakage problem of the display panel at the first via V1 becomes more and more serious.
[0077] To reduce light leakage at the first via, as shown in Figure 6, related technologies involve setting multiple light-shielding blocks 501 in the first light-shielding layer of the array substrate. For example, one light-shielding block 501 is provided for each first via V1. The light-shielding block 501 is typically rectangular. However, as shown in Figure 7, the inventors discovered that the shape of the light-shielding block 501 is limited by the metal processing technology, resulting in the actual fabricated light-shielding block 501 not being a regular rectangle, but rather having rounded corners 502 at all four corners (the edges of the corners are curved). Referring also to Figures 6 and 7, based on the structure of the light-shielding block 501, four rounded corners 502 are formed around the periphery of each pixel area 102. Furthermore, the light-shielding block 501 needs to cover at least the first via V1, therefore the size of the light-shielding block 501 is typically large. For example, the size of the light-shielding block 501 in the first direction X is usually larger than the size of the portion of the second light-shielding layer 50 used to cover the data line 41 in the first direction X. This ensures that the rounded corner 502 is not blocked by the film layer (such as the second light-shielding layer 50) on the side of the first light-shielding layer away from the substrate 101. The light from the backlight module entering the array substrate is usually linearly polarized after passing through the polarizer. This linearly polarized light diffracts at the rounded corner 502 and then partially exits, causing light leakage at the rounded corner 502, which in turn leads to a decrease in the contrast of the display panel.
[0078] Referring to Figures 4A, 4J, and 8, Figure 8 only shows a partial structure of the first light-shielding layer, the second conductive layer, and the second light-shielding layer in the array substrate 100. To address the aforementioned technical problems, the array substrate 100 provided in the embodiments of this disclosure includes a first light-shielding layer 10 comprising a first light-shielding portion 11 (as shown in Figure 4A), and a second light-shielding layer 50 comprising a second light-shielding portion 51 (as shown in Figure 4J). As shown in Figure 8, in the orthographic projections of the first light-shielding portion 11, the second light-shielding portion 51, and the first via V1 onto the substrate 101, the first light-shielding portion 11 at least partially overlaps with the first via V1, and the second light-shielding portion 51 at least partially overlaps with the first via V1. That is, the first light-shielding portion 11 and the second light-shielding portion 51 can respectively block at least a portion of the first via V1. The first light-shielding portion 11 and the second light-shielding portion 51 together constitute a first region S, which includes the orthographic projections of the first light-shielding portion 11 and the second light-shielding portion 51 onto the substrate 101. The first region S covers the first via V1, so that the first light-shielding part 11 and the second light-shielding part 51 can work together to block the first via V1, reducing light leakage at the first via V1. The second light-shielding part 51 covers at least one convex corner of the first light-shielding part 11 (hereinafter referred to as the first convex corner 12), that is, the second light-shielding part 51 can block at least one first convex corner 12 of the first light-shielding part 11; the first convex corner 12 is a rounded corner extending along an arc. In this way, light rays incident on the at least one first convex corner 12 will be diffracted and blocked by the second light-shielding part 51, thereby reducing the risk of light leakage at the at least one first convex corner 12. Furthermore, within a pixel area 102, the number of convex corners formed by the first region S (hereinafter referred to as the third convex corner S1) is less than 4. Thus, compared with the prior art, the number of third convex corners S1 within a pixel area 102 can be reduced, thereby reducing the number of light leakage points within the pixel area 102, reducing the risk of light leakage at the edge of the pixel area 102 and the area of the light leakage region, thereby improving the contrast of the display panel.
[0079] In embodiments of this disclosure, as shown in FIG8, a "convex corner" refers to a convex corner of a polygon. The two edges forming a "convex corner" can form a corner less than 180° within area A, such as the first convex corner 12 formed by the first light-shielding part 11 and the second convex corner 52 formed by the second light-shielding part 51 in FIG8. Corresponding to a "convex corner," the first light-shielding part 11, the second light-shielding part 51, or the first region S can also form a concave corner. A "concave corner" refers to a concave corner of a polygon. The two edges forming a "concave corner" can form a corner greater than 180° within area A, such as the concave corner S2 in FIG8. The third convex corner S1 formed by the first region S may include the first convex corner 12 formed by the first light-shielding part 11 and not obscured by the second light-shielding part 51, and the second convex corner 52 formed by the second light-shielding part 51 and not obscured by the first light-shielding part 11. For example, in FIG8, the first region S forms two third convex corners S1, including a first convex corner 12 and a second convex corner 52. Furthermore, all the "convex corners" described in the embodiments of this disclosure can be rounded corners in the actual structure of the array substrate.
[0080] Referring to Figure 3A, the array substrate may further include a thin-film transistor (TFT) T1, which includes a semiconductor pattern 21, a gate, a first electrode, and a second electrode. The portion where the orthographic projection of the gate line 31 onto the substrate 101 coincides with the orthographic projection of the semiconductor pattern 21 onto the substrate 101 forms the gate of the thin-film transistor, and the portion where the data line 41 connects to the semiconductor pattern 21 forms the first electrode (one of the source and drain) of the thin-film transistor T1. When the material of the semiconductor layer 20 includes metal oxide or metal oxynitride, the aforementioned thin-film transistor is an oxide thin-film transistor.
[0081] In some embodiments, referring to Figures 3A and 4F-4J, the array substrate 100 may further include a first electrode layer 61, a second electrode layer 62, a third electrode layer 63, and a common electrode layer 64 disposed between the second conductive layer 40 and the second light-shielding layer 50, and sequentially disposed in a direction away from the substrate 101. Of course, the array substrate 100 may also include an insulating layer located between adjacent conductive layers to prevent short circuits between adjacent conductive layers. Exemplarily, as shown in Figure 3A, the insulating layer may include a buffer layer 71 disposed between the substrate 101 and the first light-shielding layer 10, a third insulating layer 72 disposed between the first light-shielding layer 10 and the semiconductor layer 20, a fourth insulating layer 73 disposed between the second conductive layer 40 and the first electrode layer 61, a first planarization layer 74 disposed between the first electrode layer 61 and the second electrode layer 62, a second planarization layer 75 at least partially located between the second electrode layer 62 and the third electrode layer 63, and a fifth insulating layer 76 disposed between the third electrode layer 63 and the common electrode layer 64. Of course, the array substrate may also include other film layers, which will not be listed one by one in the embodiments disclosed herein.
[0082] As shown in FIG4F, the first electrode layer 61 includes a plurality of first sub-electrodes 611 spaced apart, each first pixel electrode 611 being located within a pixel region and forming a portion of a pixel electrode. As shown in FIG4G, the second electrode layer 62 includes a plurality of second sub-electrodes 621 spaced apart, each second sub-electrode 621 being located within a pixel region and forming a portion of a pixel electrode. As shown in FIG4H, the third electrode layer 63 includes a plurality of third sub-electrodes 631 spaced apart, each third sub-electrode 631 being located within a pixel region and forming a portion of a pixel electrode. Exemplarily, a pixel electrode may include a first sub-electrode 611, a second sub-electrode 621, and a third sub-electrode 631 located within the same pixel region. As shown in FIG4I, the common electrode layer 64 may include a plurality of openings 641, the extending direction of the openings 641 forming an angle with a second direction, and a strip-shaped common electrode 642 being formed between two adjacent openings 641. As shown in Figure 4K, the opening 641 passes through the pixel region 102; in other words, each pixel region 102 includes at least one opening 641. Furthermore, each pixel region may include two connected strip-shaped common electrodes 642, thus forming an Advanced Super Dimension Switching (ADS) structure with the pixel electrodes. As shown in Figure 3A, the common electrode layer 64 can directly contact the second light-shielding layer 50, and the second light-shielding layer 50 can transmit a common voltage signal together with the common electrode layer 64.
[0083] For example, as shown in FIG3A, the array substrate 100 further includes a second via V2 and a third via V3. The second via V2 penetrates the fourth insulating layer 73, the second insulating layer ILD, and the first insulating layer GI, and exposes the conductor region of the semiconductor pattern 21. The first via V1 and the second via V2 respectively expose portions of the source contact region and the drain contact region of the conductor region. A portion of the first electrode layer 61 (first sub-electrode 611) is located within the second via V2 and is electrically connected to the semiconductor pattern 21 through the second via V2. The portion of the first electrode layer 61 electrically connected to the semiconductor pattern 21 can form the second electrode (the other of the source and drain) of the thin-film transistor T1. The first electrode layer 61 also includes a portion located on the surface of the fourth insulating layer 73 away from the substrate 101 (hereinafter referred to as the second portion). The third via V3 penetrates the first planarization layer 74 and exposes at least a portion of the second portion. A portion of the second electrode layer 62 (second sub-electrode 621) is located within the third via V3 and is electrically connected to the first electrode layer 61 through the third via V3. The second planarization layer 75 is also located within the third via V3, used to improve the flatness at the second via V2, thereby improving the flatness of the third electrode layer 63 (third sub-electrode 631). At least a portion of the second electrode layer 62 is located on the surface of the first planarization layer away from the substrate 101, and the third electrode layer 63 overlaps with the portion of the second electrode layer 62 located on the surface of the first planarization layer away from the substrate 101.
[0084] Gate line 31 can control the thin-film transistor T1 to be turned on or off. When gate line 31 controls the thin-film transistor T1 to be turned on, the thin-film transistor T1 can transmit the data signal on data line 41 sequentially through the first electrode layer 61 and the second electrode layer 62 to the third electrode layer 63. An electric field can be formed between the third electrode layer 63 and the common electrode layer 64. The liquid crystal molecules in the liquid crystal layer are deflected under the action of the electric field to adjust the polarization direction of the light passing through the liquid crystal layer, and together with the polarizer, the grayscale adjustment function is realized.
[0085] In some embodiments, as shown in Figures 4A and 4E, the first light-shielding layer 10 may further include a plurality of third light-shielding portions 13, which extend along a first direction X and are spaced apart along a second direction Y. The orthogonal projection of the third light-shielding portion 13 onto the substrate 101 can cover the orthogonal projection of the channel region of a row of semiconductor patterns 21 onto the substrate 101. In this way, light incident on the channel region of the semiconductor patterns 21 can be blocked at least partially, thereby reducing the amount of light irradiated into the channel region and reducing the light leakage current of the thin-film transistor T1. Exemplarily, as shown in Figure 4E, the orthogonal projection of the third light-shielding portion 13 onto the substrate 101 can cover the orthogonal projection of the gate line 31 onto the substrate 101.
[0086] In some embodiments, as shown in FIG8, when the data line 41 is a broken line, the first region S also covers the orthographic projection of the second extension 44 on the substrate 101. That is, the first light-shielding part 11 and the second light-shielding part 51 can work together to separate adjacent pixel areas 102 along the first direction X, so as to reduce the risk of light leakage in adjacent pixel areas 102 along the first direction X.
[0087] In some embodiments, as shown in FIG8, in the orthographic projection of the first light-shielding portion 11, the second light-shielding portion 51, and the first via V1 onto the substrate 101, the center line (first center line 14) of the first light-shielding portion 11 and the center line (second center line 53) of the second light-shielding portion 51 in the first direction X are respectively located on both sides of the center line (third center line 42) of the first via V1 in the first direction X; that is, the first center line 14 and the second center line 53 are respectively located on both sides of the third center line 42, and the first light-shielding portion 11 and the second light-shielding portion 51 are partially overlapped in the first direction X. The first light-shielding portion 11 includes a first edge 15 and a second edge 16 disposed opposite to each other along the first direction X. In the orthographic projection of the first light-shielding portion 11 and the second light-shielding portion 51 onto the substrate 101, the second light-shielding portion 51 at least partially overlaps with the first edge 15 and covers the convex corner (first convex corner 12) of the first light-shielding portion 11 connected to the first edge 15, while the second light-shielding portion 51 does not overlap with the second edge 16. In this way, the size of the second light-shielding part 51 along the first direction X does not need to be very large, yet the second light-shielding part 51 can effectively block the first convex corner 12 of the first light-shielding part 11. This helps to reduce the size of the second light-shielding part 51 along the first direction X, and also reduces the area occupied by the first light-shielding part 11 and the second light-shielding part 51 (reducing the area of the first region S), which is beneficial to improving the aperture ratio of the array substrate. The second light-shielding part 51 covers the first convex corner 12 of the first light-shielding part 11 that connects to the first edge 15, thereby reducing the risk of light leakage at the first convex corner 12.
[0088] In some embodiments, referring to FIG8, the first light-shielding portion 11 is located between two adjacent third light-shielding portions 13. The first end of the first light-shielding portion 11 along the second direction Y (the upper end of the first light-shielding portion 11 in FIG8) is connected to the third light-shielding portion 13, and the second end (the lower end of the first light-shielding portion 11 in FIG8) is a free end. The first edge 15 and the second edge 16 each include a convex corner (first convex corner 12) at their second ends. Compared to setting the first light-shielding portion 11 as an independent block structure, connecting one end of the first light-shielding portion 11 to the third light-shielding portion 13 can reduce the number of first convex corners 12 formed by the first light-shielding portion 11. The number of first convex corners 12 is reduced from four to two, thereby reducing the number of light leakage points caused by the first light-shielding portion 11, reducing the risk and area of light leakage at the edge of the pixel area 102, and thus improving the contrast of the display panel.
[0089] Referring again to FIG8, in some embodiments, the second light-shielding layer 50 further includes a plurality of fourth light-shielding portions 54, which extend along the first direction X and are spaced apart along the second direction Y. The orthographic projection of the fourth light-shielding portions 54 on the substrate 101 can cover the orthographic projection of the first signal line on the substrate 101, thereby separating adjacent pixel areas 102 along the second direction Y and reducing the risk of color crosstalk between adjacent pixel areas 102 along the second direction Y.
[0090] The second light-shielding part 51 is located between two adjacent fourth light-shielding parts 54. The third end of the second light-shielding part 51 along the second direction Y (the lower end of the second light-shielding part 51 in FIG. 8) is connected to the fourth light-shielding part 54, and the fourth end (the lower end of the second light-shielding part 51 in FIG. 8) is a free end. This helps to reduce the size of the second light-shielding part 51 along the second direction Y and reduce the space occupied by the second light-shielding part 51 within the pixel area 102, which is beneficial to improving the aperture ratio of the array substrate. For example, the design combination of the first light-shielding part 11 and the second light-shielding part 51 shown in FIG. 8 can reduce the number of third convex corners S1 formed by the first region S on the periphery of the pixel area 102 (reduced from four rounded corners in related technologies to two convex corners as shown in FIG. 8) without reducing the aperture ratio of the array substrate, thereby reducing the number of light leakage points and the light leakage area on the periphery of the pixel area 102, and thus achieving the purpose of improving the contrast of the display panel.
[0091] In some embodiments, referring to FIG9, the first light-shielding part 11 is located between two adjacent third light-shielding parts 13. Both ends of the first light-shielding part 11 along the second direction Y are spaced apart from the third light-shielding parts 13. That is, the first light-shielding part 11 is a single block structure. In this case, both ends of the first edge 15 and the second edge 16 of the first light-shielding part 11 along the second direction Y include a convex corner (first convex corner 12). The first light-shielding part 11 includes a total of four first convex corners 12. The orthographic projection of the second light-shielding part 51 on the substrate 101 covers the orthographic projection of the first edge 15 on the substrate 101, and covers the two first convex corners 12 connected to the first edge 15. The second light-shielding part 51 blocks the two first convex corners 12.
[0092] Referring again to Figure 9, when the first light-shielding part 11 is an independent block structure, the second light-shielding part 51 can be located between two adjacent fourth light-shielding parts 54, with both ends of the second light-shielding part 51 connected to the fourth light-shielding parts 54 along the second direction Y. In this way, the second light-shielding part 51 will not form convex corners at the edge of the pixel area 102, and the pixel area 102 will only include the two first convex corners of the first light-shielding part 11 that are not covered by the second light-shielding part 51. The number of light leakage points in the pixel area 102 due to rounded corners is also 2. Thus, the number and area of light leakage points around the pixel area 102 can be reduced, thereby improving the contrast of the display panel.
[0093] In some embodiments, referring to FIG8, the radial dimension D3 of the first via V1 is greater than the linewidth D4 of the data line 41, thus the width of the data line 41 at the first via V1 is larger. In the orthographic projection of the first light-shielding portion 11 and the first via V1 on the substrate 101, one end (left end) of the first via V1 along the first direction X is located within the range of the first light-shielding portion 11 and has a first gap D1 between it and the second edge 16, while the other end (right end) is located outside the range of the first light-shielding portion 11. In this way, the first light-shielding portion 11 can not only completely cover the portion of the first via V1 located on the side of the third center line 42 near the first center line 14, but also greatly reduce the size of the first light-shielding portion 11 along the first direction X, reducing the impact of the first light-shielding portion 11 on the aperture ratio of the array substrate 100, which is beneficial to improving the aperture ratio of the array substrate 100.
[0094] In some embodiments, at least one end of the first light-shielding portion 11 along the second direction Y is a free end, as shown in FIG8, or, as shown in FIG9, both ends of the first light-shielding portion 11 along the second direction Y are free ends. The orthographic projection of the free end of the first light-shielding portion 11 onto the substrate 101 has a second interval D1 between it and the orthographic projection of the first via V1 onto the substrate 101, and the second interval D1 is equal to the first interval D1. Thus, the shading width of the end of the first light-shielding portion 11 along the second direction Y onto the first via V1 is consistent with the shading width of the first light-shielding portion 11 along the first direction X near the second edge 16 onto the first via V1, which can improve the uniformity of light shading by the first light-shielding portion 11 onto the first via V1.
[0095] In some embodiments, the first interval D1 satisfies the following equation (1):
[0096] Where A1 represents the alignment deviation between the first via V1 and the first light-shielding layer 10, A2 represents the unilateral dimensional process variation of the first light-shielding layer 10, and B represents the unilateral dimensional process variation of the first via V1. This ensures that even if there are manufacturing deviations in the dimensions of the first light-shielding part 11 or the first via V1, or alignment deviations between the first light-shielding part 11 and the first via V1, the first light-shielding part 11 can still block the first via V1, reducing the risk of light leakage at the first via V1.
[0097] In some embodiments, referring to FIG8, the radial dimension D3 of the first via V1 is greater than the linewidth D4 of the data line 41, thus the data line 41 has a larger width at the first via V1. The second light-shielding portion 51 includes a third edge 55 and a fourth edge 56 disposed opposite each other along the first direction X. The third edge 55 is further away from the second edge 16 than the fourth edge 56. In the orthographic projection of the second light-shielding portion 51 and the first via V1 onto the substrate 101, one end of the first via V1 along the first direction X is located within the range of the second light-shielding portion 51 and has a third interval D2 between it and the third edge 55, while the other end is located outside the range of the second light-shielding portion 51. In this way, the second light-shielding portion 51 can not only completely cover the portion of the first via V1 located on the side of the third centerline 42 near the second centerline 53, but also greatly reduce the size of the second light-shielding portion 51 along the first direction X, reducing the impact of the second light-shielding portion 51 on the aperture ratio of the array substrate 100, which is beneficial to improving the aperture ratio of the array substrate 100.
[0098] In some embodiments, referring to FIG8, one end of the second light-shielding portion 51 along the second direction Y is a free end, and the orthographic projection of the free end of the second light-shielding portion 51 on the substrate 101 has a fourth interval D2 between it and the orthographic projection of the first via V1 on the substrate 101; the fourth interval D2 is equal to the third interval D2. In this way, the blocking width of the end of the second light-shielding portion 51 along the second direction Y to the first via V1 is consistent with the blocking width of the second light-shielding portion 51 along the first direction X near the third edge 55 to the first via V1, which can improve the uniformity of light blocking of the first via V1 by the second light-shielding portion 51.
[0099] In some embodiments, the third interval D2 satisfies the following equation (2):
[0100] Wherein, C1 represents the alignment deviation between the first via V1 and the second light-shielding layer 50, C2 represents the unilateral dimensional process variation of the second light-shielding layer 50, and B represents the unilateral dimensional process variation of the first via V1. This ensures that even if there are manufacturing deviations in the dimensions of the second light-shielding part 51 or the first via V1, or if there are alignment deviations between the second light-shielding part 51 and the first via V1, the second light-shielding part 51 can still block the first via V1, reducing the risk of light leakage at the first via V1.
[0101] In some embodiments, referring to FIG8, the dimension D5 of the first light-shielding portion 11 along the first direction X is equal to the dimension D6 of the second light-shielding portion 51 along the first direction X. In this way, the dimensions of the first light-shielding portion 11 and the second light-shielding portion 12 along the first direction X can be greatly reduced, thereby reducing the influence of the first light-shielding portion 11 and the second light-shielding portion 51 on the aperture ratio of the array substrate 100, which is beneficial to improving the aperture ratio of the array substrate 100.
[0102] In some embodiments, as shown in FIG4E, the extension direction of the semiconductor pattern 21 forms an angle with the first direction X, and the orthographic projection of the semiconductor pattern 21 on the substrate passes through the orthographic projection of the gate line 31 on the substrate. The two conductor regions 212 of the semiconductor pattern 21 are located within two different pixel regions 102. The orthographic projection of the channel region 211 of the semiconductor pattern 21 on the substrate at least partially coincides with the orthographic projections of the gate line 31, the data line 41, and the first light-shielding layer 10 on the substrate. Exemplarily, the orthographic projection of the channel region 211 of the semiconductor pattern 21 on the substrate is located within the range of the orthographic projection of the gate line 31 on the substrate. The orthographic projection of the channel region 211 on the substrate partially coincides with the orthographic projection of the first extension segment 43 of the data line 41 on the substrate. Furthermore, as shown in FIG4E, the orthographic projection of the conductor region 212 of the semiconductor pattern 21 on the substrate also partially coincides with the orthographic projection of the second extension segment 44 of the data line 41 on the substrate, and partially coincides with the orthographic projection of the first light-shielding portion 11 of the first light-shielding layer 10 on the substrate.
[0103] As shown in FIG10A, when the first light-shielding layer 10 includes a third light-shielding portion 13, the orthographic projection of the channel region 211 on the substrate at least partially coincides with the orthographic projection of the third light-shielding portion 13 of the first light-shielding layer 10 on the substrate.
[0104] As shown in Figure 10B, the orthographic projection of the channel region 211 of the semiconductor pattern 21 onto the substrate also partially overlaps with the orthographic projection of the second light-shielding layer 50 onto the substrate 101. For example, when the second light-shielding layer 50 includes a fourth light-shielding portion 54, the orthographic projection of the channel region 211 of the semiconductor pattern 21 onto the substrate at least partially overlaps with the orthographic projection of the fourth light-shielding portion 54 of the second light-shielding layer 50 onto the substrate 101.
[0105] As shown in Figure 10C, the opening 641 of the common electrode layer 64 at least partially overlaps with the fourth light-shielding portion 54. The orthographic projection of the opening 641 onto the substrate at least partially overlaps with the third light-shielding portion 13.
[0106] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. An array substrate, comprising: Substrate; A first light-shielding layer is disposed on one side of the substrate and includes a first light-shielding portion; A semiconductor layer, disposed on the side of the first light-shielding layer away from the substrate, includes a semiconductor pattern; the semiconductor pattern includes a channel region and two conductor regions located on both sides of the channel region; A first insulating layer is disposed on the side of the semiconductor layer away from the substrate; A first conductive layer is disposed on the side of the first insulating layer away from the substrate, and includes multiple gate lines; A second insulating layer is disposed on the side of the first conductive layer away from the substrate; The first via penetrates at least the second insulating layer and exposes a portion of the conductor region; The second conductive layer is disposed on the side of the second insulating layer away from the substrate, and includes multiple data lines, which are electrically connected to the conductor region through the first via. The second light-shielding layer is disposed on the side of the second conductive layer away from the substrate, and includes a second light-shielding portion; In this configuration, multiple gate lines and multiple data lines intersect to define multiple pixel regions; in the orthographic projection of the first light-shielding portion, the second light-shielding portion, and the first via on the substrate, the first light-shielding portion and the first via at least partially overlap, the second light-shielding portion and the first via at least partially overlap, the first light-shielding portion and the second light-shielding portion together form a first region, the first region covers the first via, the second light-shielding portion covers at least one convex corner of the first light-shielding portion, and the number of convex corners formed by the first region within a pixel region is less than 4.
2. The array substrate according to claim 1, wherein, In the orthographic projection of the first light-shielding portion, the second light-shielding portion, and the first via on the substrate, the center line of the first light-shielding portion in the first direction and the center line of the second light-shielding portion in the first direction are respectively located on both sides of the center line of the first via in the first direction; the first direction is the extension direction of the gate line. The first light-shielding portion includes a first edge and a second edge disposed opposite to each other along the first direction; The orthographic projection of the second light-shielding portion on the substrate at least partially coincides with the orthographic projection of the first edge on the substrate, covers the orthographic projection of the convex corner connected to the first edge on the substrate, and does not coincide with the orthographic projection of the second edge on the substrate.
3. The array substrate according to claim 2, wherein, The first light-shielding layer further includes a plurality of third light-shielding portions, which extend along the first direction and are spaced apart along the second direction; the second direction intersects the first direction. The first light-shielding part is located between two adjacent third light-shielding parts. The first end of the first light-shielding part along the second direction is connected to the third light-shielding part, and the second end is a free end.
4. The array substrate according to claim 3, wherein, The second light-shielding layer further includes a plurality of fourth light-shielding portions, which extend along the first direction and are spaced apart along the second direction; The second light-shielding part is located between two adjacent fourth light-shielding parts, and the third end of the second light-shielding part along the second direction is connected to the fourth light-shielding part, while the fourth end is a free end; The orthographic projections of the first end and the third end onto the substrate are respectively located on opposite sides of the orthographic projection of the first via onto the substrate along the second direction.
5. The array substrate according to claim 2, wherein, The first light-shielding layer further includes a plurality of third light-shielding portions, which extend along the first direction and are spaced apart along the second direction; the second direction intersects the first direction. The first light-shielding part is located between two adjacent second light-shielding parts, and both ends of the first light-shielding part along the second direction are spaced apart from the third light-shielding part; The orthographic projection of the second light-shielding portion on the substrate covers the orthographic projection of the first edge on the substrate.
6. The array substrate according to claim 5, wherein, The second light-shielding layer further includes a plurality of fourth light-shielding portions, which extend along the first direction and are spaced apart along the second direction; The second light-shielding part is located between two adjacent fourth light-shielding parts, and the two ends of the second light-shielding part along the second direction are respectively connected to the fourth light-shielding part.
7. The array substrate according to any one of claims 3 to 6, wherein, The radial dimension of the first via is greater than the line width of the data line; In the orthographic projection of the first light-shielding portion and the first via on the substrate, one end of the first via along the first direction is located within the range of the first light-shielding portion and has a first gap with the second edge, while the other end is located outside the range of the first light-shielding portion.
8. The array substrate according to claim 7, wherein, At least one end of the first light-shielding portion along the second direction is a free end, and the orthographic projection of the free end of the first light-shielding portion on the substrate has a second interval with the orthographic projection of the first via on the substrate, the second interval being equal to the first interval.
9. The array substrate according to claim 7 or 8, wherein, The first interval is D1, and D1 satisfies: Wherein, A1 is the alignment deviation between the first via and the first light-shielding layer, A2 is the single-sided dimensional process fluctuation of the first light-shielding layer, and B is the single-sided dimensional process fluctuation of the first via.
10. The array substrate according to any one of claims 3 to 9, wherein, The radial dimension of the first via is greater than the line width of the data line; The second light-shielding portion includes a third edge and a fourth edge disposed opposite to each other along the first direction, wherein the third edge is located on the side of the fourth edge that is further away from the second edge; In the orthographic projection of the second light-shielding portion and the first via on the substrate, one end of the first via along the first direction is located within the range of the second light-shielding portion and has a third gap with the third edge, while the other end is located outside the range of the second light-shielding portion.
11. The array substrate according to claim 10, wherein, One end of the second light-shielding portion along the second direction is a free end, and the orthographic projection of the free end of the second light-shielding portion on the substrate has a fourth interval between it and the orthographic projection of the first via on the substrate; the fourth interval is equal to the third interval.
12. The array substrate according to claim 10 or 11, wherein, The third interval is D2, and D2 satisfies: Wherein, C1 is the alignment deviation between the first via and the second light-shielding layer, C2 is the single-sided dimensional process fluctuation of the second light-shielding layer, and B is the single-sided dimensional process fluctuation of the first via.
13. The array substrate according to any one of claims 2 to 12, wherein, The dimension of the first light-shielding part along the first direction is equal to the dimension of the second light-shielding part along the first direction.
14. The array substrate according to any one of claims 1 to 13, wherein, The data line includes a plurality of alternating first extension segments and a plurality of second extension segments; the plurality of first extension segments all extend along the first direction and are spaced apart along the second direction; the plurality of second extension segments all extend along the second direction and are alternately connected to the two ends of the first extension segments along the first direction. The first region covers the orthogonal projection of the second extension onto the substrate.
15. The array substrate according to claim 14, wherein, The extension direction of the semiconductor pattern forms an angle with the first direction, and the orthographic projection of the semiconductor pattern on the substrate passes through the orthographic projection of the gate line on the substrate; The two conductor regions of the semiconductor pattern are located in two different pixel regions; The orthographic projection of the channel region on the substrate at least partially coincides with the orthographic projections of the gate line, the data line, the first light-shielding layer, and the second light-shielding layer on the substrate.
16. The array substrate according to claim 14 or 15, wherein, The first light-shielding layer further includes a third light-shielding portion, wherein the orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the third light-shielding portion on the substrate; The second light-shielding layer further includes a fourth light-shielding portion, wherein the orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the fourth light-shielding portion on the substrate.
17. The array substrate according to claim 16, further comprising: A common electrode layer is disposed on the side of the second light-shielding layer near the substrate and in contact with the second light-shielding layer. The common electrode layer includes a plurality of openings. Each pixel region includes at least one opening, the opening at least partially overlaps with the fourth light-shielding portion, and the orthographic projection of the opening on the substrate at least partially overlaps with the third light-shielding portion.
18. A display panel, comprising: The array substrate as described in any one of claims 1 to 17; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate.
19. A near-eye display device, comprising: The display panel as described in claim 18; The driver circuit board, electrically connected to the display panel, is configured to transmit control signals to the display panel.