Manufacturing method for stacked transistor, stacked transistor, device, and apparatus
Patent Information
- Application Number
- PCT/CN2025/092939
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-24
- Filing Date
- 2025-05-06
- Publication Date
- 2026-08-27
Smart Images
Figure CN2025092939_27082026_PF_FP_ABST
Abstract
Description
Fabrication methods of stacked transistors, stacked transistors, devices and equipment
[0001] Cross-references to related applications
[0002] This application is based on and claims priority to Chinese Patent Application No. 202510203871.1, filed on February 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of integrated semiconductors, and more particularly to a method for fabricating stacked transistors, stacked transistors, devices, and apparatus. Background Technology
[0004] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, by integrating two or more layers of transistors in a vertical space, further increase transistor integration density and have become one of the important technologies for continuing the miniaturization of integrated circuits.
[0005] In related technologies, both monolithic and sequential methods for fabricating stacked transistors present significant challenges in terms of fabrication difficulty and complexity. Therefore, the fabrication process for stacked transistors still requires improvement in order to simplify the process and reduce fabrication difficulty. Summary of the Invention
[0006] This disclosure provides a method for fabricating a stacked transistor, a stacked transistor, a device, and an apparatus.
[0007] This disclosure provides a method for fabricating a stacked transistor. The method includes: forming a semiconductor structure on a substrate, the semiconductor structure including a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure stacked sequentially along a first direction; the first semiconductor structure including a first material layer and a second material layer stacked sequentially along the first direction; the second semiconductor structure including a first material layer and a second material layer stacked sequentially along the first direction; depositing semiconductor material in a gate region to form a dummy gate structure, the dummy gate structure surrounding the second semiconductor structure, the first sacrificial layer, and the first semiconductor structure, the height of the dummy gate structure being higher than the height of the semiconductor structure; removing the first sacrificial layer to form a first groove; and etching the first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the second material layer along a second direction. The portion of the dummy gate structure above the semiconductor structure forms a second groove, with the second direction being perpendicular to the first direction. Dielectric material is deposited within the first and second grooves to form an isolation layer at the location where the first sacrificial layer is removed, a first inner sidewall at the location where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the location where the first material layer in the first semiconductor structure is etched, and a sidewall at the location where the portion of the dummy gate structure above the semiconductor structure is etched. A first ring-gate transistor is formed on the side of the isolation layer with the first inner sidewall and the sidewall, based on the second semiconductor structure. A second ring-gate transistor is formed on the side of the isolation layer with the second inner sidewall, based on the first semiconductor structure.
[0008] A second aspect of this disclosure provides a stacked transistor. The stacked transistor is fabricated using the method provided in the first aspect above, comprising: a first ring-gate transistor; a second ring-gate transistor, wherein the first ring-gate transistor and the second ring-gate transistor are stacked and self-aligned.
[0009] A third aspect of this disclosure provides a semiconductor device comprising: a stacked transistor as provided in the second aspect.
[0010] The fourth aspect of this disclosure provides an electronic device, which includes: a circuit board and a semiconductor device provided in the third aspect, the semiconductor device being disposed on the circuit board.
[0011] In this disclosure, a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure are sequentially stacked on a substrate. Semiconductor material is deposited in the gate region to form a dummy gate structure. Then, the first sacrificial layer is removed to form a first trench. The first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the portion of the dummy gate structure that is higher than the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure are etched along a first direction to form a second trench. Subsequently, dielectric material is deposited in the first trench and the second trench to form an isolation layer at the location where the first sacrificial layer is removed, a first inner sidewall at the location where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the location where the first material layer in the first semiconductor structure is etched, and a sidewall at the location where the portion of the dummy gate structure that is higher than the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure is etched. Then, on the side of the isolation layer with the first inner sidewall and the sidewall, a first ring-gate transistor is formed based on the second semiconductor structure. On the side of the isolation layer with the second inner sidewall, a second ring-gate transistor is formed based on the first semiconductor structure. Therefore, by using the same medium material to simultaneously form the isolation layer, inner sidewall, and sidewall in the embodiments of this disclosure, redundant process steps and process complexity can be reduced.
[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of embodiments of this disclosure.
[0014] Figure 1 is a schematic diagram of an implementation process of a method for fabricating stacked transistors according to an embodiment of this disclosure;
[0015] Figure 2 is a top view of the stacked transistors in an embodiment of this disclosure;
[0016] Figures 3A to 3L are schematic diagrams of the stacked transistors during the fabrication process in the embodiments of this disclosure;
[0017] Figure 4 is a schematic diagram of the stacked transistor structure in an embodiment of this disclosure.
[0018] Reference numerals in the figures: Stacked transistor 10; First gate-around transistor (front-side transistor) 11; First nanosheet structure 111; First source / drain structure 112; First interlayer dielectric layer 113; First gate structure 114; First gate dielectric layer 1141; First gate electrode layer 1142; First source / drain contact metal 115; First metal interconnect layer 116; Second gate-around transistor (back-side transistor) 12; Second nanosheet structure 121; Second source / drain structure 122; Second interlayer dielectric layer 123; Second gate structure 124; Second gate dielectric layer 1241; Second gate electrode layer 1242; Second source / drain contact metal 125; Second metal interconnect layer 126; Insulating layer 13; Carrier 14 wafer; 20 substrate; 21 fourth sacrificial layer; 22 stacked layer; 23 third sacrificial layer; 24 semiconductor structure; 241 first semiconductor structure; 242 second semiconductor structure; 243 first sacrificial layer; 244 second sacrificial layer; 25 isolation structure; 26 oxide layer; 27 dummy gate structure; 28 protective layer; 281 first trench; 282 second trench; 29 MDI layer; 30 first inner sidewall; 31 second inner sidewall; 32 sidewall; 33 filling structure; 34 source / drain isolation dielectric layer; 35 gate isolation dielectric layer; 36 first gate cut-off structure; 37 first dielectric layer; 371 third trench; 38 second gate cut-off structure; 39 second dielectric layer. Detailed Implementation
[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure.
[0020] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments disclosed herein. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0021] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.
[0022] In one embodiment, there are two methods for fabricating stacked transistors: a monolithic method and a sequential method.
[0023] The first approach fabricates N-channel field-effect transistors (NFETs) and P-channel field-effect transistors (PFETs) on the same substrate without using substrate bonding. This dictates that transistors in the same layer must be of the same type, i.e., NFETs or PFETs. Furthermore, the upper and lower transistor layers must be strictly on the same plane, with no alignment deviations. The advantage of this approach is its higher integration density. The disadvantages of this approach include the following two points: (1) complex process, requiring extensive development and optimization of process technologies; (2) fixed polarity for each transistor layer, necessitating two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.
[0024] The second approach is based on substrate bonding and layer-by-layer fabrication. Specifically, the upper transistor is fabricated by bonding a substrate to the top of the already fabricated lower transistor, stacking the two transistors vertically. However, this approach requires strict temperature control during the thermal processing of the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this approach is that, thanks to substrate bonding, the device structure, channel crystal orientation, and even the channel material used in the upper and lower transistors can be optimized to obtain better and more matched device performance. This approach currently faces the following technical challenges: (1) fabrication of high-quality upper transistor active layers; (2) thinning and defect control of the upper bonding substrate; (3) alignment errors exist between the upper and lower transistors, requiring extremely high photolithography precision.
[0025] From a common perspective, the technical difficulties of the two schemes mentioned above are: (1) the thermal stability of the bottom transistors when fabricating the top transistor; (2) the performance of the top transistor under low thermal budget; and (3) the metal interconnection between transistors between layers.
[0026] To address the aforementioned technical problems, this disclosure provides a method for fabricating stacked transistors, which can reduce the process steps and complexity in the formation of stacked transistors.
[0027] In this embodiment of the disclosure, the stacked transistors described above can be applied to semiconductor devices such as memory and processors.
[0028] In some embodiments, the stacked transistors may include at least two transistors. For example, a first ring gate transistor and a second ring gate transistor are stacked together. The second semiconductor structure of the first ring gate transistor is self-aligned with the first semiconductor structure of the second ring gate transistor. The first source-drain structure of the first ring gate transistor is self-aligned with the second source-drain structure of the second ring gate transistor in the vertical direction. Therefore, the first ring gate transistor and the second ring gate transistor are completely self-aligned.
[0029] In some embodiments, the first gate-around transistor and the second gate-around transistor in the flip-chip stacked transistor can be transistors of the same type, and the gate-around transistor can be called a gate-all-around field effect transistor (GAAFET).
[0030] Figure 1 is a schematic diagram of an implementation process of a method for fabricating a stacked transistor in an embodiment of this disclosure. As shown in Figure 1, the method for fabricating a flip-chip stacked transistor in an embodiment of this disclosure includes the following steps.
[0031] Step S110: Form a semiconductor structure on the substrate.
[0032] In some embodiments, the semiconductor structure includes a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure stacked sequentially along a first direction. The first semiconductor structure includes a first material layer and a second material layer stacked sequentially along the first direction, and the second semiconductor structure includes a first material layer and a second material layer stacked sequentially along the first direction.
[0033] In some embodiments, step S101 can be implemented as follows: providing a substrate; sequentially stacking a first material layer and a second material layer on the substrate, forming a third sacrificial layer on the stacked material layers, and sequentially stacking the first material layer and the second material layer on the third sacrificial layer; etching the second material layer, the first material layer, and the third sacrificial layer to form a semiconductor structure, wherein the etched third sacrificial layer serves as the first sacrificial layer, the etched first material layer and the second material layer near the substrate serve as the first semiconductor structure, and the etched first material layer and the second material layer away from the substrate serve as the second semiconductor structure. That is, the first sacrificial layer serves as an isolation structure between the first semiconductor structure and the second semiconductor structure. The first direction is the stacking direction of the stacked transistors.
[0034] For example, the substrate can be any semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate.
[0035] In some embodiments, the materials forming the first material layer and the second material layer are different, and the materials forming the first sacrificial layer are also different from the materials forming the first and second material layers, so that the first sacrificial layer can be removed subsequently by material selectivity. The role of the first sacrificial layer will be explained later. The etching process can, for example, be at least one of dry etching, wet etching, reactive ion etching, etc.
[0036] In one example, the material forming the first material layer can be silicon-germanium, the material forming the second material layer can be silicon, and the material forming the first sacrificial layer can be silicon-germanium. In another example, the germanium content in the silicon-germanium material forming the first sacrificial layer is different from the germanium content in the silicon-germanium material forming the first material layer. For example, SiGe 1 can be used to form the first sacrificial layer, and SiGe 2 can be used to form the first material layer.
[0037] In one example, when the stacked transistor is a GAAFET, the material forming the substrate can be silicon, the material forming the first material layer can be silicon-germanium, and the material forming the second material layer can be silicon. Thus, the materials forming the first semiconductor structure and the second semiconductor structure can be silicon-germanium and silicon deposited alternately. Subsequently, the first material layer (i.e., silicon-germanium material) in the first semiconductor structure and the second semiconductor structure can be removed to form the first active structure and the second active structure.
[0038] In some embodiments, the semiconductor structure further includes a second sacrificial layer located between the substrate and the first semiconductor structure, with isolation structures on both sides of the second sacrificial layer, the height of which is the same as the height of the second sacrificial layer.
[0039] Understandably, in embodiments of this disclosure, a fourth sacrificial layer may be formed on the substrate, and then a first material layer and a second material layer may be stacked sequentially on the fourth sacrificial layer. A third sacrificial layer may be formed on the stacked material layers, and then a first material layer and a second material layer may be stacked sequentially on the third sacrificial layer. Afterward, the stacked layer, the third sacrificial layer and the fourth sacrificial layer may be etched to form a semiconductor structure, with the etched fourth sacrificial layer serving as the second sacrificial layer.
[0040] In some embodiments, the material forming the second sacrificial layer can be a silicon-germanium material. The germanium content in the silicon-germanium material forming the first sacrificial layer is different from the germanium content in the silicon-germanium materials forming the first material layer and the second sacrificial layer. For example, SiGe3 can be used to form the second sacrificial layer.
[0041] In some embodiments, after the semiconductor structure is formed, an insulating material can be deposited on the substrate to form an isolation structure.
[0042] Understandably, after forming the semiconductor structure, an insulating material can be deposited on the substrate and thinned so that the upper surface of the formed isolation structure is flush with the upper surface of the second sacrificial layer to expose the first semiconductor structure.
[0043] In one example, the isolation structure can be shallow trench isolation (STI). For example, the insulating material forming the isolation structure can be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc. The thinning process can be a process such as chemical-mechanical planarization (CMP).
[0044] In some embodiments, after forming the isolation structure, an oxide material can be deposited on the isolation structure to form an oxide layer that covers the semiconductor structure. When depositing the oxide to form the oxide layer, a very thin film can be deposited on the surface of the substrate using atomic layer deposition (ALD).
[0045] Step S102: Deposit semiconductor material in the gate region to form a pseudo-gate structure.
[0046] In some embodiments, the dummy gate structure surrounds the second semiconductor structure, the first sacrificial layer, and the first semiconductor structure, and the height of the dummy gate structure is greater than the height of the semiconductor structure.
[0047] For example, the semiconductor material can be polycrystalline silicon, amorphous silicon, or other similar materials.
[0048] Understandably, after forming the semiconductor structure and the isolation structure, the gate region can be opened by photolithography, and a semiconductor material such as polysilicon can be deposited in the gate region as a pseudo-gate structure shared by the front and back transistors. That is, in this embodiment of the present disclosure, the gate regions of the front and back transistors in the stacked transistors are defined by the pseudo-gate structure, thus enabling self-alignment of the upper and lower transistors in the gate region. In one example, the height of the pseudo-gate structure is greater than the height of the semiconductor structure.
[0049] In some embodiments, when an oxide layer is formed, a pseudo-gate structure can be formed on the oxide layer.
[0050] In some embodiments, after forming the dummy gate structure, an insulating material can be deposited on the dummy gate structure to form a protective layer. For example, the insulating material can be SiN.
[0051] In some embodiments, after the protective layer is formed, the oxide layer on the semiconductor structure in the source / drain region can be removed so that the semiconductor structure in the source / drain region can be removed subsequently.
[0052] Step S103: Remove the first sacrificial layer to form the first groove.
[0053] Understandably, the first sacrificial layer located between the first semiconductor structure and the second semiconductor structure can be isotropically etched to form a groove, so that an isolation structure between the front and back transistors can be subsequently formed based on the groove.
[0054] Step S104: Etch the first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the portion of the dummy gate structure above the semiconductor structure along the second direction to form a second groove.
[0055] Understandably, the second direction is perpendicular to the first direction.
[0056] In some embodiments, when the material forming the first material layer is SiGe2, a portion of the SiGe2 in the first and second semiconductor structures can be etched laterally to leave space for the inner spacer. Furthermore, a portion of the dummy gate structure that is higher than the semiconductor structure can be etched laterally to leave space for the gate spacer, thus forming a second groove.
[0057] Understandably, the inner wall and the side wall are located on the same side of the semiconductor structure.
[0058] Step S105: Deposit dielectric material in the first groove and the second groove to form an isolation layer at the location where the first sacrificial layer is removed, a first inner sidewall at the location where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the location where the first material layer in the first semiconductor is etched, and a sidewall at the location where the portion of the pseudo-gate structure above the semiconductor structure is etched.
[0059] In some embodiments, step S105 can be implemented by: depositing a dielectric material on a substrate to cover the pseudo-gate structure; and anisotropically etching the dielectric material in the source / drain regions to form an isolation layer, a first inner sidewall, a second inner sidewall, and a sidewall, respectively.
[0060] In some embodiments, when an isolation structure exists on the substrate and a protective layer exists on the dummy gate structure, a dielectric material can be deposited on the isolation structure such that the upper surface of the dielectric material is flush with the upper surface of the protective layer. Then, the dielectric material in the source / drain regions is etched. Thus, the dielectric material deposited at the removed first sacrificial layer forms an isolation layer, the dielectric material deposited at the etched first material layer of the second semiconductor structure forms a first inner sidewall, the dielectric material deposited at the etched first material layer of the first semiconductor structure forms a second inner sidewall, and the dielectric material deposited at the etched dummy gate structure forms a sidewall. In one example, the isolation layer can also be referred to as a middle dielectric isolation (MDI) layer, which serves as an isolation structure between the front-side transistor and the back-side transistor.
[0061] Understandably, the sidewalls are located on both sides of the dummy gate structure. The first inner sidewall is located on both sides of the first material layer of the second semiconductor structure, meaning the first inner sidewall is the sidewall of the gate structure of the first ring-gate transistor. The second inner sidewall is located on both sides of the first material layer of the first semiconductor structure, meaning the second inner sidewall is the sidewall of the gate structure of the second ring-gate transistor. For example, the sidewalls may have a single-layer structure, made entirely of the same material, such as porous silicon carbide (SICOH).
[0062] In this embodiment, the originally separate MDI process, inner spacer process and gate spacer process are integrated. During the formation of the gate spacer, the MDI layer and the inner spacer are formed simultaneously, which can reduce redundant process steps and process complexity.
[0063] In some embodiments, after forming the gate spacer, MDI layer and inner spacer, the protective layer on the pseudo-gate structure can be removed.
[0064] Step S106: On one side of the isolation layer having the first inner wall and the side wall, a first ring gate transistor is formed based on the second semiconductor structure.
[0065] Understandably, since the isolation layer is located between the first semiconductor structure and the second semiconductor structure, a front-side transistor can be fabricated on one side of the isolation layer, and a back-side transistor can be fabricated on the other side. The first inner sidewall is located on both sides of the first material layer of the second semiconductor structure, the second inner sidewall is located on both sides of the first material layer of the first semiconductor structure, and the sidewall is located above the first inner sidewall. Therefore, with the isolation layer as the boundary, one side of the isolation layer has the first inner sidewall, the sidewall, and the second semiconductor structure, while the other side of the isolation layer has the second inner sidewall and the first semiconductor structure. Thus, a first gate-around transistor can first be formed on the side of the isolation layer with the first inner sidewall and the sidewall, based on the second semiconductor structure.
[0066] In some embodiments, the process of forming a first ring gate transistor based on a second semiconductor structure may include: removing the semiconductor structure in the source / drain region and filling the first source / drain region corresponding to the first semiconductor structure with insulating material to form a filled structure; epitaxially growing a first source / drain structure in the second source / drain region corresponding to the second semiconductor structure; forming a first interlayer dielectric layer on the first source / drain structure; etching the portion of the dummy gate structure surrounding the second semiconductor structure to form a first gate structure; etching the first interlayer dielectric layer to expose the first source / drain structure; depositing metal material on the first source / drain structure to form a first source / drain metal; and performing back-channel interconnects on the first source / drain metal to form a first metal interconnect layer.
[0067] Understandably, etching the semiconductor structure within the source / drain region removes both the first and second semiconductor structures within that region. After exposing the source / drain region, insulating material can be filled into the first source / drain region corresponding to the first semiconductor to form a filled structure. This filled structure defines the source / drain region of the back-side transistor, enabling self-alignment of the upper and lower transistor layers in the source / drain region of a flip-chip stacked transistor. For example, the insulating material can be silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc.
[0068] In some embodiments, after removing the oxide layer in the source / drain region in step S102, the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure in the source / drain region can be removed. Then, the first sacrificial layer, the first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the dummy gate structure are etched to form the gate spacer, the MDI layer, and the inner spacer, respectively.
[0069] In some embodiments, in the presence of a second sacrificial layer and an isolation structure, after the gate spacer, MDI layer and inner spacer are formed, the second sacrificial layer and the isolation structure located in the source-drain region can be removed to fully expose the entire source-drain region.
[0070] In some embodiments, when an MDI layer is present, the filling structure may cover a portion of the MDI layer when forming the filling structure.
[0071] Understandably, after etching the semiconductor structure in the source / drain region, a source / drain groove will be formed. Therefore, source / drain epitaxial growth can be performed at this groove to form a first source / drain structure. After forming the first source / drain structure, an interlayer dielectric can be deposited on the first source / drain structure, and the interlayer dielectric can be thinned to the upper surface of the first source / drain structure to form a first interlayer dielectric layer.
[0072] For example, strained materials such as silicon-germanium or silicon carbide can be selectively epitaxially grown in the source-drain trenches to fill the source-drain trenches of the front-side transistor (first gate ring transistor), and then the first source-drain structure can be formed on the strained material through a heavy doping process. For example, the interlayer dielectric can be SiO2.
[0073] For ease of explanation, the first source / drain structure mentioned in the embodiments of this disclosure is an abbreviation, specifically referring to the first source structure and / or the first drain structure. Furthermore, subsequent mentions of first source / drain metal, second source / drain structure, second source / drain metal, etc., are similar to the first source / drain structure, where "source / drain" is an abbreviation for "source and / or drain".
[0074] After forming the first interlayer dielectric layer, the portion of the pseudo-gate structure surrounding the second semiconductor structure can be removed to form the first gate structure of the first ring gate transistor.
[0075] Understandably, the pseudo-gate structure of the first ring-gate transistor formed above is removed by an etching process to obtain a first gate groove. An insulating material is deposited at the first gate groove to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute the first gate structure.
[0076] For example, the first gate dielectric layer may be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor. The first gate electrode layer may be composed of multiple layers of electrode materials, each layer of which may include, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).
[0077] In some embodiments, the portion of the dummy gate structure surrounding the second semiconductor structure may be etched; a gate isolation dielectric layer may be formed on the retained dummy gate structure; a first material layer in the second semiconductor structure may be etched on the gate isolation dielectric layer to form a first active structure; and a first gate structure may be formed based on the first active structure.
[0078] Understandably, after etching the dummy gate structure of the first ring-gate transistor, an insulating material can be deposited on the retained dummy gate structure of the second ring-gate transistor. This insulating material is then anisotropically etched down to the bottom of the second semiconductor structure, followed by isotropic etching to form a gate isolation dielectric layer. Then, a first gate dielectric layer and a first gate electrode layer are sequentially formed on the gate isolation dielectric layer to form the first gate structure.
[0079] In some embodiments, since the second semiconductor structure includes a first material layer and a second material layer stacked sequentially, when removing the portion of the dummy gate structure surrounding the second semiconductor structure, the oxide layer surrounding the second semiconductor structure and the first material layer in the second semiconductor structure can be removed simultaneously to form the first active structure of the first ring-gate transistor. Then, an insulating material is deposited on the surface of the first active structure to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first active structure can also be referred to as a first nanosheet structure.
[0080] In some embodiments, the portion of the dummy gate structure surrounding the second semiconductor structure can be removed first by high-temperature oxidation, and then the oxide layer surrounding the second semiconductor structure and the first material layer in the second semiconductor structure can be removed. In this way, when the portion of the dummy gate structure surrounding the second semiconductor structure is removed by high-temperature oxidation, the oxide layer can protect the channel from the effects of high temperature.
[0081] Understandably, after forming the gate structure, a portion of the first interlayer dielectric layer can be etched to expose the first source / drain structure. Subsequently, metal material is deposited on the first source / drain structure to form the first source / drain contact metal. After forming the first source / drain contact metal, subsequent processes can be performed to form the first metal interconnect layer.
[0082] Understandably, back-end processes can include interconnect dielectric deposition, metal line formation, lead-out pad formation, and other processes.
[0083] It should be noted that the first source / drain structure, the first interlayer dielectric layer, the first gate structure, the first source / drain metal, and the first metal interconnect layer can all be formed by standard steps of semiconductor fabrication processes, and the embodiments disclosed herein do not impose specific limitations on them.
[0084] In some embodiments, a source-drain isolation dielectric layer may be formed on the filling structure, the height of the source-drain isolation dielectric layer being the same as the height of the isolation layer; a first source-drain structure may be formed on the source-drain isolation dielectric layer.
[0085] Understandably, after forming the filled structure, an insulating material can be deposited on the filled structure and thinned so that the upper surface of the formed source-drain isolation structure is flush with the upper surface of the MDI layer. Then, the first gate-ring transistor is fabricated on the source-drain isolation dielectric layer.
[0086] In some embodiments, after forming the first gate structure of the first ring gate transistor, a first gate cut-off structure may be formed on both sides of the first gate structure. The first gate cut-off structure is used to isolate the gate region of the stacked transistor from the gate region of the adjacent stacked transistor.
[0087] Understandably, after the first gate structure is formed, the first gate structure can be gate-cut to form a first gate-cut groove; insulating material is filled into the first gate-cut groove to form a first gate-cut structure.
[0088] For example, photoresist can be coated over the first gate structure. After exposure and development (i.e., forming a photoresist layer), a notch is formed at a predetermined location, where the notch corresponds to the gate cut-off region of the first gate-ring transistor. Next, using the photoresist layer as a mask, a portion of the first gate structure is etched to form a first gate cut-off groove. After forming the first gate cut-off groove, an insulating material can be used to fill the first gate cut-off groove to form a first gate cut-off structure located on both sides of the first gate structure.
[0089] It should be noted that the width of the first gate cut-off groove (i.e., the size of the notch in the photoresist layer) can be designed according to the actual situation, but it cannot be etched onto the second semiconductor structure. This disclosure does not limit this aspect.
[0090] In some embodiments, a first dielectric layer may be formed on the first gate structure and the first interlayer dielectric layer before the first source / drain metal is formed.
[0091] Understandably, insulating material can be deposited on the first gate structure and the first interlayer dielectric layer to form the first dielectric layer, which can also be called a pre-metal dielectric (PMD) layer. The PMD layer has the following two functions: (1) Electrical isolation: The PMD layer electrically isolates the transistor device from the metal interconnect layer, preventing current from flowing in unwanted paths and ensuring the normal operation of the circuit; (2) Physical protection: The PMD layer can block impurity sources such as mobile particles (e.g., sodium ions), preventing impurity sources from affecting the performance of the transistor device and protecting the device from the influence of the external environment. Insulating materials forming the PMD layer can be, for example, SiO2, SiN, etc.
[0092] In some embodiments, after forming a first gate ring transistor based on a second semiconductor structure, the first gate ring transistor can be flipped and the substrate removed to expose the first semiconductor structure; and a second gate ring transistor can be formed based on the first semiconductor structure.
[0093] Understandably, after forming the first gate ring transistor, the first gate ring transistor can be bonded to the carrier wafer, and then the first gate ring transistor can be flipped to prepare for the subsequent fabrication of the back-side transistor.
[0094] In some embodiments, an insulating material (such as silicon oxide) may be deposited on a first metal interconnect layer to form a first insulating layer, and the first insulating layer may be bonded to a carrier wafer, after which the first gate ring transistor may be flipped.
[0095] In some embodiments, after the first ring gate transistor is flipped, the substrate can be removed; the isolation structure can be removed to form a third groove; semiconductor material can be filled in the third groove so that the upper surface of the formed dummy gate structure is flush with the upper surface of the second sacrificial layer; and a second ring gate transistor can be formed based on the first semiconductor structure.
[0096] Understandably, since a second sacrificial layer and isolation structures on both sides of the second sacrificial layer exist in the gate region of the back-side transistor, the isolation structures in the gate region can be removed after removing the substrate to expose the second sacrificial layer. Then, materials such as polysilicon can be deposited on both sides of the exposed second sacrificial layer so that the formed pseudo-gate structure can completely define the gate region of the back-side transistor.
[0097] In some embodiments, after filling the third groove with semiconductor material so that the upper surface of the formed pseudo-gate structure is flush with the upper surface of the second sacrificial layer, the second sacrificial layer can be selectively removed.
[0098] Step S107: On the side of the isolation layer with the second inner wall, a second ring gate transistor is formed based on the first semiconductor structure.
[0099] In some embodiments, after removing the substrate, the structure can be filled by selective etching of the material to expose the first source / drain region of the back-side transistor.
[0100] Understandably, since the filling structure covers the first source / drain region of the back transistor, the filling structure can be selectively etched during the fabrication of the back transistor to expose the first source / drain region. Because the filling structure is used to locate the source / drain region of the back transistor, subsequent fabrication of the back transistor does not require region selection via photolithography; the source / drain region can be directly opened through material selection to fabricate a back transistor that is completely self-aligned with the front transistor.
[0101] In some embodiments, the process of forming a second gate ring transistor based on a first semiconductor structure may be as follows: epitaxially growing a second source / drain structure at a first source / drain region; forming a second interlayer dielectric layer on the second source / drain structure; etching the portion of the dummy gate structure surrounding the first semiconductor structure to form a second gate structure; etching the second interlayer dielectric layer to expose the second source / drain structure; depositing metal material on the second source / drain structure to form a second source / drain metal; and performing back-channel interconnects on the second source / drain metal to form a second metal interconnect layer.
[0102] Understandably, after etching the filling structure in the first source / drain region, a source / drain groove is formed. Therefore, source / drain epitaxial growth can be performed at this groove to form a second source / drain structure. After forming the second source / drain structure, an interlayer dielectric can be deposited on the second source / drain structure and thinned to the upper surface of the second source / drain structure to form a second interlayer dielectric layer. Then, the dummy gate structure of the second ring gate transistor formed above can be removed, and an insulating material can be deposited on the exposed surface of the second semiconductor structure to form a second gate dielectric layer. A metal material is then deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute the second gate structure.
[0103] In some embodiments, since the first semiconductor structure includes a first material layer and a second material layer stacked sequentially, when removing the portion of the dummy gate structure surrounding the first semiconductor structure, the oxide layer surrounding the first semiconductor structure and the first material layer in the first semiconductor structure can be removed simultaneously to form a second active structure of the second ring gate transistor. Then, an insulating material is deposited on the surface of the second active structure to form a second gate dielectric layer, and a metal material is deposited on the second gate dielectric layer to form a second gate electrode layer.
[0104] After forming the second gate structure, a portion of the second interlayer dielectric layer can be etched to expose the second source / drain structure. Subsequently, metal material is deposited on the second source / drain structure to form the second source / drain metal. After forming the second source / drain metal, subsequent processes can be performed to form the second metal interconnect layer.
[0105] In some embodiments, after forming the second gate structure of the second ring gate transistor, a second gate cut-off structure may be formed on both sides of the second gate structure.
[0106] In some embodiments, a second dielectric layer may be formed on the second gate structure and the second interlayer dielectric layer before the second source / drain metal is formed.
[0107] It should be noted that the fabrication methods of the second source / drain structure, second interlayer dielectric layer, second gate structure, second source / drain metal, second metal interconnect layer, second gate cut-off structure, and second dielectric layer of the second ring gate transistor are the same as those of the first source / drain structure, first interlayer dielectric layer, first gate structure, first source / drain metal, first metal interconnect layer, first gate cut-off structure, and first dielectric layer of the first ring gate transistor, and will not be repeated here.
[0108] In this embodiment, a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure are sequentially stacked on a substrate. Semiconductor material is deposited in the gate region to form a dummy gate structure. Then, the first sacrificial layer is removed to form a first trench. The first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the portion of the dummy gate structure above the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure are etched along a first direction to form a second trench. Subsequently, dielectric material is deposited in the first trench and the second trench to form an isolation layer at the location where the first sacrificial layer is removed, a first inner sidewall at the location where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the location where the first material layer in the first semiconductor structure is etched, and a sidewall at the location where the portion of the dummy gate structure above the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure is etched. Then, on the side of the isolation layer with the first inner sidewall and the sidewall, a first gate-around transistor is formed based on the second semiconductor structure. On the side of the isolation layer with the second inner sidewall, a second gate-around transistor is formed based on the first semiconductor structure. Therefore, by using the same medium material to simultaneously form the isolation layer, inner sidewall, and sidewall in the embodiments of this disclosure, redundant process steps and process complexity can be reduced.
[0109] The following describes the fabrication method of the stacked transistor provided in this disclosure, taking the active structure of the stacked transistor as a nanosheet structure as an example. Figure 2 is a top view of the stacked transistor in this disclosure embodiment. It should be noted that, for ease of understanding, only the nanosheet structure, gate structure, and source / drain structure are shown in the top view. Specifically, the AA' direction is the tangential direction of the stacked transistor along the gate structure; the BB' direction is the tangential direction of the stacked transistor along the source / drain structure; and the CC' direction is the tangential direction of the stacked transistor along the nanosheet structure.
[0110] The following describes the fabrication process of the stacked transistor provided in the embodiments of this disclosure. Figures 3A to 3L are schematic diagrams of the stacked transistor in the fabrication process of the embodiments of this disclosure, and Figure 4 is a schematic diagram of the stacked transistor in the embodiments of this disclosure.
[0111] Step 1: A fourth sacrificial layer 21 is formed on the original substrate 20, a stacked layer 22 is formed on the fourth sacrificial layer 21, a third sacrificial layer 23 is formed on the stacked layer 22, and then a stacked layer 22 is formed on the third sacrificial layer 23 (see (a) in Figure 3A).
[0112] For example, a Si layer can be provided, on which SiGe3 material is deposited to form a fourth sacrificial layer. Then, SiGe2 and Si materials are alternately deposited on the fourth sacrificial layer to form a stacked layer of a predetermined thickness. Next, SiGe1 material is deposited on the stacked layer to form a third sacrificial layer, and SiGe2 and Si materials are alternately deposited on the third sacrificial layer to form a stacked layer of a predetermined thickness. It should be noted that the SiGe1, SiGe2, and SiGe3 materials mentioned here are merely illustrative examples; other materials can actually be used.
[0113] Step 2: Etch stacked layer 22, third sacrificial layer 23 and fourth sacrificial layer 21 sequentially down to substrate 20 to form semiconductor structure 24 (see (b) in Figure 3A).
[0114] Understandably, etching can form a second sacrificial layer 244, a first semiconductor structure 241 close to the substrate, a second semiconductor structure 242 away from the substrate, and a first sacrificial layer 243.
[0115] Step 3: Deposit insulating material on substrate 20 to form isolation structure 25, and perform CMP and selective etching until the upper surface of the isolation structure is flush with the upper surface of the second sacrificial layer 244 (see (c) in Figure 3A).
[0116] Step 4: Form an oxide layer 26 on the substrate 20 (see (a) in Figure 3B).
[0117] Understandably, oxide layer 26 is a thin film deposited on the surface of semiconductor structure 24.
[0118] Step 5: Deposit polysilicon or other materials on oxide layer 26 to form pseudo gate structure 27 shared by front and back sides, and form protective layer 28 on pseudo gate structure 27 (see (b) in Figure 3B).
[0119] Understandably, by defining the gate regions of the front and back transistors in a stacked transistor using a pseudo-gate structure, self-alignment of the upper and lower transistors in the gate region can be achieved.
[0120] Step 6: Etch away the oxide layer 26 on the semiconductor structure in the source / drain region (see (c) in Figure 3B).
[0121] Step 7: Etch away the first semiconductor structure 241, the second semiconductor structure 242 and the first sacrificial layer 243 in the source and drain regions (see (a) in Figure 3C).
[0122] Step 8: Isotropically etch the first sacrificial layer 243 to form the first groove 281 (see (b) in Figure 3C).
[0123] Step 9: Laterally etch the SiGe 2 material in the first semiconductor structure and the second semiconductor structure to form the second groove 282, reserving space for the inner spacer (see (c) in Figure 3C).
[0124] Step 10: Laterally etch the pseudo-gate structure to form the second groove 282, reserving space for the gate spacer (see (a) in Figure 3D).
[0125] Step 11: Isotropic deposition medium material (see (b) in Figure 3D).
[0126] Step 12: Anisotropically etch the dielectric material in the source and drain regions to form the MDI layer 29, the first inner sidewall 30, the second inner sidewall 31, and the sidewall 32 (see (c) in Figure 3D).
[0127] It should be noted that the thickness of the MDI layer 29 should not exceed twice the thickness of the sidewall 32; otherwise, voids may easily occur inside the MDI layer during isotropic deposition.
[0128] Step 13: Etch protective layer 28 (see (a) in Figure 3E).
[0129] Step 14: Anisotropically etch the second sacrificial layer 244 and isolation structure 25 in the source / drain region (see (b) in Figure 3E).
[0130] Step 15: Fill the source and drain regions with insulating material to form a filling structure 33 covering the source and drain regions of the back transistor (see (c) in Figure 3E).
[0131] Step 16: Form source / drain isolation dielectric layer 34 on the filling structure 33 (see (a) in Figure 3F).
[0132] Step 17: Form the first source-drain structure 112 of the front-side transistor (see (b) in Figure 3F).
[0133] Step 18: Deposit interlayer medium in the source / drain region and etch back to form the first interlayer medium layer 113 (see (c) in Figure 3F).
[0134] Step 19: Etch the portion of the pseudo-gate structure 27 surrounding the second semiconductor structure (see (a) in Figure 3G).
[0135] Step 20: Form a gate isolation dielectric layer 35 on the retained pseudo-gate structure (see (b) in Figure 3G).
[0136] Understandably, the pseudo-gate structure can be oxidized at high temperature, and the channel will not be affected due to the protection of oxide layer 26.
[0137] Step 21: Remove the oxide layer surrounding the second semiconductor structure and the SiGe 2 material in the second semiconductor structure to form a first nanosheet structure 111, and form a first gate structure 114 of the front-side transistor based on the first nanosheet structure 111 (see (c) in Figure 3G).
[0138] Understandably, an insulating material is deposited on the surface of the first nanosheet structure 111 to form a first gate dielectric layer 1141, and a metal material is deposited on the first gate dielectric layer 1141 in the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute the first gate structure 114.
[0139] Step 22: Form a first gate cut-off structure 36 on both sides of the first gate structure (see (a) in Figure 3H).
[0140] Step 23: A first dielectric layer 37 is formed on the first gate structure 114 and the first interlayer dielectric layer 113, and a first source / drain metal 115 is formed on the first source / drain structure 112 (see (b) in Figure 3H).
[0141] Step 24: Form the first metal interconnect layer 116 (see (c) in Figure 3H).
[0142] Step 25: Deposit insulating material on the first metal interconnect layer 116 to form an insulating layer 13. After bonding the carrier wafer 14 to the insulating layer 13, flip the first ring gate transistor (see (a) in Figure 3I).
[0143] Step 26: Thin and CMP remove substrate 20 (see (b) in Figure 3I).
[0144] Step 27: Selectively etch the isolation structure 25 of the gate region to form the third groove 371 (see (c) in Figure 3I).
[0145] Step 28: Fill the third groove 371 with materials such as polysilicon to supplement the pseudo-gate structure formed above (see (a) in Figure 3J).
[0146] Step 29: Remove the fill structure 33 (see (b) in Figure 3J).
[0147] Step 30: Form the second source-drain structure 122 and the second interlayer dielectric layer 123 of the back transistor (see (c) in Figure 3J).
[0148] Step 31: Etch away the dummy gate structure of the back transistor (see (a) in Figure 3K).
[0149] Step 32: Fill the etched area with insulating material to replenish the gate isolation dielectric layer formed above (see (b) in Figure 3K).
[0150] Understandably, oxide can be formed by oxidizing the exposed pseudo-gate structure, so that the oxide acts as an isolation between the front and back gate structures, and the oxide layer 26 protects the channel during the thermal process.
[0151] Step 33: Remove the second sacrificial layer 244, the oxide layer surrounding the first semiconductor structure, and remove the SiGe 2 material in the first semiconductor structure to form the second nanosheet structure 121, and form the second gate structure 124 of the back transistor based on the second nanosheet structure 121 (see (c) in Figure 3K).
[0152] Understandably, an insulating material is deposited on the surface of the second nanosheet structure 121 to form a second gate dielectric layer 1241, and a metal material is deposited on the second gate dielectric layer 1241 to form a second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute the second gate structure 124.
[0153] Step 34: Form a second gate cut-off structure 38 on both sides of the second gate structure 124 (see (a) in Figure 3L).
[0154] Step 35: A second dielectric layer 39 is formed on the second gate structure 124 and the second interlayer dielectric layer 123, and a second source / drain metal 125 is formed on the second source / drain structure 122 (see (b) in Figure 3L).
[0155] Step 36: Form the second metal interconnect layer 126 (see Figure 4).
[0156] In this embodiment, the previously separate inner spacer process, MDI process, and gate spacer process are integrated. After etching the gaps in the gate spacer and inner spacer and removing the MDI sacrificial layer, an isotropic dielectric material is deposited and anisotropic etching is performed to fill the gaps between the channels of the front and back transistors to form the MDI layer. The lateral etched gaps are then filled to form the gate spacer and inner spacer. By using the same dielectric material to simultaneously form the gate spacer, inner spacer, and MDI layer, redundant process steps are reduced, and process complexity is lowered. Furthermore, the problem of difficult back etching of the dielectric material in the MDI and inner spacer processes is avoided. The method of this embodiment is beneficial for improving process success rate and transistor electrical performance.
[0157] In some embodiments, the stacked transistors provided in this disclosure can be inspected using analytical instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, this disclosure can use TEM slicing to inspect the structure of the stacked transistors.
[0158] This disclosure provides a semiconductor device, including: a stacked transistor as described in the above embodiments.
[0159] This disclosure provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board, the semiconductor device including the stacked transistors described above.
[0160] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0161] The above description is merely an exemplary embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for fabricating stacked transistors, comprising: A semiconductor structure is formed on a substrate, the semiconductor structure comprising a first semiconductor structure, a first sacrificial layer and a second semiconductor structure stacked sequentially along a first direction, the first semiconductor structure comprising a first material layer and a second material layer stacked sequentially along the first direction, and the second semiconductor structure comprising a first material layer and a second material layer stacked sequentially along the first direction. Semiconductor material is deposited in the gate region to form a dummy gate structure, the dummy gate structure surrounding the second semiconductor structure, the first sacrificial layer, and the first semiconductor structure, the height of the dummy gate structure being greater than the height of the semiconductor structure; Remove the first sacrificial layer to form the first groove; The first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the portion of the dummy gate structure that is higher than the semiconductor structure are etched along a second direction to form a second groove, wherein the second direction is perpendicular to the first direction; Dielectric material is deposited in the first groove and the second groove to form an isolation layer at the location where the first sacrificial layer is removed, a first inner sidewall at the location where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the location where the first material layer in the first semiconductor is etched, and a sidewall at the location where the portion of the pseudo-gate structure above the semiconductor structure is etched. On one side of the isolation layer having the first inner sidewall and the sidewall, a first gate ring transistor is formed based on the second semiconductor structure; On the side of the isolation layer with the second inner wall, a second ring gate transistor is formed based on the first semiconductor structure.
2. The method according to claim 1, wherein, The deposition of dielectric material in the first and second grooves to form an isolation layer at the location where the first sacrificial layer is removed, a first inner sidewall at the location where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the location where the first material layer in the first semiconductor is etched, and a sidewall at the location where the portion of the dummy gate structure above the semiconductor structure is etched includes: A dielectric material is deposited on the substrate to cover the pseudo-gate structure; Anisotropic etching is used to etch the dielectric material in the source and drain regions to form the isolation layer, the first inner sidewall, the second inner sidewall, and the sidewall, respectively.
3. The method according to claim 1, wherein, The method of forming a first gate-ring transistor based on the second semiconductor structure includes: Remove the semiconductor structure in the source / drain region and fill the first source / drain region corresponding to the first semiconductor structure with insulating material to form a filled structure; A first source / drain structure is epitaxially grown at the second source / drain region corresponding to the second semiconductor structure; A first interlayer dielectric layer is formed on the first source-drain structure; The portion of the dummy gate structure surrounding the second semiconductor structure is etched to form the first gate structure; The first interlayer dielectric layer is etched to expose the first source / drain structure; Metallic material is deposited on the first source / drain structure to form the first source / drain metal; Back-end interconnects are performed on the first source / drain metal to form a first metal interconnect layer.
4. The method according to claim 3, wherein, The method further includes: A source / drain isolation dielectric layer is formed on the filling structure, and the height of the source / drain isolation dielectric layer is the same as the height of the isolation layer. The first source-drain structure is formed on the source-drain isolation dielectric layer.
5. The method according to claim 3, wherein, The etching of the portion of the dummy gate structure surrounding the second semiconductor structure to form the first gate structure includes: Etch the portion of the pseudo-gate structure surrounding the second semiconductor structure; A gate isolation dielectric layer is formed on the retained pseudo-gate structure; On the gate isolation dielectric layer, the first material layer in the second semiconductor structure is etched to form the first active structure; The first gate structure is formed based on the first active structure.
6. The method according to claim 1, wherein, The semiconductor structure further includes a second sacrificial layer, which is located between the substrate and the first semiconductor structure. The second sacrificial layer has isolation structures on both sides, and the height of the isolation structures is the same as the height of the second sacrificial layer. After forming the first ring-gate transistor based on the second semiconductor structure, the method further includes: The first ring gate transistor is flipped, and the substrate is removed; Remove the isolation structure to form a third groove; Semiconductor material is filled into the third groove so that the upper surface of the formed pseudo-gate structure is flush with the upper surface of the second sacrificial layer. The second gate ring transistor is formed based on the first semiconductor structure.
7. The method according to claim 3, wherein, After forming the first gate structure, the method further includes: Gate cut-off structures are formed on both sides of the first gate structure, and the gate cut-off structures are used to isolate the gate region of the stacked transistor from the gate region of the adjacent stacked transistor.
8. A stacked transistor, said stacked transistor being fabricated using the method of any one of claims 1 to 7, comprising: First ring gate transistor; The second gate ring transistor is stacked with the first gate ring transistor and the second gate ring transistor, and the first gate ring transistor and the second gate ring transistor are self-aligned.
9. A semiconductor device, comprising: The stacked transistor as described in claim 8.
10. An electronic device, comprising: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.