Display substrate, display panel, and display apparatus
Patent Information
- Application Number
- PCT/CN2026/072092
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-24
- Filing Date
- 2026-01-13
- Publication Date
- 2026-08-27
Smart Images
Figure CN2026072092_27082026_PF_FP_ABST
Abstract
Description
Display substrate, display panel and display device
[0001] Cross-references to related applications
[0002] This application claims priority to Chinese Patent Application No. 202510205683.2, filed in China on February 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of display product manufacturing technology, and in particular to a display substrate, display panel, and display device. Background Technology
[0004] As display technology develops in depth and users increasingly utilize it, the unlocking of more usage scenarios forces AMOLED manufacturers to conduct more in-depth research into the working mechanism of their products and optimize their designs to enhance product competitiveness.
[0005] LTPS AMOLED (Low Temperature Polycrystalline Silicon Active Matrix Organic Light Emitting Diode) displays exhibit color shift due to the influence of photocurrent on node voltage under strong light and wide-angle (above 45°) illumination. Summary of the Invention
[0006] To address the aforementioned technical problems, this disclosure provides a display substrate, a display panel, and a display device, which solve the problem of color distortion caused by photocurrent affecting node voltage when the display screen is illuminated by strong light at a large angle (above 45°).
[0007] To achieve the above objectives, the technical solution adopted in this disclosure embodiment is: a display substrate, wherein multiple data lines and multiple gate lines are disposed on the display substrate, the multiple data lines and multiple gate lines intersect to define multiple pixel areas, and pixel circuits and light-emitting devices are disposed in the pixel areas, wherein the pixel circuits include a first transistor and a capacitor;
[0008] The display substrate includes a substrate and a driving circuit layer located on the substrate, the driving circuit layer including the pixel circuit;
[0009] The driving circuit layer includes a semiconductor layer, a first conductive metal layer, and a metal shielding structure stacked along a direction away from the substrate. The semiconductor layer includes the active layer of the first transistor. The first conductive metal layer includes the gate of the first transistor and the first plate of the capacitor. The orthogonal projection of the gate on the active layer is located in the middle region of the active layer.
[0010] The metal shielding structure is configured to block the incident of external ambient light into the middle region. In a first direction parallel to the extending direction of the gate line, the metal shielding structure has a first side, and the middle region has a second side located on the same side as the first side. In the first direction, the distance between the first side and the second side is △C;
[0011] △C > h1tanθ1 +... + h N tanθ N , where h1 is the thickness of the non-metal layer between the active layer and the first conductive metal layer, h N is the thickness of the (N - 1)th non-metal layer between the first conductive metal layer and the metal shielding structure, θ1 is the refraction angle of the light entering the non-metal layer between the active layer and the first conductive metal layer, θ N is the refraction angle of the light entering the (N - 1)th non-metal layer between the first conductive metal layer and the metal shielding layer, and N is a positive integer greater than or equal to 2.
[0012] Optionally, according to the formula n0sinθ0 = n1sinθ1 = n N sinθ N , θ1 and θ are obtained N , where n0 = 1, n1 is the refractive index of the non-metal layer between the active layer and the first conductive metal layer, n N is the refractive index of the (N - 1)th non-metal layer between the first conductive metal layer and the metal shielding structure, θ0 is the incident angle of the light onto the display substrate, θ0 > 60 degrees, and θ N is the refraction angle of the light in the (N - 1)th non-metal layer between the first conductive metal layer and the metal shielding structure.
[0013] Optionally, a metal shielding layer is provided between the driving circuit layer and the substrate. The metal shielding layer at least overlaps with the middle region of the active layer. In the first direction, the metal shielding layer has a third side located on the same side as the second side. In the first direction, the distance between the third side and the second side is △B, and the distance between the third side and the first side is △D;
[0014] △B < h′1tanθ′1, or △D > h′1tanθ′1 + h′2tanθ′2 +... + h′ M tanθ′ M ;
[0015] ″
[0016] Where h′1 is the thickness of the non-metallic layer between the metal shielding layer and the active layer, θ′1 is the refraction angle of light entering the non-metallic layer between the metal shielding layer and the active layer, h′2 is the overall thickness of the non-metallic layer between the active layer and the first conductive metal layer, and θ′2 is the refraction angle of light entering the non-metallic layer between the active layer and the first conductive metal layer. M θ′ is the thickness of the (M-2)th non-metallic layer between the first conductive metal layer and the metal shielding structure. M The angle of refraction is the angle at which light enters the (M-2)th non-metallic layer between the first conductive metal layer and the metal shielding layer, where M is a positive integer greater than or equal to 3.
[0017] Alternatively, according to the formula n0sinθ0=n1sinθ′1=n2sinθ′2=n M sinθ′ M To obtain θ′1, θ′2, θ M Where n0 = 1, n1 is the refractive index of the non-metallic layer between the metal shielding layer and the active layer, and n2 is the refractive index of the non-metallic layer between the active layer and the first conductive metal layer. M θ0 is the refractive index of the (M-2)th non-metallic layer between the first conductive metal layer and the metal shielding layer; θ0 is the incident angle of light onto the display substrate, θ0 > 60 degrees; θ′1 is the angle of refraction of light onto the non-metallic layer between the metal shielding layer and the active layer; θ′2 is the angle of refraction of light onto the non-metallic layer between the active layer and the first conductive metal layer; θm is the refractive index of the non-metallic layer between the first conductive metal layer and the active ... M .
[0018] Optionally, the driving circuit layer includes a second conductive metal layer located on the side of the first conductive metal layer away from the substrate, the second conductive metal layer including the second electrode plate of the capacitor, and the second electrode plate being reused as the metal shielding structure.
[0019] Optionally, the driving circuit layer further includes a third conductive metal layer, which includes data lines and power lines. In the first direction, the power lines are located on the side of the data lines closer to the first transistor, and the power lines are multiplexed as the metal shielding structure.
[0020] Optionally, a light-emitting functional layer is provided on the driving circuit layer, the light-emitting functional layer including a plurality of light-emitting devices, the light-emitting devices including a first electrode, a light-emitting material layer and a second electrode stacked along the substrate away from the substrate;
[0021] The first electrode is reused as the metal shielding structure, or the second electrode is reused as the metal shielding structure.
[0022] Optionally, a touch function layer is provided on the side of the light-emitting functional layer away from the substrate. The touch function layer includes a touch metal layer, and the touch metal layer includes a touch pattern superimposed on the intermediate region. The touch pattern is reused as the metal shielding structure.
[0023] Optionally, the pixel circuit is a 2T1C circuit, or a 3T1C circuit, or a 3T2C circuit, or a 7T1C circuit or a 7T2C circuit.
[0024] This disclosure also provides a display panel, including the display substrate described above.
[0025] This disclosure also provides a display device, including the display panel described above.
[0026] The beneficial effects of this disclosure are: by setting the metal shielding structure, ambient light is blocked, especially large-angle ambient light is blocked from entering the active layer of the first transistor in the pixel circuit, so as to avoid the photocurrent generated by the first transistor from affecting the node voltage, thereby improving the color shift problem. Attached Figure Description
[0027] Figure 1 shows the equivalent circuit diagram of the 7T1C pixel circuit;
[0028] Figure 2 shows a schematic diagram of the positional relationship between the active layer and the gate.
[0029] Figure 3 shows a schematic diagram of the display substrate structure;
[0030] Figure 4 shows a schematic diagram of the display substrate structure;
[0031] Figure 5 shows a schematic diagram of the display substrate structure;
[0032] Figure 6 shows a schematic diagram of the display substrate structure;
[0033] Figure 7 shows a schematic diagram of the positional relationship between the touch metal layer and the active layer of the first transistor in the related technology;
[0034] Figure 8 shows a schematic diagram of a simulated structure in which light incident at -45 degrees exhibits color shift;
[0035] Figure 9 shows a schematic diagram of a simulated structure in which color shift occurs when light is incident at 45 degrees.
[0036] Figure 10 shows a schematic diagram of the positional relationship between the touch metal layer and the active layer of the first transistor in an embodiment of this disclosure;
[0037] Figure 11 shows a schematic diagram of the substrate. Detailed Implementation
[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0040] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of said value.
[0041] Furthermore, throughout this document, unless otherwise defined, the terms “substantially,” “essentially,” “approximately,” and “about” are used to describe and explain small variations. When used with an event or situation, these terms can cover situations where the event or situation occurs precisely or approximately. For example, when used with a numerical value, these terms can include a range of variation of the numerical value less than or equal to 10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces arranged along the same plane within a micrometer range, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm.
[0042] The display substrate includes multiple pixel regions defined by the intersection of data lines and gate lines. Each pixel region contains a pixel circuit to drive the corresponding pixel for display. The pixel circuit can be a 2T1C circuit, a 3T1C circuit, a 3T2C circuit, a 7T1C circuit, or a 7T2C circuit. Figure 1 shows an equivalent circuit diagram of a 7T1C pixel circuit. The 7T1C pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The 7T1C pixel circuit also includes an organic light-emitting diode (OLED), a first voltage terminal VDD, a second voltage terminal VSS, a first reset voltage terminal Vinit1, a second reset voltage terminal Vinit2, a scan signal terminal SN (Gate), a first light-emitting control signal terminal EM, a second light-emitting control signal terminal EM2(n), a third light-emitting control signal terminal EM2(n-7), a data input terminal Data (Vref), and nodes N1, N2, and N3.
[0043] The gate electrode of the first transistor T1 is connected to the third light-emitting control signal terminal EM2(n-7). The first electrode of the first transistor T1 is connected to the first reset voltage terminal Vinit1. The second electrode of the first transistor T1 is connected to the first plate of capacitor C. The gate electrode of the second transistor T2 is connected to the second light-emitting control signal terminal EM2(n). The first electrode of the second transistor T2 is connected to the first plate of capacitor C. The second electrode of the second transistor T2 is connected to the second electrode of the sixth transistor T6. The gate electrode of the third transistor T3 is connected to the first plate of capacitor C. The first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4. The second electrode of the third transistor T3 is connected to the second electrode of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the gate line Gate. The first electrode of transistor 4 is connected to the data line Date. The gate electrode of the fifth transistor T5 is connected to the first light-emitting control signal terminal EM. The first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD. The second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3. The gate electrode of the sixth transistor T6 is connected to the first light-emitting control signal terminal EM. The second electrode of the sixth transistor T6 is connected to the anode of the light-emitting device. The gate electrode of the seventh transistor T7 is connected to the gate line Gate. The first electrode of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2. The second electrode of the seventh transistor T7 is connected to the anode of the light-emitting device (organic light-emitting diode OLED). The second plate of capacitor C is connected to the first power supply terminal VDD. The cathode of the light-emitting device OLED is connected to the second power supply terminal VSS.
[0044] The second transistor, T2, is a P-type transistor. Incident light enters through the gate of the second transistor, generating electron-hole pairs in the depletion region. Holes drift towards the channel and the P-substrate, while electrons accumulate in the n-well due to the high potential barrier. These accumulated electrons lower the potential barrier of the n-well, resulting in a more negative gate voltage because the gate is connected to the n-well. The current flowing from the second transistor T2 to the N1 node increases (as shown in Figure 1, where the thick blue arrow indicates the direction of leakage), the potential of the N1 node rises, and the brightness decreases.
[0045] In the design and production of LTPS (Low-Temperature Polycrystalline Silicon) products with BSM (Metal Shielding Layer), due to the different TFTs controlling RGB and the differences in the edge design of the RGB metal film layer, when strong light shines from a wide viewing angle, light of varying degrees will directly or indirectly (reflected by the BSM) shine onto the Poly (Polycrystalline Silicon Active Layer) where the second transistor T2 is located, thus generating photocurrent and causing a disproportionate decrease in RGB brightness, resulting in reduced brightness and color distortion under strong light.
[0046] Referring to Figures 2-11, in view of the above-mentioned technical problems, this disclosure provides a display substrate, wherein multiple data lines and multiple gate lines are disposed on the display substrate, and the multiple data lines and multiple gate lines intersect to define multiple pixel areas. Pixel circuits and light-emitting devices are disposed in the pixel areas. The pixel circuit includes a first transistor (i.e., the second transistor T2 shown in Figure 1) and a capacitor. The gate of the first transistor is connected to the light-emitting control signal line, the first electrode of the first transistor is connected to the first electrode plate of the capacitor, and the second electrode plate of the capacitor is connected to the power supply line VDD.
[0047] The display substrate includes a substrate and a driving circuit layer located on the substrate, the driving circuit layer including the pixel circuit;
[0048] The driving circuit layer includes a semiconductor layer, a first conductive metal layer 2, and a metal shielding structure stacked along a direction away from the substrate. The semiconductor layer includes the active layer 1 of the first transistor. The first conductive metal layer 2 includes the gate of the first transistor and the first plate of the capacitor. The orthogonal projection of the gate on the active layer 1 is located in the middle region 101 of the active layer 1.
[0049] The metal shielding structure is configured to block ambient light from entering the intermediate region 101. In a first direction (refer to the Y direction in FIG2) parallel to the extension direction of the grid line, the metal shielding structure has a first side, and the intermediate region 101 has a second side located on the same side as the first side. In the first direction, the distance between the first side and the second side is ΔC.
[0050] △C>h1tanθ1+。 。 。 +h N tanθ N Where h1 is the thickness of the non-metallic layer between the active layer 1 and the first conductive metal layer 2, h N θ1 is the thickness of the (N-1)th non-metallic layer between the first conductive metal layer 2 and the metal shielding structure, and θ1 is the refraction angle of light entering the non-metallic layer between the active layer 1 and the first conductive metal layer 2. N The angle of refraction is the angle at which light enters the (N-1)th non-metallic layer between the first conductive metal layer 2 and the metal shielding layer, where N is a positive integer greater than or equal to 2.
[0051] Figure 2 is a schematic diagram showing the positional relationship between the gate of the second transistor and the polysilicon active layer 1, and Figure 3 is a partial structural schematic diagram of the display substrate. The overlapping position of the polysilicon active layer 1 and Gate 1 constitutes a TFT. In embodiments where the active layer 1 and the substrate do not have a metal shielding layer 4, strong light directly illuminates the central region 101 of the active layer 1 of the transistor from a wide viewing angle. To prevent strong external light from illuminating the central region 101 of the active layer 1, a metal shielding structure is provided on the side of the first conductive metal layer 2 away from the substrate. The metal shielding structure can be provided separately. To save on process time and reduce the impact on the transmittance of the display substrate, the circuit structure located on the side of the first conductive metal layer 2 away from the substrate can be reused as the metal shielding structure. Preferably, in this embodiment, the circuit structure located on the side of the first conductive metal layer 2 away from the substrate is reused as the metal shielding structure.
[0052] In order to more effectively reduce the impact on the transmittance of the display substrate, the circuit structure close to the active layer 1 in the first direction can be improved (e.g., the line width can be increased) to reuse the metal shielding structure.
[0053] The simplified light transmission model is a parallel plate transmission model. Light passes through the gaps in the metal film layer, i.e., through an optical parallel plate composed of multiple non-metallic film layers, and then illuminates the middle region 101 of the active layer 1 of the second transistor. The transmission path of light directly illuminating the middle region 101 is shown in Figure 3. The transmission path shown in Figure 3 represents the critical situation where external light is about to be unable to illuminate the middle region 101 of the active layer 1 of the second transistor. In other words, as long as the edge distance of the metal shielding structure relative to the middle region 101 (the length of the portion of the metal shielding structure exposed in the middle region 101 on one side of the middle region 101, i.e., ΔC) is greater than the critical transmission path, the edge distance of the metal shielding structure relative to the middle region 101 (refer to the critical edge distance L in Figure 3) can effectively block external light from illuminating the middle region 101 of the active layer 1 of the second transistor, thereby improving the color shift problem of the display screen.
[0054] According to the law of refraction in optics, we can obtain the formula n0sinθ0=n1sinθ1=n N sinθ n According to the formula n0sinθ0=n1sinθ1=n N sinθ N To obtain θ1 and θ N Where n0 = 1, n1 is the refractive index of the non-metallic layer between the active layer 1 and the first conductive metal layer 2, and n Nθ0 is the refractive index of the thickness of the (N-1)th non-metallic layer between the first conductive metal layer 2 and the metal shielding structure, and θ0 is the incident angle of light onto the display substrate, where θ0 > 60 degrees. N The angle of refraction of light is the (N-1)th non-metallic layer between the first conductive metal layer 2 and the metal shielding structure.
[0055] Based on the obtained θ1 and θ N Therefore, according to the formula △C>h1tanθ1+...+h... N tanθ N , obtain the distance △C between the first side and the second side in the first direction.
[0056] Referring to Figure 3, a non-metallic layer, i.e., N=2, is included between the first conductive metal layer 2 and the metal shielding structure. Therefore, in the first direction, the critical value between the first edge and the second edge can be obtained using the formula h1tanθ1+h2tanθ2, where h1 is the thickness of the non-metallic layer (which is the first gate insulating layer) between the active layer 1 and the first conductive metal layer 2, and h2 is the thickness of the non-metallic layer (which is the second gate insulating layer) between the first conductive metal layer 2 and the metal shielding structure. Where θ1 and θ2 are... N2 The distance ΔC between the first side and the second side in the first direction can be obtained by using the formula n0sinθ0=n1sinθ1=n2sinθ2.
[0057] It should be noted that in the structure with the metal shielding layer 4BSM, there are two situations where light is incident on the intermediate region 101 of the active layer 1 of the second transistor: 1. Directly irradiating the intermediate region 101; 2. Irradiating the intermediate region 101 after being reflected by the metal shielding layer 4. Figure 3 illustrates the critical situation where light directly irradiates the intermediate region 101, and Figure 4 shows the critical situation where light is reflected by the metal shielding layer 4 onto the intermediate region 101. Comparing the two situations above, it can be seen that the edge distance of the metal shielding layer required for light to be reflected by the metal shielding layer 4 onto the intermediate region 101 is larger. Therefore, as long as this situation is met, the occurrence of strong light color distortion can be avoided.
[0058] In an exemplary embodiment, a metal shielding layer 4 is disposed between the driving circuit layer and the substrate. The metal shielding layer 4 overlaps at least with the intermediate region 101 of the active layer 1. In the first direction, the metal shielding layer 4 has a third side located on the same side as the second side. In the first direction, the distance between the third side and the second side is ΔB, and the distance between the third side and the first side is ΔD.
[0059] △B < h′1tanθ′1, or △D > h′1tanθ′1 + h′2tanθ′2 +... + h′ M tanθ′ M ;
[0060] where h′1 is the thickness of the non - metal layer between the metal shielding layer 4 and the active layer 1, θ′1 is the refraction angle of light entering the non - metal layer between the metal shielding layer 4 and the active layer 1, h′2 is the overall thickness of the non - metal layer between the active layer 1 and the first conductive metal layer 2, θ′2 is the refraction angle of light entering the non - metal layer between the active layer 1 and the first conductive metal layer 2, h′ M is the thickness of the (M - 2)th non - metal layer between the first conductive metal layer 2 and the metal shielding structure, θ′ M is the refraction angle of light entering the (M - 2)th non - metal layer between the first conductive metal layer 2 and the metal shielding layer, and M is a positive integer greater than or equal to 3.
[0061] Exemplarily, according to the formula n0sinθ0 = n1sinθ′1 = n2sinθ′2 = n M sinθ′ M , θ′1, θ′2, θ M are obtained, where n0 = 1, n1 is the refractive index of the non - metal layer between the metal shielding layer 4 and the active layer 1, n2 is the refractive index of the non - metal layer between the active layer 1 and the first conductive metal layer 2, n M is the refractive index of the (M - 2)th non - metal layer between the first conductive metal layer 2 and the metal shielding layer, and θ0 is the incident angle of light onto the display substrate, and θ0 > 60 degrees.
[0062] Referring to FIG. 4, there is a non - metal layer between the first conductive metal layer 2 and the metal shielding structure, that is, M = 3. In the first direction, the critical value of the distance between the third side and the second side can be obtained according to h′1tanθ′1. Further, based on this critical value, the distance △B between the third side and the second side can be determined. The critical value of the distance between the third side and the first side can be obtained according to the formula h′1tanθ′1 + h′2tanθ′2 +... + h′ M tanθ′ M is obtained. Further, based on this critical value, the distance △D between the third side and the first side can be determined. Extend the metal shielding structure and increase the edge - wrapping distance of the metal shielding structure so that △D between the third side and the first side is greater than the critical value, then light can be blocked from entering the metal shielding layer at the metal shielding structure.
[0063] In an exemplary embodiment, the driving circuit layer includes a second conductive metal layer 3 located on the side of the first conductive metal layer 2 away from the substrate. The second conductive metal layer 3 includes the second electrode plate of the capacitor, and the second electrode plate is reused as the metal shielding structure.
[0064] Referring to Figure 5, a metal shielding layer 4 is disposed on the substrate, a buffer layer is disposed on the metal shielding layer 4, an active layer 1 is disposed on the side of the buffer layer away from the substrate, a first gate insulating layer GI1 is disposed on the active layer 1, a first conductive metal layer 2 is disposed on the first gate insulating layer GI1, the first conductive metal layer 2 includes a gate 1 and a first electrode of a capacitor, a second gate insulating layer GI2 is disposed on the first conductive metal layer 2, a second conductive metal layer 3 is disposed on the side of the second gate insulating layer GI2 away from the substrate, the second conductive metal layer 3 includes a second substrate of a capacitor (i.e., Gate 2 in Figure 5), an interlayer insulating layer ILD is disposed on the side of the second conductive metal layer 3 away from the substrate, and the other film layer structures of the side of the interlayer insulating layer ILD away from the substrate can be referred to Figure 11.
[0065] For example, the length of the second electrode plate can be increased in the first direction so that it can be reused as the metal shielding structure.
[0066] In an exemplary embodiment, the driving circuit layer further includes a third conductive metal layer 6, which includes data lines and power lines. In the first direction, the power lines are located on the side of the data lines closer to the first transistor, and the power lines are multiplexed as the metal shielding structure.
[0067] The data line and the power line are arranged in the same direction. In the first direction, the power line VDD is closer to the active layer 1 than the data line. By using the power line VDD as the metal shielding structure, the impact on the transmittance of the display screen can be reduced.
[0068] Referring to Figure 6, a metal shielding layer 4 is disposed on the substrate, a buffer layer is disposed on the metal shielding layer 4, an active layer 1 is disposed on the side of the buffer layer away from the substrate, a first gate insulating layer GI1 is disposed on the active layer 1, a first conductive metal layer 2 is disposed on the first gate insulating layer GI1, the first conductive metal layer 2 includes a gate 1 and a first electrode of a capacitor, a second gate insulating layer GI2 is disposed on the first conductive metal layer 2, and a second conductive metal layer 3 is disposed on the side of the second gate insulating layer GI2 away from the substrate. Layer 3 includes a second substrate for the capacitor (i.e., Gate 2 in Figure 5). An interlayer insulating layer (ILD) is disposed on the side of the second conductive metal layer 3 away from the substrate. A metal layer (SD1) (including interconnecting traces) is disposed on the side of the interlayer insulating layer (ILD) away from the substrate. A first planarization layer (PLN1) is disposed on the metal layer (SD1). A third conductive metal layer (6SD2) is disposed on the first planarization layer (PLN1). A second planarization layer (PLN2) is disposed on the third conductive metal layer (6SD2). The other film layer structures on the side of the second planarization layer (PLN2) away from the substrate can be referred to Figure 11.
[0069] For example, the power line VDD includes a first portion covering the active layer 1. In the extending direction of the power line VDD, the power line VDD includes a second portion and a third portion adjacent to the first portion. In the first direction, the width of the first portion is greater than the width of the second portion, and the width of the first portion is greater than the width of the third portion. That is, in order to allow the power line VDD to be reused as the metal shielding structure, the width of the power line VDD corresponding to a local location in the active layer 1 of the second transistor is widened, which can further reduce the impact on the transmittance of the display screen.
[0070] It should be noted that the multiple pixel areas on the display substrate are arranged in an array, and the power line VDD is arranged in the same direction as the data line. The power line VDD can provide power to the pixel circuits of the multiple pixel areas arranged along the extension direction of the data line. That is, the extension direction of the power line VDD includes multiple first parts. In the middle region 101 of the display substrate, the second part or the third part can be located between two adjacent first parts. In the edge region of the display substrate, the second part or the third part is located on the side of the first part closer to the edge of the display substrate.
[0071] In an exemplary embodiment, a light-emitting functional layer is disposed on the driving circuit layer, the light-emitting functional layer including a plurality of light-emitting devices, the light-emitting devices including a first electrode, a light-emitting material layer and a second electrode stacked along the substrate away from the substrate;
[0072] The first electrode is reused as the metal shielding structure, or the second electrode is reused as the metal shielding structure.
[0073] In an exemplary embodiment, a touch function layer 7 is provided on the side of the light-emitting functional layer away from the substrate. The touch function layer includes a touch metal layer, and the touch metal layer includes a touch pattern superimposed on the intermediate region 101. The touch pattern is reused as the metal shielding structure.
[0074] In a conventional structure, the touch pattern and the middle region 101 of the active layer 1 do not overlap, or only partially overlap (refer to Figure 7). The color shift is most severe when light is incident on the display substrate from a direction of θ = 45° & -45°. Simulation results (Figures 8 and 9) show that the light mainly enters through the junction of the middle region 101 of the active layer 1 and the gate (the high-risk position in Figure 7), and after reflection by the monitoring shielding layer, it illuminates the middle region 101 of the active layer 1, thus causing color shift. This embodiment utilizes a metal film layer structure TMB (touch metal layer) that is further away from the second transistor in a direction perpendicular to the substrate to achieve a special angle of shielding design. As shown in Figure 10, by adjusting the relative position of the touch pattern of the touch metal layer with the middle region 101 of the active layer 1 and the gate, the high-risk position shown in Figure 7 is adjusted to the center of the touch pattern, maximizing the shielding of light incident on the high-risk position.
[0075] The touch pattern includes multiple repeating sub-touch patterns. Each sub-touch pattern includes a straight portion 71 extending along the data line's extension direction and V-shaped portions 72 located at opposite ends of the straight portion 71. The two V-shaped portions 72 are symmetrically arranged relative to the straight portion 71. In a direction perpendicular to the data line's extension direction (refer to the Y direction in Figure 7), the width of the straight portion 71 is greater than the width of the middle region 101 of the active layer 1. In the data line's extension direction (refer to the X direction in Figures 2 and 7), the length of the straight portion 71 is greater than the width of the middle region 101 of the active layer 1. This allows the touch pattern to completely cover the middle region 101 of the active layer 1, blocking ambient light from directly or indirectly incident (reflected by the metal shielding layer 4) onto the middle region 101.
[0076] For example, in the direction perpendicular to the extension direction of the data line, the width of the straight portion 71 is 2.5 to 5 μm wider than the width of the middle region 101 of the active layer 1. Without affecting other screen functions such as transmittance, the increased line width results in a better occlusion effect.
[0077] To achieve a better shielding effect, widening the traces at fixed positions is also included in this embodiment. That is, as long as the touch pattern can completely cover the middle area 101 of the active layer 1, the entire sub-touch pattern can be widened, or a local part of the sub-touch pattern can be widened, for example, the straight part 71 can be widened at least in the direction perpendicular to the extension of the data line, but it is not limited to this.
[0078] Figure 11 is a schematic diagram of the display substrate of this embodiment. The method for manufacturing the display substrate in this embodiment includes:
[0079] Provide a substrate;
[0080] A metal shielding layer BSM is disposed on the substrate, and the thickness of the metal shielding layer 4 is 0.05-0.2um;
[0081] A buffer layer is formed on the metal shielding layer 4, the thickness of the buffer layer is 0.5-1 μm, and the refractive index of the buffer layer is 1.5-2;
[0082] An active layer 1 is formed on the buffer layer, and the thickness of the active layer 1 is 0.02-0.15.
[0083] A first gate insulating layer GI1 is formed on the active layer 1. The thickness of the first gate insulating layer is 0.05-0.15 μm, and the refractive index of the first gate insulating layer is 1.3-2.
[0084] A first conductive metal layer 2 Gate1, comprising a gate and a capacitor, is formed on the first gate insulating layer, wherein the thickness of the first conductive metal layer 2 is 0.2-0.5 μm;
[0085] A second gate insulating layer GI2 is formed on the first conductive metal layer 2. The thickness of the second gate insulating layer GI2 is 0.1-0.2 μm, and the refractive index of the second gate insulating layer is 1.3-2.
[0086] A second conductive metal layer 3 Gate2, including a second electrode plate with a capacitor, is formed on the second gate insulating layer, and the thickness of the second conductive metal layer 3 is 0.2-0.5 μm;
[0087] An interlayer dielectric layer (ILD) is formed on the second conductive metal layer 3, the thickness of the interlayer dielectric layer is 0.2-1 μm, and the refractive index of the interlayer dielectric layer is 1.3-2.
[0088] A fourth conductive metal layer SD1, including interconnecting traces, is formed on the interlayer dielectric layer, and the thickness of the third conductive metal layer 6 is 0.5-1.5 μm;
[0089] A first planarization layer PLN1 is formed on the third conductive metal layer 6. The thickness of the first planarization layer is 1-2.5, and the refractive index of the first planarization layer is 1.4-2.
[0090] A third conductive metal layer 6SD2 is formed on the first planarization layer, and the thickness of the third conductive metal layer 6 is 0.5-1.5 μm;
[0091] A second planarization layer PLN2 is formed on the third conductive metal layer 6. The thickness of the second planarization layer is 1-2.5, and the refractive index of the second planarization layer is 1.4-2.
[0092] A light-emitting functional layer is formed on the second planarization layer, the light-emitting functional layer including a plurality of light-emitting devices, the light-emitting devices including stacked anodes, light-emitting material layers and cathodes;
[0093] A touch function layer 7 is formed on the light-emitting functional layer, and the touch function layer 7 includes a touch metal layer TMA, a touch insulating layer TLD, and a touch metal layer TMB.
[0094] This disclosure also provides a display panel, including the display substrate described above.
[0095] This disclosure also provides a display device, including the display panel described above.
[0096] The display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will understand that the structure of the display device described above does not constitute a limitation on the display device; the display device may include more or fewer of the aforementioned components, or combine certain components, or arrange different components. In the embodiments of this disclosure, the display device includes, but is not limited to, a monitor, a mobile phone, a tablet computer, a television set, a wearable electronic device, a navigation display device, etc.
[0097] The display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes a flexible circuit board, a printed circuit board, and a backplate.
[0098] The following points need to be explained:
[0099] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.
[0100] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.
[0101] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
[0102] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. A display substrate, characterized in that, The display substrate has multiple data lines and multiple gate lines, which intersect to define multiple pixel areas. Pixel circuits and light-emitting devices are disposed within each pixel area. The pixel circuits include a first transistor and a capacitor. The display substrate includes a substrate and a driving circuit layer located on the substrate, the driving circuit layer including the pixel circuit; The driving circuit layer includes a semiconductor layer, a first conductive metal layer, and a metal shielding structure stacked along a direction away from the substrate. The semiconductor layer includes the active layer of the first transistor. The first conductive metal layer includes the gate of the first transistor and the first plate of the capacitor. The orthogonal projection of the gate on the active layer is located in the middle region of the active layer. The metal shielding structure is configured to block ambient light from entering the intermediate region. In a first direction parallel to the extension direction of the grid line, the metal shielding structure has a first side, and the intermediate region has a second side located on the same side as the first side. In the first direction, the distance between the first side and the second side is ΔC. △C>h1tanθ1+。 。 。 +h N tanθ N Where h1 is the thickness of the non-metallic layer between the active layer and the first conductive metal layer, h N θ1 is the thickness of the (N-1)th non-metallic layer between the first conductive metal layer and the metal shielding structure, and θ1 is the angle of refraction of light entering the non-metallic layer between the active layer and the first conductive metal layer. N The angle of refraction is the angle at which light enters the (N-1)th non-metallic layer between the first conductive metal layer and the metal shielding structure, where N is a positive integer greater than or equal to 2.
2. The display substrate according to claim 1, characterized in that, According to the formula n0sinθ0=n1sinθ1=n N sinθ N To obtain θ1 and θ n Where n0 = 1, n1 is the refractive index of the non-metallic layer between the active layer and the first conductive metal layer, and n N θ0 is the refractive index of the thickness of the (N-1)th non-metallic layer between the first conductive metal layer and the metal shielding structure, and θ0 is the incident angle of light onto the display substrate, where θ0 > 60 degrees.
3. The display substrate according to claim 1, characterized in that, A metal shielding layer is disposed between the driving circuit layer and the substrate, the metal shielding layer being at least overlapping the middle region of the active layer, and in the first direction, the metal shielding layer having a third side located on the same side as the second side, the distance between the third side and the second side being ΔB in the first direction, and the distance between the third side and the first side being ΔD. △B < h′1tanθ′1, or △D > h′1tanθ′1 + h′2tanθ′2 +... + h′ M tanθ′ M ; Where h′1 is the thickness of the non-metallic layer between the metal shielding layer and the active layer, θ′1 is the refraction angle of light entering the non-metallic layer between the metal shielding layer and the active layer, h′2 is the overall thickness of the non-metallic layer between the active layer and the first conductive metal layer, and θ′2 is the refraction angle of light entering the non-metallic layer between the active layer and the first conductive metal layer. M θ′ is the thickness of the (M-2)th non-metallic layer between the first conductive metal layer and the metal shielding structure. M The angle of refraction is the angle at which light enters the (M-2)th non-metallic layer between the first conductive metal layer and the metal shielding layer, where M is a positive integer greater than or equal to 3.
4. The display substrate according to claim 3, characterized in that, According to the formula n0sinθ0=n1sinθ′1=n2sinθ′2=n M sinθ′ M To obtain θ′1, θ′2, θ M Where n0 = 1, n1 is the refractive index of the non-metallic layer between the metal shielding layer and the active layer, n2 is the refractive index of the non-metallic layer between the active layer and the first conductive metal layer, θ0 is the incident angle of light onto the display substrate, θ0 > 60 degrees, n M is the refractive index of the (M-2)th non-metallic layer between the first conductive metal layer and the metal shielding structure.
5. The display substrate according to claim 1, characterized in that, The driving circuit layer includes a second conductive metal layer located on the side of the first conductive metal layer away from the substrate. The second conductive metal layer includes the second electrode plate of the capacitor, and the second electrode plate is reused as the metal shielding structure.
6. The display substrate according to claim 1, characterized in that, The driving circuit layer further includes a third conductive metal layer, which includes data lines and power lines. In the first direction, the power lines are located on the side of the data lines closer to the first transistor, and the power lines are multiplexed as the metal shielding structure.
7. The display substrate according to claim 1, characterized in that, A light-emitting functional layer is disposed on the driving circuit layer, and the light-emitting functional layer includes a plurality of light-emitting devices. Each light-emitting device includes a first electrode, a light-emitting material layer, and a second electrode stacked along the substrate away from the substrate. The first electrode is reused as the metal shielding structure, or the second electrode is reused as the metal shielding structure.
8. The display substrate according to claim 7, characterized in that, A touch function layer is provided on the side of the light-emitting functional layer away from the substrate. The touch function layer includes a touch metal layer, and the touch metal layer includes a touch pattern superimposed on the middle region. The touch pattern is reused as the metal shielding structure.
9. The display substrate according to claim 1, characterized in that, The pixel circuit is a 2T1C circuit, or a 3T1C circuit, or a 3T2C circuit, or a 7T1C circuit or a 7T2C circuit.
10. A display panel, characterized in that, Includes the display substrate as described in any one of claims 1-9.
11. A display device, characterized in that, Includes the display panel as described in claim 10.