CXL module, method for repairing memory, controller, device, medium, and system
Patent Information
- Application Number
- PCT/CN2026/072548
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-20
- Filing Date
- 2026-01-14
- Publication Date
- 2026-08-27
Smart Images
Figure CN2026072548_27082026_PF_FP_ABST
Abstract
Description
CXL module, memory repairing method, controller, device, medium and system
[0001] The present application claims priority from the Chinese patent application No. 202510192065.9 filed on February 20, 2025, and entitled "CXL module, memory repairing method, controller, device, medium and system", the content of which is incorporated herein by reference. TECHNICAL FIELD
[0002] Embodiments of the present disclosure relate to, but are not limited to, the technical field of data access, and in particular to a CXL module, a memory repairing method, a controller, a device, a medium and a system. BACKGROUND
[0003] Due to the improvement of memory chip process and the requirement of high transmission rate, it is difficult for chip manufacturers to avoid producing unqualified or substandard memory chips in the process of producing and manufacturing memory chips. In order to improve the yield of memory chips, a self-repairing function is usually set in the memory chip so as to replace the damaged storage unit with the pre-set redundant storage unit in the memory chip during the factory test.
[0004] When the redundant storage unit inside the memory chip is insufficient, the memory chip cannot be repaired by itself, and the manufacturer can only downgrade the chip function or use the memory chip as a bad chip that does not meet the use standard and will not be put into the market. On the one hand, the chip manufacturer suffers certain economic losses; on the other hand, most of the storage resources in the memory chip can be normally used. SUMMARY
[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0006] In a first aspect, the embodiments of the present disclosure provide a CXL module, comprising a controller, and a plurality of memory chips and at least one flash memory chip connected to the controller, at least one memory chip being an unqualified chip with unrepairable failed storage units; the flash memory chip is pre-loaded with a defect information table, the defect information table comprising identification information and defect information of the unqualified chip, the defect information comprising address information of the unrepairable failed storage units in the unqualified chip; the controller is configured to: load the defect information table from the flash memory chip when powered on; obtain the address information of the unrepairable failed storage units; allocate a corresponding redundant storage unit for each unrepairable failed storage unit, and convert the access to the failed storage unit to the access to the redundant storage unit.
[0007] In a second aspect, the embodiments of the present disclosure further provide a method for repairing memory, applied to the CXL module in any of the embodiments, and the method comprises: loading a defect information table from a flash memory chip when powered on, the defect information table comprising identification information and defect information of unqualified chips, the defect information comprising address information of un-repaired failed storage units in the unqualified chips; obtaining the address information of the un-repaired failed storage units; allocating a corresponding redundant storage unit for each un-repaired failed storage unit, and converting access to the failed storage unit into access to the redundant storage unit.
[0008] In a third aspect, the embodiments of the present disclosure further provide a controller, applied to a memory module, and the controller comprises a processor; the processor is configured to implement the method for repairing memory in any of the embodiments.
[0009] In a fourth aspect, the embodiments of the present disclosure further provide a module test device for testing defect information of a memory chip in a CXL module, and the module test device comprises: a data interface configured to be connected with a database storing identification information and corresponding defect information of memory chips, so as to obtain the corresponding defect information from the database according to the identification information of the memory chip; and a test interface configured to be connected with a controller of a CXL module to be tested, so as to receive the identification information of the memory chip sent by the controller and return the corresponding defect information of the memory chip obtained from the database according to the identification information of the memory chip.
[0010] In a fifth aspect, the embodiments of the present disclosure further provide a non-transitory computer storage medium, storing a computer program, and the computer program is executed by a processor to implement the method for repairing memory in any of the embodiments of the present disclosure.
[0011] In a sixth aspect, the embodiments of the present disclosure further provide a computer system, comprising a host and a CXL module in any of the embodiments, and the host communicates with the CXL module through a CXL interface to implement discovery, configuration and data transmission of the CXL module.
[0012] Other aspects can become apparent after consideration of the drawing and detailed description.
[0013] SUMMARY
[0014] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.
[0015] FIG. 1 is a structural schematic diagram of a CXL module according to an embodiment of the present disclosure;
[0016] FIG. 2 is a flow schematic diagram of a method for repairing memory according to an embodiment of the present disclosure;
[0017] FIG. 3 is a flow diagram of a method for repairing memory according to an embodiment of the present disclosure;
[0018] FIG. 4 is a flow diagram of a method for repairing memory according to an embodiment of the present disclosure;
[0019] FIG. 5 is a flow diagram of a method for repairing memory according to an embodiment of the present disclosure;
[0020] FIG. 6 is a schematic diagram of a controller according to an embodiment of the present disclosure;
[0021] FIG. 7 is a schematic diagram of a module testing apparatus according to an embodiment of the present disclosure.
[0022] Detailed Description
[0023] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Embodiments of the present disclosure and features in the embodiments can be combined with each other as long as there is no conflict.
[0024] The present embodiments are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically show ideal examples, and the present embodiments are not limited to the shapes or values shown in the drawings.
[0025] The ordinal numbers "first", "second", and the like in the present disclosure are set in order to avoid confusion of the components, and do not represent any order, number, or importance.
[0026] The present disclosure describes a plurality of embodiments, but the description is exemplary, not limiting, and more embodiments and implementation schemes can be possible within the scope of the embodiments described in the present disclosure for those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment can be used with any other feature or element of any other embodiment, or can replace any other feature or element of any other embodiment.
[0027] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The presently disclosed embodiments, features and elements can also be combined with any conventional feature or element to form a scheme defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other disclosed schemes to form another scheme defined by the claims. Therefore, it should be understood that any of the features shown and discussed in the present disclosure can be implemented alone or in any appropriate combination. Accordingly, the embodiments are not to be restricted, except as by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.
[0028] Furthermore, in describing representative embodiments, the specification can have presented the method and process described as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps, the method or process should not be limited to the particular sequence of steps described. Other steps can be performed in between steps described, or the described steps can be executed in an order other than that described or can be performed concurrently. As will be understood by those of ordinary skill in the art, other sequences of steps can be possible. Therefore, the particular order of the steps set forth in the specification is not an limitation on the claims. Moreover, the claims should not be limited to the steps of the methods and processes set forth, as the method and process steps can vary and still be in keeping with the spirit and scope of the present disclosure.
[0029] In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.
[0030] As shown in FIG. 1, the embodiments of the present disclosure provide a CXL module, which includes a controller 110, a plurality of memory chips 120 connected with the controller 110, and at least one flash memory chip 130. At least one memory chip 120 is a substandard chip 121 having unrepairable failed storage units. The flash memory chip 130 is pre-loaded with a defect information table, which includes identification information and defect information of the substandard chip 121. The defect information includes address information of the unrepairable failed storage units in the substandard chip 121. The controller 110 is configured to: load the defect information table from the flash memory chip 130 when powered on; obtain the address information of the unrepairable failed storage units; allocate a corresponding redundant storage unit for each unrepairable failed storage unit, and convert access to the failed storage unit to access to the redundant storage unit.
[0031] CXL is developed based on PCIe 5.0 and runs on the PCIe physical layer. According to the characteristics of accessing memory, CXL is divided into three sub-protocols: 1) CXL.io, 2) CXL.mem and 3) CXL.cache. Correspondingly, CXL devices (also referred to as CXL modules) are divided into first-type CXL devices (Type1 CXL device, referred to as Type1 device), second-type CXL devices (Type2 CXL device, referred to as Type2 device) and third-type CXL devices (Type3 CXL device, referred to as Type3 device). The Type2 device and the Type3 device can set multiple device memories, which can be DDR, HBM (High Bandwidth Memory) and the like. Taking the Type2 device as an example, the Type2 device can be an acceleration card (such as a GPU) in an actual application scenario, which is provided with data by a host (Host) and is responsible for calculation. The HDM model allows the Host to directly manage and control the storage space on the Type2 device, dynamically allocates and configures the device memory according to application requirements, and directly performs read and write operations. The CXL Type3 device can provide the Host with a large-capacity DRAM (Dynamic Random Access Memory), and can also support a persistent medium (i.e., a non-volatile medium such as a flash memory chip).
[0032] The CXL module in the embodiment can be a second-type CXL device or a third-type CXL device.
[0033] Generally, the controller 110 can also be referred to as a CXL controller or a CXL control chip, which can be provided with a CXL interface based on the CXL protocol, so that the Host CPU interacts with the controller 110 through the CXL interface. For example, based on the CXL.io protocol, the Host CPU can send instructions to the controller 110; based on the CXL.mem protocol, the Host CPU can access data in the memory chip 120. The controller 110 is also provided with a DDR (Double Data Rate) controller, so that the CPU of the controller 110 manages the memory chip 120. Other hardware can be an address manager for recording the address mapping relationship in the process of data exchange tasks.
[0034] In the embodiment, before the CXL module is powered on, the defect information table can be loaded in the flash memory chip 130 by external loading. The defect information table can include identification information and defect information of the unqualified chip. Here, the unqualified chip refers to a memory chip or a memory die having a failed storage unit that cannot be repaired, for example, when the reserved redundant storage unit in the memory chip is insufficient to replace the failed storage unit, the memory chip can be determined as an unqualified chip.
[0035] The defect information includes address information of the unrepairable failed storage unit in the unqualified chip, which is used to represent the position of the failed storage unit in the unqualified chip, for example, can include row information and column information of the failed storage unit in the unqualified chip.
[0036] As an example, the identification information of the unqualified chip can include one or more of the following information: serial number of the unqualified chip, coordinate information, production date, wafer foundry enterprise information, and serial number of the wafer where the unqualified chip is located, etc. Based on the identification information, the position of the unqualified chip in the wafer can be determined.
[0037] In an optional example, the manufacturer can test the wafer before leaving the factory by using a specific chip testing device to obtain the test information of each memory chip (also referred to as memory die) in the wafer, which can include the serial number of the wafer, the position of the memory chip in the wafer (including but not limited to X coordinate and Y coordinate), and the defect information of the memory chip, etc. The serial number of the wafer and the position of the memory chip in the wafer are used as the identification information of the memory chip (i.e. the unique identity of the memory chip, also referred to as Die ID), and then the identification information of the memory chip and its corresponding defect information are stored in the database, wherein the identification information of the memory chip can be used as an index to access the database. The identification method of the memory chip given in the above embodiment is only an example, and in other embodiments, other methods can be used for identification as long as the memory chip can be uniquely identified.
[0038] After the memory chip is used in the CXL module, the test interface of the module testing device can be used to communicate with the controller of the CXL module, the identification information of each memory chip in the CXL module is read by the controller and transmitted to the module testing device. The module testing device accesses the database by using the identification information of the memory chip as an index, if the corresponding defect information exists in the database, the defect information is sent back to the controller, so that the controller stores the defect information table in the flash memory or other persistent memory of the CXL module.
[0039] When the CXL module is powered on, the controller 110 can load the defect information table from the flash chip 130, read the identification information of each memory chip 120 from the DIMM (Dual Inline Memory Module), and then use the read identification information as an index to search the defect information table to determine the unqualified chips, and determine the address information of the unrepairable failed storage units from the defect information corresponding to the unqualified chips. Then, a redundant storage unit can be allocated for each unrepairable failed storage unit, and the access to the unrepairable failed storage unit is mapped to the redundant storage unit, thereby completing the repair of the unqualified chips. Here, the unrepairable failed storage unit and the redundant storage unit allocated therefor can be located in different memory chips, or the storage units in the normal storage space in the same memory chip can be used as the redundant storage units corresponding to the failed storage units.
[0040] As an example, after determining the redundant storage unit corresponding to the failed storage unit, the controller 110 can replace the physical address of the failed storage unit with the physical address of the redundant storage unit in the mapping relationship between the external address and the physical address; or replace the media physical address of the failed storage unit with the media physical address of the redundant storage unit in the mapping relationship between the device physical address and the media physical address. Here, the granularity of address replacement can be row, column, word, or other granularity, which is not limited in the present application.
[0041] In some optional embodiments of the present embodiment, the controller 110 can determine the redundant storage unit from the memory chip that does not contain the unqualified chip; or determine the redundant storage unit from the available area of the specified one or more unqualified chips.
[0042] For example, the redundant storage unit can be determined from the redundant storage space or the normal storage space (i.e., non-redundant storage space) of the other memory chips other than the unqualified chips, and the qualified chips (other memory chips other than the unqualified chips) can be used to repair the unqualified chips.
[0043] Alternatively, the controller 110 can determine the storage unit as the redundant storage unit of the unrepairable failed storage unit from the available storage space (i.e., non-redundant storage area) of the specified one or more unqualified chips. In this way, the repair of multiple unqualified chips can be implemented by using part of the unqualified chips, which helps to improve the utilization rate of storage resources.
[0044] The CXL module in the embodiment of the present disclosure loads the defect information table from the flash chip when powered on, thereby obtaining the address information of the un-repaired failed storage unit in the unqualified chip, and allocating an available redundant storage unit for the un-repaired failed storage unit from other chips, so as to convert the access to the un-repaired failed storage unit into the access to the redundant storage unit. The repair of the unqualified chip can be implemented, thereby improving the utilization rate of the storage resource of the unqualified chip, avoiding resource waste, and reducing the economic loss of the chip manufacturer caused by the unqualified chip.
[0045] In some embodiments, the memory chip including the unqualified chip can be a chip for degraded use or a bad chip that does not meet the use standard.
[0046] For the chip for degraded use, the storage space of the chip can be improved through the repair of the unqualified chip; for the bad chip, the unqualified chip can be used as a normal chip through the repair of the unqualified chip. This helps to reduce the waste of storage resources and the economic loss of the chip manufacturer.
[0047] In some embodiments, the controller can convert the access to the failed storage unit into the access to the redundant storage unit by: writing the address mapping relationship between the failed storage unit and the redundant storage unit into the address replacement table; when receiving the access request to the failed storage unit, replacing the address of the failed storage unit in the access request with the address of the corresponding redundant storage unit according to the address replacement table, and then performing the access.
[0048] In the embodiment, the address replacement table can record the physical addresses (which can be device physical addresses or medium physical addresses) of the failed storage unit and the redundant storage unit. When the controller receives an access request to the failed storage unit (which can be an external access request sent by the host or an internal access request generated by the controller), the address replacement table can be replaced to map the access request to the redundant storage unit.
[0049] In some embodiments, the controller is configured to: identify a new failed storage unit appearing in the unqualified chip during use; determine the redundant storage unit corresponding to the new failed storage unit, and write the address mapping relationship between the new failed storage unit and the redundant storage unit into the address replacement table.
[0050] In the embodiment, the new failed storage unit refers to a failed storage unit that is not recorded in the defect information, for example, a new failed storage unit appearing in the unqualified chip during use.
[0051] As an example, in the use of the CXL module, the controller can identify a newly failed storage unit in the memory chip through a self-test algorithm or ECC error correction function, allocate a redundant storage unit for the failed storage unit in the case that the failed storage unit is located in the unqualified chip (i.e., a newly failed storage unit), and record the address mapping relationship of the two in the address replacement table, so that the newly failed storage unit can be dynamically repaired during the operation of the CXL module.
[0052] In some optional embodiments of the present embodiment, in the case that the identified failed storage unit is located in a qualified chip (i.e., other memory chips except the unqualified chip), the memory chip can be preferentially used to repair the failed storage unit. For example, the controller can record the address information of the failed storage unit and send a repair instruction to the corresponding memory chip to instruct the memory chip to repair the failed storage unit. When the memory chip itself cannot repair the failed storage unit, the failed storage unit can be repaired as a newly failed storage unit.
[0053] In the present embodiment, the controller can dynamically repair the newly failed storage unit in the unqualified chip during the operation of the CXL module, which helps to further improve the utilization rate of storage resources.
[0054] In some embodiments, the controller is further configured to generate defect information of the newly failed storage unit and determine identification information of the unqualified chip where the newly failed storage unit is located; store the defect information of the newly failed storage unit and the identification information of the unqualified chip where the newly failed storage unit is located into a defect information table; and write the defect information table back to the flash memory chip to update the defect information table in the flash memory chip.
[0055] As an example, the controller can generate defect information of the newly failed storage unit according to the address information of the newly failed storage unit, and then store the defect information of the newly failed storage unit and the identification information of the unqualified chip where the newly failed storage unit is located into the defect information table to update the defect information table, and write the updated defect information table back to the flash memory chip for backup.
[0056] In some embodiments, the defect information further includes any one or more of bin, running rate, and redundant storage space information of the unqualified chip. The controller is further configured to adjust the running parameters of the CXL module based on the defect information.
[0057] In the present embodiment, the controller can adjust the running parameters of the CXL module according to the defect information, so as to improve the performance of the CXL module.
[0058] As shown in FIG. 2, the present disclosure also provides a method for repairing a memory, which is applied to the CXL module in any of the above embodiments, and the method comprises the following steps.
[0059] Step 210, loading the defect information table from the flash chip when powered on.
[0060] The defect information table includes identification information and defect information of the unqualified chip, and the defect information includes address information of the unrepairable failed storage unit in the unqualified chip.
[0061] Step 220, obtaining the address information of the failed storage unit.
[0062] Step 230, allocating a corresponding redundant storage unit for each failed storage unit, and converting the access to the failed storage unit into the access to the redundant storage unit.
[0063] The method for repairing the memory in the embodiment can repair the unqualified chip, thereby improving the utilization rate of the storage resource of the unqualified chip, avoiding resource waste, and reducing the economic loss of the chip manufacturer caused by the unqualified chip.
[0064] In some embodiments, the memory chip including the unqualified chip is a chip used in a degraded manner or a bad chip that does not meet the use standard.
[0065] For the chip used in a degraded manner, the storage space of the chip can be improved by repairing the unqualified chip; for the bad chip, the unqualified chip can be used as a normal chip by repairing the unqualified chip, which helps to reduce the waste of storage resources and the economic loss of the chip manufacturer.
[0066] In some embodiments, converting the access to the failed storage unit into the access to the redundant storage unit can further include: writing the address mapping relationship between the failed storage unit and the redundant storage unit into an address replacement table; when an access request to the failed storage unit is received, replacing the address of the failed storage unit in the access request with the address of the corresponding redundant storage unit according to the address replacement table, and then performing the access.
[0067] In the embodiment, the address replacement table can record the physical addresses (which can be device physical addresses or medium physical addresses) of the failed storage unit and the redundant storage unit. When the controller receives an access request to the failed storage unit (which can be an external access request sent by the host or an internal access request generated by the controller), the address replacement table can be replaced to map the access request to the redundant storage unit.
[0068] In some embodiments, the method for repairing the memory can further include: determining the redundant storage unit from other memory chips other than the unqualified chip; or determining the redundant storage unit from the available storage space of one or more specified unqualified chips.
[0069] In the embodiment, the unqualified chips can be repaired by using the redundant storage space and / or non-redundant storage space of the qualified chips, or the unqualified chips can be repaired by using the available storage space of part of the unqualified chips, which helps to improve the utilization rate of storage resources.
[0070] In some embodiments, the method for repairing memory provided by the present disclosure can further include the flow shown in FIG. 3. As shown in FIG. 3, the flow can include the following steps.
[0071] Step 310: identifying a new failed storage unit in the unqualified chip during use.
[0072] Step 320: determining a redundant storage unit corresponding to the new failed storage unit, and writing an address mapping relationship between the new failed storage unit and the redundant storage unit into an address replacement table.
[0073] In the embodiment, the new failed storage unit in the unqualified chip can be dynamically repaired during the operation of the CXL module, which helps to further improve the utilization rate of storage resources.
[0074] In some embodiments, after the above step 320, the method for repairing memory can further include the flow shown in FIG. 4. As shown in FIG. 4, the flow can include the following steps.
[0075] Step 410: generating defect information of the new failed storage unit, and determining identification information of the unqualified chip where the new failed storage unit is located.
[0076] Step 420: storing the defect information of the new failed storage unit and the identification information of the unqualified chip where the new failed storage unit is located into a defect information table.
[0077] Step 430: writing the defect information table back to the flash memory chip to update the defect information table in the flash memory chip.
[0078] As an example, the controller can generate the defect information of the new failed storage unit according to the address information of the new failed storage unit, and then store the defect information of the new failed storage unit and the identification information of the unqualified chip where the new failed storage unit is located into the defect information table, so as to update the defect information table, and write the updated defect information table back to the flash memory chip for backup.
[0079] In some embodiments, the defect information further includes any one or more of the degradation information, the running rate and the redundant storage space information of the unqualified chip. In addition, the method for repairing memory can further include adjusting the operation parameters of the CXL module based on the defect information.
[0080] In the embodiment, the operation parameters of the CXL module can be adjusted according to the defect information, which can improve the performance of the CXL module.
[0081] Referring to FIG. 5, FIG. 5 shows a flowchart of one embodiment of the method for repairing memory according to the present disclosure. As shown in FIG. 5, the flowchart can include the following steps.
[0082] Step 510, obtaining the identification information of the unqualified chip and the corresponding defect information thereof.
[0083] In the embodiment, the identification information of the unqualified chip and the corresponding defect information thereof can be obtained from the bare chip test information provided by the chip manufacturer, or can be obtained by testing the memory chip through the module test device.
[0084] For example, the identification information of the unqualified chip can include the number of the wafer where the unqualified chip is located and the coordinates of the unqualified chip in the wafer. Based on the identification information, the position of the unqualified chip in the wafer can be determined.
[0085] In some optional embodiments of the embodiment, the identification information of the unqualified chip and the corresponding defect information thereof can be obtained by: reading the identification information of the memory chip in the CXL module by using the controller of the CXL module; sending the identification information to the module test device so that the module test device looks up the corresponding defect information from the database according to the identification information; and receiving the identification information of the unqualified chip and the corresponding defect information thereof returned by the module test device.
[0086] In the embodiment, the module test device can communicate with the controller of the CXL module and the database, the database pre-stores the identification of the unqualified chip and the defect information thereof, the module test device can access the database through the data interface provided by the chip manufacturer, and look up the corresponding defect information by taking the identification information of the chip as an index. The controller of the CXL module can read the identification information of each memory chip contained in the CXL module and send it to the module test device, the module test device takes the received identification information of the memory chip as an index to look up the database, if the database contains the identification information of a certain memory chip and the corresponding defect information thereof, the memory chip is an unqualified chip, the module test device obtains the identification information of each unqualified chip and the corresponding defect information thereof from the database, and then returns to the controller of the CXL module, so that the controller stores it in the flash memory chip of the CXL module after encoding and other processing.
[0087] Step 520, encoding the obtained identification information of the unqualified chip and the corresponding defect information thereof according to the requirements of the predetermined format, generating a defect information table and loading it into the flash memory chip.
[0088] In the embodiment, the identification information of the unqualified chip and the corresponding defect information obtained can be encoded into a predetermined format by an external device outside the CXL module, a defect information table is generated, and the defect information table is loaded into the flash memory chip through external loading.
[0089] In the embodiment, steps 510 to 520 are completed before the CXL module is powered on, so that the defect information table is loaded from the flash memory chip into the processor of the controller when the CXL module is started.
[0090] Step 530, loading the defect information table from the flash memory chip when powered on.
[0091] As an example, the CXL module can load the defect information table into the flash memory of the controller when powered on to improve the repair speed.
[0092] Step 540, obtaining address information of the failed storage unit.
[0093] Step 550, allocating a corresponding redundant storage unit for each failed storage unit, and converting the access to the failed storage unit to the access to the redundant storage unit.
[0094] In the embodiment, the defect information of the unqualified chip can be obtained in advance and written into the flash memory chip of the memory module through external loading. When the memory module is powered on, the unqualified chip can be repaired according to the defect information, so that the unqualified chip can be applied to the memory module, which helps to improve the utilization rate of the unqualified chip and thus reduce the economic loss of the chip manufacturer.
[0095] An embodiment of the present disclosure also provides a controller applied to a memory module. As shown in FIG. 6, the controller can include a processor 610, a CXL interface 620 for connecting a host, a first storage interface 630 for connecting a memory chip, a second storage interface 640 for connecting a flash memory chip, and other hardware 650. The processor 610 is configured to execute the method for repairing the memory in any embodiment of the present disclosure.
[0096] The processor of the embodiment can be a general processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc., and can also be other conventional processors, etc. The processor can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a ready programmable gate array (FPGA), discrete logic or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or a combination thereof. That is, the processor of the embodiment can be any processing device or combination of devices that implement the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. If the embodiments of the present disclosure are implemented partially in software, instructions for the software can be stored in a suitable nonvolatile computer-readable storage medium, and one or more processors can be used to execute the instructions in hardware to implement the methods of the embodiments of the present disclosure.
[0097] As shown in FIG. 7, the embodiment of the present disclosure also provides a module test device for testing defect information of memory chips in a CXL module, including: a data interface 710 configured to be connected with a database 720 storing identification information and corresponding defect information of memory chips, so as to obtain the corresponding defect information from the database 720 according to the identification information of the memory chips; and a test interface 730 configured to be connected with a controller of a CXL module 740 to be tested, so as to receive the identification information of the memory chips sent by the controller, and return the defect information corresponding to the identification information of the memory chips obtained from the database.
[0098] In the embodiment, the database stores identification information and corresponding defect information of unqualified chips, the identification information represents a unique identity of the memory chip, for example, can include a number of the memory chip, a position of the memory chip in a wafer, etc., and the defect information can include address information of failed memory cells, for example. As an example, the database 720 can be arranged in a cloud server of a chip manufacturer, and is in communication connection with the module test device through an open interface.
[0099] Alternatively, the database 720 can also be arranged in a local server, and after obtaining the identification information and corresponding defect information of unqualified chips from the chip manufacturer in advance, the information is stored in the database, so that the module test device accesses through the data interface 710.
[0100] In the embodiment, the module test device can be in communication connection with the CXL module to be tested and the database, so as to obtain the corresponding defect information from the database according to the identification information of the memory chips in the CXL module, and return the controller of the CXL module, which can realize identification of unqualified chips in the CXL module and acquisition of defect information.
[0101] An embodiment of the present disclosure further provides a non-transitory computer storage medium, which stores a computer program. The computer program is executed by a processor to implement the method for repairing memory in any of the embodiments of the present disclosure.
[0102] An embodiment of the present disclosure provides a computer system, which comprises a host and a CXL module in any of the embodiments of the present disclosure. The host communicates with the CXL module through a CXL interface to implement any one or more of discovery, configuration and data transmission of the CXL module.
[0103] An embodiment of the present disclosure provides a computer product, which is executed by a processor to implement the method for repairing memory in any of the embodiments of the present disclosure.
[0104] Those skilled in the art can understand that all or some of the steps in the method disclosed above, the functions of the modules / units in the system and the device can be implemented as software, firmware, hardware or a combination thereof. In the hardware implementation, the division between the function modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit such as an application-specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as known to those skilled in the art, communication media typically includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and can include any information delivery medium.
Claims
1. A CXL module comprising a controller and a plurality of memory chips and at least one flash memory chip connected to the controller, wherein, At least one of the memory chips is a defective chip having unrepairable failed storage units; The flash memory chip is pre-loaded with a defect information table, the defect information table including identification information and defect information of the defective chip, the defect information including address information of the unrepairable failed storage units in the defective chip; The controller is configured to load the defect information table from the flash memory chip when powered on; Obtain the address information of the failed storage units; allocate a corresponding redundant storage unit for each of the failed storage units, and convert access to the failed storage units to access to the redundant storage units.
2. The CXL module of claim 1, wherein, The defective chip is a chip used in a degraded manner or a bad chip that does not meet the use standard.
3. The CXL module of claim 1, wherein, The controller converts access to the failed storage units to access to the redundant storage units, including: Write the address mapping relationship between the failed storage units and the redundant storage units into an address replacement table; When an access request to the failed storage units is received, replace the address of the failed storage units in the access request with the address of the corresponding redundant storage units according to the address replacement table, and then perform access.
4. The CXL module of claim 1, wherein, The controller is further configured to determine the redundant storage units from memory chips other than the defective chip; or, Determine the redundant storage units from the available storage space of one or more specified defective chips.
5. The CXL module of claim 1, wherein, The controller is configured to: Identify new failed storage units in the defective chip during use; Determine the redundant storage units corresponding to the new failed storage units, and write the address mapping relationship between the new failed storage units and the redundant storage units into the address replacement table.
6. The CXL module of claim 5, wherein, The controller is further configured to: Generate defect information of the new failed storage units, and determine identification information of the defective chip in which the new failed storage units are located; Store the defect information of the new failed storage units and the identification information of the defective chip in which the new failed storage units are located into the defect information table; And, Write the defect information table back to the flash memory chip to update the defect information table in the flash memory chip.
7. The CXL module of claim 1, wherein, The identification information of the defective chip includes the number of the wafer in which the defective chip is located and the coordinates of the defective chip in the wafer.
8. The CXL module of one of claims 1 to 7, wherein, The defect information further includes any one or more of the degradation information, operating speed, and redundant storage space information of the defective chip; The controller is further configured to adjust the operating parameters of the CXL module based on the defect information.
9. A method for repairing a memory, applied to the CXL module of any one of claims 1 to 8, the method comprising: Loading a defect information table from a flash memory chip when powered on, the defect information table including identification information and defect information of a defective chip, the defect information including address information of unrepairable failed storage units in the defective chip; Obtaining the address information of the failed storage units; allocating a corresponding redundant storage unit for each of the failed storage units, and converting an access to the failed storage unit into an access to the redundant storage unit.
10. The method of claim 9, wherein, The unqualified chip is a chip that is used in a degraded manner or a bad chip that does not meet the use standard.
11. The method of claim 9, wherein, The converting the access to the failed storage unit into the access to the redundant storage unit comprises: writing an address mapping relationship between the failed storage unit and the redundant storage unit into an address replacement table; Upon receiving an access request to the failed storage unit, replacing the address of the failed storage unit in the access request with the address of the corresponding redundant storage unit according to the address replacement table, and then performing the access.
12. The method of claim 9, further comprising: The redundant storage unit is determined from memory chips other than the unqualified chip. Alternatively, The redundant storage unit is determined from available storage space of one or more of the unqualified chips.
13. The method of claim 9, further comprising: identifying a new failed storage unit in the unqualified chip during use; determining a corresponding redundant storage unit for the new failed storage unit, and writing an address mapping relationship between the new failed storage unit and the redundant storage unit into the address replacement table.
14. The method of claim 13, further comprising: generating defect information of the new failed storage unit, and determining identification information of the unqualified chip in which the new failed storage unit is located; storing the defect information of the new failed storage unit and the identification information of the unqualified chip in which the new failed storage unit is located into the defect information table; and writing the defect information table back to the flash memory chip to update the defect information table in the flash memory chip. The identification information of the unqualified chip includes a number of a wafer in which the unqualified chip is located and coordinates of the unqualified chip in the wafer.
15. The method of claim 9, wherein, The defect information further includes any one or more of degradation information, operating speed, and redundant storage space information of the unqualified chip.
16. The method according to one of claims 9 to 15, wherein The method further comprises adjusting operating parameters of the CXL module based on the defect information.
17. The method of claim 9, before the CXL module is powered on, the method further comprises: obtaining identification information of the unqualified chip and corresponding defect information thereof; encoding the obtained identification information of the unqualified chip and corresponding defect information thereof according to a predetermined format requirement, generating the defect information table, and loading the defect information table to the flash memory chip. The obtaining the identification information of the unqualified chip and corresponding defect information thereof comprises:
18. The method of claim 17, wherein, reading identification information of memory chips in the CXL module by using a controller of the CXL module; sending the identification information to a module test device, so that the module test device looks up corresponding defect information from a database according to the identification information; receiving identification information of unqualified chips and corresponding defect information thereof returned by the module test device. The controller comprises a processor; the processor is configured to execute the method for repairing memory of any one of claims 9 to 18.
19. A controller for use in a memory module, wherein, 20.A module testing device for testing defect information of memory chips in a CXL module, comprising: a data interface configured to connect with a database storing identification information of memory chips and corresponding defect information, to obtain corresponding defect information from the database according to identification information of memory chips; a test interface configured to connect with a controller of a CXL module to be tested, to receive identification information of memory chips sent by the controller, and return corresponding defect information obtained from the database according to the identification information of memory chips.
21. A non-transitory computer storage medium holding a computer program, wherein, The computer program is executed by a processor to implement the method for repairing memory according to any one of claims 9-18. 22.A computer system comprising a host and a CXL module according to any one of claims 1-8, wherein the host communicates with the CXL module through a CXL interface to implement any one or more of discovery, configuration and data transmission of the CXL module.