CXL module, control chip, memory module and data transmission method

Abstract

A CXL module, a control chip, a memory module, and a data transmission method. The CXL module comprises a control chip (100) and a plurality of memory chips (101) connected to the control chip (100) by means of a memory interface of the control chip (100); the control chip (100) is configured to perform ECC coding on data that needs to be stored in the memory chips (101) so as to generate an ECC check code for every 512 bits of data and, on the basis of the memory interface, transmits by means of one burst at least 512 bits of data, the ECC check code of the 512 bits of data, and 2 bits of metadata, wherein the transmission comprises writing data into the memory chips (101) from the control chip (100), or reading data from the memory chips (101) to the control chip (100), and the ECC check code is less than or equal to 30 bits and can correct an error of 1 bit, 2 bits or 3 bits.

Description

CXL module, control chip, memory module and data transmission method

[0001] This application claims priority to Chinese Patent Application No. 2025101925614, filed on February 20, 2025, entitled "A CXL Module, Control Chip, Memory Module and Data Transmission Method", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, data transmission technology, and particularly to a Compute Express Link (CXL) module, a control chip, a memory module, and a data transmission method. Background Technology

[0003] With the development of technologies such as cloud computing, big data, and artificial intelligence, higher demands are being placed on memory reliability. Memory manufacturers and system designers (who manufacture memory controller chips) are constantly introducing new technologies and methods to improve the reliability, availability, and maintainability of memory to meet the growing performance and stability requirements. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] One embodiment of this disclosure provides a CXL module, including a control chip and multiple memory chips connected to the control chip via a memory interface. The control chip is configured to perform ECC encoding on data to be stored in the memory chips, generating an Error Correcting Code (ECC) checksum for every 512 bits of data; and, based on the memory interface, transmit at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst. The transmission includes writing from the control chip to the memory chips or reading from the memory chips to the control chip. The ECC checksum is less than or equal to 30 bits and can correct 1, 2, or 3 bit errors.

[0006] One embodiment of this disclosure also provides a data transmission method applied to a control chip in a CXL module. The CXL module further includes multiple memory chips connected to a memory interface of the control chip. The method includes: ECC encoding of data to be stored in the memory chips, generating an ECC checksum for every 512 bits of data; transmitting at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst based on the memory interface; wherein the transmission includes writing from the control chip to the memory chip or reading from the memory chip to the control chip, and the ECC checksum is less than or equal to 30 bits and capable of correcting 1-bit, 2-bit, or 3-bit errors.

[0007] One embodiment of this disclosure also provides a control chip in a CXL module. The control chip includes a memory controller and a memory interface. The memory controller is connected to a plurality of memory chips through the memory interface. The memory controller is configured to perform a data transmission method as described in any embodiment of this disclosure.

[0008] One embodiment of this disclosure also provides a memory module in a CXL module, including peripheral circuitry and multiple memory chips. The multiple memory chips are connected to the control chip of the CXL module through the peripheral circuitry and a memory interface. The peripheral circuitry is configured to transmit at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst. The transmission includes saving 512 bits of data from the control chip, the ECC checksum of the 512 bits of data, and 2 bits of metadata to the multiple memory chips, or reading 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata from the multiple memory chips to the control chip. The ECC checksum is less than or equal to 30 bits and is capable of correcting 1-bit, 2-bit, or 3-bit errors.

[0009] The CXL module, control chip, memory module, and data transmission method disclosed in the above embodiments perform ECC encoding on the data to be stored in the memory chip, generating an ECC check code for every 512 bits of data; wherein every 512 bits is a transmission unit of CXL, and the generated ECC check code is less than or equal to 30 bits, while using the on-die ECC mechanism to verify 512 bits requires a 32-bit check code, thus reducing the size of the check code and the required storage space.

[0010] The CXL module, control chip, memory module, and data transmission method disclosed in the above embodiments transmit at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst. Specifically, 512 bits of data, a checksum of 30 bits or less, and 2 bits of metadata are transmitted together. The data consisting of the checksum of 30 bits or less and the metadata can be transmitted together via a single sampling edge of a burst or via a single pin, thus fully utilizing transmission resources, improving transmission efficiency, and providing a feasible implementation scheme for metadata transmission in the CXL module.

[0011] The embodiments of this disclosure generate a checksum of no more than 30 bits for 512-bit data, which can correct errors of 1, 2, or 3 bits. Compared to using on-die ECC checksums, which can only correct 1-bit errors, this improves error correction capability and is of great significance for improving memory reliability. Moreover, the generation of the ECC checksum in the embodiments of this disclosure is completed by the control chip, without requiring modification of the verification logic inside the memory chip, making it simple and easy to implement.

[0012] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0013] Overview of the attached figures

[0014] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0015] Figure 1 is a schematic diagram of a CXL module according to an embodiment of the present disclosure;

[0016] Figure 2 is a flowchart of a data transmission method according to an embodiment of the present disclosure;

[0017] Figure 3 is a schematic diagram of the structure of the control chip in a CXL module according to an embodiment of the present disclosure;

[0018] Figure 4 is a schematic diagram of the memory module in an embodiment of the CXL module of this disclosure.

[0019] Detailed Explanation

[0020] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein, which will be apparent to those skilled in the art. Although many possible combinations of features are shown in the accompanying drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0021] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0022] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0023] Compute Express Link (CXL) technology, based on PCIe, is primarily used for expanding memory bandwidth and improving overall system performance. In computing architectures requiring extensive use of high-speed interconnects, the application of CXL technology is an undeniable technological trend.

[0024] Ensuring data integrity is a fundamental requirement when applying CXL technology. DRAM chips are designed with a standard on-die ECC mechanism for error checking, which can calculate an 8-bit ECC checksum for 128 bits of data. This 8-bit checksum is stored in a dedicated memory space within the DRAM chip. The control logic of the DRAM chip includes the on-die ECC processing mechanism. During write operations, the DRAM chip calculates the on-die ECC checksum and stores it in the dedicated memory space. During read operations, it checks the read data for errors based on the on-die ECC checksum and sends the correct read data to the memory controller. While the on-die ECC mechanism can ensure data integrity and improve system reliability, its verification capability is not strong enough; for example, it can only detect and verify 1-bit data errors. Therefore, it is necessary to improve the verification capability of the CXL module.

[0025] In addition, CXL technology also needs to transmit 2 bits of metadata, and it is also necessary to consider how to store and transmit the metadata.

[0026] This disclosure provides a CXL module, as shown in FIG1. ​​The CXL module includes a control chip 100 and a plurality of memory chips 101 connected to the control chip 100 through a memory interface of the control chip 100. The plurality of memory chips 101 can be disposed on a memory module. The memory module in the figure is only an example and may also include peripheral circuits 102 and other components.

[0027] The control chip 100 is configured to perform ECC encoding on data (such as CXL messages) to be saved to the memory chip 101, wherein the ECC encoding generates an ECC checksum for every 512 bits of data, the ECC checksum being less than or equal to 30 bits and capable of correcting 1-bit, 2-bit, or 3-bit data errors; and is configured to transmit at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst based on the memory interface; the transmission includes: writing data from the control chip 100 to the memory chip 101, or reading data from the memory chip 101 to the control chip 100.

[0028] In this embodiment, the control chip generates an ECC checksum of 30 bits or less for every 512 bits of data. Then, it transmits the 512 bits of data and their ECC checksums together to the memory chip for storage. When reading the 512 bits of data, the ECC checksum is also read out. The control chip then uses this ECC checksum to verify and correct the read data. The memory chip in this article can also be referred to as a memory chip.

[0029] The BCH (Bose-Chaudhuri-Hocquenghem) algorithm can be used to generate ECC check codes (also known as BCH codes). BCH codes are cyclic error correction codes built on a finite field (Galois field), defined by a generator polynomial, and capable of correcting multiple bit errors, making them suitable for scenarios involving random and burst errors. However, this disclosure is not limited to this; other error correction algorithms such as Hamming codes, Reed-Solomon codes, and Low-Density Parity-Check codes (LDPC codes) can also be used. In this embodiment, the length of the ECC check code generated for every 512 bits of data can be 30 bits to correct 3-bit errors; it can also be 20 bits or 22 bits to correct 2-bit errors, depending on the algorithm used and the configured parameters; this disclosure does not limit this.

[0030] In the CXL module of this disclosure, the control chip performs ECC encoding on the data to be saved to the memory chip, generating an ECC check code for every 512 bits of data; where every 512 bits is a transmission unit of CXL, the generated ECC check code is less than or equal to 30 bits, and using the on-die ECC mechanism to verify 512 bits requires a 32-bit check code, thus reducing the size of the check code and the required storage space.

[0031] The control chip of the CXL module in this embodiment transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst. That is, it transmits 512 bits of data, a checksum of 30 bits or less, and 2 bits of metadata together. The data consisting of the checksum of 30 bits or less and the metadata can be transmitted together via a single sampling edge of a burst or via a single pin, thus fully utilizing transmission resources, improving transmission efficiency, and providing a feasible implementation scheme for metadata transmission in the CXL module.

[0032] The control chip of the CXL module in this disclosure generates a checksum of no more than 30 bits for 512-bit data, which can correct 1-bit, 2-bit, or 3-bit errors. Compared to using on-die ECC checksums, which can only correct 1-bit errors, this improves error correction capability and is of great significance for improving memory reliability. Furthermore, the generation of the ECC checksum in the above embodiments of this disclosure is completed by the control chip, without requiring modification of the verification logic within the memory chip, making it simple and easy to implement.

[0033] In an exemplary embodiment of this disclosure, the control chip transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst. This includes transmitting the 512 bits of data, the ECC checksum, and the 2 bits of metadata together in a burst of length 17. In CXL technology, the burst length (BL) refers to the number of data units that can be continuously transmitted in a single memory access operation; a burst length of BL17 indicates that 17 data units can be continuously transmitted in a single memory access operation. This embodiment of the disclosure extends the standard burst length of data access (DQ) in CXL technology from BL16 to BL17, enabling the transmission of the ECC checksum and metadata within the increased data units without modifying the memory interface, thus easily achieving compatibility with existing interfaces.

[0034] In an exemplary embodiment of this disclosure, a burst of length 17 can use 9 clock cycles; for example, DDR5 with an x4 configuration structure (x4 configuration structure means that the data bit width of the memory chip is 4, which can be connected to 4 data pins of the memory interface) can achieve sampling on both the rising and falling edges of the clock, and a burst using 8 clock cycles can achieve BL16 to complete the transmission of 16 data units; a burst using 9 clock cycles can achieve BL17 by using only the rising edge of the 9th clock cycle to complete the transmission of 17 data units.

[0035] In one example of this embodiment, the control chip is configured to transmit 512 bits of data, along with the ECC checksum and 2 bits of metadata, in a burst of length 17. This includes transmitting 32 bits of the 512 bits of data on the rising and falling edges of the first 8 clock cycles of the 9 clock cycles, and transmitting the ECC checksum and 2 bits of metadata on the rising edge of the last clock cycle of the 9 clock cycles.

[0036] In one example of this embodiment, the control chip may also be configured to perform CRC4 transmission verification on the falling edge of the last clock of the nine clocks to improve data verification capability; however, in another example, the falling edge of the last clock may not be used.

[0037] In one example of this embodiment, the memory interface includes 64 data pins; every 32 data pins are connected to 8 x 4 configured memory chips in a sub-channel. For example, a DDR5 memory module has 2 sub-channels, and each memory sub-channel includes 8 x 4 configured DDR5 memory chips with a data width of 32 bits.

[0038] The following example illustrates the transmission of 512 bits of data, along with the ECC checksum and 2 bits of metadata, in a single burst of length 17. The memory chips used in this example are those found in DDR5 memory modules. Both the rising and falling edges of the clock signal used in the burst can be used as sampling edges for data transmission. The controller chip's memory interface includes 64 data pins, with 32 pins connected to eight x4 configuration memory chips in a sub-channel. The first 16 sampling edges of the burst are used to transmit the 512 bits of data, such as writing or reading 512 bits of data from the eight x4 configuration memory chips. The 17th sampling edge of the burst (the rising edge of the 9th clock cycle) is used to transmit the ECC checksum and 2 bits of metadata, again for writing or reading these data from the eight x4 configuration memory chips. The 18th sampling edge of the burst is not used and is not included in the burst length. It can be reserved for future use (Reserved for Future Use, RFU). Alternatively, a CRC4 transmission check can be performed every 64 bits of data, but the check result is not stored and does not occupy storage space.

[0039] Taking an 8x4 configuration DRAM chip (denoted as the first DRAM chip to the eighth DRAM chip) as an example, in the case of transmitting 512 bits of data, the ECC checksum of the 512 bits of data and 2 bits of metadata through a burst of length 17, taking a 30-bit ECC checksum as an example, the data transmitted by each DRAM data pin on each sampling edge of the burst is as follows: BL0 to BL17 represent the first to the 18th sampling edges of the burst, DQ0 to DQ3 represent the four data pins on a DRAM chip, ECC0 to ECC29 represent the 30-bit ECC checksum, MD0 to MD1 represent the 2 bits of metadata, and RFU represents reservation;

[0040] First DRAM chip:

[0041] Second DRAM chip:

[0042] Third DRAM chip:

[0043] Fourth DRAM chip:

[0044] Fifth DRAM chip:

[0045] Sixth DRAM chip:

[0046] Seventh DRAM chip:

[0047] Eighth DRAM chip:

[0048] As can be seen from the table above, on each data pin of the DRAM chip with an 8x4 configuration structure, 512 bits of data are transmitted in the first 16 sampling edges of the burst, ECC checksum and 2 bits of metadata are transmitted in the 17th sampling edge of the burst, and the 18th sampling edge of the burst is reserved for no data transmission and is therefore not included in the burst length.

[0049] In this application example, the on-die ECC mode and CRC8 checksum built into the DRAM chip can be disabled. Disabling the on-die ECC mode means that the chip no longer performs the on-die ECC function, but the first memory space in the chip that stores the on-die ECC checksum bits remains open. ECC checksums of 30 bits or less and 2 bits of metadata can be stored in the first memory space without occupying additional storage space.

[0050] In another exemplary embodiment, the number of data pins of the control chip is increased from 64 to 72. The control chip transmits at least 512 bits of data, along with the ECC checksum and 2 bits of metadata, in a single burst. This includes transmitting the 512 bits of data, the ECC checksum, the 2 bits of metadata, and 32 bits of extended metadata together in a burst of length 8 or 16. The additional 8 data pins are used to transmit the ECC checksum, the 2 bits of metadata, and the 32 bits of extended metadata, allowing a maximum transmission of 64 bits.

[0051] In an exemplary embodiment of this disclosure, the 72 data pins of the memory interface are connected to 18 x4 configuration memory chips. Correspondingly, the control chip transmits 512 bits of data, along with the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata, in a burst of length 8. This includes: writing 512 bits of data to or reading 512 bits of data from 16 x4 configuration memory chips using 64 of the 72 data pins in a burst of length 8; and writing the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata to or reading the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata from 2 x4 configuration memory chips using the remaining 8 of the 72 data pins in a burst of length 8. In this embodiment, the 18 x4 configuration memory chips can be installed on a DDR4 standard memory module. The DDR4 standard uses 8-bit bursts, taking eight consecutive rising edges of the clock as sampling edges, transmitting 64 bits of data on each sampling edge. In another embodiment, eight x8 configuration memory chips can be used instead of the aforementioned 16 x4 configuration memory chips to store 512 bits of data. Alternatively, two x4 configuration memory chips or one x8 configuration memory chip can be used to store the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata for the 512 bits of data. These solutions yield equivalent results.

[0052] In one example of this embodiment, the control chip is configured to write the ECC checksum and 2 bits of metadata to one of the memory chips in the two x4 configuration structure, and to write the 32 bits of extended metadata to the other memory chip; or, to read the ECC checksum and 2 bits of metadata from one of the memory chips in the two x4 configuration structure, and to read the 32 bits of extended metadata from the other memory chip.

[0053] The following is an application example where the number of memory interface data pins on the control chip is increased from 64 to 72, connected to 18 x4 DRAM chips to transmit 512 bits of data, along with the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata. When transmitting 512 bits of data for one cache line, 16 x4 DRAM chips are used to store the data, while the other two x4 DRAM chips store 30 bits of ECC checksum, 2 bits of metadata, and 32 bits of extended metadata, totaling 64 bits. The 30 bits of ECC checksum and 2 bits of metadata are stored on one DRAM chip, and the 32 bits of extended metadata are stored on another DRAM chip.

[0054] This example uses a 30-bit ECC checksum. The data transmitted by each DRAM data pin in the x4 configuration at each sampling edge of the burst is shown in the table below. In the table, BL0 to BL7 represent the 1st to 8th sampling edges of the burst, DQ0 to DQ3 represent the 4 data pins on a DRAM chip, ECC0 to ECC29 represent the 30-bit ECC checksum, MD0 to MD1 represent the 2-bit metadata, and EMD0 to EMD31 represent the 32-bit extended metadata.

[0055] First DRAM chip

[0056] Second DRAM chip

[0057] The third to fifteenth DRAM chips are used to store data d64 to d479, and are not shown here again.

[0058] Sixteenth DRAM chip

[0059] Seventeenth DRAM chip

[0060] Eighteenth DRAM chip

[0061] As shown in the table above, four of the eight additional data pins are used to transmit 30 bits of ECC checksum and 2 bits of metadata, such as writing or reading the 30 bits of ECC checksum and 2 bits of metadata from the seventeenth DRAM chip. The other four data pins are used to transmit 32 bits of extended metadata, such as writing or reading the 32 bits of extended metadata from the eighteenth DRAM chip. This solution only requires two additional DRAM chips to ensure that the metadata, ECC checksum, extended metadata, and data of the CXL module are transmitted together, without incurring additional transmission time.

[0062] In an exemplary embodiment of this disclosure, of the 72 data pins of the memory interface, every 36 data pins are connected to 9 x 4 configured memory chips in a sub-channel. For example, a DDR5 memory module has 2 sub-channels, and each memory sub-channel consists of 9 x 4 configured DDR5 memory chips with a data width of 36 bits. Correspondingly, the control chip transmits 512 bits of data, along with the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata, through a burst of length 16. This includes: writing 512 bits of data to or reading 512 bits of data from eight x4 memory chips using a burst of length 16 on 32 of the 36 data pins; and writing the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata to or reading the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata from one x4 memory chip using a burst of length 16 on the other four of the 36 data pins.

[0063] Below is an application example that increases the memory interface of the control chip from 64 data pins to 72 data pins. Each of these 72 data pins, consisting of 36 pins, connects to nine x4 configuration memory chips in a sub-channel, using DRAM chips from a DDR5 memory module as an example. In the DDR5 standard, both the rising and falling edges of the clock are sampling edges for data transmission, with a burst length of BL16. For each sub-channel, transmitting 512 bits of data for one cache line requires eight x4 configuration DDR5 chips; an external DRAM chip is connected to the four additional data pins to transmit 30 bits of ECC parity, 2 bits of metadata, and 32 bits of extended metadata, totaling 64 bits.

[0064] This example uses a 30-bit ECC checksum. The data transmitted by each DRAM data pin in the x4 configuration at each sampling edge of the burst is shown in the table below. In the table, BL0 to BL7 represent the 1st to 8th sampling edges of the burst, DQ0 to DQ3 represent the 4 data pins on a DRAM chip, ECC0 to ECC29 represent the 30-bit ECC checksum, MD0 to MD1 represent the 2-bit metadata, and EMD0 to EMD31 represent the 32-bit extended metadata.

[0065] First DRAM chip:

[0066] Second DRAM chip:

[0067] The third to seventh DRAM chips are used to store data d128 to d447, and are not shown here again.

[0068] Eighth DRAM chip:

[0069] Ninth DRAM chip:

[0070] This example demonstrates that for each sub-channel, only one additional DRAM chip is needed to transmit the CXL module's metadata, extended metadata, and ECC check bits along with the data, without incurring additional transmission time.

[0071] This disclosure also provides a data transmission method in one embodiment, applied to a control chip in a CXL module. The CXL module further includes multiple memory chips connected to the memory interface of the control chip, as shown in FIG2. The method includes:

[0072] Step S501: Perform ECC encoding on the data to be saved to the memory chip, generating an ECC checksum for every 512 bits of data; the ECC encoding can be BCH encoding;

[0073] Step S502: Based on the memory interface, transmit at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst.

[0074] In this step, the transmission includes writing from the control chip to the memory chip, or reading from the memory chip to the control chip. The ECC checksum is less than or equal to 30 bits and can correct 1-bit, 2-bit, or 3-bit errors.

[0075] The data transmission method of the above embodiments of this disclosure performs ECC encoding on the data to be saved to the memory chip, generating an ECC check code for every 512 bits of data; wherein every 512 bits is a transmission unit of CXL, and the generated ECC check code is less than or equal to 30 bits, while using the on-die ECC mechanism to check 512 bits requires a 32-bit check code, thus reducing the size of the check code and the required storage space.

[0076] The data transmission method of the above embodiments disclosed herein transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst. That is, 512 bits of data, a checksum of 30 bits or less, and 2 bits of metadata are transmitted together. The data consisting of the checksum of 30 bits or less and the metadata can be transmitted together through a single sampling edge of a burst or through a single pin, which can fully utilize transmission resources, improve transmission efficiency, and provide a feasible implementation scheme for the transmission of metadata in the CXL module.

[0077] The method described in the above embodiments of this disclosure generates a checksum of no more than 30 bits from 512 bits of data, which can correct errors of 1 bit, 2 bits, or 3 bits. Compared to using on-die ECC checksums, which can only correct 1 bit of errors, this method improves error correction capability and is of great significance for improving memory reliability. Moreover, the generation of the ECC checksum in the above embodiments of this disclosure is completed by the control chip, without the need to modify the verification logic inside the memory chip, making it simple and easy to implement.

[0078] In an exemplary embodiment of this disclosure, the transmission of at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst includes: transmitting the 512 bits of data, the ECC checksum of the 512 bits of data, and the 2 bits of metadata together in a single burst of length 17. This embodiment of the disclosure extends the standard burst length of Data Access (DQ) in CXL technology from BL16 to BL17, implementing the transmission of the ECC checksum and metadata on an additional sampling edge. No changes to the memory interface pins are required.

[0079] In an exemplary embodiment of this disclosure, the 17-bit burst uses 9 clock cycles. The transmission of 512 bits of data, along with the ECC checksum and 2 bits of metadata, via the 17-bit burst includes: transmitting 32 bits of the 512 bits of data on the rising and falling edges of the first 8 clock cycles, and transmitting the ECC checksum and 2 bits of metadata on the rising edge of the last clock cycle. The ECC checksum and 2 bits of metadata can be stored in the memory location originally used to store the on-die ECC checksum, without occupying additional storage space. In one example of this embodiment, the method further includes: performing CRC4 transmission verification on the falling edge of the last clock cycle, or not using the falling edge of the last clock cycle.

[0080] In an exemplary embodiment of this disclosure, when the memory interface is increased from the standard 64 data pins to 72 data pins, the transmission of at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst includes: transmitting the 512 bits of data, the ECC checksum of the 512 bits of data, the 2 bits of metadata, and the 32 bits of extended metadata together in a burst of length 8 or 16.

[0081] In an exemplary embodiment of this disclosure, 72 data pins of the memory interface are connected to 18 x4 configuration memory chips. The transmission of 512 bits of data, along with the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata, via a burst of length 8, includes: writing 512 bits of data to or reading 512 bits of data from 16 x4 configuration memory chips connected to the 64 data pins via a burst of length 8, based on 64 of the 72 data pins; and writing the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata to or reading the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata from 2 x4 configuration memory chips connected to the other 8 data pins via a burst of length 8, based on the remaining 8 data pins of the 72 data pins.

[0082] In one example of this embodiment, writing the ECC checksum, 2-bit metadata, and 32-bit extended metadata to two x4 configuration memory chips includes: writing the ECC checksum and 2-bit metadata to one of the two x4 configuration memory chips, and writing the 32-bit extended metadata to the other memory chip; reading the ECC checksum, 2-bit metadata, and 32-bit extended metadata from the two x4 configuration memory chips includes: reading the ECC checksum and 2-bit metadata from one of the two x4 configuration memory chips, and reading the 32-bit extended metadata from the other memory chip.

[0083] In an exemplary embodiment of this disclosure, where 36 data pins out of 72 data pins of the memory interface are connected to memory chips in a 9x4 configuration structure in a sub-channel, the transmission of 512 bits of data along with the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata in a burst of length 16 includes: performing an operation based on each of the 36 data pins of the 72 data pins of the memory interface: transmitting data to 32 of the 36 data pins in a burst of length 16. The system writes or reads 512 bits of data to or from eight x4 configuration memory chips connected to the 32 data pins. Based on the additional four data pins out of the 36 data pins, it writes or reads ECC checksum, 2 bits of metadata, and 32 bits of extended metadata to or from one x4 configuration memory chip connected to those four data pins via a 16-bit burst. This embodiment can transmit 512 bits of ECC checksum, 2 bits of metadata, and 32 bits of extended metadata simultaneously using the additional eight data pins, without increasing transmission time and achieving high bandwidth utilization.

[0084] This disclosure also provides a control chip in a CXL module, as shown in FIG3. The control chip includes a memory controller 601 and a memory interface 602. The memory controller 601 is connected to multiple memory chips through the memory interface 602. The memory controller 601 is configured to execute the data transmission method as described in any embodiment of this disclosure. The control chip in this embodiment may also include other components, such as a microprocessor, an address management module, a computing module, etc., and this disclosure is not limited thereto.

[0085] This disclosure also provides a memory module in a CXL module, as shown in Figure 4, including: a peripheral circuit 701 and multiple memory chips 702; the multiple memory chips 702 are connected to the control chip of the CXL module through the peripheral circuit 701; wherein:

[0086] The peripheral circuit 701 is configured to transmit at least 512 bits of data, along with the ECC checksum and 2 bits of metadata, in a single burst. This transmission includes saving the 512 bits of data from the control chip, along with the ECC checksum and 2 bits of metadata, to the plurality of memory chips 702, or reading the 512 bits of data, along with the ECC checksum and 2 bits of metadata, from the plurality of memory chips 702 to the control chip 701. The ECC checksum is less than or equal to 30 bits and is capable of correcting 1, 2, or 3 bit errors.

[0087] The peripheral circuit 701 in this embodiment can transmit data and commands between the control chip and the memory chip, including but not limited to the following circuits: an address decoding circuit, configured to decode the address signals issued by the memory controller; a data buffer circuit, configured to temporarily store data read from the memory chip, waiting for the memory controller to read it; or temporarily store data to be written by the memory controller, and then transmit the data in at a speed acceptable to the memory chip; a command decoding and control logic circuit, configured to decode and logically process each control instruction issued by the memory controller, such as read commands and write commands, and convert them into operation signals that the memory chip can recognize and execute; and a clock buffer and synchronization circuit, configured to buffer and distribute the system clock signal to ensure that the memory chip and the memory controller work under a unified clock cycle.

[0088] In this embodiment, verifying 512 bits of data requires an ECC checksum of 30 bits or less. Compared to using an on-die ECC mechanism, which requires a 32-bit ECC checksum, this reduces the size of the checksum and thus the storage space required. The reduced checksum can then be used to transmit 2 bits of metadata, improving transmission efficiency and bandwidth utilization. Each verification generates an ECC checksum of 30 bits or less, compared to the 8-bit checksum generated per verification using an on-die ECC mechanism. This allows for the correction of more bit errors and enhances error correction capabilities. The calculation of the ECC checksum is performed by the control chip, eliminating the need to modify the verification logic within the memory chip, making it simple and easy to implement. This provides a feasible implementation scheme for the transmission of metadata in the CXL module.

[0089] In an exemplary embodiment of this disclosure, the memory module is provided with a first storage space for storing the on-die ECC checksum; the peripheral circuit saves the 512-bit ECC checksum and 2-bit metadata from the control chip to the plurality of memory chips, including: saving an ECC checksum of 30 bits or less and the 2-bit metadata to the memory chip provided with the first storage space. The ECC checksum and 2-bit metadata are stored in the location of the memory chip originally used to store the on-die ECC checksum, without occupying additional storage space.

[0090] In an exemplary embodiment of this disclosure, the memory chips on the memory module are divided into one or more groups, each group comprising 18 x4 configuration memory chips, which are connected to 72 data pins of a control chip. The peripheral circuit transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst, including: writing the received 512 bits of data into 16 x4 configuration memory chips connected to 64 of the 72 data pins in a single burst of length 8. Alternatively, 512 bits of data can be read from the 16 x4 configuration memory chips to 64 of the 72 data pins; and, through a burst of length 8, the received ECC checksum, 2 bits of metadata, and 32 bits of extended metadata can be written to two x4 configuration memory chips connected to the other 8 data pins of the 72 data pins, or the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata from the two x4 configuration memory chips can be read to the other 8 data pins of the 72 data pins.

[0091] In one example of this embodiment, one of the memory chips in the two x4 configuration structure is configured to store the ECC checksum and 2 bits of metadata, and the other memory chip is configured to store the 32 bits of extended metadata.

[0092] In an exemplary embodiment of this disclosure, the memory module includes two sub-channels, each sub-channel including nine x4-configured memory chips, the nine x4-configured memory chips being connected to 36 of the 72 data pins of the control chip; the peripheral circuit transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst, including: writing the received 512 bits of data into eight x4-configured memory chips connected to 32 of the 36 data pins in a single burst of length 16. Alternatively, 512 bits of data from the eight x4 configuration memory chips can be read out to 32 of the 36 data pins; and, through a burst of length 16, the received ECC checksum, 2 bits of metadata, and 32 bits of extended metadata can be written to one x4 configuration memory chip connected to the other four data pins of the 36 data pins, or the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata from the one x4 configuration memory chip can be read out to the other four data pins of the 36 data pins.

[0093] In an exemplary embodiment of this disclosure, the peripheral circuit is further configured to support on-die ECC checksum mode and external ECC checksum mode (i.e., the mode of generating ECC checksums outside the chip, also known as out-die ECC checksum mode); when the on-die ECC checksum mode is off and the external ECC checksum mode is on, the ECC checksum of less than or equal to 30 bits and 2 bits of metadata are saved in the first storage space, and the memory chip storing 512 bits of data is different from the memory chip storing the ECC checksum and 2 bits of metadata.

[0094] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0095] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0096] In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly defined.

[0097] In this disclosure, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, "linked" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the meaning of the above terms in this disclosure according to the specific circumstances.

[0098] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0099] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A CXL module, comprising a control chip and a plurality of memory chips connected to the control chip via a memory interface of the control chip, wherein: The control chip is configured to perform ECC encoding on the data to be saved to the memory chip, generating an ECC checksum for every 512 bits of data; and, based on the memory interface, to transmit at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst; wherein the transmission includes writing from the control chip to the memory chip, or reading from the memory chip to the control chip, and the ECC checksum is less than or equal to 30 bits and capable of correcting 1 bit, 2 bits, or 3 bits of error.

2. The CXL module according to claim 1, wherein, The control chip transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst, including: the control chip transmits 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata together in a burst of length 17.

3. The CXL module according to claim 2, wherein, The burst with a length of 17 uses 9 clock cycles; The control chip transmits 512 bits of data, along with the ECC checksum and 2 bits of metadata, in a burst of length 17. This includes transmitting 32 bits of the 512 bits of data on the rising and falling edges of the first 8 clock cycles, and transmitting the ECC checksum and 2 bits of metadata on the rising edge of the last clock cycle.

4. The CXL module according to claim 3, wherein, The control chip is also configured to perform CRC4 transmission verification on the falling edge of the last clock cycle or not use the falling edge of the last clock cycle.

5. The CXL module according to claim 1, wherein, The memory interface includes 64 data pins; each 32 data pins are connected to eight memory chips in a subchannel with a 4x4 configuration.

6. The CXL module according to claim 1, wherein, The memory interface includes 72 data pins; The control chip transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst. Specifically, the control chip transmits 512 bits of data, the ECC checksum of the 512 bits of data, 2 bits of metadata, and 32 bits of extended metadata together in a burst of length 8 or 16.

7. The CXL module according to claim 6, wherein, The memory interface has 72 data pins connected to 18 memory chips in a x4 configuration. The control chip transmits 512 bits of data, along with the ECC checksum of the 512 bits of data, 2 bits of metadata, and 32 bits of extended metadata, in a single burst of length 8. The control chip, based on 64 of the 72 data pins, writes 512 bits of data to or reads 512 bits of data from the 16 x 4 configuration memory chips through a burst of length 8. The control chip, based on the other 8 data pins out of the 72 data pins, writes ECC checksums, 2 bits of metadata, and 32 bits of extended metadata to two x4 configuration memory chips through a burst of length 8, or reads ECC checksums, 2 bits of metadata, and 32 bits of extended metadata from the two x4 configuration memory chips.

8. The CXL module according to claim 7, wherein, The control chip is configured to write the ECC checksum and 2 bits of metadata to one of the memory chips in the two x4 configuration structure, and transmit the 32 bits of extended metadata to the other memory chip; or, to read the ECC checksum and 2 bits of metadata from one of the memory chips in the two x4 configuration structure, and read the 32 bits of extended metadata from the other memory chip.

9. The CXL module according to claim 6, wherein, Of the 72 data pins of the memory interface, every 36 data pins are connected to 9 x 4 configured memory chips in a sub-channel. The control chip transmits 512 bits of data, along with the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata, in a single burst of length 16. The control chip, based on 32 of the 36 data pins, writes 512 bits of data to or reads 512 bits of data from the 8 x 4 configuration memory chips through a burst of length 16. The control chip, based on four additional data pins out of the 36 data pins, writes ECC checksums, 2 bits of metadata, and 32 bits of extended metadata to a memory chip with a length of 16 in a single burst, or reads ECC checksums, 2 bits of metadata, and 32 bits of extended metadata from the memory chip with the same x4 configuration structure.

10. A data transmission method applied to a control chip in a CXL module, the CXL module further comprising a plurality of memory chips connected to a memory interface of the control chip, the method comprising: The data that needs to be saved to the memory granules is ECC encoded, and an ECC check code is generated for every 512 bits of data. Based on the memory interface, at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata are transmitted in a single burst. The transmission includes writing from the control chip to the memory chip or reading from the memory chip to the control chip. The ECC checksum is less than or equal to 30 bits and can correct 1-bit, 2-bit, or 3-bit errors.

11. The method according to claim 10, wherein, The transmission of at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst includes: transmitting the 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata together in a single burst of length 17.

12. The method according to claim 11, wherein, The burst with a length of 17 uses 9 clock cycles; The method of transmitting 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata together through a burst of length 17 includes: transmitting 32 bits of data from the 512 bits of data on the rising and falling edges of the first 8 clock cycles, and transmitting the ECC checksum and 2 bits of metadata on the rising edge of the last clock cycle.

13. The method according to claim 12, further comprising: Perform CRC4 transmission verification on the falling edge of the last clock cycle or do not use the falling edge of the last clock cycle.

14. The method of claim 10, wherein, In the case that the memory interface includes 72 data pins, the transmission of at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst includes: The 512-bit data, along with the ECC checksum of the 512-bit data, 2 bits of metadata, and 32 bits of extended metadata, are transmitted in a burst of length 8 or 16.

15. The method according to claim 14, wherein, With the 72 data pins of the memory interface connected to 18 memory chips in a x4 configuration, the transmission of 512 bits of data, along with the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata, via a burst of length 8, includes: Based on 64 of the 72 data pins, 512 bits of data are written to or read from the 16 x 4 configuration memory chips connected to the 64 data pins through a burst of length 8. Based on the other 8 data pins of the 72 data pins, ECC checksums, 2 bits of metadata, and 32 bits of extended metadata are written to or read from the memory chips of the 2x4 configuration structure through a burst of length 8.

16. The method according to claim 15, wherein, The step of writing ECC checksum, 2 bits of metadata, and 32 bits of extended metadata to two x4 configuration memory chips includes: writing the ECC checksum and 2 bits of metadata to one of the two x4 configuration memory chips, and writing the 32 bits of extended metadata to the other memory chip; The step of reading the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata from the two x4 configuration memory chips includes: reading the ECC checksum and 2 bits of metadata from one of the two x4 configuration memory chips, and reading the 32 bits of extended metadata from the other memory chip.

17. The method according to claim 14, wherein, In the case where every 36 data pins of the memory interface are connected to memory chips in a 9x4 configuration structure within a sub-channel, the transmission of 512 bits of data, along with the ECC checksum of the 512 bits of data, 2 bits of metadata, and 32 bits of extended metadata, in a single burst of length 16, includes: Operations are performed on every 36 of the 72 data pins of the memory interface: Based on 32 of the 36 data pins, 512 bits of data are written to or read from the 8 x 4 configuration memory chips connected to the 32 data pins through a burst of length 16. Based on the other four data pins of the 36 data pins, an ECC checksum, 2 bits of metadata, and 32 bits of extended metadata are written to or read from a memory chip with a length of 16 using a burst of 4 data pins connected to a 1x4 configuration structure.

18. A control chip in a CXL module, the control chip including a memory controller and a memory interface, the memory controller being connected to a plurality of memory chips via the memory interface, the memory controller being configured to perform a data transfer method as claimed in any one of claims 10 to 17.

19. A memory module in a CXL module, comprising peripheral circuitry and a plurality of memory chips, wherein the plurality of memory chips are connected to a control chip of the CXL module via the peripheral circuitry, wherein: The peripheral circuitry is configured to transmit at least 512 bits of data, along with the ECC checksum and 2 bits of metadata, in a single burst. This transmission includes saving the 512 bits of data from the control chip, along with the ECC checksum and 2 bits of metadata, to the plurality of memory chips, or reading the 512 bits of data, along with the ECC checksum and 2 bits of metadata, from the plurality of memory chips to the control chip. The ECC checksum is less than or equal to 30 bits and is capable of correcting 1-bit, 2-bit, or 3-bit errors.

20. The memory module according to claim 19, wherein, The memory module is provided with a first storage space for storing on-die ECC checksums; The peripheral circuit saves the 512-bit ECC checksum and 2-bit metadata from the control chip into the plurality of memory chips, including: saving an ECC checksum of less than or equal to 30 bits and 2-bit metadata into the memory chip with the first storage space.

21. The memory module according to claim 19, wherein, The memory chips on the memory module are divided into one or more groups, each group including 18 memory chips with a x4 configuration structure, and the 18 memory chips with a x4 configuration structure are connected to the 72 data pins of the control chip. The peripheral circuit transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst, including: The received 512 bits of data are written to 16 x 4 configuration memory chips connected to 64 of the 72 data pins through a burst of length 8, or 512 bits of data are read from the 16 x 4 configuration memory chips to 64 of the 72 data pins. The received ECC checksum, 2 bits of metadata, and 32 bits of extended metadata are written into two x4 configuration memory chips connected to the other eight data pins of the 72 data pins through a burst of length 8, or the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata in the two x4 configuration memory chips are read out to the other eight data pins of the 72 data pins.

22. The memory module according to claim 21, wherein, One of the memory chips in the two x4 configuration structure is configured to store the ECC checksum and 2 bits of metadata, and the other memory chip is configured to store the 32 bits of extended metadata.

23. The memory module according to claim 19, wherein, The memory module includes two sub-channels, each sub-channel including nine memory chips with a 4x4 configuration structure, and the nine memory chips with a 4x4 configuration structure are connected to 36 of the 72 data pins of the control chip; The peripheral circuit transmits at least 512 bits of data, the ECC checksum of the 512 bits of data, and 2 bits of metadata in a single burst, including: The received 512 bits of data are written to 8 x 4 configuration memory chips connected to 32 of the 36 data pins through a burst of length 16, or the 512 bits of data in the 8 x 4 configuration memory chips are read out to 32 of the 36 data pins. The received ECC checksum, 2 bits of metadata, and 32 bits of extended metadata are written into a memory chip of a 1x4 configuration structure connected to the other 4 data pins of the 36 data pins through a burst of length 16, or the ECC checksum, 2 bits of metadata, and 32 bits of extended metadata in the memory chip of the 1x4 configuration structure are read out to the memory chip of the 1x4 configuration structure.

24. The memory module according to claim 20, wherein, The peripheral circuit is also configured to support on-die ECC checksum mode and external ECC checksum mode; when on-die ECC checksum mode is off and external ECC checksum mode is on, the ECC checksum of less than or equal to 30 bits and 2 bits of metadata are saved in the first storage space, and the memory chip storing 512 bits of data is different from the memory chip storing the ECC checksum and 2 bits of metadata.

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