Sample-hold circuit for an image sensor, circuit arrangement comprising same and solid-state imaging device comprising same

Abstract

Provided is a sample-hold circuit for an image sensor, a circuit arrangement comprising the sample-hold circuit and an analog-to-digital conversion circuitry, and to a solid-state imaging device comprising the sample-hold circuit and a solid-state image sensor. The sample-hold circuit (200) comprises a first capacitor (Cs) and a second capacitor (Cf), control circuitry (300, S1, S2, S1d), and amplifier circuitry (Amp), wherein the control circuitry is configured to electrically connect the components of the sample-hold circuit, such that an input signal (Vin) is sampled by the first capacitor while an output signal (Vout) is held by the amplifier circuitry0 based on the charge held by the second capacitor.

Description

[0001] Sample-Hold Circuit for an Image Sensor, Circuit Arrangement and Solid-State Imaging Device

[0002] Field

[0003] The present disclosure relates to a sample-hold circuit for an image sensor, to a circuit arrangement comprising the sample-hold circuit and an analog-to-digital conversion circuitry, and to a solid-state imaging device comprising the sample-hold circuit and a solid-state image sensor.

[0004] Background

[0005] Image sensors work by converting light into electrical signals. They contain an array of pixels, each of which captures incoming photons through photo-sensitive materials. When photons hit these pixels, they generate electron-hole pairs. The charge is then collected and measured for each pixel, forming a digital representation of the image.

[0006] After the charge is collected, it is measured and quantized to determine the intensity of the light collected by the respective pixel. This can be done using various types of Analog-to-digital (A / D) conversion circuitry. For example, US 7,532,148 B2 and US 9,473,722 B2 show example A / D conversion circuitry that is being used for this purpose.

[0007] T o enable or improve the sampling of the signal by the A / D conversion circuitry, the respective signal is commonly held by a so-called Sample-Hold (S / H) circuit. A sample-hold circuit is an electronic circuit used in analog systems to capture and hold a voltage level for a period of time. It samples an input signal at a specific moment and retains this value in its output after the sampling period, allowing for further processing without variation due to changes in the input signal.

[0008] In many types of image sensors, the pixels of the image sensors are read out in a two-step process, as discussed in US 7,532,148 B2 and US 9,473,722 B2, in which both a “reset level” and a “signal level” of the respective pixel are quantized using the A / D circuit. In a straightforward implementation, this can be done by first sampling the reset level using the same S / H circuit and then sampling the signal level using the S / H circuit. However, this process takes time, as the respective signal voltage levels need to stabilize before they can be held by the S / H circuit. To speed up this process, a circuit has been proposed that uses independent S / Hcircuits for the reset level and the signal level. While this speeds up the conversion process, it leads to an increased power consumption, increased silicon area, and can cause FPN (Fixed Pattern Noise) due to a mismatch between the two S / H circuits.

[0009] There may be a desire for an improved concept for sampling and holding voltage signals emanating from an image sensor.

[0010] Summary

[0011] This desire is addressed by the subject matter of the independent claims.

[0012] A first aspect of the present disclosure relates to a sample-hold circuit for an image sensor. The sample-hold circuit comprises a first capacitor and a second capacitor. The sample-hold circuit comprises control circuitry. The sample-hold circuit comprises amplifier circuitry. The control circuitry is configured to electrically connect the components of the sample-hold circuit, such that an input signal is sampled by the first capacitor while an output signal is held by the amplifier circuitry based on the charge held by the second capacitor.

[0013] A second aspect of the present disclosure comprises a circuit arrangement comprising the above sample-hold circuit. The circuit arrangement further comprises analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry is configured to, during a sampling phase of the sample-hold circuit, perform analog-to-digital conversion on the output signal being held by the amplifier circuitry of the sample-hold circuit that is based on the charge held by the second capacitor of the sample-hold circuit.

[0014] A third aspect of the present disclosure relates to a solid-state imaging device comprising the above sample-hold circuit and a solid-state image sensor. The sample-hold circuit is configured to perform a sample-hold operation on an output of a photoelectric conversion circuit of the solid-state image sensor. The output of the photoelectric conversion circuit comprises a reset signal during a first time interval and an image signal during a second time interval. The sample-hold circuit is configured to sample and hold the output of the photoelectric conversion circuit such that, during the first time interval, the reset signal is sampled by the first capacitor and a previously applied image signal is held by the amplifier circuitry, and, during the second time interval, the image signal is sampled by the first capacitor and the previously applied reset signal is held by the amplifier circuitry.Brief description of the Figures

[0015] Some examples of apparatuses and / or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which

[0016] Fig. 1a shows a timing diagram of a conventional continuous read-out scheme without a S / H circuit;

[0017] Fig. 1b shows a timing diagram of a read-out scheme with dual S / H circuits;

[0018] Fig. 1c shows a circuit diagram of a circuit arrangement with dual S / H circuits;

[0019] Fig. 2 shows a circuit diagram of a circuit arrangement with a single charge redistribution S / H circuit;

[0020] Fig. 3a shows a circuit diagram of a S / H circuit that uses charge redistribution between two capacitors;

[0021] Fig. 3b shows a diagram of a solid-state imaging device comprising one S / H circuit that uses charge redistribution between two capacitors;

[0022] Fig. 3c shows a more detailed circuit diagram of a S / H circuit that uses charge redistribution between two capacitors;

[0023] Fig. 3d shows a timing diagram for a S / H circuit that uses charge redistribution between two capacitors;

[0024] Fig. 4a shows a circuit diagram of a S / H circuit and a timing diagram for a phase, in which a first capacitor is used to sample an input signal and a second capacitor is reset;

[0025] Fig. 4b shows a circuit diagram of a S / H circuit and a timing diagram for a phase, in which two capacitors hold their respective charges;

[0026] Fig. 4c shows a circuit diagram of a S / H circuit and a timing diagram for a phase, in which charge redistribution is performed from a first capacitor to a second capacitor;Fig. 4d shows a circuit diagram of a S / H circuit and a timing diagram for a phase, in which a first capacitor is used to sample an input signal and an output voltage is provided that is based on a charge being held by a second capacitor;

[0027] Fig. 4e shows a circuit diagram of a S / H circuit and a timing diagram for a phase, in which a first capacitor is used to sample an input signal and a second capacitor is reset;

[0028] Fig. 5 shows a circuit diagram of a CMOS (Complementary Metal-Oxide Semiconductor) implementation of a S / H circuit; and

[0029] Fig. 6 shows a diagram of functional simulation results.

[0030] Detailed Description

[0031] The present disclosure relates to a charge redistribution S / H scheme for use in image sensors.

[0032] Many image sensors are read out row by row, e.g., as described by US 7,532,148 B2 and US 9,473,722 B2. To increase the frame rate of the image sensor, the row time( H-time), i.e., the time required to quantize the intensity of light sensed by the photoelectric conversion circuits (i.e., the pixels) of the image sensors, is to be reduced.

[0033] The light intensity sensed by the respective pixels can be determined by quantizing both a “reset signal” and a “image signal” of the respective pixel using an A / D circuit. As these two levels are provided by the respective pixels sequentially, they are sampled sequentially as well. Fig. 1a shows a timing diagram of a conventional continuous read-out scheme without S / H circuit. Fig. 1a shows four signals - a RST (Reset) signal, a TG signal (a driving signal to a gate of the photoelectric conversion element of the pixel), a VSL signal (an analog voltage output by the photoelectric conversion element), and an ADC signal (to control operation of the A / D converter). From Fig. 1a, the sampling scheme can be seen. First, the RST signal being “high” activates the Floating Diffusion (FD) reset. When the RST signal is set to “low”, the VSL signal exhibits the “reset signal”, which requires some time to settle. When the “reset signal” voltage has settled, the ADC signal is used to activate the analog-to-digital conversion 100 of the “reset signal” voltage. After A / D conversion of the “reset signal” voltage is completed, the TG signal is set to high to perform the photoelectric conversion and the ADC signal is used to trigger an ALU (Algorithmic Logical Unit) circuit to use the output of the A / D conversion. When TG is set to “low”, photoelectric conversion is completed, and the VSL exhibitsthe “image signal” voltage. Again, the “image signal” voltage needs some time to settle. When the “image signal” voltage has settled, the ADC signal is used to activate the analog-to-digital conversion 105 of the “image signal” voltage held by the S / H circuit. After A / D conversion of the “image signal” voltage is completed, the RST signal is set to high again and the ADC signal is used to trigger an ALU (Algorithmic Logical Unit) circuit to use the output of the A / D conversion.

[0034] This procedure can be sped up by using two S / H circuits, as shown in Fig. 1b and 1c.

[0035] Fig. 1b shows a timing diagram of a read-out scheme with dual S / H circuits. In Fig. 1b, six signals are shown - RST, TG, VSL and ADC (known from Fig. 1a), and S / H reset (for controlling the “reset signal” S / G circuit 130a shown in Fig. 1c), and S / H signal (for controlling the “image signal” S / H circuit 130b shown in Fig. 1c).

[0036] Fig. 1c shows a circuit diagram of a circuit arrangement with dual S / H circuits. On the left, an N-channel MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) 110 of the photoelectric conversion circuitry of a pixel is shown, which is connected, at its source terminal, to a current source 120 that is further connected to ground. The voltage at the source terminal of transistor 110 is VSL, which is input into the two S / H circuits 130a / 130b. Switches are used to alternately connect the output of the S / H circuits 130a / 130b to an operational amplifier 140, which is used to compare the output of the respective S / H circuit 130a / 130b to a ramping signal, e.g., as discussed in US 7,532,148 B2 and US 9,473,722 B2. The respective S / H circuits 130a, 130b each include a switch S to disconnect capacitor Cs from input voltage terminal jnand an N-Channel MOSFET 135 in cascode configuration with a biasing current source providing biasing current l ias. The output voltage Vout is provided from the source terminal of the transistor 135.

[0037] As can be seen from Fig. 1b, by using separate S / H circuits for the “reset signal” voltage and the “image signal" voltage, one of the S / H circuits can be used to sample VSL while the respective other S / H circuit holds a previously sampled voltage that is then sampled by the A / D circuit. As a result, the time between the A / D conversion phases 100, 105 can be reduced significantly. This effectively removes the AD reset time and AD signal time in the H-time compared with continuous readout scheme without S / H circuit, and thus reduces the time required for sampling a row. However, using two S / H circuits results in increased power consumption, increased silicon area, and can cause FPN due to a mismatch between the reset S / H circuit 130a and signal S / H circuit 130b.Various examples of the present disclosure may avoid these drawbacks by using a single S / H circuit while reducing the row time.

[0038] Fig. 2 shows a circuit diagram of a circuit arrangement with a proposed single charge redistribution S / H circuit 200, which is shown in more detail in Figs. 3a and 3c. Similar to the dual S / H circuit shown in Fig. 1c, an N-channel MOSFET 110 of the photoelectric conversion circuitry of a pixel is shown, which is connected, at its source terminal, to a current source 120 that is further connected to ground. The voltage at the source terminal of transistor 110 is VSL, which is input into the proposed single S / H circuit 200. The output of the S / H circuit 200 is provided to operational amplifier 140, which is used to compare the output of the respective S / H circuit 130a / 130b to a ramping signal, e.g., as discussed in US 7,532,148 B2 and US 9,473,722 B2. The operational amplifier 140 can be considered to be part of analog-to-digital conversion circuitry, which may include further components, such as a clock counter 150 being used to measure a number of clock cycles between a reference time and a change in the output of the operational amplifier 140. The circuit arrangement shown in Fig. 2 thus further comprises analog-to-digital conversion circuitry 140, 150.

[0039] The proposed charge redistribution S / H circuit 200 is based on a charge redistribution scheme. While one capacitor (first capacitor Cs in Fig. 3a to Fig. 5) is sampling the input signal, the other capacitor (second capacitor Cf in Fig. 3a to 5) stores the previous sampled value, making the sampled signal available for A / D conversion. This way, only one S / H circuit is used for sampling and holding both the “reset signal” voltage and the “image signal” voltage. Due to the resulting correlated double sampling readout scheme, the offset of the S / H circuit will be removed completely. Moreover, since only one S / H circuit is used, the power consumption can be reduced by half compared with a dual S / H readout scheme. Also, since only one amplifier is used, the area is also reduced compared with the dual S / H readout scheme. On the other hand, the thermal noise may be increased by 1 KT / C compared with the dual S / H scheme if Cs and Cf are equal.

[0040] Fig. 3a shows a circuit diagram of a S / H circuit 200 for an image sensor that uses charge redistribution between two capacitors. The S / H circuit 200 comprises a first capacitor Cs and a second capacitor Cf. The S / H circuit 200 further comprises control circuitry 300 and amplifier circuitry Amp. The control circuitry is configured to electrically connect the components of the sample-hold circuit, such that the input signal Vnis sampled by the first capacitor while the output signal Vout is held by the amplifier circuitry based on the charge held by the second capacitor. This way, a single S / H circuit with two capacitors suffices to speed up the A / D operation, as sampling of a new input voltage jncan be performed while A / D conversion ofthe voltage held by the S / H circuit can be performed based on the charge held by the second capacitor Cf.

[0041] This can be achieved by using the control circuitry to selectively connect the capacitors to the input terminal (to sample the input voltage using the first capacitor Cs), to each other (to perform charge redistribution between Cs and Cf) and to the operational amplifier (to output the output voltage based on the charge held by the second capacitor Cf). In particular, the control circuitry may be configured to electrically connect the components of the sample-hold circuit such that, during a sampling phase, the input signal is applied to the first capacitor Cs to charge the first capacitor Cs and the second capacitor Cf is electrically connected to the amplifier circuitry Amp. At least during a portion of the sampling phase, the amplifier circuitry Amp outputs the output voltage based on the charge held by the second capacitor Cf. During a redistribution phase, the first capacitor may be electrically disconnected from the input signal Vin and electrically connected to the second capacitor Cf, so that charge redistribution is performed between the first capacitor Cs and the second capacitor Cf.

[0042] This S / H circuit 200 may, for example, be used in conjunction with or as part of a solid-state image sensor. Fig. 3b shows a diagram of a solid-state imaging device 350 comprising one S / H circuit 200 (e.g., one S / H circuit 200 for each pixel (column) of a row of the image sensor) that uses charge redistribution between two capacitors. For example, the S / H circuit may be electrically connected to the photoelectric conversion circuitry of the solid-state image sensor, e.g., as shown in Fig. 2, e.g., between the photoelectric conversion circuitry 110 and the operational amplifier 140 and counter 150 being used for A / D conversion. For example, the sample-hold circuit 200 may be configured to perform a sample-hold operation on an output of the photoelectric conversion circuit (pixel) 110 of the solid-state image sensor. The output of the sample-hold circuit 200 may be provided to the A / D conversion circuitry 140, 150. For example, the control circuitry 300 of the sample-hold circuit 200 may be controlled by a controller of the solid-state imaging device 350, e.g., by providing control signals to control switches inside the respective S / H circuits 200.

[0043] Fig. 3c shows a more detailed circuit diagram of a S / H circuit 200 that uses charge redistribution between two capacitors Cs, Cf. In the proposed S / H circuit, the control circuitry is configured to electrically connect the components of the sample-hold circuit, such that an input signal Vjnis sampled by the first capacitor while an output signal Vout is held by the amplifier circuitry based on the charge held by the second capacitor. This can be achieved by using switches S1, S2, S1d to selectively couple the components inside the S / H circuit 200. As shown in Fig. 3c, the control circuitry may comprise a first switch S1 and a second switch S2.The first switch being arranged between an input terminal (denoted by Vjnin Fig. 3c) of the sample-hold circuit and the first capacitor Cs. A first terminal of the first switch S1 is electrically connected to the input terminal, and a second terminal of the first switch is connected to a first terminal of the first capacitor Cs and a first terminal of the second switch. The second switch S2 is arranged between the first capacitor Cs and the second capacitor Cf. The first terminal of the second switch S2 is electrically connected to a first terminal of the first capacitor Cs and the second terminal of the first switch S1. A second terminal of the second switch is electrically connected to a first terminal of the second capacitor Cs, a first terminal of a third switch S1d, and a negative input terminal of the amplifier circuitry Amp. The control circuitry may further comprise the third switch S1d being electrically connected to the terminals of the second capacitor Cf. The first capacitor is electrically connected, at the first terminal, to the second terminal of the first switch S1 and the first terminal of the second switch S2, and, at a second terminal, to ground. The second capacitor Cf is electrically connected, at the first terminal, to the negative input terminal of the amplifier circuitry Amp, the second terminal of the second switch S2 and the first terminal of the third switch S1d. The second capacitor Cf is electrically connected, at a second terminal, to the output terminal of the amplifier circuitry Amp and to a second terminal of the third switch S1d. The amplifier circuitry Amp is electrically connected, at the negative input terminal, to the second switch S2, the first terminal of the second capacitor Cf and the first terminal of the third switch S1d. The amplifier circuitry Amp is electrically connected, at its output terminal, to the second terminals of the second capacitor Cf and the third switch S1d. The amplifier circuitry Amp is electrically connected, at its positive input terminal, to ground.

[0044] Operation of the S / H circuit 200 of Figs. 2, 3a to 3c and Fig. 4a to 5 is illustrated in connection with Fig. 3d and Figs. 4a to 4d.

[0045] Fig. 3d shows a timing diagram for a S / H circuit that uses charge redistribution between two capacitors. The timing diagram shows four signals, RST and TG (known from Fig. 1a and 1b) and Cs and Cf, representing the behavior of the first capacitor Cs and the second capacitor Cf. The diagram begins with RST being set to high to perform the Floating Diffusion and then to low, to trigger sampling the “reset signal” voltage (also denoted “reset signal” in the following). This is done during the first “Sample” phase shown for capacitor Cs. During this time, capacitor Cf is used to perform the hold operation, followed by a reset of Cf. When TG is set to high, the photoelectric conversion is being performed. During this time, charge redistribution is performed between Cs and Cf, to redistribute the sampled “reset signal” voltage to Cf. This is followed by Cs sampling the next voltage (“image signal”) and the “reset signal” voltage being output (held) by the S / H circuit based on the charge held in Cf. At the end of the samplephase, Cf is reset again before RST is set to high to trigger the next FD phase. During this time, charge redistribution is performed between Cs and Cf, to redistribute the sampled “image signal” voltage to Cf. Then, the timing diagram returns to sampling the “reset signal” and outputting the previously sampled “image signal”.

[0046] Thus, the proposed concept can be used for the aforementioned two-step process, in which both the “reset signal” and a “image signal” of the respective pixel are quantized using the A / D circuit. Thus, the output VSL of the photoelectric conversion circuit 110 (not shown in Fig.

[0047] 3d) may comprise the reset signal during a first time interval (after RST returns to “low” in Fig.

[0048] 3d) and the image signal during a second time interval (after TG returns to “low” in Fig. 3d). The sample-hold circuit may be configured to sample and hold the output of the photoelectric conversion circuit such that, during the first time interval, the reset signal is sampled by the first capacitor and a previously applied image signal is held by the amplifier circuitry (and output to the A / D conversion circuitry), and, during the second time interval, the image signal is sampled by the first capacitor and the previously applied reset signal is held (and output to the A / D conversion circuitry) by the amplifier circuitry. As a result, the analog-to-digital conversion circuitry 140, 150, may during the first time interval, perform analog-to-digital conversion on the previously applied image signal and, during the second time interval, perform analog-to-digital conversion on the previously applied reset signal. The first and second timer interval may be separated by time intervals, during which the second capacitor is reset.

[0049] The operations shown in Fig. 3d are discussed in more detail in connection with Figs. 4a to 4e. Figs. 4a to 4e illustrate the operation of the single S / H circuit 200. In Figs. 4a to 4e, on top, the effective configuration of the S / H circuit 200 is shown at the top (based on which of the switches are open and closed), with a diagram on the bottom showing whether the switches are closed (indicated by the respective signals S1, S1d, S2 being “high”) or open (“indicated by the respective signals S1, S1d, S2 being “low”).

[0050] Fig. 4a shows a circuit diagram of the S / H circuit 200 and a corresponding timing diagram for a phase (“Sample Cs and reset Cf” phase), in which the first capacitor is used to sample an input signal and a second capacitor is reset. During this phase, S1 and S1d are set to “high”, and S2 is set to “low”. Setting S1 to high causes switch S1 to close, connecting the first capacitor Cs to Vjn. Setting S1d to high causes switch S1d to close, shorting, and thus resetting, the second capacitor Cf. The second switch S2 is open so Vjncan be sampled by the first capacitor Cs.Fig. 4b shows a circuit diagram of the S / H circuit 200 and a corresponding timing diagram for a phase (“Hold Cs and hold reset Cf” phase), in which the two capacitors Cs, Cf hold their respective charges. This is achieved by setting S1, S2 and S1d to “low”, thus opening the switches S1 , S2 and S1d. Cs holds the previously sampled input voltage, while Cf has previously been reset.

[0051] Fig. 4c shows a circuit diagram of the S / H 200 circuit and a corresponding timing diagram for a phase (“Charge redistribution from Cs to Cf” phase), in which charge redistribution is performed from the first capacitor Cs to the second capacitor Cf. This is achieved by setting S1 and S1d to “low”, thus causing switches S1 and S1d to be open, and setting S2 to “high”, thus closing switch S2. This allows for charge redistribution between the two capacitors Cs and Cf.

[0052] Fig. 4d shows a circuit diagram of the S / H circuit 200 and a corresponding timing diagram for a phase (“Sample Cs and AD conversion of Cf” phase), in which the first capacitor Cs is used to sample the input signal Vjnand A / D conversion can be performed (outside the S / H circuit 200) on the output voltage Vout, see Fig. 3c, that is based on a charge being held by the second capacitor Cf.

[0053] Fig. 4e shows a circuit diagram of the S / H circuit 200 and a corresponding timing diagram for a phase (“Sample Cs and reset Cf”, see also Fig. 4a), in which the first capacitor Cs is used to sample the input signal and the second capacitor Cf is reset.

[0054] As is evident from Figs. 4a to 4e, several different phases are distinguished. These different phases include a sampling phase (which can, again, be sub-divided into two different phases) and a redistribution phase. The sampling phase is, for example, shown in Figs. 4a, 4d and 4e, while the redistribution phase is shown in Fig. 4c. The control circuitry is configured to close the first switch and open the second switch in the sampling phase. This way, the first capacitor Cs is connected to the input voltage Vjnwhile being disconnected from the remaining components of the S / H circuit 200, enabling the first capacitor to sample the input voltage. The control circuitry is further configured to open the first switch (disconnecting the first capacitor Cs from the input voltage) and close the second switch (electrically connecting the first capacitor and the second capacitor) in the redistribution phase. This way, the sampled charge can be redistributed from the first capacitor to the second capacitor.

[0055] Before charge redistribution is performed, the second capacitor may be reset to avoid the previously sampled charges being retained. Therefore, the control circuitry may be configuredto electrically connect the components of the sample-hold circuit such that, during a first portion of the sampling phase (shown in Fig. 4d), the output signal of the amplifier circuitry Amp is based on the previously redistributed charge, and during a second portion of the sampling phase (shown in Fig. 4a ad 4e), the second capacitor is reset. This can be by the control circuitry opening the third switch S1d during the first portion of the sampling phase (see Fig.

[0056] 4d) and closing the third switch S1d during the second portion of the sampling phase (see Fig. 4a and 4e).

[0057] As outlined in connection with Fig. 2, the output of the S / H circuit 200 may be provided to A / D conversion circuitry 140, 150. For example, the analog-to-digital conversion circuitry may be configured to, during the sampling phase of the sample-hold circuit, perform analog-to-digital conversion on an output signal being held by the amplifier circuitry of the sample-hold circuit that is based on the charge held by the second capacitor of the sample-hold circuit. For example, the A / D conversion circuitry described in US 7,532,148 B2 or US 9,473,722 B2 may be used for this purpose.

[0058] Fig. 5 shows a circuit diagram of a CMOS (Complementary Metal-Oxide Semiconductor) implementation of the proposed S / H circuit. In Fig. 5, the operational amplifier is implemented using P-channel MOSFET MPamp, which is operated as part pf a cascode structure. In other words, the amplifier circuitry may comprise a PMOS transistor (MPamp) that is operated as part of a cascode structure. The cascode structure includes the P-channel MOSFET MPampand a biasing current source (providing bias current l ias). The cascode structure can be implemented for the PMOS MPamp to increase the DC (Direct Current) gain of the amplifier to make it less sensitive for PVT variation.

[0059] The source terminal of MPampis electrically connected to a supply voltage rail, the gate terminal is electrically connected to the second terminal of S2, the first terminal of S1d and the first terminal of Cf. The drain terminal of MPampis electrically connected to the second terminal of S1d, the second terminal of Cf and the biasing current source. The output signal is also taken from the drain terminal of MPamp. As an alternative to using a P-channel MOSFET, a N-Chan-nel MOSFET may be used. In this case, the circuit may be adapted to the operation of the N-Channel MOSFET.

[0060] When using the CMOS implementation shown in Fig. 5, Vout= 2 * Vaz- Vin, with Vazbeing the voltage applied to the gate of MPamp. Cs and Cf may be chosen to be equally sized to achieve a gain of 1x. The Switches S1,S2 and S1d may be implemented as complementary CMOS switches.Fig. 6 shows a diagram of functional simulation results. On the top of the diagram, Vout is shown, followed by Vn, S1 and S1d (in the same row), S2 and VAZ (the voltage at the gate of the PMOS transistor of Fig. 5). First, S1 and S1d are both “high”, closing the respective switches, such that Vjnis sampled by Cs and the charge held by Cf sets the output voltage Vout. Then, S1 and S1d are set to “low”, opening the switches (see Fig. 4b). Then, S2 is set to “high”, closing switch S2 to affect a redistribution from Cs to Cf (see Fig. 4c). Then S2 is set to “low”, S1 is set to “high” and S1d stays low. During this phase, the input voltage jnis sampled by Cs and the charge held by Cf sets the output voltage Vout. This is followed by S1d being set to “high” to reset Cs. This restarts the cycle.

[0061] In the proposed concept, only one S / H circuit is used for both reset and signal (i.e. , for the reset signal and the image signal). Due to using a correlated double sampling readout scheme, the offset of from the S / H circuit can be remove entirely. Since only 1 S / H circuit is used, the power consumption can also be reduced by half compared with the dual S / H readout scheme of Figs. 1b and 1c. Since only one amplifier is used, the silicon area can also reduced compared with the dual S / H readout scheme. The proposed concept may yield a higher read noise by 1 KT / C compared with the dual S / H scheme.

[0062] The following examples pertain to further embodiments of the present disclosure:

[0063] (1) A sample-hold circuit for an image sensor, comprising a first capacitor and a second capacitor, control circuitry, and amplifier circuitry,

[0064] wherein the control circuitry is configured to electrically connect the components of the sample-hold circuit, such that an input signal (Vjn) is sampled by the first capacitor while an output signal (Vout) is held by the amplifier circuitry based on the charge held by the second capacitor.

[0065] (2) The sample-hold circuit according to (1), wherein the control circuitry is configured to electrically connect the components of the sample-hold circuit such that, during a sampling phase, the input signal is applied to the first capacitor to charge the first capacitor and the second capacitor is electrically connected to the amplifier circuitry, and, during a redistribution phase, the first capacitor is electrically disconnected from the input signal and electrically connected to the second capacitor, so that charge redistribution is performed between the first and the second capacitor.(3) The sample-hold circuit according to (2), wherein the control circuitry comprises a first switch and a second switch, with the first switch being arranged between an input terminal of the sample-hold circuit and the first capacitor, and with the second switch being arranged between the first capacitor and the second capacitor, and with the control circuitry being configured to close the first switch and open the second switch in the sampling phase, and to open the first switch and close the second switch in the redistribution phase.

[0066] (4) The sample-hold circuit according to one of (2) or (3), wherein the control circuitry is configured to electrically connect the components of the sample-hold circuit such that, during a first portion of the sampling phase, the output signal of the amplifier circuitry is based on the previously redistributed charge, and during a second portion of the sampling phase, the second capacitor is reset.

[0067] (5) The sample-hold circuit according to (4), wherein the control circuitry comprises a third switch being electrically connected to the terminals of the second capacitor, with the control circuitry being configured to close the third switch during the second portion of the sampling phase.

[0068] (6) The sample-hold circuit according to one of (1) to (5), wherein a first terminal of the second capacitor is electrically connected to an input terminal of the amplifier circuitry, and a second terminal of the second capacitor is electrically connected to an output terminal of the amplifier circuitry.

[0069] (7) The sample-hold circuit according to one of (1) to (6), wherein the amplifier circuitry comprises a PMOS transistor that is operated as part of a cascode structure.

[0070] (8) The sample-hold circuit according to one of (1) to (7), wherein the sample-hold circuit is configured to perform a sample-hold operation on an output of a photoelectric conversion circuit of a solid-state image sensor, wherein the output of the photoelectric conversion circuit comprises a reset signal during a first time interval and an image signal during a second time interval, with the sample-hold circuit being configured to sample and hold the output of the photoelectric conversion circuit such that, during the first time interval, the reset signal is sampled by the first capacitor and a previously applied image signal is held by the amplifier circuitry, and, during the second time interval, the image signal is sampled by the first capacitor and the previously applied reset signal is held by the amplifier circuitry.(9) A circuit arrangement comprising the sample-hold circuit according to one of (1) to (8) and analog-to-digital conversion circuitry, wherein the analog-to-digital conversion circuitry is configured to, during a sampling phase of the sample-hold circuit, perform analog-to-digital conversion on the output signal being held by the amplifier circuitry of the sample-hold circuit that is based on the charge held by the second capacitor of the sample-hold circuit.

[0071] (10) A solid-state imaging device comprising the sample-hold circuit according to (8) and a solid-state image sensor.

[0072] (11) The solid-state imaging device according to (11), further comprising analog-to- digital conversion circuitry, wherein the analog-to-digital conversion circuitry is configured to, during the first time interval, perform analog-to-digital conversion on the previously applied image signal and, during the second time interval, perform analog-to- digital conversion on the previously applied reset signal.

[0073] The aspects and features described in relation to a particular one of the previous examples may also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the features into the further example.

[0074] Examples may further be or relate to a (computer) program including a program code to execute one or more of the above methods when the program is executed on a computer, processor or other programmable hardware component. Thus, steps, operations or processes of different ones of the methods described above may also be executed by programmed computers, processors or other programmable hardware components. Examples may also cover program storage devices, such as digital data storage media, which are machine-, processor- or computer-readable and encode and / or contain machine-executable, processorexecutable or computer-executable programs and instructions. Program storage devices may include or be digital storage devices, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media, for example. Other examples may also include computers, processors, control units, (field) programmable logic arrays ((F)PLAs), (field) programmable gate arrays ((F)PGAs), graphics processor units (GPU), application-specific integrated circuits (ASICs), integrated circuits (ICs) or system-on-a-chip (SoCs) systems programmed to execute the steps of the methods described above.It is further understood that the disclosure of several steps, processes, operations or functions disclosed in the description or claims shall not be construed to imply that these operations are necessarily dependent on the order described, unless explicitly stated in the individual case or necessary for technical reasons. Therefore, the previous description does not limit the execution of several steps or functions to a certain order. Furthermore, in further examples, a single step, function, process or operation may include and / or be broken up into several sub-steps, -functions, -processes or -operations.

[0075] If some aspects have been described in relation to a device or system, these aspects should also be understood as a description of the corresponding method. For example, a block, device or functional aspect of the device or system may correspond to a feature, such as a method step, of the corresponding method. Accordingly, aspects described in relation to a method shall also be understood as a description of a corresponding block, a corresponding element, a property or a functional feature of a corresponding device or a corresponding system.

[0076] The following claims are hereby incorporated in the detailed description, wherein each claim may stand on its own as a separate example. It should also be noted that although in the claims a dependent claim refers to a particular combination with one or more other claims, other examples may also include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly proposed, unless it is stated in the individual case that a particular combination is not intended. Furthermore, features of a claim should also be included for any other independent claim, even if that claim is not directly defined as dependent on that other independent claim.

Claims

ClaimsWhat is claimed is:

1. A sample-hold circuit for an image sensor, comprising:a first capacitor and a second capacitor;control circuitry; andamplifier circuitry,wherein the control circuitry is configured to electrically connect the components of the sample-hold circuit, such that an input signal is sampled by the first capacitor while an output signal is held by the amplifier circuitry based on the charge held by the second capacitor.

2. The sample-hold circuit according to claim 1, wherein the control circuitry is configured to electrically connect the components of the sample-hold circuit such that, during a sampling phase, the input signal is applied to the first capacitor to charge the first capacitor and the second capacitor is electrically connected to the amplifier circuitry, and, during a redistribution phase, the first capacitor is electrically disconnected from the input signal and electrically connected to the second capacitor, so that charge redistribution is performed between the first and the second capacitor.

3. The sample-hold circuit according to claim 2, wherein the control circuitry comprises a first switch and a second switch, with the first switch being arranged between an input terminal of the sample-hold circuit and the first capacitor, and with the second switch being arranged between the first capacitor and the second capacitor, and with the control circuitry being configured to close the first switch and open the second switch in the sampling phase, and to open the first switch and close the second switch in the redistribution phase.

4. The sample-hold circuit according to claim 2, wherein the control circuitry is configured to electrically connect the components of the sample-hold circuit such that, during a first portion of the sampling phase, the output signal of the amplifier circuitry is based on the previously redistributed charge, and during a second portion of the sampling phase, the second capacitor is reset.

5. The sample-hold circuit according to claim 4, wherein the control circuitry comprises a third switch being electrically connected to the terminals of the second capacitor, with the control circuitry being configured to close the third switch during the second portion of the sampling phase.

6. The sample-hold circuit according to claim 1 , wherein a first terminal of the second capacitor is electrically connected to an input terminal of the amplifier circuitry, and a second terminal of the second capacitor is electrically connected to an output terminal of the amplifier circuitry.

7. The sample-hold circuit according to claim 1, wherein the amplifier circuitry comprises a PMOS transistor that is operated as part of a cascode structure.

8. The sample-hold circuit according to claim 1, wherein the sample-hold circuit is configured to perform a sample-hold operation on an output of a photoelectric conversion circuit of a solid-state image sensor, wherein the output of the photoelectric conversion circuit comprises a reset signal during a first time interval and an image signal during a second time interval, with the sample-hold circuit being configured to sample and hold the output of the photoelectric conversion circuit such that, during the first time interval, the reset signal is sampled by the first capacitor and a previously applied image signal is held by the amplifier circuitry, and, during the second time interval, the image signal is sampled by the first capacitor and the previously applied reset signal is held by the amplifier circuitry.

9. A circuit arrangement comprising the sample-hold circuit according to claim 1 and analog-to-digital conversion circuitry, wherein the analog-to-digital conversion circuitry is configured to, during a sampling phase of the sample-hold circuit, perform analog-to-digital conversion on the output signal being held by the amplifier circuitry of the sample-hold circuit that is based on the charge held by the second capacitor of the sample-hold circuit.

10. A solid-state imaging device comprising the sample-hold circuit according to claim 8 and a solid-state image sensor.

11. The solid-state imaging device according to claim 10, further comprising analog- to-digital conversion circuitry, wherein the analog-to-digital conversion circuitry is configured to, during the first time interval, perform analog-to-digital conversion onthe previously applied image signal and, during the second time interval, perform analog-to-digital conversion on the previously applied reset signal.

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