General purpose input / output test system, and system-on-chip comprising same

Abstract

The present invention relates to a general purpose input / output (GPIO) test system and a system-on-chip comprising same, the test system controlling test signal transmission / reception between a plurality of IP blocks within the system-on-chip and the GPIO in a test mode such that the GPIO can be tested. The GPIO test system according to the present invention comprises: a first pad group controller which performs pad function input / output and pad function operation control in a function mode for respective first GPIO pads constituting a first pad group, and which performs a first pad test input / output and pad test operation control in a test mode; and a first hard macro interface for transmitting and receiving port input / output in the test mode for respective ports constituting a first IP block.

Description

General-purpose I / O test system and system-on-chip including the same

[0001] The present invention relates to a general-purpose input / output test system and a system-on-chip including the same, and more specifically, to a general-purpose input / output test system and a system-on-chip including the same that enables testing of general-purpose input / output (GPIO) by controlling the transmission and reception of test signals between a plurality of IP blocks and general-purpose input / output (GPIO) within the system-on-chip in a test mode.

[0002] The present invention is based on the research results of the research project "Development of DFT system design automation solution in System on chip" (Executing organization: Itda Semiconductor Co., Ltd., Research period: September 1, 2024 to August 31, 2027), which was conducted with support from Scale-up TIPS (Project No.: RS-2024-00507894), organized by the Ministry of SMEs and Startups of the Republic of Korea and managed by the Technology Promotion Agency for SMEs (TIPA).

[0003] A System-on-Chip (SoC) is a technology designed to implement complex electronic systems on a single chip by integrating various Intellectual Property (IP) blocks, such as a central processing unit (CPU), memory, digital signal processing units, and analog circuits, onto a single semiconductor chip.

[0004] Figure 1 is a block diagram illustrating a conventional system-on-chip (SoC).

[0005] The SoC includes a plurality of IP blocks (111, 112, 113), and each IP block (111, 112, 113) has one or more ports for transmitting and receiving signals with an external device. The SoC includes a General Purpose Input / Output (GPIO) (120) for interfacing with an external device. The General Purpose Input / Output (120) consists of tens to hundreds of GPIO pads, and each GPIO pad is connected to an external device of the SoC to transmit and receive data or to detect the state of the internal circuit of the SoC.

[0006] IP blocks (111, 112, 113) may include processor blocks, memory blocks, multimedia blocks, network blocks, logic blocks, security blocks, interface blocks, hard macro blocks, etc.

[0007] In the case of a typical SoC, since the number of IP block ports is much greater than the number of GPIO pads, the GPIO pads must be able to be selectively connected to multiple ports, and for this purpose, an input / output multiplexer (IOMUX) (130) may be used.

[0008] The input / output multiplexer (130) allows a single GPIO pad to be connected to any of the multiple ports according to a control signal, thereby enabling flexible reconfiguration of the connection between the ports inside the SoC and the GPIO pad. For example, the same GPIO pad may be configured to be connected to a port of a security block at a specific time to transmit encryption-related data, and at another time to be connected to a port of a sensor interface block to receive sensor data.

[0009] Meanwhile, SoCs must support a test mode to detect functional defects and verify circuit operation after manufacturing, and to this end, a Design-for-Test (DFT) structure must be incorporated. Conventional SoC designs often consider only I / O connection structures centered on functional operation, and since no separate test path is provided for GPIO pads, there has been a problem in that GPIO defects cannot be sufficiently verified during the manufacturing process or during the testing phase after mass production.

[0010] To solve these problems, recent I / O multiplexers are being designed to simultaneously perform the DFTMUX function for internal circuit observation and control in test mode as well as in function mode. However, if an I / O multiplexer is designed with a structure that supports both function mode and test mode in this way, the following problems may occur.

[0011] First, design complexity increases. Since multiple ports are connected to a single GPIO pad and separate path selection control must be configured for both functional and test modes, the path selection logic of the I / O multiplexer becomes very complex. Furthermore, as multiple control signals and data paths overlap, wiring complexity, area, and power consumption increase, making it difficult to analyze the timing and ensure the reliability of the entire SoC.

[0012] In addition, while the DFT structure itself is inserted by EDA (Electronic Design Automation) tools, the preceding Pre-DFT work must mostly be performed manually by DFT engineers. Generally, since functional designers and DFT designers design individually, design errors and omitted tests may occur due to a lack of information sharing between them regarding GPIO-related I / O multiplexer settings, port-pin mapping, and mode switching settings.

[0013] In addition, since defects such as short, open, and leakage between GPIO pads are difficult to detect with general logic tests alone, a direct control and observation path in test mode is required. However, in conventional structures, the test paths of GPIO pads are not clearly defined or are inconsistent, which leads to a problem where the overall test coverage is limited.

[0014] Furthermore, in the SoC design flow, DFT is often perceived as a separate area from functional design; consequently, functional designers design without considering DFT, and DFT designers attempt to insert DFT structures without a sufficient understanding of functional behavior. In particular, although the configuration for GPIO testing should be established during the Pre-DFT phase, it tends to remain a gray zone due to unclear responsibility.

[0015] The objective of the present invention is to provide a general-purpose input / output test system and a system-on-chip including the same, which is configured by hardware-connecting the ports of an IP block and the GPIO pads, and which can flexibly control the selection of the actual test path using a controller based on the IEEE 1687 standard.

[0016] Another objective of the present invention is to provide a general-purpose input / output test system and a system-on-chip including the same, which enables testing of general-purpose input / output (GPIO) through the transmission and reception of test signals between a plurality of IP blocks and general-purpose input / output (GPIO) in test mode by flexibly controlling path selection after configuring all connections to be possible in hardware.

[0017] A general-purpose input / output test system according to one embodiment of the present invention includes a first pad group controller that performs pad function input / output and pad function operation control in a function mode and first pad test input / output and pad test operation control for each of a plurality of first GPIO pads constituting a first pad group, and a first hard macro interface that transmits and receives port input / output in a test mode for each of a plurality of ports constituting a first IP block.

[0018] The general-purpose input / output test system further includes a second pad group controller that performs pad function input / output and pad function operation control in function mode and second pad test input / output and pad test operation control for each of a plurality of second GPIO pads constituting a second pad group, and a first GPIO multiplexer that transmits the first pad test input / output and the second pad test input / output to a first hard macro interface.

[0019] Port input / output includes at least one of a function port input / output, a first pad test input / output, or a second pad test input / output.

[0020] The general-purpose input / output test system further includes a second GPIO multiplexer that allows the first pad test input / output to be transmitted to the second IP block.

[0021] The general-purpose input / output test system further includes a first GPIO router that distributes the first pad test input / output to a first GPIO multiplexer and a second GPIO multiplexer.

[0022] The general-purpose input / output test system further includes a second GPIO router that outputs first pad test outputs transmitted from a first GPIO router to a second GPIO multiplexer and transmits first pad test inputs transmitted from the second GPIO multiplexer to the first GPIO router.

[0023] The first IP block is a hard macro block, and the second IP block is a non-hard macro block.

[0024] The general-purpose I / O test system further includes a second hard macro interface that transmits and receives port I / O in test mode for each of the plurality of ports constituting the second IP block.

[0025] The second IP block is a hard macro block.

[0026] A general-purpose input / output test system according to another embodiment of the present invention includes a first pad group controller that performs pad function input / output and pad function operation control in a function mode and first pad test input / output and pad test operation control for each of a plurality of first GPIO pads constituting a first pad group, a second pad group controller that performs pad function input / output and pad function operation control in a function mode and second pad test input / output and pad test operation control in a test mode for each of a plurality of second GPIO pads constituting a second pad group, and a first GPIO multiplexer that transmits the first pad test input / output and the second pad test input / output to a port of a first IP block.

[0027] The general-purpose input / output test system further includes a second GPIO multiplexer that allows the first pad test input / output to be transmitted to the second IP block.

[0028] The general-purpose input / output test system further includes a first GPIO router that distributes the first pad test input / output to a first GPIO multiplexer and a second multiplexer.

[0029] The general-purpose input / output test system further includes a second GPIO router that outputs first pad test outputs transmitted from a first GPIO router to a second GPIO multiplexer and transmits first pad test inputs transmitted from the second GPIO multiplexer to the first GPIO router.

[0030] The 1st IP block and the 2nd IP block are non-hard macro blocks.

[0031] A general-purpose input / output test system according to another embodiment of the present invention includes a first pad group controller that performs pad function input / output and pad function operation control in a function mode and first pad test input / output and pad test operation control for each of a plurality of first GPIO pads constituting a first pad group, a first GPIO multiplexer that transmits the first pad test input / output to a port of a first IP block, and a second GPIO multiplexer that transmits the first pad test input / output to a port of a second IP block.

[0032] The general-purpose input / output test system further includes a first GPIO router that distributes the first pad test input / output to a first GPIO multiplexer and a second GPIO multiplexer.

[0033] The general-purpose input / output test system further includes a second GPIO router that outputs first pad test outputs transmitted from a first GPIO router to a second GPIO multiplexer and transmits first pad test inputs transmitted from the second GPIO multiplexer to the first GPIO router.

[0034] The general-purpose input / output test system further includes a first hard macro interface that transmits and receives port input / output in test mode for each of the plurality of ports constituting the first IP block.

[0035] The general-purpose I / O test system further includes a second hard macro interface that transmits and receives port I / O in test mode for each of the plurality of ports constituting the second IP block.

[0036] According to the present invention, a system-on-chip comprising the above-described general-purpose input / output test system is provided.

[0037] According to the present invention, the ports of an IP block and GPIO pads are configured by hardware-connecting them, and the selection of the actual test path is flexibly controlled using an IEEE 1687 controller, thereby eliminating constraints on path selection and enabling testing of the entire range of pad-port combinations, which has the effect of expanding the test coverage of the entire SoC.

[0038] According to the present invention, by configuring all connections to be possible in hardware and processing path selection using an IEEE 1687 controller, there is an advantage of reducing the design burden in the Pre-DFT stage and clearly separating the roles between the functional designer and the DFT designer.

[0039] According to the present invention, by performing path setting and control in test mode through an IEEE 1687 controller, various test information can be integrated and controlled through a standardized interface, thereby providing the advantage of scalability, reusability, and automation support for the test structure.

[0040] According to the present invention, by utilizing an IEEE 1687-based control structure, compatibility with existing test equipment and software tools is improved, test automation and test sequence management are facilitated, and test efficiency and consistency in the SoC mass production line can be ensured.

[0041] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art to which the present invention pertains (referred to as "person skilled in the art") from the description in the claims.

[0042] Embodiments of the present invention will be described with reference to the accompanying drawings described below, wherein similar reference numerals indicate similar elements, but are not limited thereto.

[0043] Figure 1 is a block diagram illustrating a conventional system-on-chip (SoC).

[0044] FIG. 2 is a block diagram illustrating a system-on-chip to which a general-purpose input / output test system according to the present invention is applied.

[0045] FIG. 3 is a configuration diagram of a pad group controller according to one embodiment of the present invention.

[0046] FIG. 4 is a detailed circuit diagram of a pad interface according to the present invention.

[0047] FIG. 5 is a configuration diagram of a pad group controller according to another embodiment of the present invention.

[0048] FIG. 6 is a diagram of an SoC configuration including a GPIO router according to the present invention.

[0049] FIG. 7 is a configuration diagram of a GPIO router according to the present invention.

[0050] FIG. 8 is a detailed circuit diagram of a GPIO splitter cell according to the present invention.

[0051] FIG. 9 is a configuration diagram illustrating a GPIO multiplexer according to one embodiment of the present invention.

[0052] FIG. 10 is a diagram briefly showing the connection status of the GPIO multiplexer illustrated in FIG. 9.

[0053] FIG. 11 is a configuration diagram illustrating a GPIO multiplexer according to another embodiment of the present invention.

[0054] FIG. 12 is an example diagram of the first internal circuit of the first-1 pad-port map connection part of FIG. 11.

[0055] FIG. 13 is an example diagram of the first internal circuit of the first-2 pad-port map connection part of FIG. 11.

[0056] FIG. 14 is an example diagram of the second internal circuit of the first-1 pad-port map connection part of FIG. 11.

[0057] FIG. 15 is an example diagram of the second internal circuit of the first-second pad-port map connection part of FIG. 11.

[0058] FIG. 16 is an example diagram of the third internal circuit of the first-1 pad-port map connection part of FIG. 11.

[0059] FIG. 17 is an example diagram of the third internal circuit of the first-second pad-port map connection of FIG. 11.

[0060] FIG. 18 is a configuration diagram illustrating a hard macro interface according to the present invention.

[0061] [Explanation of the symbol]

[0062] 211, 212, 213: Pad group

[0063] 221, 222, 223, 224, 225, 226: IP Block

[0064] 231, 232, 233: Pad group controllers

[0065] 241, 242, 244, 246: Hard Macro Interface

[0066] 251, 252, 253: GPIO multiplexer

[0067] 261, 262, 263, 264, 265, 266, 267: GPIO Router

[0068] Hereinafter, specific details for implementing the present invention will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions regarding widely known functions or configurations will be omitted if there is a risk of unnecessarily obscuring the essence of the present invention.

[0069] In the attached drawings, identical or corresponding components are assigned the same reference numerals. Additionally, in the description of the following embodiments, the description of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0070] The advantages and features of the embodiments disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to fully inform a person skilled in the art of the scope of the invention.

[0071] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0072] For example, the term “technique” may refer to systems, methods, computer-readable instructions, modules, algorithms, hardware logic, and / or operations throughout the document as permitted by the context described above.

[0073] In this specification, singular expressions include plural expressions unless the context clearly specifies them as singular. Additionally, plural expressions include singular expressions unless the context clearly specifies them as plural. Throughout the specification, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0074] In the present invention, terms such as 'comprising', 'comprising', etc. may indicate the presence of features, steps, actions, elements and / or components, but do not exclude the addition of one or more other functions, steps, actions, elements, components and / or combinations thereof.

[0075] In the present invention, where a specific component is described as being 'combined,' 'combined,' 'connected,' 'associated,' or 'reacted' to any other component, the specific component may be directly combined, combined, connected, and / or associated with, or reacted to the other component, but is not limited thereto. For example, one or more intermediate components may exist between the specific component and the other component. Additionally, in the present invention, "and / or" may include each of the one or more listed items or a combination of at least some of the one or more items.

[0076] In the present invention, terms such as 'first', 'second', etc., are used to distinguish a specific component from another component, and the components described above are not limited by these terms. For example, the 'first' component may be used to refer to an element of the same or similar form as the 'second' component.

[0077] General-purpose I / O test system

[0078] FIG. 2 is a block diagram illustrating a system-on-chip to which a general-purpose input / output test system according to the present invention is applied.

[0079] A system-on-chip may be composed of a general-purpose input / output (GPIO) consisting of multiple GPIO pads and multiple IP blocks. The multiple GPIO pads constituting the general-purpose input / output may be divided into at least two pad groups (211, 212, 213). Each pad group (211, 212, 213) may be grouped based on placement location and may include one or more GPIO pads. Each GPIO pad may belong to at least one pad group (211, 212, 213), and one GPIO pad may constitute one pad group.

[0080] FIG. 2 illustrates a system-on-chip composed of three pad groups (211, 212, 213) and six IP blocks (221, 222, 223, 224, 225, 226), but the number of pad groups and IP blocks is not limited thereto. Each pad group (211, 212, 213) may consist of the same number of GPIO pad(s) or different number of GPIO pad(s). For example, the first pad group (211) may consist of n1 GPIO pads, the second pad group (212) may consist of n2 GPIO pads, and the third pad group (213) may consist of n3 GPIO pads. Here, n1, n2, and n3 may be the same natural number or different natural numbers.

[0081] Each GPIO pad can be connected to a different IP block for each test mode and may operate as an input or an output. To this end, pad operation control is required to control the operation of the GPIO pad. Each GPIO pad may be provided with a pad input that is input from within the SoC to the GPIO pad and a pad output that is output from the GPIO pad to within the SoC, along with multiple pad operation control signals. The pad operation control signals may include a drive strength (DS) signal to determine the output drive strength of the pad, a pull enable (PE) signal to determine whether the pad pull circuit is enabled, a pull-up / down (PU) signal to determine one of pull-up and pull-down in the enabled state of the pad pull circuit, an input enable (IE) signal to determine the pad operation as an input, and an output enable (OE) signal to determine the pad operation as an output. The drive strength (DS) signal, pull enable (PE) signal, pull up / down (PU) signal, input enable (IE) signal, and output enable (OE) signal are each independent pad operation control signals, and these can be collectively referred to as pad operation control signals.

[0082] Pad inputs include pad function inputs input to GPIO pads in function mode and pad test inputs input to GPIO pads in test mode. Pad outputs include pad function outputs output from GPIO pads in function mode and pad test outputs output from GPIO pads in test mode.

[0083] IP blocks (221, 222, 223, 224, 225, 226) may include processor blocks, memory blocks, multimedia blocks, network blocks, logic blocks, security blocks, interface blocks, hard macro blocks, etc. IP blocks that are not hard macro blocks may be collectively referred to as non-hard macro blocks. Non-hard macro blocks may include processor blocks, memory blocks, multimedia blocks, network blocks, logic blocks, security blocks, interface blocks, etc.

[0084] The six IP blocks (221, 222, 223, 224, 225, 226) of FIG. 2 can be divided into multiple block groups. Multiple IP blocks constituting the SoC can be distributed and arranged within the SoC, and multiple IP blocks can be grouped into block groups based on their placement locations. In FIG. 2, it is assumed that the first IP block (221), the second IP block (222), and the third IP block (223) are grouped into the first block group, the fourth IP block (224) and the fifth IP block (225) are grouped into the second block group, and the sixth IP block (226) is grouped into the third block group. The number of IP blocks constituting each block group is not limited to a specific number, and the number of block group(s) and the IP block(s) belonging to each block group can be freely determined and changed by the SoC designer.

[0085] In FIG. 2, the first IP block (221), the second IP block (222), the fourth IP block (224), and the sixth IP block (226) may be hard macro blocks, and the third IP block (223) and the fifth IP block (225) may be non-hard macro blocks. The number of hard macro blocks and the number of non-hard macro blocks constituting the SoC can be freely determined and changed by the SoC designer.

[0086] A general-purpose input / output test system includes a first pad group controller (231) that performs pad function input / output and pad function operation control in function mode and first pad test input / output and pad test operation control for each of a plurality of GPIO pads constituting a first pad group (211), and a first hard macro interface (241) that transmits and receives port input / output in test mode for each of a plurality of ports constituting a first IP block (221). The port input / output may include at least one of the first pad test input / output, function port input / output, and register test data.

[0087] The general-purpose input / output test system may further include a second pad group controller (232) and a third pad group controller (233). The second pad group controller (232) performs pad function input / output and pad function operation control in function mode for each of the plurality of GPIO pads constituting the second pad group (212), and performs second pad test input / output and pad test operation control in test mode. The third pad group controller (233) performs pad function input / output and pad function operation control in function mode for each of the plurality of GPIO pads constituting the third pad group (213), and performs third pad test input / output and pad test operation control in test mode. Additional pad group controllers may be included depending on the number of pad groups of the general-purpose input / output (GPIO), and it is preferable that the pad groups and pad group controllers be configured to correspond one-to-one.

[0088] The first hard macro interface (241) may receive at least one of the first pad test input / output from the first pad group controller (231) or the second pad test input / output from the second pad group controller (232). The first hard macro interface (241) may transmit and receive port input / output to each of the plurality of ports constituting the first IP block (221) in test mode. This port input / output may include at least one of the pad test input / output, function port input / output, and register test data transmitted from the pad group controller.

[0089] The general-purpose input / output test system may further include a second hard macro interface (242) that performs port input / output for each of the plurality of ports constituting the second IP block (222) in test mode, a fourth hard macro interface (244) that performs port input / output for each of the plurality of ports constituting the fourth IP block (224), and a sixth hard macro interface (246) that performs port input / output for each of the plurality of ports constituting the sixth IP block (226).

[0090] In test mode, the second hard macro interface (242) can receive pad test input / output from at least one of the first and second pad group controllers (231, 232). The fourth hard macro interface (244) can receive pad test input / output from at least one of the first, second, and third pad group controllers (231, 232, 233). The sixth hard macro interface (246) can receive pad test input / output from at least one of the second and third pad group controllers (232, 233).

[0091] A general-purpose I / O test system may further include GPIO multiplexers (MUX) (251, 252, 253) placed in each block group. The SoC of the example in FIG. 2 consists of three block groups, and thus includes three GPIO multiplexers (251, 252, 253). Each GPIO multiplexer (251, 252, 253) supports multiple I / O so that GPIO pads of one or more pad groups can be connected to one or more IP blocks.

[0092] The first pad test input / output of the first pad group controller (231) and the second pad test input / output of the second pad group controller (232) are connected to the input side of the first GPIO multiplexer (251). The first hard macro interface (241), the second hard macro interface (242), and the third IP block (223) may be optionally connected to the output side of the first GPIO multiplexer (251). Through the first GPIO multiplexer (251), the GPIO pads of the first pad group (211) and the second pad group (212) may be physically connected to the corresponding ports of the first IP block (221), the second IP block (222), and the third IP block (223), respectively.

[0093] The first pad test input / output of the first pad group controller (231), the second pad test input / output of the second pad group controller (232), and the third pad test input / output of the third pad group controller (233) are connected to the input side of the second GPIO multiplexer (252). The fourth hard macro interface (244) and the fifth IP block (225) may be optionally connected to the output side of the second GPIO multiplexer (252). Through the second GPIO multiplexer (252), the GPIO pads of the first pad group (211), the second pad group (212), and the third pad group (213) may be physically connected to the corresponding ports of the fourth IP block (224) and the fifth IP block (225), respectively.

[0094] The second pad test input / output of the second pad group controller (232) and the third pad test input / output of the third pad group controller (233) are connected to the input side of the third GPIO multiplexer (253). The sixth hard macro interface may be connected to the output side of the third GPIO multiplexer (253). Through the third GPIO multiplexer (253), the GPIO pads of the second pad group (212) and the third pad group (213) may each be physically connected to the corresponding port of the sixth IP block (226).

[0095] The first IP block (221), the second IP block (222), the fourth IP block (224), and the sixth IP block (226), which are hard macro blocks, can be connected to the first GPIO multiplexer (251), the second GPIO multiplexer (252), and the third GPIO multiplexer (253) through the first hard macro interface (241), the second hard macro interface (242), the fourth hard macro interface (244), and the sixth hard macro interface (246), respectively. Meanwhile, the third IP block (223) and the fifth IP block (225), which are non-hard macro blocks, can be connected to the first GPIO multiplexer (251) and the second GPIO multiplexer (252), respectively, without mediating a hard macro interface.

[0096] A general-purpose input / output test system may further include multiple GPIO routers. A first-1 GPIO router (261) distributes the first pad test input / output of the first pad group controller (231) to the first GPIO multiplexer (251). A first-2 GPIO router (262) receives the first pad test input / output of the first pad group controller (231) through the first-1 GPIO router (261) and distributes it to the second GPIO multiplexer (252). A second-1 GPIO router (263) distributes the second pad test input / output of the second pad group controller (232) to the first GPIO multiplexer (251). A second-2 GPIO router (264) receives the second pad test input / output of the second pad group controller (232) through the second-1 GPIO router (263) and distributes it to the second GPIO multiplexer (252). The 2-3 GPIO router (265) receives the 2nd pad test input / output of the 2nd pad group controller (232) through the 2-2 GPIO router (264) and distributes it to the 3rd GPIO multiplexer (253). The 3-1 GPIO router (266) distributes the 3rd pad test input / output of the 3rd pad group controller (233) to the 2nd GPIO multiplexer (252). The 3-2 GPIO router (267) receives the 3rd pad test input / output of the 3rd pad group controller (233) through the 3-1 GPIO router (266) and distributes it to the 3rd GPIO multiplexer (253).

[0097] One example of a pad group controller

[0098] FIG. 3 is a configuration diagram of a pad group controller according to one embodiment of the present invention.

[0099] The pad group controller of FIG. 3 may be any one of the first pad group controller (231), the second pad group controller (232), or the third pad group controller (233) of FIG. 2.

[0100] A pad group controller includes one or more pad interfaces (310, 320) configured to correspond to each GPIO pad (301, 302), and a test controller (330) that outputs a test mode signal for determining an operation mode to the pad interfaces (310, 320) and pad test operation control signals for controlling pad operation in the test mode. GPIO pads (301, 302) connected to a single pad group controller may form the same pad group. It is preferable that the number of pad interfaces included in the pad group controller be equal to the number of GPIO pads forming the pad group. The operation modes of the pad interfaces may include a test mode and a function mode.

[0101] Each corresponding GPIO pad (301, 302) is connected to the pad interface (310, 320). The pad interface (310, 320) provides pad operation control (PAD CTRL) signals to the GPIO pad (301, 302), receives a pad output (PAD OUT) signal from the GPIO pad (301, 302), and provides a pad input (PAD IN) signal to the GPIO pad (301, 302). Pad operation control signals may include a drive strength (DS) signal for determining the output drive strength of the pad, a pull enable (PE) signal for determining whether the pad pull circuit is activated, a pull-up / down (PU) signal for determining one of pull-up and pull-down in the activated state of the pad pull circuit, an input enable (IE) signal for determining the pad operation as an input, and an output enable (OE) signal for determining the pad operation as an output.

[0102] A GPIO function controller (304) and a GPIO router (305) may be connected to the pad interface (310, 320). The operation mode of the pad interface (310, 320) is determined by the control of the test controller (330), and the operation mode may include a function mode or a test mode. The GPIO router (305) may be any one of the first-1 GPIO router (261), first-2 GPIO router (262), second-1 GPIO router (263), second-2 GPIO router (264), second-3 GPIO router (265), third-1 GPIO router (266), or third-2 GPIO router (267) of FIG. 2.

[0103] In function mode, the GPIO function controller (304) outputs pad function input (PAD FUNC IN) signals and pad function operation control (PAD FUNC CTRL) signals to pad interfaces (310, 320) and receives pad function output (PAD FUNC OUT) signals from each pad interface (310, 320). In test mode, the GPIO router (305) outputs pad test input (PAD TEST IN) signals to each pad interface (310, 320) and receives pad test output (PAD TEST OUT) signals from each pad interface (310, 320).

[0104] A first pad interface (310) can be connected to the first GPIO pad (301), and an n-th pad interface (320) can be connected to the n-th GPIO pad (302). A pad group consists of a total of n GPIO pads, and a pad interface corresponding one-to-one can be connected to each GPIO pad.

[0105] The first pad interface (310) and the nth pad interface (320) receive a TEST MODE signal from the test controller (330) indicating whether the test mode is enabled or disabled. When the test mode is disabled, each pad interface (310, 320) operates in function mode, and when the test mode is enabled, each pad interface (310, 320) operates in test mode.

[0106] The signal flow when the first pad interface (310) operates in function mode is as follows. The GPIO function controller (304) outputs pad function operation control (PAD FUNC CTRL 1) signals to the first pad interface (310) to control the operation of the first GPIO pad (301), and the first pad interface (310) provides pad operation control (PAD CTRL 1) signals to the first GPIO pad (301) based on the pad function operation control (PAD FUNC CTRL 1) signals. In addition, a pad output (PAD OUT 1) signal generated from the first GPIO pad (301) is received by the first pad interface (310), and the first pad interface (310) outputs a pad function output (PAD FUNC OUT 1) signal to the GPIO function controller (304) based on the pad output (PAD OUT 1) signal. Additionally, a pad function input (PAD FUNC IN 1) signal generated by the GPIO function controller (304) is input to the first pad interface (310), and the first pad interface (310) outputs a pad input (PAD IN 1) signal to the first GPIO pad (301) based on the pad function input (PAD FUNC IN 1) signal.

[0107] Meanwhile, the signal flow when the first pad interface (310) operates in test mode is as follows. The test controller (330) outputs pad test operation control (PAD TEST CTRL 1) signals to the first pad interface (310) to control the operation of the first GPIO pad (301), and the first pad interface (310) outputs pad operation control (PAD CTRL 1) signals to the first GPIO pad (301) based on the pad test operation control (PAD TEST CTRL 1) signals. In addition, a pad output (PAD OUT 1) signal generated from the first GPIO pad (301) is input to the first pad interface (310), and the first pad interface (310) outputs a pad test output (PAD TEST OUT 1) signal to the GPIO router (305) based on the pad output (PAD OUT 1) signal. Additionally, a pad test input (PAD TEST IN 1) signal input from the GPIO router (305) is input to the first pad interface (310), and the first pad interface (310) outputs a pad input (PAD IN 1) signal to the first GPIO pad (301) based on this pad test input (PAD TEST IN 1) signal.

[0108] Similarly, the signal flow when the n-th pad interface (320) operates in function mode is as follows. The GPIO function controller (304) outputs pad function operation control (PAD FUNC CTRL n) signals for controlling the operation of the n-th GPIO pad (302) to the n-th pad interface (320), and the n-th pad interface (320) outputs pad operation control (PAD CTRL n) signals to the n-th GPIO pad (302) based on the pad function operation control (PAD FUNC CTRL n) signals. Additionally, a pad output (PAD OUT n) signal is input from the n-th GPIO pad (302) to the n-th pad interface (320), and the n-th pad interface (320) outputs a pad function output (PAD FUNC OUT n) signal to the GPIO function controller (304) based on the pad output (PAD OUT n) signal. Additionally, a pad function input (PAD FUNC IN n) signal input from the GPIO function controller (304) is input to the n-th pad interface (320), and the n-th pad interface (320) outputs a pad input (PAD IN n) signal to the n-th GPIO pad (302) based on this pad function input (PAD FUNC IN n) signal.

[0109] Meanwhile, the signal flow when the n-th pad interface (320) operates in test mode is as follows. The test controller (330) outputs pad test operation control (PAD TEST CTRL n) signals to the n-th pad interface (320) to control the operation of the n-th GPIO pad (302), and the n-th pad interface (320) outputs pad operation control (PAD CTRL n) signals to the n-th GPIO pad (302) based on the pad test operation control (PAD TEST CTRL n) signals. Additionally, a pad output (PAD OUT n) signal is input from the n-th GPIO pad (302) to the n-th pad interface (320), and the n-th pad interface (320) outputs a pad test output (PAD TEST OUT n) signal to the GPIO router (305) based on the pad output (PAD OUT n) signal. Additionally, a pad test input (PAD TEST IN n) signal input from the GPIO router (305) is transmitted to the n-th pad interface (320), and the n-th pad interface (320) outputs a pad input (PAD IN n) signal to the n-th GPIO pad (302) based on the pad test input (PAD TEST IN n) signal.

[0110] The test controller (330) may be a controller based on the IEEE 1687 standard (IJTAG: Internal Joint Test Action Group). The test controller (330) can set the test mode register (331) and the test operation control register (332) through the IJTAG interface. Each register (331, 332) may be configured as a test data register (TDR) that operates in a shift manner.

[0111] The test mode register (331) may be composed of a single flip-flop and outputs a test mode signal that determines whether the first pad interface (310) and the n-th pad interface (320) will operate in test mode or function mode. This test mode signal may be a 1-bit control signal indicating the activation or deactivation of the test mode.

[0112] The test operation control register (332) may be composed of multiple flip-flops and may output multiple pad test operation control (PAD TEST CTRL 1, PAD TEST CTRL n) signals corresponding to each pad interface. For example, if the pad test operation control (PAD TEST CTRL 1) signals for controlling the operation of the first GPIO pad are composed of a total of five control signals, including drive strength (DS), pull enable (PE), pull up / down (PU), input enable (IE), and output enable (OE), the test operation control register (332) may output control signals that determine the value or activation status of each control signal. At this time, the test operation control register (332) may include flip-flops corresponding to each control signal for the first GPIO pad. Two or more flip-flops may be used to determine the value of a single control signal. For example, since a control value of 2 bits or more may be required for the drive strength (DS), multiple flip-flops may be used to configure the drive strength control signal. Additionally, the test operation control register (332) may additionally include flip-flops that determine the value or activation status of the pad test operation control signals for the nth GPIO pad.

[0113] FIG. 4 is a detailed circuit diagram of a pad interface according to one embodiment of the present invention.

[0114] The pad interface may be either the first pad interface (310) or the nth pad interface (320) of FIG. 3.

[0115] The pad interface is configured to operate in either functional mode or test mode depending on the state of the test mode signal, and includes various logic circuits for the selective processing of pad outputs, pad inputs, and pad operation control signals.

[0116] The pad interface comprises a first AND operator (411) that performs a logical AND operation between the inverted signal of the TEST MODE signal and the PAD OUT signal to output a PAD FUNC OUT signal, a second AND operator (412) that performs a logical AND operation between the TEST MODE signal and the PAD OUT signal to output a PAD TEST OUT signal, an inverter (413) that inverts the TEST MODE signal and provides it to the first AND operator (411), a pad input multiplexer (414) that receives control from the TEST MODE signal and selects between the PAD FUNC IN signal and the PAD TEST IN signal to output a PAD IN signal, and for each pad operation control signal, receives control from the TEST MODE signal and selects between the PAD FUNC CTRL signal and the PAD TEST CTRL signal to pad It includes one or more operation control multiplexers (415, 416) that output operation control signals. It is preferable to include as many operation control multiplexers (415, 416) as there are pad operation control signals.

[0117] First, the pad output path is described. The pad interface includes a first AND operator (411). The first AND operator (411) performs an AND operation between the inverted signal of the TEST MODE signal and the PAD OUT signal to generate a PAD FUNC OUT signal when operating in function mode. To this end, the TEST MODE signal is inverted by an inverter (413) and then input to the first AND operator (411). Therefore, the PAD OUT signal is transmitted to the PAD FUNC OUT only when the TEST MODE signal is deactivated (i.e., in function mode).

[0118] Additionally, the pad interface includes a second AND operator (412). The second AND operator (412) performs an AND operation between a TEST MODE signal and a PAD OUT signal to generate a PAD TEST OUT signal when the TEST MODE is activated.

[0119] Next, the pad input path is described. The pad interface includes a pad input multiplexer (414). The pad input multiplexer (414) selects either a pad function input (PAD FUNC IN) signal or a pad test input (PAD TEST IN) signal and outputs it as a pad input (PAD IN) signal according to the control of the test mode (TEST MODE) signal. As a result, the pad input path can be automatically switched according to the operating mode.

[0120] Additionally, the pad interface includes a motion control multiplexer (415, 416) for generating a pad motion control signal. The motion control multiplexer (415, 416) uses a TEST MODE signal as a control signal to select one of a pad function operation control (PAD FUNC CTRL) signal and a pad test operation control (PAD TEST CTRL) signal, and outputs the selected signal as a pad operation control (PAD CTRL) signal.

[0121] Here, the pad operation control signal includes a drive strength (DS), pull enable (PE), pull up / down (PU), input enable (IE), and output enable (OE), and the operation control multiplexer (415, 416) can be configured to correspond to each pad operation control signal.

[0122] The operation control multiplexer (415) receives control from the test mode signal for the driving intensity (DS) signal and selects between the pad function operation control (PAD FUNC CTRL_DS) signal and the pad test operation control (PAD TEST CTRL_DS) signal to output as the pad operation control (PAD CTRL_DS) signal. Additionally, the operation control multiplexer (416) receives control from the test mode signal for the output enable (OE) signal and selects between the pad function operation control (PAD FUNC CTRL_OE) signal and the pad test operation control (PAD TEST CTRL_OE) signal to output as the pad operation control (PAD CTRL_OE) signal.

[0123] Likewise, an operation control multiplexer that selects between a pad function operation control signal and a pad test operation control signal for a pull enable (PE) signal, an operation control multiplexer that selects between a pad function operation control signal and a pad test operation control signal for a pull up / down (PU) signal, and an operation control multiplexer that selects between a pad function operation control signal and a pad test operation control signal for an input enable (IE) signal may be further included.

[0124] When the TEST MODE signal is deactivated, a high level is input to the first input terminal of the first AND operator (411) and a low level is input to the first input terminal of the second AND operator (412). When the TEST MODE signal is activated, a high level is input to the first input terminal of the second AND operator (412) and a low level is input to the first input terminal of the first AND operator (411). When a low level is input to the first input terminal of the AND operator, it is output as a low level regardless of the value input to the second input terminal, and when a high level is input to the first input terminal of the AND operator, the value input to the second input terminal is output.

[0125] Accordingly, when the TEST MODE signal is deactivated, the PAD OUT is output to the PAD FUNC OUT through the first AND operator (411), and the output terminal of the second AND operator (412) remains at a low level. Meanwhile, when the TEST MODE signal is activated, the output terminal of the first AND operator (411) remains at a low level, and the PAD OUT is output to the PAD TEST OUT through the second AND operator (412).

[0126] The pad input multiplexer (414) selects the pad function input (PAD FUNC IN) and outputs it to the pad input (PAD IN) when the test mode (TEST MODE) signal is deactivated, and selects the pad test input (PAD TEST IN) and outputs it to the pad input (PAD IN) when the test mode (TEST MODE) signal is activated.

[0127] The operation control multiplexer (415) selects the pad function operation control (PAD FUNC CTRL_DS) and outputs the pad operation control (PAD CTRL_DS) when the test mode (TEST MODE) signal is deactivated, and selects the pad test operation control (PAD TEST CTRL_DS) and outputs the pad operation control (PAD CTRL_DS) when the test mode (TEST MODE) signal is activated. Meanwhile, the operation control multiplexer (416) selects the pad function operation control (PAD FUNC CTRL_OE) and outputs the pad operation control (PAD CTRL_OE) when the test mode (TEST MODE) signal is deactivated, and selects the pad test operation control (PAD TEST CTRL_OE) and outputs the pad operation control (PAD CTRL_OE) when the test mode (TEST MODE) signal is activated.

[0128] Another embodiment of a pad group controller

[0129] The pad group controller of FIGS. 3 and 4 is configured such that, during testing, a single test operation control register outputs all pad test operation control signals for all GPIO pads. The test operation control register is a test data register (TDR) composed of multiple flip-flops that operate in a shifting manner and has a structure that sets data by sequentially pushing (shifting).

[0130] In this structure, changing just one bit of the setting consumes cycles corresponding to the length of the entire TDR, that is, the number of flip-flops. As the size of the system-on-chip (SoC) increases and the number of GPIO pads connected to a single pad group controller increases, the number of pad test operation control signals to be processed by a single test operation control register increases, and accordingly, the number of flip-flops constituting the test operation control register also increases.

[0131] Most test operation control signals rarely need to be changed once set. However, since input and output enable signals configure the corresponding pads to function as input or output in any test mode, they must be modified multiple times whenever the test mode changes during the test.

[0132] The problem is that even if the input or output operation of a single pad changes, requiring a change to only a single input enable or output enable, the entire value of the test operation control register must be re-shifted and reset. This consumes a cycle equivalent to the entire length of the test operation control register every time, resulting in a significant decrease in test efficiency and an increase in total test time. This, in turn, leads to the problem of increased test costs.

[0133] Accordingly, the present embodiment additionally includes a separate test operation control register that outputs an input enable signal and an output enable signal in test mode. By configuring at least two test operation control registers to each output different pad test operation control signals, the change of input and output enable signals can be performed more efficiently.

[0134] FIG. 5 is a configuration diagram of a pad group controller according to another embodiment of the present invention.

[0135] The pad group controller includes one or more pad interfaces (430) configured to correspond to each GPIO pad, and a test controller (420) that outputs a test mode signal for determining an operation mode to the pad interfaces (430) and pad test operation control signals for controlling pad operation in the test mode.

[0136] The pad operation control signal may include a drive strength (DS) signal for determining the output drive strength of the pad, a pull enable (PE) signal for determining whether to activate the pad's pull circuit, a pull-up / down (PU) signal for selecting one of pull-up and pull-down when the pad's pull circuit is activated, an input enable (IE) signal for determining the pad's operation as an input, and an output enable (OE) signal for determining the pad's operation as an output.

[0137] The pad test operation control signal may include a test drive strength control signal, a test pull enable control signal, a test pull-up / down control signal, a test input enable control signal, and a test output enable control signal, each corresponding to the above pad operation control signal. Additionally, the pad function operation control signal may include a function drive strength control signal, a function pull enable control signal, a function pull-up / down control signal, a function input enable control signal, and a function output enable control signal, each corresponding to the pad operation control signal.

[0138] Each pad interface (430) is connected to a corresponding GPIO pad to provide a pad operation control signal to the GPIO pad, receive a pad output signal from the GPIO pad, and provide a pad input signal to the GPIO pad. The basic operation of the pad interface (430) is the same as that of the pad interfaces (310, 320) of FIG. 3.

[0139] The test controller (420) is configured to include a test mode register (331) that outputs a test mode signal determining whether the pad interface (430) will operate in a test mode or a function mode, a first test operation control register (421) that outputs one or more pre-set pad test operation control signals in the test mode, and a second test operation control register (422) that outputs the remaining pre-set pad test operation control signals in the test mode. Here, the first test operation control register (421) outputs a pad test operation control signal with a low change frequency, and the second test operation control register (422) outputs a pad test operation control signal with a high change frequency. Based on such change frequencies, the two test operation control registers (421, 422) are each assigned to output test operation control signals.

[0140] The test controller (420) may be a controller based on the IEEE 1687 standard (IJTAG: Internal Joint Test Action Group). The test controller (420) can set the test mode register (331), the first test operation control register (421), and the second test operation control register (422) through the IJTAG interface. Each register (331, 421, 422) may be configured as a test data register (TDR) that operates in a shift manner.

[0141] The first test operation control register (421) is configured to output a test drive strength control signal, a test pull enable control signal, and a test pull-up / down control signal, and the second test operation control register (422) is configured to output a test input enable control signal and a test output enable control signal.

[0142] The test mode register (331) may be composed of a single flip-flop and outputs a test mode signal that determines whether the pad interface (430) will operate in test mode or function mode. This test mode signal may be a 1-bit control signal indicating the activation or deactivation of the test mode.

[0143] The first test operation control register (421) and the second test operation control register (422) may each be composed of a plurality of flip-flops and may output a plurality of pad test operation control signals to the pad interface (430). The first test operation control register (421) may include flip-flops corresponding to a test drive strength control signal, a test pull enable control signal, and a test pull-up / down control signal. The second test operation control register (422) may include flip-flops corresponding to a test input enable control signal and a test output enable control signal.

[0144] The configuration of the first AND operator (411), the second AND operator (412), the inverter (413), and the pad input multiplexer (414) constituting the pad interface (430), as well as the pad output path and the pad input path, are the same as those in FIG. 4.

[0145] The pad interface (430) includes a plurality of operation control multiplexers (441, 451, 452). Each operation control multiplexer receives control from a test mode signal, selects one of the function operation control (PAD FUNC CTRL) signal and the test operation control (PAD TEST CTRL) signal, and outputs it as a pad operation control (PAD CTRL) signal that is finally applied to the GPIO pad. The operation control multiplexers correspond to the types of pad operation control signals, namely, drive strength (DS), pull enable (PE), pull up / down (PU), input enable (IE), and output enable (OE), respectively.

[0146] For example, the operation control multiplexer (441) receives control of the test mode (TEST MODE) signal for the drive intensity (DS) signal and selects one of the function drive intensity control (PAD FUNC CTRL_DS) signal and the test drive intensity control (PAD TEST CTRL_DS) signal output from the first test operation control register (421) and outputs it as the drive intensity control (PAD CTRL_DS) signal. Similarly, in the case of a pull enable (PE) signal, an operation control multiplexer may be included that selects between the function pull enable control signal and the test pull enable control signal output from the first test operation control register (421). Additionally, in the case of a pull-up / down (PU) signal, an operation control multiplexer may be further included that selects between the function pull-up / down control signal and the test pull-up / down control signal output from the first test operation control register (421).

[0147] Additionally, the operation control multiplexer (451) receives control of the test mode signal for the output enable signal and selects one of the function output enable control (PAD FUNC CTRL_OE) signal and the test output enable control (PAD TEST CTRL_OE) signal output from the second test operation control register (422) and outputs it as the output enable (PAD CTRL_OE) signal. Likewise, the operation control multiplexer (452) receives control of the test mode signal for the input enable signal and selects one of the function input enable control (PAD FUNC CTRL_IE) signal and the test input enable control (PAD TEST CTRL_IE) signal output from the second test operation control register (422) and outputs it as the input enable (PAD CTRL_IE) signal.

[0148] The values ​​of the test drive strength control signal, test pull enable control signal, and test pull-up / down control signal rarely change after the initial test setup. On the other hand, the values ​​of the test input enable control signal and test output enable control signal must be changed frequently whenever the test mode is changed.

[0149] Therefore, by assigning signals with a high change frequency (input enable and output enable) to a separate test operation control register, only the necessary parts can be rapidly updated without the need to repeatedly shift the entire register during testing. This significantly reduces the time required for shifting, thereby increasing test efficiency and effectively reducing test time and costs.

[0150] GPIO Router

[0151] FIG. 6 is a diagram of an SoC configuration including a GPIO router according to the present invention.

[0152] As mentioned in the description of FIG. 2, the SoC (500) is composed of multiple IP blocks, and the multiple IP blocks can be grouped into multiple block groups (530, 540, 550, 560, 570) according to their placement location. FIG. 6 is an example of an SoC composed of five block groups.

[0153] The SoC (500) includes a pad group (510) composed of a plurality of GPIO pads, and the pad group (510) is typically placed on the outer edge of the SoC (500) to facilitate signal input and output with the outside.

[0154] Additionally, the SoC (500) includes a pad group controller (520) positioned near the pad group (510). The pad group controller (520) may be any one of the first pad group controller (231), the second pad group controller (232), or the third pad group controller (233) of FIG. 2.

[0155] The pad group controller (520) is configured to perform different functions for each GPIO pad constituting the pad group (510) according to the operation mode. More specifically, the pad group controller (520) performs pad function input / output and pad function operation control for each GPIO pad in function mode. In addition, when test mode is enabled, the pad group controller (520) performs pad test input / output and pad test operation control for each GPIO pad. This enables testing of the internal circuitry and pad operation of the SoC (500), and can be utilized to verify the electrical characteristics and operating status of the pads after manufacturing or during the system initialization phase.

[0156] To this end, it is desirable that the input / output signals of the GPIO pads be configured to be linked with multiple IP blocks placed inside the SoC. That is, the input / output signals of the GPIO pads must be distributed to multiple block groups to which each IP block belongs. However, due to the layout characteristics inside the SoC, some block groups must be physically separated from the pad group (510) or the pad group controller (520). In such cases, a means of transmission is required to efficiently distribute and collect pad test input / output signals to each block group.

[0157] In the present invention, a plurality of GPIO routers may be included as such transmission means. For example, the first GPIO router (531) receives a pad test output signal from the pad group controller (520) and distributes it to the first block group (530) and the lower third GPIO router (551). Additionally, it receives pad test input signals from the first block group (530) and the lower third GPIO router (551), respectively, and transmits them to the pad group controller (520).

[0158] Meanwhile, if all IP blocks included in the second block group (540) do not use the GPIO pads of the pad group (510), a separate GPIO router that distributes pad test input / output to the second block group (540) may be omitted. In this case, the component connected to the first GPIO router (531) as a subordinate GPIO router becomes the third GPIO router (551).

[0159] The third GPIO router (551) distributes the pad test output distributed from the upper first GPIO router (531) to the third block group (550) and the lower fourth GPIO router (561), and transmits the pad test input received from the third block group (550) and the lower fourth GPIO router (561) to the upper first GPIO router (531). The fourth GPIO router (561) distributes the pad test output distributed from the upper third GPIO router (551) to the fourth block group (560) and the lower fifth GPIO router (571), and transmits the pad test input received from the fourth block group (560) and the lower fifth GPIO router (571) to the upper third GPIO router (551). The 5th GPIO router (571) transmits the pad test output distributed from the upper 4th GPIO router (561) to the 5th block group (570) and transmits the pad test input input from the 5th block group (570) to the upper 4th GPIO router (561).

[0160] Accordingly, the pad test output from the GPIO pad can be distributed to the first block group (530), the third block group (550), the fourth block group (560), and the fifth block group (570) sequentially through the first GPIO router (531), the third GPIO router (551), the fourth GPIO router (561), and the fifth GPIO router (571). Additionally, the pad test input output from the fifth block group can be input to the GPIO pad sequentially through the fifth GPIO router (571), the fourth GPIO router (561), the third GPIO router (551), and the first GPIO router (531). A pad test input output from the fourth block group (560) can be input to a GPIO pad through the fourth GPIO router (561), the third GPIO router (551), and the first GPIO router (531) in sequence, a pad test input output from the third block group (550) can be input to a GPIO pad through the third GPIO router (551) and the first GPIO router (531), and a pad test input output from the first block group (530) can be input to a GPIO pad through the first GPIO router (531).

[0161] The GPIO routers according to the present invention have a hierarchical structure in which the side logically adjacent to the pad group controller (520) is defined as the upper layer, and the direction away from it is defined as the lower layer. Accordingly, the first GPIO router (531) transmits pad test outputs received from the pad group controller (520) to the third GPIO router (551), which is the lower layer, and relays pad test inputs collected from the lower layer to the upper layer. The physical arrangement of block groups within the system-on-chip (SoC) can be determined according to design efficiency regardless of the distance from the pad group controller (520). However, in terms of the logical hierarchical structure, the fifth block group (570) corresponds to the lowest layer that transmits and receives signals through the first, third, and fourth GPIO routers (531, 551, 561), and as a result, the fifth GPIO router (571) performs only output distribution from the upper layer and input transmission to the upper layer without a lower router connection terminal.

[0162] FIG. 7 is a configuration diagram of a GPIO router according to the present invention.

[0163] The GPIO router of FIG. 7 may correspond to any one of the first GPIO router (531), the third GPIO router (551), or the fourth GPIO router (561) of FIG. 6. The GPIO router includes a plurality of GPIO splitter cells (610, 620) that correspond to each GPIO pad, one side of which is connected to a pad group controller or an upper GPIO router, and the other side of which is connected to a block group and a lower GPIO router.

[0164] FIG. 8 is a detailed circuit diagram of a GPIO splitter cell according to the present invention.

[0165] The GPIO distributor cell includes a logical OR operator (611) that performs a logical OR operation on a pad test input (PAD TEST IN) signal output from a block group and a pad test input (PAD TEST IN) signal input from a lower GPIO router and outputs the result to an upper direction (pad group controller or upper GPIO router), and a first buffer (612) and a second buffer (613) that distribute a pad test output (PAD TEST OUT) input from a pad group controller or upper GPIO router to a block group and a lower GPIO router.

[0166] The logical OR operator (611) performs a logical OR operation on the pad test input (PAD TEST IN) output from the block group and the pad test input (PAD TEST IN) output from the lower GPIO router and outputs the result to the upper pad group controller or GPIO router. Accordingly, if the pad test input signal is active (high) in either the lower GPIO router or the block group, the signal can be transmitted to the upper level. That is, the upper GPIO router can detect when a signal comes in from any of the multiple lower paths.

[0167] The first buffer (612) buffers the pad test output (PAD TEST OUT) input from the pad group controller or the upper GPIO router and then transmits it to the block group, and the second buffer (613) buffers the pad test output (PAD TEST OUT) input from the pad group controller or the upper GPIO router and then transmits it to the lower GPIO router. Through this, the pad test output signal from the upper can be reliably branched into multiple paths, and all lower block groups can receive the same pad test output signal.

[0168] The GPIO router according to the present embodiment can implement a bidirectional test signal transmission structure capable of efficiently aggregating lower pad test input signals and transmitting them to the upper level, while simultaneously stably distributing pad test output signals from the upper level via multiple paths. Such a structure provides test flexibility and scalability for various block groups within a complex SoC and is effective in ensuring signal integrity during testing.

[0169] One embodiment of a GPIO multiplexer

[0170] The SoC can operate in various test mode types depending on the type of test target and the test scope, and the operation method of IP blocks and port I / O may vary according to each test mode type. For example, test mode types may include scan test mode, memory BIST (Built-In Seft Test) mode, logic BIST (Built-In Seft Test) mode, JTAG (Joint Test Action Group) test mode, IJTAG (Internal Joint Test Action Group) test mode, and external automatic test equipment interface test mode.

[0171] Depending on each of these test mode types, different data signals for performing tests may be provided to each port of the IP block, and the input / output direction of the port may also be dynamically configured. For example, in the SoC implementation shown in FIG. 2, in the first test mode type, a first pad among the first pad group (211) of the SoC may operate as an input pad, and the input pad may be connected to the first port of the first IP block (221). In this case, a pad test input signal may be transmitted from the first port of the first IP block (221) to the first pad of the first pad group (211).

[0172] Additionally, in the second test mode type, the first pad of the first pad group (211) operates as an output pad and can be connected to the third port of the second IP block (222). In this case, a pad test output signal output from the first pad of the first pad group (211) is transmitted to the third port of the second IP block (222). Additionally, in the third test mode type, the first pad of the first pad group (211) operates as an output pad and can be connected to the fourth port of the first IP block (221). In this case, a pad test output signal output from the first pad of the first pad group (211) is transmitted to the fourth port of the first IP block (221).

[0173] In this way, the first pad of the first pad group (211) can be connected to the first port of the first IP block (221) as an input pad, connected to the third port of the second IP block (222) as an output pad, or connected to the fourth port of the third IP block (223) as an output pad, depending on the test mode type. In other words, for each GPIO pad, the input / output direction and the connection target port must be dynamically set according to the test mode type.

[0174] Referring to FIG. 2, each GPIO pad of the first pad group (211) can be connected to one port selected according to the test mode type among the ports of the first IP block (221) to the fifth IP block (225). That is, the port of the IP block to which each GPIO pad is connected may differ depending on the test environment settings. Similarly, each GPIO pad of the second pad group (212) can also be connected to one port according to the test mode type among the ports of the first IP block (221) to the sixth IP block (226), and each GPIO pad of the third pad group (213) can be selectively connected to one port according to the test mode type among the ports of the fourth IP block (224) to the sixth IP block (226).

[0175] As such, it is desirable that the ports of the IP blocks connected to each GPIO pad of the pad group be selectively configured according to the designer's intent for each test mode type. This allows the SoC designer to set the optimal test path based on test requirements or the configuration of the test equipment.

[0176] To implement this port connection flexibility, all GPIO pads within a pad group are connected to a GPIO multiplexer, and each GPIO pad can have a physical connection path to the ports dynamically established by the GPIO multiplexer.

[0177] In other words, the GPIO multiplexer selects and connects a specific port to each GPIO pad based on control signals input for each test mode type, and blocks connections to the remaining ports, thereby ensuring that only a single port is connected in correspondence with a single test mode type. This configuration allows for flexible support of multiple test scenarios for each GPIO pad, while simultaneously preventing signal collisions or electrical interference by blocking unnecessary paths.

[0178] For example, the first GPIO multiplexer (251) illustrated in FIG. 2 is configured to be hardware-connectable to a first pad included in a first pad group (211) with a first port of a first IP block (221), a third port of a second IP block (222), and a fourth port of a third IP block (223). The ports connected to the first pad are not limited to the first port of the first IP block (221), the third port of the second IP block (222), and the fourth port of the third IP block (223), and may be configured to be connected to any port of the first IP block to the third IP block according to the intention of the SoC designer.

[0179] And, the first GPIO multiplexer (251) controls the first pad to be connected only to the first port of the first IP block (221) in the first test mode type, controls the first pad to be connected only to the third port of the second IP block (222) in the second test mode type, and controls the first pad to be connected only to the fourth port of the third IP block (223) in the third test mode type.

[0180] In this way, the GPIO multiplexer has a hardware configuration in which a single GPIO pad can be connected to multiple ports, but by operating to be connected to only a single port per test mode, it can provide a structure that satisfies the functional requirements of various test modes.

[0181] FIG. 9 is a configuration diagram illustrating a GPIO multiplexer according to the present invention.

[0182] A GPIO multiplexer includes a first port connection unit (810) configured to correspond to a first GPIO pad (801) and supporting a selective connection between the first GPIO pad (801) and ports (802, 803, 804) of two or more IP blocks, and a test controller (830) that controls the connection path according to a test mode type. The first port connection unit (810) is a circuit that selectively connects an input / output path between the first GPIO pad (801) and a plurality of ports (802, 803, 804), and the connection with each port is controlled by a port selection signal. The port selection signal is generated by a test mode type register (831) included in the test controller (830). It is preferable that one port connection unit be configured to correspond to one GPIO pad.

[0183] The GPIO multiplexer of FIG. 9 illustrates an example of operating in three test mode types, and separate ports are connected for each test mode type, but the scope of the present invention is not limited thereto. The number of test mode types is not limited to three, and a single GPIO pad may be connected to the same port in two or more test mode types.

[0184] The test controller (830) may be a controller based on the IEEE 1687 standard, namely IJTAG (Internal Joint Test Action Group). The test controller (830) controls the port connection configuration according to the test mode type by setting the test mode type register (831) through the IJTAG interface. The test mode type register (831) may be composed of a test data register (TDR) that operates in a shift manner and may internally include logic elements such as flip-flops.

[0185] The first port connection part (810) is configured with a plurality of logical AND operators so that a first pad test output signal from the first GPIO pad (801) is transmitted to a selected port, or a pad test input signal from the selected port is transmitted to the GPIO pad (801).

[0186] The first port connection unit (810) includes a first AND operator (811) in which a first pad test output (PAD TEST OUT 1) signal from a first GPIO pad (801) and a first port selection signal from a test mode type register (831) are each input to an input terminal and a first-1 port (802) is connected to an output terminal; a second AND operator (812) in which a first pad test output (PAD TEST OUT 1) signal and a second port selection signal from a test mode type register (831) are each input to an input terminal and a first-2 port (803) is connected to an output terminal; and a third AND operator (813) in which a first pad test output (PAD TEST OUT 1) signal and a third port selection signal from a test mode type register (831) are each input to an input terminal and a first-3 port (804) is connected to an output terminal.

[0187] Additionally, the first port connection section (810) comprises a fourth AND operator (814) in which a fourth port selection signal from the first-1 port (802) and the test mode type register (831) is respectively connected to an input terminal and a first pad test input (PAD TEST IN 1) signal is output from an output terminal to the first GPIO pad (801); a fifth AND operator (815) in which a fifth port selection signal from the first-2 port (803) and the test mode type register (831) is respectively connected to an input terminal and a first pad test input (PAD TEST IN 1) signal is output from an output terminal to the first GPIO pad (801); and a sixth AND operator in which a sixth port selection signal from the first-3 port (804) and the test mode type register (831) is respectively connected to an input terminal and a first pad test input (PAD TEST IN 1) signal is output from an output terminal to the first GPIO pad (801). It includes an arithmetic unit (816).

[0188] The first-1 port (802), connected to the output terminal of the first AND operator (811) and the input terminal of the fourth AND operator (814), is identical; the first-2 port (803), connected to the output terminal of the second AND operator (812) and the input terminal of the fifth AND operator (815), is identical; and the first-3 port (804), connected to the output terminal of the third AND operator (813) and the input terminal of the sixth AND operator (816), is identical. The first-1 port (802), the first-2 port (803), and the first-3 port (804) may all be different, or two or more ports may be identical.

[0189] The first GPIO pad (801) and the first port connection (810) can be connected via a pad group controller and a GPIO router. The first port connection (810) and the ports (802, 803, 804) may be connected via a hard macro interface or a separate interface, or they may be connected directly. If the IP block is a hard macro block, the first port connection (810) and the ports (802, 803, 804) may be connected via a hard macro interface. If the IP block is a non-hard macro block, the first port connection (810) and the ports (802, 803, 804) may be connected directly or via a separate interface without a hard macro interface.

[0190] If the GPIO multiplexer of FIG. 9 is the first GPIO multiplexer (251) of FIG. 2, the first GPIO pad (801) may be any one GPIO pad belonging to the first pad group (211) and the second pad group (212). Additionally, the first-1 port (802), the first-2 port (803), and the first-3 port (804) may each be any one of at least one of the first IP block (221), the second IP block (222), and the third IP block (223).

[0191] For all GPIO pads of the first pad group (211) and the second pad group (212), a port connection can be connected corresponding to each GPIO pad.

[0192] The second port connection section (820) comprises a seventh AND operator (821) in which a second pad test output (PAD TEST OUT 2) signal from the second GPIO pad (805) and a seventh port selection signal from the test mode type register (831) are each input to an input terminal and a second-1 port (806) is connected to an output terminal; an eighth AND operator (822) in which a second pad test output (PAD TEST OUT 2) signal and an eighth port selection signal from the test mode type register (831) are each input to an input terminal and a second-2 port (807) is connected to an output terminal; a ninth AND operator (823) in which a second pad test output (PAD TEST OUT 2) and a ninth port selection signal from the test mode type register (831) are each input to an input terminal and a second-3 port (808) is connected to an output terminal; and a second-1 port (806) and a tenth port selection signal are each input to an input terminal It further includes a 10th AND operator (824) that is connected and outputs a 2nd pad test input (PAD TEST IN 2) signal to the 2nd GPIO pad (805) through an output terminal, a 11th AND operator (825) that outputs a 2nd pad test input (PAD TEST IN 2) signal to the 2nd GPIO pad (805) through an output terminal, and a 2nd 3rd port (808) and a 12th port selection signal that are connected to an input terminal and output a 2nd pad test input (PAD TEST IN 2) signal to the 2nd GPIO pad (806) through an output terminal.

[0193] Each port is connected to an AND operator for the output path and an AND operator for the input path, respectively, according to the test mode type. The first AND operator (811) is connected to the pad test output path between the first GPIO pad (801) and the first-1 port (802), and the fourth AND operator (814) is connected to the pad test input path between the first GPIO pad (801) and the first-1 port (802). In the second test mode type, the second AND operator (812) is connected to the pad test output path between the first GPIO pad (801) and the first-2 port (803), and the fifth AND operator (815) is connected to the pad test input path between the first GPIO pad (801) and the first-2 port (803). In the third test mode type, the third AND operator (813) is connected to the pad test output path between the first GPIO pad (801) and the first-third port (804), and the sixth AND operator (816) is connected to the pad test input path between the first GPIO pad (801) and the first-third port (804).

[0194] Depending on whether the port selection signal is enabled for each test mode type, only one of the input path or output path between the first GPIO pad and the port is enabled. That is, it is designed so that only one path (input or output) is enabled for each test mode type, thereby preventing interference between multiple paths.

[0195] The test mode type register (831) outputs a port selection signal to the first port connection part (810) such that when a GPIO pad operates as an input pad in a specific test mode type, only the logical AND operator connected to the pad test input path is enabled, and the logical AND operator connected to the pad test output path is disabled.

[0196] For example, when the first GPIO pad (801) operates as an input pad in the first test mode type, the test mode type register (831) enables and outputs a port select signal only to the fourth AND operator (814) connected to the input path, and outputs a deactivation signal to other AND operators to block the path. When the first GPIO pad (801) operates as an output pad in the second test mode type, the test mode type register (831) enables and outputs a port select signal only to the second AND operator (812) connected to the output path, and outputs a deactivation signal to other AND operators to block the path. When the first GPIO pad (801) operates as an output pad in the third test mode type, the test mode type register (831) enables and outputs a port select signal only to the third AND operator (813) connected to the output path, and outputs a deactivation signal to other AND operators to block the path.

[0197] The output terminal of each AND operator transmits a pad test input or pad test output only when the port select signal is active (high), and when the port select signal is inactive (low), the output of the AND operator remains at a low level.

[0198] Accordingly, in the first test mode type, since the port selection signal is activated only at the fourth AND operator (814), only the pad test input path from the first-1 port (802) to the first GPIO pad (801) is connected. In the second test mode type, since the port selection signal is activated only at the second AND operator (812), only the pad test output path from the first GPIO pad (801) to the first-2 port (803) is connected. And, in the third test mode type, since the port selection signal is activated only at the third AND operator (813), only the pad test output path from the first GPIO pad (801) to the first-3 port (804) is connected.

[0199] As such, the GPIO multiplexer of the present invention has the advantage of improving testing and debugging flexibility and enhancing chip area efficiency by selectively connecting one GPIO pad to the ports of various IP blocks according to test mode type.

[0200] Another embodiment of a GPIO multiplexer

[0201] FIG. 10 is a diagram briefly showing the connection status of the GPIO multiplexer illustrated in FIG. 9.

[0202] The GPIO multiplexer (900) is configured such that, during testing, one GPIO pad (901) is selectively connected to one port (902, 903, 904) depending on the test mode type. That is, one GPIO pad (901) can be connected to any one of the multiple ports (902, 903, 904). Here, the multiple ports (902, 903, 904) may belong to the same IP block or to different IP blocks.

[0203] Conversely, from the perspective of the ports, each port can only have one GPIO pad connected in a specific test mode type. That is, it does not support the operation of a single port being selectively connected among multiple GPIO pads. However, a function may be required where a single port can be selectively connected to any one of multiple GPIO pads in a specific test mode type.

[0204] FIG. 11 is a configuration diagram illustrating a GPIO multiplexer according to another embodiment of the present invention.

[0205] The GPIO multiplexer comprises a first pad mode selector (1011) configured to be connected to a first GPIO pad (1001) and receive a test mode signal from a test controller (1060) to selectively connect the first GPIO pad (1001) to one of a first mapping group (1020) or a second mapping group (1030); a second pad mode selector (1012) configured to be connected to a second GPIO pad (1002) and receive a test mode signal from a test controller (1060) to connect the second GPIO pad (1002) to one of a first mapping group (1020) or a third mapping group (1040); and a first mapping configured to receive a Map Select signal (Map Select 1) from a test controller (1060) to switch the connection relationship between the first GPIO pad (1001) and the second GPIO pad (1002), and between the first port (1051) and the second port (1052). Includes group (1020).

[0206] According to the present invention, a GPIO multiplexer can flexibly change the connection relationship between each GPIO pad, a mapping group, and each port according to a test mode signal and a map selection signal. This allows for support of various connection scenarios in a specific test mode type, and since any one port can be selectively connected to one of a plurality of GPIO pads, design freedom and test flexibility can be improved.

[0207] The GPIO multiplexer may additionally include a third pad mode selector (not shown) and a fourth pad mode selector (not shown). The third pad mode selector is connected to a third GPIO pad (not shown) and receives a test mode signal from a test controller (1060) to selectively connect the third GPIO pad to a second mapping group (1030). Additionally, the fourth pad mode selector is connected to a fourth GPIO pad (not shown) and receives a test mode signal from a test controller (1060) to selectively connect the fourth GPIO pad to a third mapping group (1040). The test controller (1060) provides a map select signal (Map Select 2) to the second mapping group (1030) and a map select signal (Map Select 3) to the third mapping group (1040) to control the operation mode of each mapping group.

[0208] The first mapping group (1020) is configured to switch the connection between the GPIO pad and the port according to the map select signal (Map Select 1). The first mapping group (1020) includes a first-1 pad-port map connection unit (1021) configured to operate when the first map is selected and to connect the first GPIO pad (1001) to the first port (1051) and to connect the second GPIO pad (1002) to the second port (1052), and a first-2 pad-port map connection unit (1022) configured to operate when the second map is selected and to connect the first GPIO pad (1001) to the second port (1052) and to connect the second GPIO pad (1002) to the first port (1051).

[0209] The second mapping group (1030) is configured to switch the connection between the GPIO pad and the port according to the Map Select signal (Map Select 2). The second mapping group (1030) includes a second-1 pad-port map connection unit (1031) configured to operate during the first map selection and to connect the first GPIO pad (1001) to the third port (1053) and to connect the third GPIO pad to the fourth port (1054), and a second-2 pad-port map connection unit (1032) configured to operate during the second map selection and to connect the first GPIO pad (1001) to the fourth port (1054) and to connect the third GPIO pad to the third port (1053).

[0210] The third mapping group (1040) is configured to switch the connection between the GPIO pad and the port according to the Map Select signal (Map Select 3). The third mapping group (1040) includes a third-1 pad-port map connection unit (1041) configured to operate during the first map selection and to connect the second GPIO pad (1002) to the fifth port (1055) and the fourth GPIO pad to the sixth port (1056), and a third-2 pad-port map connection unit (1042) configured to operate during the second map selection and to connect the second GPIO pad (1002) to the sixth port (1056) and the fourth GPIO pad to the fifth port (1055).

[0211] FIG. 11 illustrates an exemplary configuration in which two GPIO pads and two ports are connected to each mapping group, but the scope of the present invention is not limited thereto. FIG. 11 illustrates that each mapping group includes two pad-port map connections, but this is not a limitation. In addition, while two test mode types are set, the number of test mode types, the number of mapping groups, the number of GPIO pads and ports connected to each mapping group, and the number of pad-port map connections per mapping group can be varied according to the designer's design and system requirements.

[0212] The test controller (1060) may be a controller based on the IEEE 1687 standard, i.e., IJTAG (Internal Joint Test Action Group). The test controller (1060) enables the output of a test mode signal (TEST MODE) and map select signals (Map Select 1 ~ Map Select 3) by setting the mode & map select register (1061) through the IJTAG interface. The mode & map select register (1061) may be composed of a test data register (TDR) that operates in a shift mode and may internally include logic elements such as flip-flops.

[0213] The operation of the GPIO multiplexer of FIG. 11 will be explained below.

[0214] The GPIO multiplexer dynamically switches the connection status between each GPIO pad, mapping group, and each port according to the test mode signal (TEST MODE) and map selection signals (Map Select 1 ~ Map Select 3) output from the mode & map selection register (1061) of the test controller (1060).

[0215] The test controller (1060) operates according to the IEEE 1687 standard, namely the IJTAG (Internal Joint Test Action Group) method. The test controller (1060) controls the mode & map select register (1061) in a shift manner through the IJTAG interface. The mode & map select register (1061) is configured to output a test mode signal (TEST MODE) and map select signals (Map Select 1 ~ Map Select 3) according to the shift input value. The test mode signal is distributed simultaneously to all pad mode selectors. That is, all pad mode selectors receive a common test mode signal and control all GPIO pads to operate in the same test mode type. Meanwhile, individual map select signals can be output to each mapping group.

[0216] The first pad mode selector (1011) receives a test mode signal and determines whether the first GPIO pad (1001) is connected to either the first mapping group (1020) or the second mapping group (1030). The second pad mode selector (1012) receives a test mode signal and determines whether the second GPIO pad (1002) is connected to either the first mapping group (1020) or the third mapping group (1040). Additionally, the third pad mode selector selectively connects the third GPIO pad to the second mapping group (1030). The fourth pad mode selector selectively connects the fourth GPIO pad to the third mapping group (1040).

[0217] According to the map selection signal (Map Select 1) input from the mode & map selection register (1061), when the first map is selected, the first-1 pad-port map connection part (1021) of the first mapping group (1020) operates to connect the first GPIO pad (1001) to the first port (1051) and the second GPIO pad (1002) to the second port (1052). When the second map is selected, the first-2 pad-port map connection part (1022) operates to connect the first GPIO pad (1001) to the second port (1052) and the second GPIO pad (1002) to the first port (1051).

[0218] Additionally, according to the map selection signal (Map Select 2) input from the mode & map selection register (1061), when the first map is selected, the 2-1 pad-port map connection part (1031) of the second mapping group (1030) operates to connect the first GPIO pad (1001) to the third port (1053) and the third GPIO pad to the fourth port (1054). When the second map is selected, the 2-2 pad-port map connection part (1032) operates to connect the first GPIO pad (1001) to the fourth port (1054) and the third GPIO pad to the third port (1053).

[0219] Additionally, according to the map selection signal (Map Select 3) input from the mode & map selection register (1061), when the first map is selected, the 3-1 pad-port map connection part (1041) of the 3rd mapping group (1040) operates to connect the 2nd GPIO pad (1002) to the 5th port (1055) and the 4th GPIO pad to the 6th port (1056). When the 2nd map is selected, the 3-2 pad-port map connection part (1042) operates to connect the 2nd GPIO pad (1002) to the 6th port (1056) and the 4th GPIO pad to the 5th port (1055).

[0220] Through this operation, the connection relationship between each GPIO pad and port can be switched in real time according to the test mode signal and map selection signal. Since the same port can be selectively connected to one of multiple GPIO pads, it supports various test scenarios and allows test configurations to be easily expanded without design changes, even in complex systems.

[0221] FIG. 12 is an example diagram of the first internal circuit of the first-1 pad-port map connection part of FIG. 11, and FIG. 13 is an example diagram of the first internal circuit of the first-2 pad-port map connection part of FIG. 11.

[0222] The first-1 pad-port map connection (1021) of FIG. 12 includes a first-1 output buffer (1101) connected between the first GPIO pad (1001) and the first port (1051) in the input path (pad test output path) of the first port (1051), a first-1 input buffer (1102) connected between the first GPIO pad (1001) and the first port (1051) in the output path (pad test input path) of the first port (1051), a second-12 output buffer (1103) connected between the second GPIO pad (1002) and the second port (1052) in the input path (pad test output path) of the second port (1052), and a second-12 input buffer (1104) connected between the second GPIO pad (1002) and the second port (1052) in the output path (pad test input path) of the second port (1052).

[0223] The first-second pad-port map connection (1022) of FIG. 13 includes a second-first output buffer (1105) connected between the first GPIO pad (1001) and the second port (1052) in the input path (pad test output path) of the second port (1052), a second-first input buffer (1106) connected between the first GPIO pad (1001) and the second port (1052) in the output path (pad test input path) of the second port (1052), a second-second output buffer (1107) connected between the second GPIO pad (1002) and the first port (1051) in the input path (pad test output path) of the first port (1051), and a second-second input buffer (1108) connected between the second GPIO pad (1002) and the first port (1051) in the output path (pad test input path) of the first port (1051).

[0224] For each port, only one of the input buffer and the output buffer may be activated. Each port may operate as an input port or an output port. When the port operates as an input port, data may be received from the first GPIO pad (1001) or from the second GPIO pad (1002) depending on whether the first pad-port map connection (1021) and the second pad-port map connection (1022) are activated. Additionally, when the port operates as an output port, data may be output to the first GPIO pad (1001) or to the second GPIO pad (1002) depending on whether the first pad-port map connection (1021) and the second pad-port map connection (1022) are activated.

[0225] Specifically, in the first-1 pad-port map connection (1021) of FIG. 12, when the first port (1051) operates as an input port, only the first output buffer (1101) is activated and the first input buffer (1102) is deactivated, so that only a port input path (pad test output path) is formed between the first GPIO pad (1001) and the first port (1051). Conversely, when the first port (1051) operates as an output port, only the first input buffer (1102) is activated and the first output buffer (1101) is deactivated, so that only a port output path (pad test input path) is formed between the first GPIO pad (1001) and the first port (1051). Meanwhile, when the second port (1052) operates as an input port, only the 12th output buffer (1103) is activated and the 12th input buffer (1104) is deactivated, so that only a port input path (pad test output path) is formed between the second GPIO pad (1002) and the second port (1052). Conversely, when the second port (1052) operates as an output port, only the 12th input buffer (1104) is activated and the 12th output buffer (1103) is deactivated, so that only a port output path (pad test input path) is formed between the second GPIO pad (1002) and the second port (1052).

[0226] In the first-second pad-port map connection (1022) of FIG. 13, when the second port (1052) operates as an input port, only the second-first output buffer (1105) is activated and the second-first input buffer (1106) is deactivated, so that only a port input path (pad test output path) is formed between the first GPIO pad (1001) and the second port (1052). Conversely, when the second port (1052) operates as an output port, only the second-first input buffer (1106) is activated and the second-first output buffer (1105) is deactivated, so that only a port output path (pad test input path) is formed between the first GPIO pad (1001) and the second port (1052). Meanwhile, when the first port (1051) operates as an input port, only the second output buffer (1107) is activated and the second input buffer (1108) is deactivated, so that only a port input path (pad test output path) is formed between the second GPIO pad (1002) and the first port (1051). Conversely, when the first port (1051) operates as an output port, only the second input buffer (1108) is activated and the second output buffer (1107) is deactivated, so that only a port output path (pad test input path) is formed between the second GPIO pad (1002) and the first port (1051).

[0227] When the input buffers (1102, 1104, 1106, 1108) are disabled, the input terminals are tied to a 0 level to prevent them from becoming floating, thereby preventing noise or malfunction. When the output buffers (1101, 1103, 1105, 1107) are disabled, the output terminals are opened to a high-impedance (High-Z) state.

[0228] FIGS. 12 and FIGS. 13 illustrate a state in which both the first port (1051) and the second port (1052) operate as input ports. The first-1 pad-port map connection (1021) and the first-2 pad-port map connection (1022) operate mutually exclusively according to a map selection signal, and the unselected pad-port map connection remains in an inactive state.

[0229] When the 1-1 pad-port map connection unit (1021) is operated, the 11th output buffer (1101) and the 12th output buffer (1103) are activated, and in this case, the 1st GPIO pad (1001) and the 1st port (1051), and the 2nd GPIO pad (1002) and the 2nd port (1052) are connected, respectively. When the 1-2 pad-port map connection unit (1022) is operated, the 21st output buffer (1105) and the 22nd output buffer (1107) are activated, and in this case, the 1st GPIO pad (1001) and the 2nd port (1052), and the 2nd GPIO pad (1002) and the 1st port (1051) are connected, respectively. The input terminals of the 11th input buffer (1102), the 12th input buffer (1104), the 21st input buffer (1106), and the 22nd input buffer (1108) are all tied to level 0.

[0230] The first-1 pad-port map connection section (1021) is responsible for the connection between the first GPIO pad (1001) and the first port (1051), and between the second GPIO pad (1002) and the second port (1052). Since the first port (1051) operates as an input port, the first output buffer (1101) is activated, forming a port input path (pad test output path) through which data flows from the first GPIO pad (1001) toward the first port (1051). At this time, the first input buffer (1102) is deactivated, and the input terminal of the first input buffer (1102) is tied to level 0. When the second port (1052) operates as an input port, the second output buffer (1103) is activated, forming a port input path (pad test output path) through which data flows from the second GPIO pad (1002) toward the second port (1052). At this time, the 12th input buffer (1104) is deactivated and the input terminal of the 12th input buffer (1104) is tied to level 0.

[0231] The first-second pad-port map connection (1022) is responsible for cross-connecting between the first GPIO pad (1001) and the second port (1052), and between the second GPIO pad (1002) and the first port (1051). Since the first port (1051) operates as an input port, the second-second output buffer (1107) is activated, forming a port input path (pad test output path) through which data flows from the second GPIO pad (1002) toward the first port (1051). At this time, the second-second input buffer (1108) is deactivated, and the input terminal of the second-second input buffer (1108) is tied to level 0. When the second port (1052) operates as an input port, the second-first output buffer (1105) is activated, forming a port input path (pad test output path) through which data flows from the first GPIO pad (1001) toward the second port (1052). At this time, the 21st input buffer (1106) is deactivated and the input terminal of the 21st input buffer (1106) is tied to level 0.

[0232] FIG. 14 is an example diagram of the second internal circuit of the first-1 pad-port map connection part of FIG. 11, and FIG. 15 is an example diagram of the second internal circuit of the first-2 pad-port map connection part of FIG. 11.

[0233] FIGS. 14 and 15 illustrate a state in which the first port (1051) operates as an input port and the second port (1052) operates as an output port. The first-1 pad-port map connection (1021) and the first-2 pad-port map connection (1022) operate mutually exclusively according to a map selection signal, and the unselected pad-port map connection remains in an inactive state.

[0234] The first-1 pad-port map connection section (1021) is responsible for the connection between the first GPIO pad (1001) and the first port (1051), and between the second GPIO pad (1002) and the second port (1052). When the first port (1051) operates as an input port, the first output buffer (1101) is activated to form a port input path (pad test output path) through which data flows from the first GPIO pad (1001) to the first port (1051). At this time, the first input buffer (1102) is deactivated, and the input terminal of the deactivated first input buffer (1102) is tied to level 0. When the second port (1052) operates as an output port, the second input buffer (1104) is activated to form a port output path (pad test input path) through which data flows from the second port (1052) to the second GPIO pad (1002). At this time, the 12th output buffer (1103) is deactivated, and the output terminal of the deactivated 12th output buffer (1103) is opened to a high impedance state.

[0235] The first-second pad-port map connection (1022) is responsible for cross-connecting between the first GPIO pad (1001) and the second port (1052), and between the second GPIO pad (1002) and the first port (1051). When the first port (1051) operates as an input port, the second-second output buffer (1107) is activated, forming a port input path (pad test output path) through which data flows from the second GPIO pad (1002) toward the first port (1051). At this time, the second-second input buffer (1108) is deactivated, and the input terminal of the deactivated second-second input buffer (1108) is tied to level 0. When the second port operates as an output port, the second-first input buffer (1106) is activated, forming a port output path (pad test input path) through which data flows from the second port (1052) toward the first GPIO pad (1001). At this time, the 21st output buffer (1105) is deactivated, and the output terminal of the deactivated 21st output buffer (1105) is opened to a high impedance state.

[0236] FIG. 16 is an example diagram of the third internal circuit of the first-1 pad-port map connection part of FIG. 11, and FIG. 17 is an example diagram of the third internal circuit of the first-2 pad-port map connection part of FIG. 11.

[0237] FIGS. 16 and 17 are examples of internal state circuits when both the first port (1051) and the second port (1052) operate as output ports. The first-1 pad-port map connection (1021) and the first-2 pad-port map connection (1022) operate mutually exclusively according to a map selection signal, and the unselected pad-port map connection remains in an inactive state.

[0238] The first-1 pad-port map connection (1021) is responsible for connecting to output data from the first port (1051) to the first GPIO pad (1001) and from the second port (1052) to the second GPIO pad (1002). Since the first port (1051) operates as an output port, the first input buffer (1102) is activated, and a port output path (pad test input path) is formed in which data flows from the first port (1051) toward the first GPIO pad (1001). At this time, the first output buffer (1101) is deactivated, and the output terminal of the deactivated first output buffer (1101) becomes a high-impedance state. Since the second port (1052) operates as an output port, the 12th input buffer (1104) is activated, and a port output path (pad test input path) is formed in which data flows from the second port (1052) toward the second GPIO pad (1002). At this time, the 12th output buffer (1103) is deactivated, and the output terminal of the deactivated 12th output buffer (1103) becomes a high impedance state.

[0239] The first-second pad-port map connection (1022) is responsible for cross-connecting to output data from the first port (1051) to the second GPIO pad (1002) and from the second port (1052) to the first GPIO pad (1001). When the first port (1051) operates as an output port, the second-second input buffer (1108) is activated, forming a port output path (pad test input path) through which data flows from the first port (1051) to the second GPIO pad (1002). At this time, the second-second output buffer (1107) is deactivated, and the output terminal of the deactivated second-second output buffer (1107) becomes a high-impedance state. When the second port (1052) operates as an output port, the second input buffer (1106) is activated, and a port output path (pad test input path) is formed in which data flows from the second port (1052) toward the first GPIO pad (1001). At this time, the second output buffer (1105) is deactivated, and the output terminal of the deactivated second output buffer (1105) becomes a high impedance state.

[0240] Hard Macro Interface

[0241] FIG. 18 is a configuration diagram illustrating a hard macro interface according to the present invention.

[0242] The hard macro interface of FIG. 18 may be one of the first hard macro interface (241), the second hard macro interface (242), the fourth hard macro interface (244), and the sixth hard macro interface (246) of FIG. 2. If the IP block is a hard macro block, the hard macro interface may be placed between the GPIO multiplexer and the IP block.

[0243] The hard macro interface provides port I / O to each port of the hard macro block in test mode. The port I / O may include at least one of pad test I / O, function port I / O, and register test data transmitted from the pad group controller. Through these various I / O paths, the hard macro interface enables flexible control and verification of each port of the hard macro block under test mode, and allows for the selective configuration of appropriate signal paths according to various test purposes. Accordingly, logic testing, signal flow verification, and fault diagnosis within the hard macro block can be performed efficiently.

[0244] A port of a hard macro block (1403) is connected to the hard macro interface, and a hard macro function controller (1401) that provides function port input / output to the hard macro port in function mode and test mode, and a GPIO multiplexer (1402) that performs pad test input / output with a GPIO pad in test mode are connected.

[0245] The hard macro interface includes a plurality of hard macro interface units (1410) configured to correspond to one port of the hard macro block and transmitting port input / output to the corresponding hard macro port in test mode, and a test controller (1411) that controls register test data to be output.

[0246] The hard macro interface unit (1410) includes decoding logic (1413) that selects one of register test data, pad test input / output transmitted from the GPIO multiplexer (1402), and function port input / output transmitted from the hard macro function controller (1401), and connects it to a port of the hard macro block (1403). The hard macro interface unit (1410) further includes a first buffer and a second buffer (1414, 1415) inserted into the input path and output path, respectively, between the decoding logic (1413) and the port of the hard macro block (1403).

[0247] Depending on the test mode type, the hard macro port may need to transmit and receive function port I / O identical to that of the function mode. For example, to test the performance of other hard macro blocks or other ports within the same hard macro block, function port I / O identical to that of the function mode may need to be transmitted and received on a specific port. Additionally, depending on the test mode type, pad test I / O transmitted and received from GPIO pads may need to be transmitted and received through the corresponding port. In this case, it is possible to test whether signal transmission and reception between the GPIO pad and the port is performed normally.

[0248] For another test mode type, predetermined register test data may need to be input into a hard macro port. In this case, the register test data is set to a fixed value and provided through the port to configure test scenarios. Conversely, in certain test mode types, the port may not be used for testing.

[0249] The SoC designer can pre-set the type of data to be input / output to the hard macro port according to each test mode type, and the decoding logic (1413) is configured to select at least one of pad test input / output, function port input / output, and register test data for each test mode type based on the SoC designer's settings and connect it to the corresponding port.

[0250] The test controller (1411) may be a controller based on the IEEE 1687 standard (IJTAG: Internal Joint Test Action Group). The test controller (1411) can set the test data setting register (1412) through the IJTAG interface. The register (1412) may each be composed of a test data register (TDR) that operates in a shift manner.

[0251] The test data setting register (1412) may be configured as a flip-flop and provides register test data that is output to a port of a hard macro block according to the test mode type. This register test data may be a single-bit or multi-bit signal, and to support multi-bit data, the test data setting register (1412) may include a plurality of flip-flops.

[0252] Many variations and modifications may be made to the embodiments described above, and such elements should be understood as being one of other acceptable examples. All such modifications and variations are intended to be included within the scope of this disclosure and protected by the following claims.

[0253] Although the present invention has been described above with specific details such as specific components, limited embodiments, and drawings, this is provided only to aid in a more comprehensive understanding of the invention, and the invention is not limited to the above embodiments, and a person skilled in the art to which the invention belongs can make various modifications and variations from this description.

[0254] Accordingly, the scope of the present invention is not limited to the embodiments described above, and all modifications equivalent to or equivalent to the claims set forth below, as well as the claims set forth below, shall be considered to fall within the scope of the scope of the present invention.

Claims

1. A first pad group controller that, for each of a plurality of first GPIO pads constituting a first pad group, performs pad function input / output and pad function operation control in function mode and performs first pad test input / output and pad test operation control in test mode, and A first hard macro interface comprising a first hard macro interface that transmits and receives port input / output in test mode for each of a plurality of ports constituting a first IP block, General-purpose I / O test system.

2. In Paragraph 1, A second pad group controller that, for each of a plurality of second GPIO pads constituting a second pad group, performs pad function input / output and pad function operation control in function mode and performs second pad test input / output and pad test operation control in test mode, and A first GPIO multiplexer further comprising the first pad test input / output and the second pad test input / output to be transmitted to the first hard macro interface, General-purpose I / O test system.

3. In Paragraph 2, The above port input / output includes at least one of the above function port input / output, the above first pad test input / output, or the above second pad test input / output. General-purpose I / O test system.

4. In Paragraph 2, A second GPIO multiplexer further comprising the first pad test input / output being transmitted to a second IP block, General-purpose I / O test system.

5. In Paragraph 4, A first GPIO router further comprising the first pad test input / output being distributed to the first GPIO multiplexer and the second GPIO multiplexer, General-purpose I / O test system.

6. In Paragraph 5, A second GPIO router further comprising: outputting first pad test outputs transmitted from the first GPIO router to a second GPIO multiplexer and transmitting first pad test inputs transmitted from the second GPIO multiplexer to the first GPIO router. General-purpose I / O test system.

7. In Paragraph 4, The first IP block is a hard macro block, and the second IP block is a non-hard macro block, General-purpose I / O test system.

8. In Paragraph 4, A second hard macro interface further comprising a plurality of ports constituting the second IP block, for transmitting and receiving port input / output in test mode for each of the plurality of ports. General-purpose I / O test system.

9. In Paragraph 8, The above second IP block is a hard macro block, General-purpose I / O test system.

10. A first pad group controller that, for each of a plurality of first GPIO pads constituting the first pad group, performs pad function input / output and pad function operation control in function mode and performs first pad test input / output and pad test operation control in test mode, and A second pad group controller that, for each of a plurality of second GPIO pads constituting a second pad group, performs pad function input / output and pad function operation control in function mode and performs second pad test input / output and pad test operation control in test mode, and A first GPIO multiplexer comprising the first pad test input / output and the second pad test input / output to be transmitted to the port of the first IP block, General-purpose I / O test system.

11. In Paragraph 10, A second GPIO multiplexer further comprising the first pad test input / output being transmitted to a second IP block, General-purpose I / O test system.

12. In Paragraph 11, A first GPIO router further comprising the first pad test input / output being distributed to the first GPIO multiplexer and the second multiplexer, General-purpose I / O test system.

13. In Paragraph 12, A second GPIO router further comprising: outputting first pad test outputs transmitted from the first GPIO router to a second GPIO multiplexer and transmitting first pad test inputs transmitted from the second GPIO multiplexer to the first GPIO router. General-purpose I / O test system.

14. In Paragraph 11, The above first IP block and the above second IP block are non-hard macro blocks, General-purpose I / O test system.

15. A first pad group controller that, for each of a plurality of first GPIO pads constituting the first pad group, performs pad function input / output and pad function operation control in function mode and performs first pad test input / output and pad test operation control in test mode, and A first GPIO multiplexer that transmits the first pad test input / output to a port of the first IP block, and A second GPIO multiplexer comprising the first pad test input / output being transmitted to a port of a second IP block, General-purpose I / O test system.

16. In Paragraph 15, A first GPIO router further comprising the first pad test input / output being distributed to the first GPIO multiplexer and the second GPIO multiplexer, General-purpose I / O test system.

17. In Paragraph 16, A second GPIO router further comprising: outputting first pad test outputs transmitted from the first GPIO router to a second GPIO multiplexer and transmitting first pad test inputs transmitted from the second GPIO multiplexer to the first GPIO router. General-purpose I / O test system.

18. In Paragraph 15, A first hard macro interface further comprising a first hard macro interface that transmits and receives port input / output in test mode for each of the plurality of ports constituting the first IP block. General-purpose I / O test system.

19. In Paragraph 18, A second hard macro interface further comprising a plurality of ports constituting the second IP block, for transmitting and receiving port input / output in test mode for each of the plurality of ports. General-purpose I / O test system.

20. A system-on-chip comprising a general-purpose input / output test system according to any one of claims 1 through 19.

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