Integrated circuit having microvault memories

Abstract

An integrated circuit comprising multiple microvaults arranged adjacent to a first surface, each with a read periphery and a write periphery. The circuit includes bonding areas on the first surface. Microvaults feature programmable read and write clock cycle lengths, potentially based on different clocks. An interlock can be used to prevent simultaneous read and write operations. Read and write operations may use programmable voltages. The read / write periphery may be integrated, including address decoders and sense amplifiers. Microvaults can be arranged in chiplets with face-to-face bonding and through-silicon vias.

Description

Attorney Docket: P25-061-SEC-W001INTEGRATED CIRCUIT HAVING MICRO VAULT MEMORIESCROSS-REFERNCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Application No.63 / 760,258, filed February 19, 2025, the entire disclosure of which is hereby incorporated in its entirety.BACKGROUNDRelevant Field

[0002] The present disclosure relates to integrated circuits. More particularly, the present disclosure relates to integrated circuits having multiple modules including a microvault memory.Description of Related Art

[0003] Chiplets refer to miniature chips that are designed to work as a single entity while using advanced packaging technology. These miniaturized chips are created by dividing the larger chip into several smaller chips, each with its own function or capability. The concept originated from the semiconductor industry's need to overcome the physical restrictions of traditional monolithic chip designs and achieve higher levels of integration. The idea behind chiplets is to create a modular system of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality.

[0004] Chiplets can be based on different architectures, such as CPU, GPU, memory, or IO, and can be assembled and stacked in a variety of ways, depending on the specific application requirements. One of the advantages of the chiplet approach is the ability to mix and match different chiplets from different manufacturers to create custom solutions that meet specific computing needs. This approach also allows for faster time to market, reduced development costs, and increased flexibility, as chiplets can be upgraded or replaced without the need for a complete system redesign.

[0005] The use of chiplets may be used in various industries, including consumer electronics, cloud computing, and data centers, where the demand for high-performance computing and energy efficiency is high. Chiplets are expected to play a significant role in the future of computing and are likely to unlock new possibilities for creating more powerful and / or sophisticated electronic devices.Attorney Docket: P25-061-SEC-W001SUMMARY

[0006] In some embodiments, an integrated circuit may comprise a plurality of microvaults. These microvaults can be disposed in spaced relation relative to each other and adjacent to a first surface. Each microvault may have a respective read periphery and a respective write periphery. The integrated circuit may also include a plurality of bonding areas, including a first bonding area, which can be disposed on the first surface.In certain embodiments, the read periphery of each microvault may have a programmable read-clock cycle length, while the write periphery may have a programmable write-clock cycle length. These clock cycle lengths can be based off of a first clock, or in some cases, the write-clock cycle length may be based off of a second clock that is different from the first clock.

[0007] The integrated circuit may include an interlock that can be configured to prevent simultaneous read and write operations of the respective microvault. In some embodiments, the write periphery may write to the respective microvault using a first voltage, while the read periphery may read the respective microvault using a second voltage. Both the first and second voltages may be programmable in certain implementations.

[0008] In some embodiments, the respective read periphery and the respective write periphery may be integrated together to form an integrated read / write periphery.This integrated read / write periphery can include a read / write address decoder, which may be configured to decode both read and write addresses. The read / write periphery may also include a sense amplifier in certain implementations.

[0009] The read / write periphery may be disposed adjacent to the respective microvault at a side opposite to the first surface, or it may be disposed in a front-end-of-the-line layer of the integrated circuit. In some embodiments, the respective microvault may be disposed on a back-end-of-the-line layer of the integrated circuit.

[0010] The integrated circuit may further comprise an address port that can be configured to decode either a read address or a write address. In some implementations, the read periphery may be disposed adjacent to the write periphery, with the read periphery including a read address decoder and the write periphery including a write address decoder.In certain embodiments, the integrated circuit may include an application programming interface. The plurality of microvaults may include a first microvault and a second microvault, and the integrated circuit may further comprise a multiplexer configured toAttorney Docket: P25-061-SEC-W001address these microvaults. This multiplexer can be a read multiplexer, a write multiplexer, or a read / write multiplexer.

[0011] The first bonding area may be operatively coupled to the first and second microvaults and can include various ports such as a read / write port, a read / write data port, a read / write address port, separate read and write address ports, or separate read and write data ports.

[0012] In some embodiments, the first and second microvaults may be disposed in a first chiplet. The integrated circuit may further comprise a second chiplet disposed on the first chiplet, which may contain additional microvaults. These chiplets can be coupled together via complementary bonding areas, allowing for communication between microvaults in different chiplets.

[0013] The integrated circuit may also include a face-to-face bonded chiplet, where at least one of the plurality of microvaults can be implemented as a 3D memory module within this chiplet. This face-to-face bonded chiplet may be connected to the first surface via the first bonding area, which can include bump-less bonds.

[0014] In certain embodiments, the integrated circuit may comprise a plurality of registers configured to facilitate data transfer between the plurality of microvaults and the first bonding area. Some implementations may include at least two microvaults disposed adjacent to each other, with a counter circuit configured to control access to these microvaults in a multi-cycled pipelined configuration.

[0015] The integrated circuit may include microvaults arranged in at least two chiplets, connected by a through-si licon via (TSV). Phase counters associated with different chiplets can be used to coordinate multi-cycled pipelined access to the microvaults.In some embodiments, an application System-on-Chip (SoC) may be disposed adjacent to the first surface, configured to interface with the plurality of microvaults via bumpless bonds. The integrated circuit may also include a SRAM vault disposed adjacent to the first microvault, which can be in operative communication with the first bonding area or a second bonding area.The integrated circuit may further comprise address registers and data registers operatively coupled to the first bonding area. These registers can be configured to hold and communicate addresses and data to the microvaults, respectively.

[0016] In certain implementations, a microvault may comprise at least one column of 3D-NORs or 3D-NANDs formed from a plurality of transistors. TheseAttorney Docket: P25-061-SEC-W001transistors can be configured with various connections to read / write enable lines, bit lines, and select lines, allowing for different memory architectures within the microvaults.BRIEF DESCRIPTION OF THE DRAWINGS

[0017] These and other aspects will become more apparent from the following detailed description of the various embodiments of the present disclosure with reference to the drawings wherein:

[0018] Fig. 1 is a block diagram of an integrated circuit that may be part of a semiconductor device such as a chiplet in accordance with an embodiment of the present disclosure;

[0019] Fig. 2 shows a perspective view of an assembly having the integrated circuit of Fig. 1 implemented on a semiconductor device that is electrically connected to another device to form the assembly in accordance with an embodiment of the present disclosure;

[0020] Fig. 3 shows a block diagram illustrating the memory address space of the integrated circuit of Fig. 1 in accordance with an embodiment of the present disclosure;

[0021] Fig. 4 shows a block diagram illustrating the memory address space with the signal interfaces of the integrated circuit of Fig. 1 in accordance with an embodiment of the present disclosure;

[0022] Fig. 5 shows an illustration of an integrated circuit that may be part of a semiconductor device such as a chiplet in accordance with an embodiment of the present disclosure;

[0023] Fig. 6 shows a perspective of an assembly having the integrated circuit of Fig. 1 implemented on a semiconductor device that is electrically connected to a system-on-a-chip in accordance with an embodiment of the present disclosure;

[0024] Fig. 7 shows a perspective view of an assembly having a semiconductor device with an array of processing elements and a second semiconductor device having an array of microvaults;

[0025] Fig. 8 shows an assembly of a semiconductor devices including several memory types in accordance with an embodiment of the present disclosure;

[0026] Fig. 9 shows an assembly of semiconductor devices including a semiconductor device with a system-on-chip and another semiconductor withAttorney Docket: P25-061-SEC-W001microvaults disposed on top in accordance with an embodiment of the present disclosure;

[0027] Fig. 10 shows a semiconductor assembly incorporating a daisy-chained configuration of microvaults operatively connected to a multiplexer and managed by a counter for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure.

[0028] Fig. 11 shows a semiconductor assembly incorporating a daisy-chained configuration of microvaults in multiple semiconductor devices that are operatively connected to multiplexers and managed by counters for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure;

[0029] Fig. 12 illustrates a three-dimensional (3D) memory column configured as a 3D-NOR or 3D-AND structure, featuring a series of ferroelectric field-effect transistors (FeFETs) with interconnected drain terminals linked to a common select line and individual gate terminals connected to respective read / write enable lines, all coupled to a common bit line, in accordance with an embodiment of the present disclosure;

[0030] Fig. 13 depicts a three-dimensional (3D) memory column configured as a 3D-NAND structure, consisting of a vertical stack of ferroelectric field-effect transistors (FeFETs), in accordance with an embodiment of the present disclosure;

[0031] Fig. 14 depicts a three-dimensional (3D) memory column configured as a 3D-NAND with an integrated pass gate, in accordance with an embodiment of the present disclosure;

[0032] Fig. 15 illustrates a three-dimensional (3D) memory column 1500, which may be configured as either a 3D-NOR or a 3D- AND structure with independent Read / Write enable capabilities, in accordance with an embodiment of the present disclosure;

[0033] Fig. 16 shows a cross-sectional view of a 3D memory structure configured as a single -port 3D NAND, in accordance with an embodiment of the present disclosure;

[0034] Fig. 17 shows a cross-sectional view of a 3D memory structure that is a dual-port 3D NAND arrangement, in accordance with an embodiment of the present disclosure;Attorney Docket: P25-061-SEC-W001

[0035] Fig. 18 illustrates a 3D memory structure that can be configured as a 3D NOR Vertical Transistor memory array, in accordance with an embodiment of the present disclosure;

[0036] Fig. 19 shows a planar FeFET in accordance with an embodiment of the present disclosure;

[0037] Fig. 20 shows electrical characteristics of an embodiment of a FeFET in accordance with an embodiment of the present disclosure;

[0038] Fig. 21 shows an illustration of an integrated circuit that may be part of a semiconductor device such as a chiplet in accordance with an embodiment of the present disclosure;

[0039] Fig. 22 shows an assembly of semiconductor devices including a semiconductor device with a system-on-chip and another semiconductor with microvaults disposed on top in accordance with an embodiment of the present disclosure;

[0040] Fig. 23 shows a semiconductor assembly incorporating a daisy-chained configuration of microvaults operatively connected to a multiplexer and managed by a counter for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure; and

[0041] Fig. 24 shows a semiconductor assembly incorporating a daisy-chained configuration of microvaults in multiple semiconductor devices that are operatively connected to multiplexers and managed by counters for coordinated data selection, retrieval and writing, in accordance with an embodiment of the present disclosure.DETAILED DESCRIPTION

[0042] Fig. 1 illustrates a block diagram of an integrated circuit (IC) 100, which can be packaged as a bondable chiplet (e.g., face-to-face chiplet bondable) in accordance with an embodiment of the present disclosure. The integrated circuit 100 includes a modules group 106 composed of a plurality of microvaults, specifically modules 108, 110, 112, and 114. Each microvault is disposed in spaced relation to one another and adjacent to a first surface of the chiplet, with each microvault having its own dedicated read periphery and write periphery. This configuration allows for independent read and write operations, enhancing the overall efficiency of the integrated circuit.

[0043] In this configuration, each module is equipped with a dedicated write port (104, 105, 123, 124) and a corresponding write periphery (99, 101, 102, 103). TheAttorney Docket: P25-061-SEC-W001write peripheries are designed to write to their respective microvaults using a specific voltage, which can be programmable to accommodate various operational requirements. Additionally, the IC 100 features dedicated read peripherals (116, 118, 120, 122) and read ports (124, 126, 128, 130) for reading from the modules 108, 110, 112, and 114. The read peripheries are also capable of reading from their respective microvaults using a different programmable voltage, ensuring flexibility in data handling. In some specific embodiments, read / write buses (wires) may be shared where it is configured such that only one of the read / write operations may be performed at any given moment.

[0044] Each module within the modules group 106 has its own dedicated write port and write periphery, ensuring that data can be written independently to each microvault. The integrated circuit 100 is designed to be packaged as part of a chip let, which can be electrically connected to another integrated circuit device (e.g., another chiplet or IC package) using methods such as bonding, soldering, wafer-to-wafer bonding, face-to-face chiplet bonding, chiplet-to-wafer bonding, or chiplet-to-interposer bonding. This connectivity may include interposers or other interfacing technologies common to heterogeneous 3D system-in-package solutions.

[0045] Each read port (124, 126, 128, 130) in the chiplet may feature electrical contacts on one or multiple sides of the chiplet. These read ports utilize multi-cycle pipelined circuitry, allowing for efficient data transfer. Upon bonding to another device (e.g., wafer, chiplet, chip, SOC, package, FPGA), the electrical contacts align to provide dedicated access to specific microvaults of the modules 108, 110, 112, and 114. This arrangement can facilitate that each processing / computing element has exclusive access to its respective microvault, enhancing efficiency and scalability by preventing resource contention.

[0046] The write peripheries (99, 101, 102, 103) are responsible for processing and writing data into the memory cells within the microvaults. Each write periphery may include or be connected to dedicated contacts for electrical connection, allowing individual access to each microvault's write logic system. This configuration may support independent write operations, enhancing data throughput and reliability by eliminating or reducing the need for a shared write address space. The write periphery can also be integrated with the read periphery to form a combined read / write periphery, which may include a read / write address decoder capable of decoding both read and write addresses.Attorney Docket: P25-061-SEC-W001

[0047] An interlock mechanism may be employed to prevent simultaneous read and write operations on the respective microvaults. This interlock ensures that while data is being written to a microvault, the read operations are disabled, and vice versa, maintaining data integrity and preventing conflicts. Each of the modules 108, 110, 112, 114 may include a respective interlock 119, 120, 121, 122.

[0048] Each write periphery circuit may include a write driver that converts incoming data into suitable signals to change the state of the memory cells. These signals may involve voltage levels, current pulses, or other forms of energy, depending on the memory technology used. The write driver can provide sufficient power to alter the memory cells' state without causing damage. The write periphery may also feature a programmable write-clock cycle length, which can be based on a specific clock signal, allowing for flexibility in timing.

[0049] A data buffer within each write periphery 99, 101, 102, 103 temporarily stores data to be written, optimizing the pace of write operations. This buffer can balance the speed of incoming data with the memory cells' write speed, preventing data loss and enhancing system performance. The read periphery 116, 118, 120, 122 may also have a programmable read-clock cycle length, which can be based on the same clock or a different clock, providing additional flexibility in operation.

[0050] Each write periphery 99, 101, 102, 103 may also feature a write control unit that orchestrates the sequence of write operations. This unit generates control signals to activate the write driver, controls data flow from the buffer, and coordinates the timing of write processes to ensure efficient and reliable operations. The read periphery 116, 118, 120, 122 may include a read address decoder configured to decode read addresses, while the write periphery includes a write address decoder for decoding write addresses.

[0051] Data encoding mechanisms within the write peripheries may improve reliability and data integrity by encoding data before writing it to memory cells of the modules 108, 110, 112, 114. This allows for error detection and correction during subsequent data reads, which is a configuration in some systems that prioritize data integrity, such as servers or research devices. The timing unit within each write periphery 99, 101, 102, 103 can provide clock signals to synchronize system operations, ensuring that all operations occur in a timely manner relative to each other.

[0052] The IC 100 may be implemented as a face-to-face bonded chiplet, with modules 108, 110, 112, and 114 formed from non-volatile memory. In someAttorney Docket: P25-061-SEC-W001embodiments, the IC 100 may include dynamic allocation circuitry for memory blocks based on module usage 108, 110, 112, 114, allowing for flexible memory management.The plurality of modules 108, 110, 112, 114 (e.g., microvaults) may be arranged in at least two chiplets, with through-silicon vias (TSVs) connecting the chiplets, facilitating communication and data transfer between them.

[0053] The IC 100 can feature multiple clocks, each feeding a respective module 108, 110, 112, 114, providing decoupled timing for each module 108, 110, 112, 114. The modules group 106 can be arranged in various topologies, with bit-cell density potentially exceeding that of embedded SRAM cells by up to tenfold, in some specific embodiments. The first bonding area on the first surface of the chiplet may be operatively coupled to the microvaults.

[0054] The silicon substrate can serve as the foundation for IC fabrication, focusing on creating active components like transistors through processes such as diffusion, ion implantation, and material deposition. This layer, known as Front-End-Of-The-Line (FEOL), is may be used for signal processing and control. A second layer that traditionally handles interconnect fabrication, can be used to establish electrical connections between IC components. This Back-End-Of-The-Line (BEOL) phase involves forming interconnects and insulating layers to enable signal routing throughout the IC.

[0055] Various embodiments of the IC 100 may include stacked die, monolithic designs, TSVs, or silicon through vias. Stacked die designs involve multiple dies with different functions, while monolithic designs integrate all functions onto a single die for compactness and efficiency. The IC 100 may also include a SRAM vault disposed adjacent to the first microvault, with the first bonding area in operative communication with the SRAM vault.

[0056] The IC 100 may feature interlocks to prevent data read-write conflicts, for example when the modules group 106 is ganged. The modules group 106 can be formed from various non-volatile or semi-volatile memory technologies, providing flexibility in memory type selection. The plurality of micro vaults may include a first microvault and a second microvault, with a multiplexer configured to address both microvaults, allowing for efficient data management.

[0057] The integrated circuit may also include an application programming interface (API) to facilitate communication between the microvaults and external devices. The first bonding area may include read / write ports, read / write data ports, andAttorney Docket: P25-061-SEC-W001read / write address ports, ensuring comprehensive access to the microvaults. The bonding areas may utilize bump-less bonds for enhanced connectivity.

[0058] The IC 100 may include a counter circuit configured to control access to at least two microvaults in a multi -cycled pipelined configuration, ensuring efficient data processing. Additionally, the integrated circuit may feature a plurality of registers configured to facilitate data transfer between the microvaults and the bonding area, enhancing the overall data handling capabilities.

[0059] The integrated circuit 100 (or an attached chiplet) may also include an address register operatively coupled to the first bonding area, configured to hold and communicate addresses to the microvaults. This address register may be a read address register, a write address register, or a read / write address register, depending on the operational requirements. Similarly, a data register may be included, configured to hold and communicate data to the microvaults, with options for read, write, or read / write configurations.

[0060] The first microvault may comprise at least one column of 3D-NORs or 3D-NANDs formed from a plurality of transistors (such as a Ferroelectric Field-Effect Transistor), with each transistor including a gate coupled to a read / write enable line, a source coupled to a bit line, and a drain coupled to a select line. Also, as previously mentioned, the IC 100 may also include a face-to-face bonded chiplet, wherein at least one of the plurality of microvaults is implemented as a 3D memory module within the chiplet.

[0061] Fig. 2 shows a perspective view of an assembly 200 of the integrated circuit 212 implemented on a chiplet 230 that is bonded to a second device 226 in accordance with an embodiment of the present disclosure. The integrated circuit 212 represents the circuitry within the chiplet 230. The second device 226 may be a chiplet, semiconductor wafer, semiconductor package, encased circuitry, etc. For example, the second device 226 may be an Al accelerator, allowing each processing unit to have read / write access to one module (or a predetermined set) of the modules group 236. In another embodiment, the second device 226 may function as a network controller, utilizing an offload circuit to read data from each of the modules to process incoming and outgoing packets. The assembly 200 includes a modules group 236 comprising a plurality of modules, including a first module 232 and a second module 234. Although several modules are depicted, only modules 232 and 234 are labeled for clarity. The integrated circuit 212 further comprises dedicated peripherals for each module,Attorney Docket: P25-061-SEC-W001including peripherals 202a and 202b for modules 232 and 234, respectively. These peripherals 202a, 202b may include integrated read / write peripherals or separate read and write peripherals (e.g., different write / read circuitry sections within or on the peripherals 202a, 202b.

[0062] Each module's dedicated peripheral interfaces with the respective port, allowing the second device 226 to write and / or read data to any module within the modules group 236. The port may be a read / write port or may include two separate read and write ports. The second device 226 may utilize an address and data bus with a clock and an enable signal to perform read / write operations. Other methods of writing and reading data may also be employed, such as serial connections, parallel connections, various buses, or ports, including DDR (Double Data Rate) Interface, SRAM (Static Random-Access Memory) Interface, NAND Flash Memory Interface, NOR Flash Memory Interface, HBM (High Bandwidth Memory) Interface, GDDR (Graphics Double Data Rate) Interface, NVMe (Non-Volatile Memory Express) Interface, SPI, I2C, etc. Each module has a port with an address 218 (to send an address to a module) and data 220 (which is the read or write data from or to the module).

[0063] The modules group 236 is formed on a chiplet 230 that has two sides, including a surface 228 that can be bonded to and complement a second device 226.The chiplet 230 may be created by forming circuitry on a silicon substrate 204 and then adding a second layer 206. In other embodiments, these layers may be reversed, and additional layers may be added or removed. The address 218 and data 220 can be utilized for reading or writing from or to the respective modules.

[0064] The second device 226 may use an address and data bus with a clock and an enable signal to read or write data from the modules. As previously mentioned, other methods of reading or writing data may also be considered, such as serial connections, parallel connections, various buses, or ports, including DDR, SRAM, NAND Flash, NOR Flash, HBM, GDDR, NVMe, SPI, I2C, etc.

[0065] All read ports may be configured to be inactive when a write operation is applied to the respective write peripheral and vice versa. The read ports may also be configured to process reads concurrently with each other. Each dedicated write peripheral may be configured to write to an address space, where the write peripheral for the first module 232 writes via a first portion of the address space, and the write peripheral for the second module 234 writes via a second portion of the address space.Attorney Docket: P25-061-SEC-W001Each module of the plurality of modules 236 may include an independent read port for concurrent reading via its respective read port.

[0066] Each read port for a respective module may include contacts for circuitry found within the second device 226 to interface via metallic contacts. Thus, there may be metallic contacts on the top layer 208 that are configured to interface with metallic contacts on the surface 228 of the chiplet 230, allowing for a read space that is coextensive with the read space of a module in the modules group 236. The read spaces and / or the write spaces of the modules group 236 may all be coextensive with each other.

[0067] In one embodiment, the peripheral for the first module 232 may be implemented on a silicon substrate 204 (sometimes referred to as the Front-end-of-the-line). The second layer 206 (sometimes called the Back-end-of-the-line) may be built next in the manufacturing process on top of the silicon substrate 204 (and any circuitry) and may contain the respective memory bit cells. In an alternative embodiment, the peripheral for the first module 232 is implemented in the second layer 206 and is disposed between the modules group 236 and the surface 228 of the chiplet 230.

[0068] The modules group 236 may be configured to process write commands only during reset. The write commands may be “slow write” commands, meaning the modules group 236 may have very low write speeds relative to their read speeds. The write logic may be frozen (or disabled) when the modules group 236 are used for reading data. In some specific embodiments, the integrated circuit 212 provides functionality to allocate memory blocks to the modules group 236 based on their usage.In other embodiments, the memory addresses are fixed along with the allocation.

[0069] The architecture of the write peripherals 202 may include various components, such as write drivers, address decoders, sense amplifiers, data input latches, and data buses, among others. Write drivers or write buffers may be responsible for transferring data onto the memory cells, enhancing the input signal to achieve a level appropriate for the memory cell. Address decoders interpret the memory address fed as input for writing data. By activating the specific row and column of the memory array linked to that address, they select the target memory cell. Sense amplifiers identify and boost the signal from the memory cells during reading operations and participate in refreshing the memory cell post data write. The write operation is initiated by a write enable signal, which propels the write drivers and decoders into the writing process.Data input latches serve as temporary storage units, retaining the data set to be writtenAttorney Docket: P25-061-SEC-W001into memory until the write operation is executed. A data bus facilitates the movement of data from the data input latches to the memory cells.

[0070] A write operation to the modules group may be performed through a priority arbitration circuit that facilitates access to the modules in a predetermined order. Each dedicated write peripheral may be configured to write to a virtual address space that is mapped onto a physical memory space. The integrated circuit 212 may include high voltage write logic used within the write peripherals, and the second semiconductor device 226 may comprise a plurality of processing elements, with each processing element including a respective interface to communicate with its corresponding module in the modules group 236. Furthermore, the chiplet 230 may include an interface to the dedicated write peripherals on the second side to interface with a complementary interface on the second semiconductor device 226.

[0071] The integrated circuit 212 may also include power gating circuitry that selectively powers down a module of the modules 236 when not in use. Additionally, the integrated circuit 212 may have dedicated write peripherals connected to dedicated I / O pads to enable data transfer external to the package of the integrated circuit.

[0072] The integrated circuit 212 may utilize multiple modules from the modules group 236 grouped together. These modules may be synchronized with one another in specific embodiments. In some cases, all the modules are synchronized, while in other instances, only specific modules are synchronized. For instance, the circuit on the second device 226 may need to synchronize with a specific module when reading data from one of the modules in the modules group 236.

[0073] To synchronize the modules, the integrated circuit 212 may use various timing technologies. In some cases, a plurality of clocks may feed each respective module of the modules group 236, allowing each module to have decoupled timing relative to the other modules in the group. This decoupling ensures that any delay in one module will not affect the functioning of other modules. It is worth noting that the clocks used may or may not need to be synchronized. In some cases, a common clock can be used to synchronize the modules. In yet other embodiments, the clock signal or signals may be provided by the second device 226.

[0074] In alternative embodiments, other synchronization techniques can be used, such as phase comparison of the clock signals or a phase-locked loop (PLL) synchronization method. Another embodiment for synchronizing the modules in the IC could use delay-locked loop (DLL) synchronization. In this method, a delay element isAttorney Docket: P25-061-SEC-W001added to the clock signal path, and the output is compared to the input clock signal. The feedback loop adjusts the delay element until the output of the DLL matches the input, resulting in synchronization of the clock signals.

[0075] In another embodiment, the integrated circuit 212 could use a combination of different synchronization techniques to achieve synchronization between the modules. For example, some modules may use PLL synchronization while others use clock delay lines or DLL synchronization, depending on their specific requirements. Additionally, the integrated circuit 212 can also employ redundant synchronization techniques to ensure reliability and redundancy in case one method fails. For example, the integrated circuit 212 could use both PLL synchronization and DLL synchronization simultaneously, so that if one method fails, the other can still maintain synchronization. The integrated circuit 212 may or may not have the read and / or write peripherals integrated with it and each module in the modules group 236 may have an integrated circuit 212, in some specific embodiments.

[0076] Fig. 3 shows a block diagram 300 illustrating the memory address space of the integrated circuit of Fig. 1 in accordance with an embodiment of the present disclosure. The memory address space includes a write address space 316 and read data address spaces 310, 312, 314.

[0077] The write address space 316 consists of various units where data, e.g., weights, and / or instructions can be stored. These units are referred to as memory addresses. The module group 302 includes multiple memory modules 304, 306, 308.The write address space 316 may be distributed among the memory modules 304, 306, 308 such that the write address space 316 spans from 0 to N*M-1. As shown in Fig. 3, the modules group 302 has N memory modules 304, 306, 308, where N is a positive integer, and each module has a memory size of M. The total number of unique write memory addresses in the write address space will be N*M, which can be referenced by an integer from 0 to N*M-1. In other embodiments, the write address space 316 may be unique to each module and may be coextensive to the

[0078] Starting at 0, memory addresses of the write address space 316 are ordered sequentially up to N*M-1. In other words, the first address is 0 and the final address is N*M-1, encompassing a total of N*M addresses. This ordering can be linear (each address increases by one) or some other specified pattern depending.

[0079] The write memory addressing can be implemented in a variety of ways based on the system architecture. One method used in a specific embodiment is to useAttorney Docket: P25-061-SEC-W001the base and limit registers. The base register holds the smallest legal physical write memory address, and the limit register specifies the size of the range. Therefore, to generate a logical address, you would add the base to the relative address. In other embodiments, a memory addressing scheme may be used where the base used is set to be 0. Yet additional write addressing techniques will be appreciated by one or ordinary skill in the relevant art.

[0080] For any device that writes to the modules group 302, each memory module can possess a unique set of write memory addresses such all memory addresses within the modules group 302 is unique with respect to writing data, e.g., the first module starting at 0 and the last one ending at N*M-1. This allocation, in some embodiments, may be dependent on the memory management system of the device writing data to the modules 304, 306, 308, which could range from simple fixed partitioning schemes to more complex dynamic partitioning models. In other embodiments, a dedicate write peripheral and dedicated write address space may be used, such as when the write address space and the read address space of a particular module may be coextensive.

[0081] In another example, a straightforward linear model where each module (304, 306, or 308) has an equal size of M addresses, the first module 304 would possess write addresses 0 to M-l, the second module would have write addresses M to 2M-1, the third module would have write addresses 2M to 3*M-1, and so forth. The Nth module 308, therefore, would possess write addresses from (N-1)*M to N*M-1.

[0082] It is contemplated that one of ordinary skill in the relevant art may use other implementations of write memory addresses from 0 to N*M-1 that depends on various factors such as the hardware architecture, operating system, memory management schemes, and the nature of the programs being run on the system, etc.

[0083] The modules group 302 can have different read data address spaces 310, 312, 314. These read address spaces 310, 312, 314 may have overlapping addresses spaces, may have contiguous address spaces, or may have coextensive address spaces.The read address spaces 310, 312, 314 may be independent relative to each other. The system 300 may include three independent read address spaces, labeled as read address spaces 310, 312, and 314. Each of these read address spaces may be distinct from the others, meaning that reads can be performed in each space without affecting the others.

[0084] The read address spaces 310, 312, 314 may be defined as contiguous blocks of memory addresses, each with its own starting address and ending address. InAttorney Docket: P25-061-SEC-W001modules group 302, each read address space 310, 312, 314 may have a range of addresses that corresponds to values from 0 to M-l, where M is a maximum value determined by the size of the modules 304, 306, 308 being used.

[0085] In one embodiment, allowing one processing unit to interface with each read address space 310, 312, 314, the concurrent reads may be implemented as described herein. The independence of the read address spaces 310, 312, 314 ensures that each processing unit can access its desired data without causing any interference or conflict with other processing units.

[0086] Fig. 4 shows a block diagram illustrating the memory address space with the signal interfaces of the integrated circuit of Fig. 1 in accordance with an embodiment of the present disclosure. The signals used in Fig. 4 may be used with any embodiment described herein. However, one of ordinary skill in the relevant art will appreciate that different signaling schemes may be used.

[0087] The modules group 402 includes modules 404, 406, 408 that may share a common write peripheral 410. However, in other embodiments each and every module has its own write peripheral 410. The write peripheral 411 includes a write address bus that includes the address of the data being written, a write data bus that includes the data, a write clock cause the writes to occur (e.g., either on a leading or trailing edge of the clock signal, etc.). The writes only occur if the write enable signal indicates a write should occur. Any logic may be used, e.g., high voltage may correspond to 1 and a low voltage may correspond to 0, or vice versa. In some embodiments, the write peripheral 411 may be on the chiplet 230 and in other embodiments, the write peripheral 411 is on the second device 226.

[0088] The modules group 402 has modules 404, 406, 408 where each has a respective read peripheral 410, 412, 414. Each of the read peripheral 410, 412, 414 has a read address bus to send an address for reading, a read data bus to receive the data, a read clock which is the clock used to control the timing of the output of the digital data, and an output enable that is a precondition to outputting data. Any logic may be used, e.g., high voltage may correspond to 1 and a low voltage may correspond to 0, or vice versa. In yet additional embodiments, multi -bit or analog data storage may be used. In some embodiments, one or more of the read peripherals 410, 412, 414 may be on the chiplet 230 and in other embodiments, one or more of the read peripherals 410, 412, 414 are on the second device 226.Attorney Docket: P25-061-SEC-W001

[0089] Fig. 5 shows an illustration of an integrated circuit 500 that may be part of a semiconductor device such as a chiplet in accordance with an embodiment of the present disclosure. The integrated circuit 500 may be disposed on a semiconductor device, such as a chiplet, that has a silicon substrate 506 and a second layer portion 508.Within the integrated circuit 500, there may be an array section forming the module 502 where a three-dimensional column array of memory bit cells 522 has the necessary components to store memory in non-voltage, semi-volatile memory, or a memory format as described herein.

[0090] The integrated circuit 500 may include a modules group having a plurality of modules including a first module and a second module, etc. even though only a single module 502 is shown. The memory bit cells 522 are written to by the shared write port 512, 516, which includes both a write address bus line 512 and a write data bus 516. These buses run through the second layer 508 and can be connected to a second semiconductor device via an interposer. The second device has electrical contacts that complement those on the surface 518, allowing it to be electrically coupled to the write address and data buses. The memory bit cells 522 can be read from via the read port 524, 526, which includes a read address bus line 524 and a read data bus 526.Both of these buses can also run through the second layer 508 to the second semiconductor device coupled to the surface 518, which also has complementary electrical contacts to allow it to be electrically coupled to the read address and data buses.

[0091] Various kinds of memory technologies may be used for the memory bit cells 522, such as a vertical connectivity fabric structure formed from non-volatile memory unit cells arranged in a three-dimensional column array 522. The memory bit cells 522 may utilize one or more of a cross-point, 3D NANDs, 3D NORs, 3D ANDs, and / or a stacked planar layer.

[0092] In some embodiments, the integrated circuit 500 is electrically connected to a second semiconductor device (not shown in Fig. 5) comprising another integrated circuit, which may be a system-on-chip or a Field-Programmable-Gate-Array. In some embodiments, the memory bit cells 522 may be formed from various non-volatile memory types, such as FeFET, FeRAM, ReRAM, SOT, or STT.Additionally, alternatively, or optionally, the memory bit cells may be formed from non-volatile memory unit cells having 2-terminal devices, 3 -terminal devices, or 4-terminal devices.Attorney Docket: P25-061-SEC-W001

[0093] For example, the memory unit bit cells 522 may be formed from ferroelectric materials, such as a ferroelectric tunnel junction, a diode, a capacitor, a single-gate transistor, or a dual-gate transistor. Alternatively, the memory unit bit cells 522 may be formed from memristive materials, such as at least one ReRAM, or magnetic materials, such as at least one spin-orbit-torque device or at least one spin-transfer-torque device. Moreover, the non-volatile memory unit cells 522 may also be formed from phase-change materials or anti-ferroelectric materials.

[0094] In some alternative embodiments, the non-volatile memory unit cells522 can be formed from other types of materials, such as phase change materials, antiferroelectric materials, or multi-bit PCM materials. The non-volatile unit cells can be formed utilizing different structures, such as resistive random-access memory (RRAM) technology, magnetic random-access memory (MRAM) technology, or ferroelectric random-access memory (FRAM) technology.

[0095] Moreover, in some implementations, 3D NAND technology may be utilized to form the memory unit bit cells 522. For example, the memory unit bit cells 522 may be formed from stacked memory layers where each layer includes a plurality of memory cells that can be accessed using shared bit lines. In such a case, the read port 524, 526 may be coupled to the bit lines, and the write port 512, 516 may be coupled to the word lines that control the access to each layer.

[0096] In another embodiment, the 3D connectivity fabric structure can be built with stacked layers of either NAND gates, NOR gates, or AND gates, and in some cases, different types of logic gates may be combined to optimize the structure's functionality. In addition, the 3D connectivity fabric structure may be formed utilizing through-silicon-via (TSV) technology, which allows the vertical interconnection of the different layers of the structure.

[0097] Additionally, the non-volatile memory unit cells may include 2-terminal devices, such as a capacitive or a memristive device with or without an additional selector device such as a diode in series, 3 -terminal devices, such as a floating-gate transistor, a transistor with an access gate, or 4-terminal devices, such as a transistor with two access gates. The type and configuration of the non-volatile memory unit cells 522 may depend on the specific application requirements, including the speed, power consumption, and reliability of the circuit. The memory unit cell may include or be a single ferroelectric transistor or 6T SRAM cell. The memory unit cell may be aAttorney Docket: P25-061-SEC-W001combination of many different devices, including, but not limited to, one or more of a transistor, a memristor, a capacitor, etc.

[0098] In some embodiments of the present disclosure, a ferroelectric material can be utilized to form the non-volatile memory unit cells 522. The ferroelectric material may be implemented as any kind of device, including, but not limited to, a thin-film device, such as a ferroelectric tunnel junction, a capacitor, a single-gate transistor, or dual-gate transistors, etc.

[0099] In another embodiment, the non-volatile memory unit cells522 may be formed from a memristive material, such as a Metal Oxide Memristor (MOM), Conductive-Bridging RAM (CBRAM), or valence change memory (VCM), each of which provides different benefits regarding power consumption, speed, endurance, etc.

[0100] Moreover, in some embodiments, the non-volatile memory unit cells 522 may be formed from a magnetic material, such as spin-orbit-torque (SOT) devices, spin-transfer-torque (STT) devices, or perpendicular magnetic tunnel junctions (p-MTJ).

[0101] In one embodiment, the modules group may include many modules where each of which can be accessed through dedicated read ports 524, 526 with a dedicate read peripheral 520 while sharing the same write port 512, 516 and shared write peripheral 510. The shared write port 512, 516 can be configured to selectively write to one or more of the plurality of modules within the modules group including the memory bit cells 522. Each of the modules may have the same or different sizes, and different module sizes may be configured to optimize the utilization of the memory array with different operating scenarios, etc.

[0102] Furthermore, the integrated circuit 500 may be formed utilizing different manufacturing processes and techniques, which include but not limited to, a CMOS or Bipolar-CMOS-DMOS (BCD) process, a silicon-on-insulator (SOI) process, a FinFET process, a silicon germanium (SiGe) process, a gallium arsenide (GaAs) process, etc.

[0103] In some embodiments, the where a three-dimensional column array of memory bit cells 522 forms is configured as a microvault. Additionally or alternatively, each of the micvrovaults will have a dedicated read peripheral 520 and a write peripheral 510 that is also a dedicated write peripheral rather than a shared write peripheral. That is, in some embodiments, each mircovault includes a dedicate write connection and a dedicated read connection, predetermined number of microvaultsAttorney Docket: P25-061-SEC-W001(e.g., 2 or 4), may have a dedicated write connection and a dedicated read connection, with or without dedicated respective peripheries, etc.

[0104] Fig. 6 shows a perspective of an assembly 600 having the integrated circuit of Fig. 1 implemented on a semiconductor device, such as the chiplet 230, that is electrically connected to a system-on-a-chip (“SOC”) 610 in accordance with an embodiment of the present disclosure. The semiconductor device, in this embodiment, is the chiplet 230 that is electrically connected to a system-on-a-chip (“SOC”) 610.

[0105] Referring to Fig. 6, the SOC 610 includes a silicon substrate 602 on which a plurality of processing elements is formed, including a processing element 606.The processing elements can communicate with each other through a Network-on-Chip (“NOC”) 604, which is a communication fabric that directs data transfer between the processing elements. The communication fabric can take various forms, including buses, switches, NOCs, etc. The NOC 604 in the SOC 610 directs data traffic between the various nodes (e.g., the processing element 606) and links, which provide the communication paths between the nodes.

[0106] The plurality of processing elements including the processing element 606 processing elements can be any suitable type of processors capable of executing instructions, including microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), or application-specific integrated circuits (ASICs).

[0107] Additionally, the SOC 610 may comprise various modules, such as module 232, which are grouped together to provide memory functionality to the assembly 600 as described here. The modules in modules group 236 can be coupled to a respective processing element provide it readable memory. In some embodiments, the coupling between the module (e.g., module 232) and the processing element (e.g., 606) can be achieved through interconnects on the silicon substrate 602.

[0108] After the circuitry is formed on the silicon substrate 602, a second layer 608 can be disposed on top of the substrate. The second layer 608 can be any suitable material, such as an insulating material, a metal, a dielectric, or interconnect layer, and it may be bonded to the chiplet 230. The bonding can be done using any suitable technique, including but not limited to, adhesives, soldering, or welding, etc.

[0109] In general, the assembly 600 provides a means of integrating the chiplet 230, which can include the integrated circuit of Fig. 1, with the SOC 610. Integrating the chiplet 230 provides various advantages, such as enhanced functionality, higher performance, and lower power consumption. Moreover, the integration of the chipletAttorney Docket: P25-061-SEC-W001230 with the SOC 610 can be accomplished in various ways, depending on the particular application and design objectives of the system.

[0110] The assembly 600 can incorporate various variations and modifications, depending on the specific requirements of the system. For example, the processing elements formed on the silicon substrate 602 can vary in their number, type, and arrangement. Similarly, the modules in modules group 236 can vary in their number, type, and function.

[0111] Furthermore, the second layer 608 can be modified to include additional functionality. For instance, the second layer 608 can include passive components, such as resistors, capacitors, and inductors, or active components, such as transistors or diodes. Incorporating these components in the second layer 608 can further enhance the functionality and performance of the system.

[0112] In another variation, the assembly 600 can incorporate a heterogeneous integration approach, where the chiplet 230 is fabricated using a different technology than that used for the SOC 610. This approach allows for the optimal use of different fabrication technologies for different parts of the system, resulting in improved performance and reduced power consumption.

[0113] Fig. 7 shows a perspective view of an assembly 700 having a semiconductor device 707 with an array of processing elements 706 (on a grid of processing element 706a, a to 706n,n, where the first subscribe is the columns and the second subscript is the row), and a second semiconductor device 709 having an array of microvaults 708. The array of microvaults 708 are on a grid of microvaults 708a, a to 708n,n, where the first subscript is the columns and the second subscript is the row).These subscripts may line up such that a respective subscript of a processing element 706 corresponds to a respective subscript of a microvault 708. The microvaults 708 are a type of module described herein where it is positioned in a vertical direction, e.g., above a respective processing element 706. The layer 770 may be a chiplet. Also, the semiconductor device 709 may also be a chiplet. The chiplets 707,709 may be bonded together. The different layers 710 (e.g., 710a, 710c through 7 lOd can correspond) may be allocated for separate Al models (e.g., parameters in a neural network, such as a CNN or transformer model).

[0114] The layer 770 functions as a key -value (KV) cache within the assembly 700. This KV cache architecture allows the processing elements 706 to efficiently store and retrieve data in the form of key-value pairs, optimizing access times for frequentlyAttorney Docket: P25-061-SEC-W001used data. The KV cache 770 may be a KV cache for a LLM transformer. By leveraging the vertical alignment with the microvaults 708, the KV cache 770 can provide rapid access to parameters and weights required for Al model computations.

[0115] The assembly 700 is the overarching structure that houses the various components shown in Fig. 7. It provides mechanical support and integration for the other elements, allowing them to function as a unified system.

[0116] The assembly 700 includes two semiconductor devices - the semiconductor device 707 and the semiconductor device 709. The semiconductor device 707 contains an array of processing elements labeled 706a, a to 706n,n.Similarly, the semiconductor device 709 contains an array of microvaults labeled 708a, a to 708n,n.

[0117] The subscripts a, a to n,n indicate that the processing elements 706 and microvaults 708 are arranged in a grid pattern, with the first subscript referring to the column and the second subscript referring to the row. This grid arrangement allows each processing element 706 to have a corresponding microvault 708 positioned vertically above it. For example, processing element 706a, a has microvault 708a,a above it, processing element 706b, b has microvault 708b, b above it, and so on. The alignment of the grid allows tight integration between the processing and storage components.

[0118] In some embodiments, the semiconductor devices 707 and 709 are potentially separate chiplets that are integrated using packaging techniques into the unified assembly 700. The chiplet form factor allows greater flexibility and customization in assembling the system. This arrangement is such that each processing element 706 can access its respective microvault 708 located above it to retrieve relevant data, such as weights for neural networks or Al models, or to write data, such as KV cache memory in KV cache 770. This may provide high bandwidth and low latency access to the data needed for efficient processing.

[0119] Input data enters the system via the input DRAM memories 702. This data flows into the processing elements 706, where it is operated on locally using weights or parameters from the vertically integrated microvaults 708. The processing results output via the output DRAM memories 704. The input DRAM memories 702 consist of multiple individual DRAM modules labeled 702a, 702b, and 702c. The DRAM memories 702 can be any type of dynamic random access memory, including but not limited to DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, and HBM. TheAttorney Docket: P25-061-SEC-W001DRAM memories provide high-bandwidth data input capabilities to feed data, such as inference inputs or training data, into the processing pipeline.

[0120] In some embodiments, each individual DRAM module 702a, 702b, and 702c has a dedicated interface and data path to each processing element 706. For example, DRAM module 702a may feed data only to processing element 706a, a, while DRAM module 702b feeds data only to processing element 706b, b. This provides modular scalability, as additional DRAM modules can be added to feed more processing elements.

[0121] The number of input DRAM memories 702 and individual modules 702a-702c may vary depending on the application requirements. For instance, there could be 4, 8, 16, or more input DRAM modules. The capacity of each module can range from gigabytes to terabytes depending on factors such as access speed, power, and cost budget.

[0122] High-speed interfaces like DDR5, GDDR6, or HBM3 may be used to maximize data transfer bandwidth between the input DRAM memories 702 and the processing elements 706 across the semiconductor device 707. Shared data buses, crossbar switches, or on-chip networks may interconnect groups of DRAM modules 702 and processing elements 706.

[0123] In some implementations, the input DRAM modules 702 may be stacked or arranged in a multi-dimensional configuration to increase overall memory capacity and bandwidth while reducing latency and power consumption. Specialized memory controllers and schedulers may manage parallel data access across multiple input DRAM modules 702.

[0124] The input DRAM memories 702 may supply the high-bandwidth data needs of the parallel processing elements 706, to help enable fast and efficient data-intensive computations such as neural network inferencing. Each processing element 706 can directly access the required input data from its dedicated DRAM module 702 without contending with other processors for data access.

[0125] In alternative embodiments, instead of, or in additional to, the DRAM memories 702, 706, adjacent accelerator chiplets may be in communication with the semiconductor device 707. That is, there may be a grid-like arrangement of assemblies 700 in communication with each other to perform Al inference and / or Al training (e.g., transformer inference, CNN interference, ANN interference, etc.). In some embodiments, there may be clusters of semiconductor devices 707 that share a bank orAttorney Docket: P25-061-SEC-W001portion of DRAM memories 702 and / or 706. In some embodiments, the input DRAM memories 702 and the output DRAM memories 704 may be combined into the same DRAM memory.

[0126] The assembly 700 includes a semiconductor device 707 that comprises an array of processing elements labeled from 706a, a to 706n,n. Each processing element in the array may be configured to execute specialized computations and data processing operations. For instance, in some embodiments, the processing elements could be optimized for artificial intelligence workloads like neural network inference.In other cases, the processing elements may focus more on general-purpose capabilities.Ultimately, the capabilities of each processing element depend on its specific microarchitecture which can be tailored for certain applications if desired.

[0127] The processing elements 706 can access nearby memory storage to retrieve data that feeds into their computations. This memory may be physically separate from the processing element arrays 706 as is the case with the microvaults 708 shown in Fig. 7. The processing elements 706 and microvaults 708 are aligned so that each microvault is positioned directly above its corresponding processing element in a vertical configuration. This tight coupling provides fast data transfer speeds between each vault-element pair.

[0128] In terms of physical implementation, the array of processing elements 706 resides within the semiconductor device 707. The semiconductor device 707 could potentially be manufactured as a standalone chiplet using advanced packaging techniques. This modular chiplet can then be integrated with other components like the microvault chiplet 709 through high-density interconnections. Some options include bumpless hybrid bonding, interposers, or even monolithic 3D integration. Ultimately, combining chiplets allows creating powerful heterogenous systems with optimized dies.

[0129] The specific number, design, and interconnect scheme of processing elements 706 present can vary between implementations of assembly 700. For instance, simpler systems may need only a 2x2 grid of elements whereas a sophisticated Al accelerator could feature a 32x32 array. The processing elements 706 themselves can also have different memory access routes across the assemblies. Point-to-point links, crossbar switches, or shared buses are possible connection structures. Such architectural decisions depend on the performance and area constraints trying to be met.Attorney Docket: P25-061-SEC-W001

[0130] The second semiconductor device 709 may be a separate device from the first semiconductor device 707. Like the first semiconductor device 707, the second semiconductor device 709 may also be implemented as a chiplet. The second semiconductor device 709 includes an array of microvaults 708, arranged on a grid spanning from microvault 708a, a to 708n,n.

[0131] As mentioned, the micro vaults 708 on the second semiconductor device 709 are positioned vertically above the processing elements 706 on the first semiconductor device 707. Each microvault 708 lines up with and corresponds to the processing element 706 underneath it, based on the subscripts identifying their position in the grid. For example, microvault 708a, a is vertically aligned with and corresponds to processing element 706a, a. This allows each processing element 706 to access the microvault 708 above it.

[0132] The microvaults 708 act as a memory structure, storing things like Al model weights that can be both read from and written to by the processing elements 706 underneath during operations like neural network inference. This bidirectional communication allows the processing elements 706 to rapidly access the weights and data needed for their computations while also enabling them to update the microvaults with new data or modified parameters as needed. The microvaults 708 may be optimized for fast read and write times, ensuring efficient data handling for dynamic workloads.

[0133] In some embodiments, the second semiconductor device 709 containing the array of microvaults 708 is directly bonded to the first semiconductor device 707 with the processing elements 706. This bonding aligns each microvault 708 with its corresponding processing element 706 underneath. Electrically conductive interconnects between the devices allow each processing element 706 to communicate directly upwards with its respective overlying microvault 708. This provides a compact, modular, and efficient system architecture.

[0134] The microvaults 708 may contain multiple memory layers, labeled 710a to 710d, each storing weights or data for a different Al model. For example, layer 710a contains the weights for model A, layer 710b contains the weights for model B, and so on. Stacking these layers vertically contributes to the high density and fast access times of the microvault design.

[0135] The microvaults 708 can be implemented using various memory technologies, including but not limited to SRAM, FeFET, ReRAM, SOT, and STT,Attorney Docket: P25-061-SEC-W001optimized for fast readout times to supply data to the processing elements 706 with minimal latency. Specific embodiments may configure the microvaults 708 to have much faster read speeds compared to their write speeds. The microvaults 708 may be implimented using any FeFET or memory structure described herein.

[0136] In some embodiments, each microvault 708 may have a capacity between 4 kilobytes to 128 kilobytes for storing parameters for machine learning models or other data. The bit density per layer may exceed 0.4 gigabits per square millimeter. The microvaults’ 708 compact size, between less than 100 micrometers on each side in one embodiment or 12 micrometers by 12 micrometers in another, allows high-density integration of the memory modules.

[0137] The array-based arrangement of the microvaults 708 may enables concurrent parallel data access by the processing elements 706, supporting high-throughput data processing by the assembly 700. The one-to-one alignment of the microvaults 708 and processing elements 706 also ensures that each processing element 706 has dedicated access to its required data without contention.

[0138] The microvaults 708 share the semiconductor device interface provided by the second semiconductor device 709, which facilitates writing data to the microvaults 708 from the input DRAM memories 702. Reading data from the microvaults 708 to the processing elements 706 and output DRAM memories 704 is handled through dedicated pathways between each vertically aligned microvault 708 and processing element pair.

[0139] The microvault memory layers 710 refer to multiple layers of microvault memories stacked vertically within the second semiconductor device 709. As illustrated in Fig. 7, there are four separate microvault memory layers labeled as 710a, 710b, 710c, and 7 lOd. Each layer contains an array of microvaults, such as the array of microvaults 708 shown in the diagram.

[0140] In one embodiment, the microvaults 708 may utilize a stacked 3D NAND architecture built from multiple layers of NAND memory arrays using charge trap flash technology. Each microvault 708 may contain a dedicated set of wordline drivers on the bottom layer to facilitate access to the 3D NAND cell arrays above, spaced by alternating dielectric layers. The 3D NAND implementation may be used to maximize density and throughput by leveraging vertical scaling.

[0141] In an alternative embodiment, the microvaults 708 employ a 3D NOR architecture constructed from multiple tiers of NOR flash memory arrays. Each planeAttorney Docket: P25-061-SEC-W001features NOR strings with a source line and bit line architecture, stacked on top of each other using vias. The 3D NOR arrangement optimizes random read access times to stored data.

[0142] The microvaults 708 may also adopt a hybrid configuration with different types of volatile and / or non-volatile memory, such as combining FeRAM and ReRAM cells, organized into vertical sub-arrays. This heterogeneous 3D integration allows optimizing for speed, endurance, and retention within the same vault structure.

[0143] In certain embodiments, the microvaults 708 integrate processing logic like analog computing directly into the memory array stack itself. This processing-in-memory approach places basic computational operators within the memory peripheral or bit cells, enabling highly parallel and efficient in-situ data processing.

[0144] Some implementations may utilize 2.5D or 3D stacking to integrate the microvaults 708 with other components like logic, CPUs, GPUs or application-specific accelerators. This tight packaging integration via techniques like high-bandwidth memory cube architectures reduces data transfer latency and power consumption.

[0145] The microvaults 708 may also employ a virtualized architecture, with an external memory controller handling translation between the physical array organization and dynamically allocated virtual memory domains. These virtual domains mapped onto the physical array effectively creates separate virtual vaults with flexible capacities tailored to application needs.

[0146] In certain embodiments, the microvaults 708 are designed as Computational RAM (CRAM) with integrated processing capabilities within the bit cell peripheral to enable highly parallel in-memory computing architectures. Gateless transistor structures integrated into the CRAM arrays facilitate efficient execution of bulk bitwise operations.

[0147] Some implementations arrange the microvaults 708 into modular Memory Processing Unit (MPU) structures containing dedicated processing logic tailored for workloads like Al inferencing. The MPU architecture couples vault arrays to vector processors via high-speed interfaces like HBM2 enabling low-latency data transfers.

[0148] The microvaults 708 may also implement content-addressable capabilities by integrating comparison logic into the memory peripheral. This facilitates searching or accessing data based on content rather than explicit addresses, enabling powerful pattern matching capabilities.Attorney Docket: P25-061-SEC-W001

[0149] Certain embodiments may stack multiple microvault dies on top of base logic dies featuring things like GPUs or Al accelerators. This creates dense, high-bandwidth heterogeneous systems optimized for data-centric workloads while minimizing data movement.

[0150] The microvault memory layers 710 may be fabricated utilizing three-dimensional integrated circuit manufacturing processes to stack multiple dies or wafers containing microvault 708 arrays on top of each other. Through-silicon vias (TSVs) or other vertical interconnect technologies can be employed to enable communication between the layers.

[0151] In some embodiments, each microvault memory layer 710 corresponds to a different artificial intelligence (Al) model or application. For example, layer 710a could store the weights and parameters for Al model A, layer 710c could store the weights and parameters for Al model C, and so on. This allows multiple Al models to be stored efficiently within the same microvault memory 708 structure.

[0152] The microvaults 708 may possess capacities ranging from 4 kilobytes to 128 kilobytes in some embodiments. In other cases, the capacity could be between 4 kilobytes to 16 kilobytes. Each microvault could have lateral dimensions less than 100 micrometers by less than 100 micrometers, while extending vertically to incorporate potentially over 200 memory cell layers in some implementations.

[0153] In some embodiments, the bit density of per square millimeter per layer within the microvault memory layers 710 may facilitate high-capacity storage with a small footprint. The layers may utilize non-volatile memory technologies, such as FeFET, STT-MRAM, or ReRAM, to retain data when power is removed.

[0154] In operation, the processing elements 706 may access weights or parameters from the microvault memory layers 710 to perform neural network inferencing or other machine learning computations.

[0155] The inference results of the various AIs may be sent to the output DRAM memories 704. which comprise individual DRAM memory modules labeled 704a, 704b, and 704c. The output DRAM memories 704 are positioned adjacent to the array of microvaults 708 and the second semiconductor device 709. The output DRAM memories 704 may serve as temporary data storage that can buffer output data retrieved from the microvaults 708 before it is transmitted externally.

[0156] Each DRAM memory module 704a, 704b, and 704c may have similar or different storage capacities, depending on the design requirements. For example, inAttorney Docket: P25-061-SEC-W001one embodiment, each module contains 16 megabits of storage. The DRAM storage cells utilize a capacitor to retain data bits in the form of electrical charges. Due to charge leakage, the DRAM memories may require periodic refresh cycles to maintain the stored data integrity. To enable concurrent reads and writes across multiple modules, each DRAM module 704a, 704b, and 704c can have dedicated internal control circuitry and I / O ports.

[0157] The data outputs from the individual microvaults 708 may get aggregated and buffered in the output DRAM memories 704 before being transmitted to external components via peripheral circuitry. Buffering the data allows the transmission rate to be regulated to match the requirements of the external interfaces.It also enables data processing operations like formatting, encoding, or encryption to be performed by the second semiconductor device 709 prior to output.

[0158] In some embodiments, the output DRAM modules 704a, 704b, and 704c are designed to provide high-density, low-cost temporary data storage to support the high-bandwidth parallel reads from the array of microvaults 708. Optimizing these performance parameters allows efficient extraction of data from the microvaults to feed the computational workflows hosted on external chips or devices. Specific implementations may utilize various types of DRAM, including asynchronous DRAM, synchronous DRAM, graphics DRM, and low-power DRM tailored to the application.Overall, the output DRAM memories 704 facilitate seamless data movement from the integrated microvaults to external execution pipelines.

[0159] Fig. 8 shows an assembly 800 of a semiconductor devices 802, 804, 806, 808, 810, 812, 814 including several memory types in accordance with an embodiment of the present disclosure. Specifically, Fig. 8 shows an exemplary assembly 800 of semiconductor devices 802, 804, 806, 808, 810, 812, 814 configured to provide a hierarchical memory structure. The assembly 800 is modular and scalable, allowing for various combinations and numbers of semiconductor devices, which may be implemented as chiplets in certain embodiments, to be stacked to meet specific performance and density requirements.

[0160] The assembly 800 includes an application semiconductor 802, that may be a plurality of processing elements as described herein. On top of the semiconductor device 802 is semiconductor device 814 that includes an array of microvaults. One top of the semiconductor device 814 is semiconductor device 812, which may also include an array of microvaults. On top of the semiconductor device 812, are semiconductorAttorney Docket: P25-061-SEC-W001devices 810, 808, which may be SRAM vaulted dies. One top of the semiconductor device 808, is semiconductor devices 806, 804 may be DRAM vaulted dies. These vaults 816 may be arranged in a grid-like fashion such that 816a, a to 816n,n subscripts the vaults. Each of these vaults may include a respective microvault from semiconductor devices 804, 812, respective SRAM vaults from semiconductor devices 810, 808, and respective DRAM vaults from semiconductor devices 806, 804.

[0161] At the base of assembly 800 lies the semiconductor device 802, which comprises a plurality of processing elements. These processing elements execute computational tasks and facilitating data flow within the system.

[0162] Directly above semiconductor device 802 is semiconductor device 814, which includes an array of microvaults. These microvaults utilize Field-Effect Transistors (FeFETs) known for their non-volatile characteristics and suitability for high-density memory applications. The FeFET-based microvaults may be designed to enable high-speed read operations essential for rapid data retrieval during processing tasks, such as Al inferencing, while supporting slower write operations that are more tolerant to latency. Stacked on top of semiconductor device 814 is semiconductor device 812, which similarly includes an array of microvaults. The presence of multiple layers of microvaults in semiconductor devices 814 and 812 exemplifies the scalable nature of the assembly, where additional memory capacities and functionalities can be integrated through additional layers.

[0163] Further contributing to the memory hierarchy, semiconductor devices 810 and 808, positioned above semiconductor device 812, are depicted as SRAM vaulted dies. SRAM provides fast access memory that can serve as a cache or buffer to the slower, but denser, FeFET microvault memory layers beneath.

[0164] At the top of the assembly 800 and hence the memory structure are semiconductor devices 806 and 804, illustrated as DRAM vaulted dies. DRAM is typically used for main memory due to its relatively high speed and low cost per bit compared to SRAM, offering a balance between performance and economy.

[0165] The arrangement of vaults 816 in a grid-like fashion, subscripted from 816a, a to 816n,n, indicates that each processing element at a given location (a,b) in semiconductor device 802 has dedicated access to the corresponding vertically aligned vaults of microvaults and memory cells in the layers above. This vertical stacking and alignment ensure that data and control signals can be directly routed between processing elements and their respective memory stacks, facilitated by interconnectAttorney Docket: P25-061-SEC-W001technologies such as through-silicon vias (TSVs) and micro-bumps, which are sued in the assembly's 8003D integrated circuit architecture.

[0166] The modular and scalable design of assembly 800 allows for various combinations of semiconductor devices or chiplets to be integrated into more extensive systems. The flexibility in the number and combination of stacks provides the adaptability to tailor the assembly to the requirements of different applications and performance demands. Each vault within the vaults 816 within the assembly 800 presents a multi-die structure that contributes to the overall capacity and performance of the system.

[0167] Fig. 9 shows an assembly of semiconductor devices including a semiconductor device with a system-on-chip 914 and another semiconductor 906 with microvaults disposed on top in accordance with an embodiment of the present disclosure. The assembly 900 integrates a semiconductor device 906 and a semiconductor device 914, which may be implemented as separate chiplets bonded together. The semiconductor device 914 includes various components to facilitate reading data from the microvaults on the semiconductor device 906, such as a read address register input interconnect 924, read data register 922, and read data register output interconnect 950. These components pass the read address to the microvaults on semiconductor device 906 and return the read data back to the semiconductor device 914.

[0168] Specifically, the read address enters via interconnect 924 into the read address register 926. The output of this register 962 connects through interconnects and bumpless bonds to another read address register 938 on the semiconductor device 906, which then addresses the target microvault 936. The microvault 936 outputs read data via interconnect 940 to a read data register 942, which passes the data back through bumpless bonds 910, 918 to read data register 922 on semiconductor device 914. This data can then be accessed externally via the read data register output interconnect 950.Additionally, the semiconductor device 914 and 906 have interconnected Through-Silicon Vias 916 and 944 to allow communication with devices potentially stacked above semiconductor device 906.

[0169] The semiconductor device 906 features various memory structures to provide data storage capabilities. This includes a microvault 936, which offers high-density, low-latency data storage, along with other peripheral memory components like read data register 942 and read address register 938 to facilitate data reads. TheAttorney Docket: P25-061-SEC-W001microvault 936 resides on the BEOL portion of the chiplet, allowing dense 3D integration of memory layers. In some implementations, the micro vault utilizes nonvolatile memory technologies like FeFET or STT-MRAM for data retention without power.

[0170] The semiconductor device 914 comprises processing elements and data routing circuitry to retrieve and manipulate data stored in semiconductor device 906.Components like read address register 926 and read data register 922 handle sending read addresses and receiving data from the microvault 936 respectively. The device 914 also includes interconnects 924, 950 and Through-Silicon Via 916 to communicate externally.

[0171] The two devices 906 and 914 integrate via fine-pitch interconnects like bumpless hybrid bonds 908, 910, 918, 920, 930 and 932. This allows direct data transfer pathways between processing components in device 914 and memory structures in device 906. Alignment during bonding ensures dedicated access - for instance, read data register output interconnect 950 on 914 links directly to read data register 922 to receive requested data.

[0172] The pathways facilitating data flow during reads can be summarized as follows: A read address enters through interconnect 924 into read address register 926 on device 914. This gets communicated via interconnects and bumpless bonds to read address register 938 on device 906, which then addresses microvault 936. Requested data gets passed via interconnect 940 to read data register 942, then transfers through bonds back to read data register 922 on 914, where it becomes available externally via interconnect 950.

[0173] The assembly 900 exemplifies a modular, high-density architecture optimized for data-centric applications like Al inferencing. Tight integration of processing and storage dies via advanced packaging techniques allows localized data access with minimal latency and power. Scalability is also enabled by incorporating multiple chiplets, in this case devices 906 and 914. The assembly 900 illustrates a potential configuration suited for space-constrained, high-performance computing systems.

[0174] The Through-Silicon Via (TSV) 916 is an electrical connection that passes vertically through the semiconductor device 914. Its purpose is to provide a pathway for signals to travel between the top and to a processing element within the semiconductor device 914. This allows the device to be stacked and interconnected withAttorney Docket: P25-061-SEC-W001other components in a vertical configuration. The TSV 916, along with other TSVs on the device, facilitates high-density 3D integration and heterogeneous stacking of multiple devices like chiplets.

[0175] The TSV 916 interacts with several other components within the system.On the top side of semiconductor device 914, it connects to interconnect 912, which couples it to bumpless bonds 918. These bonds interface with complementary bumpless bonds 910 on the bottom side of semiconductor device 906 when the two devices are stacked. This allows signals to travel from device 914 to device 906 through the TSV 916. The route continues as signals go through interconnect 902 to TSV 944 on device 906. TSV 944 provides a vertical signal pathway to the top surface of device 906 where additional devices could be stacked. In the reverse direction, signals can travel from TSV 944 down through device 906, back up TSV 916, and down into device 914. So the TSV 916 provides bidirectional vertical communication across device boundaries.

[0176] There are a few possible variations for the TSV 916 implementation.First, multiple TSVs arranged in an array could be used instead of a single via to increase throughput and redundancy. Second, the dimensions and materials of the TSV could be optimized- for example, smaller TSV diameters using denser materials like tungsten could be advantageous. Additionally, the interface circuitry driving signals into the TSV, like interconnects 912 and 902, could employ variable line drivers to support different voltage levels or signal integrity enhancements. Further embodiments may include integrated monitoring circuitry within TSV 916 to track metrics like temperature and link utilization. And alternative signaling schemes besides electrical signals could be employed in future cases. For instance, integrated silicon photonics utilizing modulated light to convey data through the TSVs could enable very high bandwidth and low latency connectivity. There are multiple avenues to further develop the capabilities of TSV-based vertical links like TSV 916 within these complex 3D integrated architectures.

[0177] There are several variations and alternatives for the interconnect 912 implementation. For example, different conductive materials such as copper or aluminum may be utilized to fabricate the pathways forming interconnect 912 and optimize for conductivity or thermal dissipation. Additionally, interconnect 912 may feature redundant signal paths or self-repair capabilities using spare interconnect lines to improve reliability and resilience. The bumpless bonds 918 and 910 connecting devices 906 and 914 could also be replaced with other high-density bonding approachesAttorney Docket: P25-061-SEC-W001like hybrid bonding or Through-Silicon Vias. Furthermore, alternate signaling schemes besides simple digital logic could be employed on interconnect 912, such as analog signaling or multi-level digital waveforms to enhance data transmission capabilities.The routing and dimensions of interconnect 912 can also be adapted according to bandwidth requirements or circuit layout considerations. Overall, many structural and functional alternatives exist for crafting interconnect 912 to meet application needs.

[0178] The bumpless bonds 918 are electrical connections located on the semiconductor device 914 between an interconnect 912 and bumpless bonds 910 of the semiconductor device 906. The bumpless bonds 918 provide an electrical pathway for signals to travel between the semiconductor device 914 and any additional semiconductor devices, such as the semiconductor device 906, stacked on top of the assembly 900. The signals communicated over the bumpless bonds 918 can include data signals, control signals, address signals, or any other signals needed to coordinate operations between the multiple semiconductor devices.

[0179] There are several possible variations for the bumpless bonds 918. The number of individual bond sites can range from just a few to hundreds, depending on signal bandwidth requirements. The bonding method can utilize techniques like direct bonding, plasma-activated bonding, adhesive bonding, or compression bonding. Hybrid bonding approaches are also possible, combining direct wafer bonds with intermediate metal bonds. The size and pitch of each bond site can vary and may use pitches under 10 micrometers to enable high-density connections. Redundant bonds can provide backup pathways. Shielding structures may surround bonds for noise immunity.Overall, many embodiments of bumpless bonds 918 are possible to meet cost, reliability, and performance needs.

[0180] The bumpless bonds 910 provide an interface for communicating signals between the semiconductor device 906 and semiconductor device 14. Specifically, the bumpless bonds 910 of the semiconductor device 906 are electrically coupled to the complementary bumpless bonds 918 of the semiconductor device 914. This allows signals like read / write data and addresses to be transmitted between the two devices.The bumpless nature of the bonds allows for a low-profile, high-density interconnection.

[0181] The bumpless bonds 910 interact with other components in the system to facilitate data transfer operations. For writes, data enters the semiconductor device 914 via the Through-Silicon Via 916, passes through interconnect 912 and bumplessAttorney Docket: P25-061-SEC-W001bonds 918 before reaching bumpless bonds 910 of device 906. For reads, addresses flow from the read address register 926 of device 914 through interconnects 928, 930 and bumpless bonds 932 into the read address register 938 on device 906. Read data then returns through bumpless bonds 908 and 920 back to device 914. So the bumpless bonds 910 provide key data and address routing between the devices.

[0182] Possible variations of the bumpless bonds 910 include using different bond densities, materials, or electrical contact configurations to optimize performance.The bonds can use alloying or doping techniques to improve conductivity. Additionally, the routing of signals can be changed, for example by using separate ports for input and output instead of shared ports. More bumpless bonds can be added to increase bandwidth between devices. Shielding may be added around the bonds to reduce interference. Overall, many modifications to the bumpless bonds 910 are possible within the scope of electrically interconnecting multiple devices.

[0183] The Through-Silicon Via (TSV) 944 is an electrical connection that passes vertically through the semiconductor device 906 from the top surface to the bottom surface. Its purpose is to facilitate communication of signals and data between the semiconductor device 906 and any additional semiconductor devices potentially stacked on top of it in a 3D integrated circuit configuration. The TSV 944 enables high-density interconnections between multiple stacked semiconductor layers, providing an efficient means for data routing and signaling.

[0184] The TSV 944 interfaces with surrounding circuitry within the semiconductor device 906, allowing signals to be transmitted upwards or downwards depending on the system configuration. On one end, the TSV 944 couples to the read data register 942 via interconnect 946. The read data register 942 can use the TSV 944 path to transfer read data from the microvault 936 to external semiconductor devices.This enables efficient data offloading from the on-chip memory. On the other end, the TSV 944 continues through to the top surface of semiconductor device 906, where it may interface with complementary contacts or interconnects on the bonded semiconductor above it. This facilitates the vertical transfer of signals and data along the assembly 900.

[0185] There can be many variations in the specific implementation of the TSV 944. Its dimensions can range from a few microns to tens of microns to match pitch requirements. The TSV 944 can be tapered, straight, or have non-uniform crosssections. It may utilize different conductive materials as liners and fills, includingAttorney Docket: P25-061-SEC-W001metals like copper, tungsten or alloys. Insulating liners made of materials like silicon dioxide can separate the conductive fill from the substrate. The contacts and interconnects coupling into the TSV 944 can also have diverse layouts. Multiple TSVs can be placed adjacent to each other in a high-density array configuration if desired.Overall, many architectural optimizations in the design and fabrication process of the TSV 944 are possible within the scope of the present disclosure.

[0186] Fig. 10 shows a semiconductor assembly 1000 incorporating a daisy-chained configuration of microvaults 1036, 1058, operatively connected to a multiplexer 1060 and managed by a counter 1062 for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure. This assembly 1000 is designed to carry out data processing tasks, potentially for applications such as artificial intelligence (Al) and machine learning, where high-speed data access and processing are utilized.

[0187] The assembly 1000 comprises two primary semiconductor devices: semiconductor device 1006 and semiconductor device 1014. Semiconductor device 1014 is depicted as containing several interfaces and registers for data communication, including a read address register input interconnect 1024. This interconnect 1024 facilitates the delivery of read addresses to a read address register 1026, which temporarily holds these addresses before they are transmitted to corresponding microvaults 1036, 1058 in semiconductor device 1006 for data retrieval operations.

[0188] In semiconductor device 1014, interconnect 1028 serves as a pathway for read addresses from the read address register 1026 to transition to bumpless bonds 1030. Bumpless bonds 1030 and 1032 represent high-density, low-profile electrical connections between semiconductor device 1014 and semiconductor device 1006, ensuring the transmission of read addresses with minimal signal loss and physical space requirements.

[0189] Through interconnect 1034, the received addresses reach the read address register 1038 in semiconductor device 1006, which then directs the microvault 1036 to output the requested read data. Microvault 1036, an memory storage unit, may encompass a variety of memory technologies, such as FeFETs and / or 3D-NAND structures as described herein, to facilitate the storage and rapid retrieval of data.

[0190] The multiplexer 1060 selects the appropriate data stream from multiple microvault 1036, 1058 outputs. Controlled by a counter 1062, which may operate according to a predefined sequence or be driven by external control signals, theAttorney Docket: P25-061-SEC-W001multiplexer 1060 arbitrates between the outputs of microvault 1036 and another microvault, denoted as microvault 1058. Microvault 1058, similar in function and potential memory technology to microvault 1036, provides an additional source of data for the multiplexer 1060 to select from.

[0191] Once the desired data is selected by the multiplexer 1060, it is temporarily stored in a read data register 1042, also located within semiconductor device 1006. This register 1042 acts as a buffer, holding the data for subsequent processing or transmission. The read data is then routed via interconnect 1004 to bumpless bonds 1008, which facilitate the transfer of data to the semiconductor device 1014.

[0192] Bumpless bonds 1010, 1018 facilitate the continued data's journey through the assembly 1000, ensuring data transfer from semiconductor device 1006 to semiconductor device 1014. Once the read data arrives at semiconductor device 1014, it is channeled via interconnect 1048 to a read data register, specifically read data register 1022, where it can be accessed by external systems, such as an applicationspecific integrated circuit (ASIC) or a system-on-chip (SoC), via the read data register output interconnect 1050.

[0193] Additionally, the assembly 1000 encompasses Through-Silicon Vias (TSVs) 1016 and 1044, providing vertical electrical connections through the semiconductor devices 1014 and 1006, respectively. These TSVs enable the stacking of additional semiconductor devices or chiplets atop the assembly 1000, thus allowing for vertical expansion of the system’s capabilities. Interconnects 1012 and 1046 serve as horizontal pathways for signals to travel to and from the TSVs 1016 and 1044, respectively.

[0194] Although the description presents a specific configuration, the assembly 1000 may be subject to various modifications and alternative embodiments. For example, the number and arrangement of microvaults, the specific types of memory technologies employed within the microvaults, and the configuration of interconnects and bonding areas may be tailored to meet the requirements of different applications.

[0195] In some embodiments, the semiconductor devices 1006 and 1014 may be designed to accommodate additional functionality, such as thermal management layers for heat dissipation, hardware-based encryption modules for data security, or power management circuits to optimize energy consumption. The detailed structure of Fig. 10, therefore, serves as a foundation upon which a variety of sophisticatedAttorney Docket: P25-061-SEC-W001semiconductor systems can be constructed, each tailored to the specific needs of its intended application.

[0196] In the configuration of assembly 1000 as depicted in Fig. 10, the microvaults, exemplified by microvaults 1036 and 1058, present a daisy-chaining configuration that allows for an expandable and flexible memory architecture within the semiconductor device 1006. This daisy-chaining is facilitated through a series of interconnected pathways and controlled by the multiplexer 1060 in coordination with the counter 1062.

[0197] Each microvault, such as 1036 and 1058, is designed to hold and provide rapid access to data, which may be in the form of stored charge, magnetic states, ferroelectric material states, or other physical embodiments of binary information. The microvaults are interconnected such that the output of one microvault can be routed to the input of another, creating a chain of memory elements. This is achieved through a series of interconnects, such as interconnect 1034 for microvault 1036 and interconnect 1056 for microvault 1058, which serve as conduits for the read data signals emanating from the microvaults.

[0198] The multiplexer 1060 manages the flow of data from this daisy chain of microvaults. It is designed with multiple inputs, each connected to the output of a micro vault via respective interconnects. In the example provided, interconnect 1040 carries the read data from microvault 1036, and interconnect 1056 carries the read data from microvault 1058 to the multiplexer 1060. The multiplexer 1060 is capable of selecting which input to connect to its output at any given time, thus controlling which microvault's data is forwarded to the read data register 1042.

[0199] The counter 1062 orchestrates the operation of the multiplexer 1060. It may be a binary counter or any form of sequential logic circuit that produces a series of output states in response to a clock signal. The counter 1062 progresses through its states with each tick of the clock, which may be provided by an external clock source or generated internally within the semiconductor device 1006. As the counter 1062 advances, it outputs a control signal that instructs the multiplexer 1060 on which input to select.

[0200] For instance, at the first clock pulse, the counter 1062 may instruct the multiplexer 1060 to connect the output from microvault 1036 to the read data register 1042. At the next clock pulse, the counter may switch the connection to micro vault 1058's output, and so on, cycling through the available microvaults in a predefinedAttorney Docket: P25-061-SEC-W001order. The counter's sequence and timing can be configured based on the desired data access patterns and the specific requirements of the processing tasks at hand.

[0201] This clock-driven coordination allows for an efficient and organized retrieval of data from a potentially large array of microvaults. It ensures that each microvault has an equal opportunity to present its data for processing, and it simplifies the control scheme by reducing it to a predictable, rhythmic progression of states. This is particularly advantageous in systems where a large volume of data must be processed in parallel, as it provides a systematic method for accessing and utilizing the stored information.

[0202] It should be noted that while Fig. 10 illustrates only two microvaults, the described daisy-chaining mechanism can be extended to accommodate any arbitrary number of microvaults. Additional microvaults can be added to the chain, with each new microvault connected to the multiplexer via an additional input line. The multiplexer 1060 and counter 1062 would be scaled accordingly to manage the increased number of inputs, maintaining the same clock-driven, sequential data retrieval process across the expanded memory architecture.

[0203] This daisy-chaining of microvaults, in conjunction with the multiplexing and counter-driven control system, exemplifies a modular and scalable approach to memory design in semiconductor devices. It allows for the customization of memory arrays to match the capacity and performance needs of a wide range of applications, from embedded systems to large-scale data centers, providing a versatile solution for modem computing challenges.

[0204] Fig. 11 shows a semiconductor assembly 1100 incorporating a daisy-chained configuration of microvaults in multiple semiconductor devices 1106, 1116 that are operatively connected to multiplexers and managed by counters for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure.

[0205] The present detailed description relates to Fig. 11 of the accompanying drawings, which illustrates an embodiment of an assembly 1100 as part of an integrated circuit. The assembly 1100 may be seen as a hierarchical stmcture that includes a bottom semiconductor device 1122, a middle semiconductor device 1116, and a top semiconductor device 1106 (each of these may be chiplets). Each semiconductor device is configured to interface with the others through a series of bumpless bonds, such as bumpless bonds 1128, 1129, 1158, 1159, 1160, 1161, 1162, and 1163, which facilitateAttorney Docket: P25-061-SEC-W001electrical connectivity without the added profile of traditional bonding methods, thus enabling a compact and dense stacking of semiconductor layers.

[0206] The bottom semiconductor device 1122 includes a read address register 1126, which may be configured to store and communicate read addresses to microvaults located across the assembly 1100. The read address register 1126 communicates via an interconnect 1174, which serves as a conduit for signals directed to bumpless bonds 1128. These bonds in turn engage with bumpless bonds 1129 of the middle semiconductor device 1116, thus transferring the read addresses into the middle semiconductor device. The bottom semiconductor device 1122 also comprises a read data register 1124, which may serve as a repository for read data received. Read data is received through an interconnect 1176 that connects to bumpless bonds 1158, which are in communication with bumpless bonds 1159 of the middle semiconductor device 1116.

[0207] The middle semiconductor device 1116 serves as an intermediary layer within the assembly 1100, housing microvaults such as microvault 1132 and microvault 1118, each of which may be designed to store and rapidly provide access to data. These microvaults are linked to other components within the device via interconnects, such as interconnect 1130 and interconnect 1134, which guide the flow of read addresses and read data, respectively. The middle semiconductor device 1116 also features a read address register 1146, which receives read addresses from interconnect 1130, and a read data register 1154, which collects read data from TSV 1152.

[0208] The multiplexer 1114, within the middle semiconductor device 1116 selects between various data streams. This multiplexer is controlled by a phase counter 1110, which determines the sequence of data selection based on the input received from the top semiconductor device 1106 via the TSV 1152. The read data register 1112 serves as a holding area for the selected data stream from the multiplexer 1114.

[0209] The top semiconductor device 1106 features a phase counter 1102 and a read data register 1104, which are used for coordinating data flow within the assembly 1100. The phase counter 1102, in conjunction with multiplexer 1150, dictates the output of read data from microvaults 1138 and 1164 based on the selected phase. The read data register 1104 captures the output from the multiplexer 1150, which is then relayed through interconnect 1108 to bumpless bonds 1162, facilitating communication with the middle semiconductor device 1116.Attorney Docket: P25-061-SEC-W001

[0210] The assembly 1100 illustrates the integration of multiple microvaults across different semiconductor devices. For example, the microvault 1132 on the middle semiconductor device 1116 may receive read addresses from read address register 1146 via an interconnect 1134, path "1". Similarly, microvault 1118 may receive read addresses from the same register via an interconnect 1156, path "2".Microvaults 1138 and 1164 on the top semiconductor device 1106 receive read addresses via interconnect 1140 and paths "3" and "4", respectively, from read address register 1 142, which is in communication with the middle semiconductor device 1116 via TSV 1136 and bumpless bonds 1160 and 1161.

[0211] Each microvault, such as 1132, 1118, 1138, and 1164, can potentially output read data to the multiplexer 1114 or 1150, where the data is then selected based on the configuration of the respective phase counter, 1110 or 1102. The selected data is temporarily stored in a read data register, either 1112 or 1104, before being transmitted down the assembly 1100 through the respective bumpless bonds and interconnects, ultimately reaching the read data register 1124 of the bottom semiconductor device 1122. This arrangement allows for a synchronized read-out of data from all microvaults, which may be essential in applications requiring parallel processing and high-speed data access.

[0212] The TSVs, such as 1136 and 1152, provide vertical connectivity across the semiconductor devices, enabling the integration of additional layers or functionalities atop the existing assembly 1100. These TSVs are coupled to various interconnects and bumpless bonds that establish the necessary pathways for signal transmission both within and between the semiconductor devices.

[0213] In some embodiments, the microvaults within the assembly 1100 may include various memory technologies, such as 3D-NAND or 3D-NOR structures, and are arranged to facilitate parallel processing and efficient data retrieval. Each micro vault may include additional features, such as thermal management layers for heat dissipation, hardware-based encryption modules for data security, or power management circuits to optimize energy consumption.

[0214] Datapath 1 within the assembly 1100 exemplifies a route through which read addresses and corresponding read data are transmitted across the assembly, specifically directing operations from the read address register 1126 located on the bottom semiconductor device 1122 to the read data register 1124 within the same device.Attorney Docket: P25-061-SEC-W001

[0215] The process begins with the read address register 1126 holding a specific read address. This address is sent through interconnect 1174, which acts as a channel for the signal. The read address is then transmitted to bumpless bonds 1128, which are meticulously designed to create a reliable electrical connection without the physical protrusion associated with traditional bonding methods. These bonds ensure a low-profile interface that preserves the compactness of the semiconductor stack.

[0216] The signal continues from bumpless bonds 1128 to engage with bumpless bonds 1129 of the middle semiconductor device 1116. The read address is earned forward by interconnect 1130, which delivers the address to the read address register 1146 of the middle semiconductor device. Read address register 1146, in turn, propagates the read address through interconnect 1134, designated as path "1" guiding the signal to the microvault 1132.

[0217] Upon receiving the read address, microvault 1132 accesses the requested data. This data is then outputted through interconnect 1170 and directed to the multiplexer 1114. In some embodiments, multiplexer 1114 functions as a selective switch that chooses between data streams based on the configuration determined by phase counter 1110. This phase counter may be designed to cycle through a sequence that dictates the timing and selection of data streams, ensuring that each microvault is read in a coordinated manner.

[0218] The selected data from multiplexer 1114 is then captured by read data register 1112, which holds the data momentarily. The data is subsequently sent via interconnect 1120, which carries the signal to bumpless bonds 1159. These bonds are part of a sophisticated electrical interconnection system that, along with bumpless bonds 1158 on the bottom semiconductor device 1122, enables vertical and horizontal integration within the semiconductor stack.

[0219] The signal, now in the form of read data, traverses from bumpless bonds 1159 to bumpless bonds 1158 and is finally introduced into interconnect 1176. This interconnect completes the connection to read data register 1124, which is configured to receive and hold the read data. The read data register 1124 may be equipped to retain the data for subsequent processing or external communication.

[0220] Datapath 2 within the assembly 1100 delineates a route specifically designed for the transmission of read addresses from the read address register 1126 on the bottom semiconductor device 1122 to the micro vault 1118 located on the middleAttorney Docket: P25-061-SEC-W001semiconductor device 1116 and the subsequent transfer of read data back to the read data register 1124 on the bottom device.

[0221] The journey commences at the read address register 1126, where a read address is held in preparation for dispatch. This register is an part of the semiconductor device's control mechanism, orchestrating the retrieval of data by issuing specific addresses to the memory units. From the read address register 1126, the read address is sent through the interconnect 1174, which provides a secure and reliable pathway for electrical signals within the integrated circuit.

[0222] The read address continues from the interconnect 1174 to bumpless bonds 1128, which offer a seamless and low-profile connection to the middle semiconductor device 1116 via the corresponding bumpless bonds 1129. These bonds maintain the signal's integrity during inter-layer communication and are designed to accommodate the requirements of modern semiconductor architectures.

[0223] The signal is then channeled via interconnect 1130 to the read address register 1146 within the middle semiconductor device 1116. The read address register 1146 acts as a secondary store and hold register From there, the read address is directed down interconnect 1156, labeled as path "2," which terminates at the microvault 1118.

[0224] Upon receipt of the read address, microvault 1118 accesses the corresponding data. This data retrieval process is facilitated by the microvault's internal architecture, which may comprise an array of memory cells optimized for rapid access and data stability. The read data is outputted from microvault 1118 and travels through interconnect 1172, which leads to the multiplexer 1114.

[0225] Multiplexer 1114 determines which data stream to forward based on input from the phase counter 1110. The phase counter 1110 operates in synchronization with the system clock or an external control signal, cycling through various states to control the selection process of the multiplexer 1114 in a precise and predictable manner.

[0226] The output of the multiplexer 1114, now carrying the selected read data, is conveyed to read data register 1112. This register temporarily stores the read data, acting as a buffer. The read data is then dispatched via interconnect 1120 towards bumpless bonds 1159.

[0227] Bumpless bonds 1159 form the interface with bumpless bonds 1158 on the bottom semiconductor device 1122, where the signal is transmitted downward through the assembly. The read data then traverses the interconnect 1176 to reach itsAttorney Docket: P25-061-SEC-W001final destination, the read data register 1124. The read data register 1124 captures the read data, holding it in readiness for further processing or transmission to external circuits.

[0228] Datapath 3 within the assembly 1100 is another communication route that illustrates the data transfer sequence from the read address register 1126 on the bottom semiconductor device 1122, through various components, ultimately to the microvault 1138 on the top semiconductor device 1106, and then back to the read data register 1124 on the bottom device.

[0229] The sequence initiates at the read address register 1126, which serves as the origin point for read addresses. The register 1126 securely holds the address before it is dispatched through the interconnect 1174. Interconnect 1174 acts as a dedicated channel, ensuring that the read address is conveyed with precision to the bumpless bonds 1128. These bumpless bonds 1128 facilitate a streamlined connection to the bumpless bonds 1129 of the middle semiconductor device 1116, preserving the integrity and compactness of the signal pathway.

[0230] Upon reaching the middle semiconductor device 1116, the read address is relayed through interconnect 1130 to the read address register 1146. The read address register 1146 acts as a juncture that further propagates the address signal through the Through-Silicon Via (TSV) 1136. The TSV 1136 is a vertical interconnect that pierces through the semiconductor substrate, providing a direct link from the middle semiconductor device 1116 to the top semiconductor device 1106, thus exemplifying the 3D integration capabilities of semiconductor design.

[0231] The read address ascends from TSV 1136 and emerges onto bumpless bonds 1160 on the middle semiconductor device 1116. The bumpless bonds 1160 are connected to the bumpless bonds 1161 of the top semiconductor device 1106. The address signal is conducted through interconnect 1140 to the read address register 1142 on the top device 1106.

[0232] The read address register 1142, upon receiving the read address, directs the signal along interconnect 1144. This path, denoted as "3," leads the address to the microvault 1138. Microvault 1138, designed for data storage, retrieves the requested information in response to the read address. The read data is outputted through interconnect 1166, which feeds the data into the multiplexer 1150.

[0233] The multiplexer 1150 in the top semiconductor device 1106 is governed by the phase counter 1102, which dictates the selection of the data stream to beAttorney Docket: P25-061-SEC-W001channeled to the read data register 1104. The chosen data stream is temporarily housed in the read data register 1104, where it awaits downstream transmission.

[0234] The read data departs from the read data register 1104 via interconnect 1108, which connects to bumpless bonds 1162. These bonds 1162 engage with the corresponding bumpless bonds 1163 on the middle semiconductor device 1116, transferring the read data to TSV 1152.

[0235] TSV 1152 operates as a vertical conduit, allowing the read data to traverse down into the middle semiconductor device 11 16, where it is received by the read data register 1154. The read data register 1154 holds the read data momentarily before it is directed to the multiplexer 1114 through interconnect 1156.

[0236] The multiplexer 1114 in the middle semiconductor device 1116, coordinated by the phase counter 1110, selects the appropriate data for output. The read data is then channeled to the read data register 1112, where it is briefly stored.Following this, the read data travels via interconnect 1120 to bumpless bonds 1159.

[0237] The bumpless bonds 1159 form an interface with bumpless bonds 1158 on the bottom semiconductor device 1122. The read data signal is then carried through interconnect 1176, culminating its journey at the read data register 1124 on the bottom device.

[0238] Datapath 4 within the assembly 1100 is a path that establishes the flow of read addresses from the read address register 1126 on the bottom semiconductor device 1122 to the microvault 1164 located on the top semiconductor device 1106, and subsequently facilitates the movement of read data back down to the read data register 1124 on the bottom device.

[0239] This datapath begins at the read address register 1126, which is responsible for holding and issuing the read addresses necessary for data retrieval from the microvaults. The read address is sent from the register 1126 through interconnect 1174, a pathway that maintains signal integrity and facilitates electrical communication.

[0240] From interconnect 1174, the read address is directed to bumpless bonds 1128. These bonding areas create an interconnection between the bottom semiconductor device 1122 and the middle semiconductor device 1116 through bumpless bonds 1129. The design of these bumpless bonds facilitates data transmission.

[0241] Once the read address reaches the middle semiconductor device 1116, it is carried forward by interconnect 1130 to the read address register 1146. This register acts as an intermediary, preparing the address for its vertical ascent through the deviceAttorney Docket: P25-061-SEC-W001stack. The address is then transmitted via the Through-Silicon Via (TSV) 1136 that facilitates vertical integration by providing a direct electrical link through the semiconductor substrate.

[0242] After ascending through TSV 1136, the read address emerges onto bumpless bonds 1160, which are aligned to connect with bumpless bonds 1161 on the top semiconductor device 1106. The read address then proceeds along interconnect 1140 to the read address register 1142 located on the top device.

[0243] The read address register 1142 serves to forward the read address to its final destination, the microvault 1164, through interconnect 1148, labeled as path "4".Microvault 1164, upon receiving the read address, retrieves the requested data, which is then outputted through interconnect 1168. This data is directed to the multiplexer 1150, which is under the control of phase counter 1102.

[0244] The phase counter 1102 determines which data stream is selected by the multiplexer 1150, which then sends the read data to the read data register 1104. The read data register 1104 acts as a temporary repository, holding the data until it can be sent downwards through the device stack.

[0245] The data leaves the read data register 1104 and travels via interconnect 1108 to bumpless bonds 1162. These bonds maintain a connection to bumpless bonds 1163 on the middle semiconductor device 1116. The read data is then transferred to TSV 1152, which carries the data vertically down to the read data register 1154 on the middle semiconductor device 1116.

[0246] The read data register 1154 temporarily holds the read data before it is fed into the multiplexer 1114 via interconnect 1156. The multiplexer 1114, coordinated by the phase counter 1110, channels the appropriate data stream to the read data register 1112. This register serves as a staging area for the read data, which is then sent through interconnect 1120 to bumpless bonds 1159.

[0247] Bumpless bonds 1159 interface with bumpless bonds 1158 on the bottom semiconductor device 1122 to provide a downward transmission of the read data. Finally, the signal is routed through interconnect 1176 and arrives at read data register 1124, where the data is made available for subsequent processing or external communication.

[0248] Fig. 12 illustrates a three-dimensional (3D) memory column 1200 configured as a 3D-NOR or 3D-AND structure, featuring a series of ferroelectric fieldeffect transistors (FeFETs) 1202 with interconnected drain terminals 1204 linked to aAttorney Docket: P25-061-SEC-W001common select line 1212 and individual gate terminals 1206 connected to respective read / write enable lines 1214 (e.g., 1214a for FeFET 1202a, all coupled to a common bit line, in accordance with an embodiment of the present disclosure.

[0249] Thus, Fig. 12 depicts a three-dimensional (3D) memory column, designated as element 1200, which can be configured in various embodiments as either a 3D-NOR or 3D-AND structure, providing flexibility in the application and use of the integrated circuit. This memory column is an assembly of multiple ferroelectric fieldeffect transistors (FeFETs), collectively referred to as fefets 1202, where each FeFET is indicated by elements such as 1202a, 1202b, 1202c, and 1202d, among others potentially present in the array.

[0250] Within each FeFET, such as 1202a, there is a drain terminal 1204a. This drain terminal is part of the memory cell's output path and is connected to a common select line 1212. In some embodiments, the common select line 1212 serves as a control mechanism that enables the selection of a particular FeFET for data read or write operations.

[0251] The gate terminal of each FeFET, exemplified by 1206a for FeFET 1202a, is individually connected to a respective read / write enable line, such as 1214a.This enables control of the FeFET's state, allowing it to be in a conductive (on) state for reading or writing data or in a non-conductive (off) state to prevent data flow. The presence of individual read / write lines for each FeFET may allow for precise control and operation of each memory cell.

[0252] Moreover, each FeFET, such as 1202a, comprises a source terminal, such as 1208a, which is coupled to a common bit line 1210. The bit line 1210 provides a conduit for data being written to or read from the FeFETs. In some embodiments, this bit line can be shared across multiple memory columns, which can facilitate parallel processing and increased data throughput.

[0253] In accordance with various embodiments of the present disclosure, the 3D memory column 1200 may incorporate additional elements and configurations to enhance performance and functionality. For instance, the 3D memory column 1200 may include insulating materials, conductive pathways, and other structural components not explicitly shown in Fig. 12 but which are inherent to the implementation of such 3D memory structures. The FeFETs 1202 may also exhibit variations in terms of material composition, structural dimensions, and electrical properties, contributing to a range of performance characteristics suitable for different applications.Attorney Docket: P25-061-SEC-W001

[0254] Furthermore, the memory column 1200 may be incorporated into larger memory arrays, forming part of a memory module or system. These arrays can be arranged in various configurations, such as rows and columns, to create a matrix that efficiently addresses the demands of high-density data storage. The memory column 1200 can also be interfaced with other circuit elements and control logic, which may govern the operation of the memory array, including data management protocols, error correction algorithms, and power optimization strategies.

[0255] In some embodiments, the memory column 1200 may be fabricated using advanced semiconductor manufacturing techniques, such as photolithography, etching, deposition, and planarization processes. The choice of materials for the FeFETs, including the ferroelectric material, the semiconductor channel, and the conductive elements, can be selected based on desired electrical characteristics, such as charge retention, switching speed, and energy efficiency.

[0256] The 3D memory column 1200, as illustrated in Fig. 12, may include FeFETs, such as 1202, fabricated from a variety of materials that provide the necessary electrical and physical properties to achieve the desired functionality. For instance, in some embodiments, the channel layer of each FeFET in the FeFETs 1202 could be constructed from materials such as Indium Gallium Zinc Oxide (IGZO) or other Amorphous Oxide Semiconductors (AOS) like Zinc Tin Oxide or Indium Tungsten Oxide (IWO). These materials are selected fortheir electronic properties, such as carrier mobility and stability.

[0257] The ferroelectric material rigidly coupled to the channel layer in each FeFET may comprise hafnium zirconium oxide (HfZrO2) or other transition metal oxides, perovskites, etc. These ferroelectric materials are chosen for their ability to maintain a polarization state when an electric field is applied, which is used for the nonvolatile memory characteristics of the FeFETs. The thickness, crystalline structure, and stoichiometry of the ferroelectric layer can be controlled to achieve the desired coercive voltage, remanent polarization, and other electrical parameters for reliable data storage and retrieval.

[0258] The drain 1204 and source 1208 terminals of the FeFETs 1202 are connected to the common select line 1212 and common bit line 1210, respectively.These common lines may be formed from conductive materials such as tungsten, titanium nitride, or other metals and metal alloys that provide low-resistance pathways for electrical signals. The configuration of these terminals and their respective commonAttorney Docket: P25-061-SEC-W001lines ensures that the FeFETs can be accessed and controlled effectively during operation.

[0259] Each gate terminal, such as the gate 1206 of the FeFET 1202a, is connected to its respective read / write enable line, such as 1214a. The gate terminals are help control the state of the FeFET, and the materials chosen for these terminals may include various conductive materials that can provide a reliable electrical interface with the ferroelectric material. The read / write enable 1214 lines are designed to deliver suitable voltage levels to the gates 1206 of the FeFETs 1202 for switching between states.

[0260] The memory column 1200 as a whole is designed to support a range of operating parameters. In some embodiments, these parameters may include, but are not limited to, an off-state current of less than 10A-8 amps per centimeter cubed, an on-state current greater than 10 -7 amps per centimeter cubed, and a channel mobility that is maintained despite the presence of the ferroelectric layer. The channel layer's thickness can be less than 30 nm to ensure high device density, while the ferroelectric layer's characteristics, such as coercive voltage and remanent polarization, are optimized to provide the necessary memory functionality.

[0261] In some embodiments, the FeFETs 1202 may include additional materials or dopants to enhance their electrical properties. For instance, dopants such as gallium (Ga), indium (In), or zinc (Zn) may be introduced into the channel layer to modulate the carrier concentration or to adjust the threshold voltage of the FeFETs.Similarly, the ferroelectric layer may include dopants like lanthanum (La) or niobium (Nb) to adjust its ferroelectric properties.

[0262] In other embodiments, the 3D memory column 1200 may be integrated with additional semiconductor devices and structures to form complex memory systems. These systems can provide storage capabilities and support various memory architectures.

[0263] Fig. 13 depicts a three-dimensional (3D) memory column 1300 configured as a 3D-NAND structure, consisting of a vertical stack of ferroelectric fieldeffect transistors (FeFETs) 1302, each with source 1304 and drain 1308 terminals. The source 1304 of each FeFET, such as 1304a for FeFET 1302a, is coupled to the start of a bit line 1310 or connected to the drain of the preceding FeFET, exemplified by source 1304b of FeFET 1302b coupled to drain 1308a of FeFET 1302a. Each FeFET includes a gate 1306, such as 1306a for FeFET 1302a, connected to a respective read / writeAttorney Docket: P25-061-SEC-W001enable line, illustrated by 1314a for FeFET 1302a, in accordance with an embodiment of the present disclosure.

[0264] The 3D memory column 1300 is composed of a series of vertically stacked Field-Effect Transistors (FeFETs), identified collectively as FeFETs 1302.These transistors, which include FeFETs 1302a, 1302b, 1302c, 1302d, and so on, are characterized by their incorporation of ferroelectric materials within their gate structure. Each FeFET in the series is of the memory column contributes to the memory storage capabilities of the device.

[0265] In the depicted embodiment, each FeFET, such as FeFET 1302a, includes a source terminal 1304, for instance, source 1304a, which is coupled to a bit line 1310. The bit line 1310 serves as a conduit for electrical signals that are used to read from and write to the memory cell associated with FeFET 1302a. In scenarios where FeFET 1302a is not the bottom-most transistor in the column, its source 1304b may be connected to the drain 1308a of the immediately preceding FeFET, such as FeFET 1302a, facilitating a serial connection that defines the vertical NAND architecture.

[0266] Each FeFET within the FeFETs 1302 is further equipped with a gate terminal 1306, exemplified by gate 1306a for FeFET 1302a. This gate terminal 1306 is coupled to a respective read / write enable line, exemplified by 1314a for FeFET 1302a.The read / write enable line 1314a is responsible for controlling the state of the FeFET, allowing it to either conduct or prevent the flow of current through the device, thereby enabling the writing or reading of data.

[0267] Moreover, each FeFET of the FeFETs 1302 also includes a drain terminal 1308, such as drain 1308a for FeFET 1302a, which is typically connected to the source of the subsequent FeFET in the vertical stack. This arrangement ensures that the charge stored in the ferroelectric material of the gate can modulate the cun-ent flowing from the source to the drain, allowing for the storage and retrieval of data.

[0268] The memory column 1300 within Fig. 13 is indicative of a memory architecture that can be utilized in various applications, from portable electronics to enterprise-level data storage systems. In some embodiments, the ferroelectric material used in the FeFETs may include various compositions, such as hafnium oxide, zirconium oxide, or any combination thereof, which can be doped with elements such as lanthanum or yttrium to adjust the ferroelectric properties as required.Attorney Docket: P25-061-SEC-W001

[0269] In some variations, the 3D memory column 1300 can incorporate additional features that enhance performance, reliability, or manufacturability. For instance, the FeFETs 1302 may include protective layers to shield the ferroelectric material from environmental factors or process-induced damage. The column 1300 may also be integrated with other circuit elements, such as capacitors or diodes, to facilitate operations like charge pumping or to provide additional functionality within the memory array.

[0270] The 3D memory column 1300 may be fabricated from a variety of materials that confer specific electrical properties to enhance device performance. In some embodiments, the channel layer of each FeFET may be formed from materials such as Indium Gallium Zinc Oxide (IGZO). Other materials for the channel layer could include Amorphous Oxide Semiconductors (AOS) like Zinc Tin Oxide or Aluminum Zinc Oxide.

[0271] The ferroelectric layer within the FeFETs 1302 may comprise materials such as Hafnium Zirconium Oxide (HfZrO2). The ferroelectric layer's thickness and material composition can be controlled through methods like Atomic Layer Deposition (ALD) to achieve the desired coercive voltages, remanent polarizations, and endurance characteristics. In some implementations, the coercive voltage of the ferroelectric layer may be tuned to be between -3 Volts to +3 Volts, facilitating low-voltage operation of the memory devices.

[0272] The source and drain terminals of the FeFETs 1302 may be composed of conductive materials such as Tungsten or Titanium Nitride. These materials may also be selected to optimize the contact resistance with the channel layer, reducing overall power consumption and improving the lon / Ioff ratio of the device.

[0273] Additionally, the FeFETs 1302 may be engineered to exhibit specific electrical parameters. For instance, the channel layer’s thickness may be less than 30 nm in some embodiments. In some embodiments, the channel layer may demonstrate a carrier concentration of 10 17 to 10A20 per centimeter-cubed, which can be adjusted through doping with elements such as Gallium, Indium, or Zinc to modulate the electrical properties.

[0274] The memory cells formed by the FeFETs 1302 within the 3D memory column 1300 may also target operational parameters such as read and write latencies, endurance, and energy consumption. For example, read and write operations may be executed with energies less than 10 picojoules and within timeframes less than 20Attorney Docket: P25-061-SEC-W001nanoseconds, contributing to the low power and high-speed attributes of the memory column.

[0275] Furthermore, the 3D-NAND configuration of the memory column 1300 may be designed to achieve a high off-state resistance to on-state resistance ratio (Roff / Ron), which is used for distinguishing between different data states and ensuring reliable data retention. This ratio may be about 10A3 or greater, which helps to maintain a high signal-to-noise ratio during memory operations.

[0276] The FeFETs 1302 in the memory column 1300 may also be designed to sustain a high degree of reliability, with endurance ratings greater than or equal to 10Al 1 cycles, ensuring the longevity and durability of the memory device. This endurance is complemented by the ferroelectric layer's ability to maintain data retention for at least 1 minute at room temperature, which is 25 °C.

[0277] Fig. 14 depicts a three-dimensional (3D) memory column configured as a 3D-NAND with an integrated pass gate, in accordance with an embodiment of the present disclosure. This figure illustrates a series of ferroelectric field-effect transistors (FeFETs) 1402, each including source 1404 and drain 1408 terminals, gated by respective gate terminals 1406 and coupled to read / write enable lines 1414. The FeFETs are interconnected, forming a vertical memory structure with pass gates 1418 linked to a pass gate line 1416.

[0278] Thus, Fig. 14 illustrates a three-dimensional (3D) memory column, designated as element 1400, which can be configured as a 3D-NAND structure with an integrated pass gate. This configuration enables enhanced control over individual memory cells within the 3D structure, potentially improving read / write operations and facilitating efficient memory management.

[0279] In detail, the 3D memory column 1400 comprises multiple ferroelectric field-effect transistors (FeFETs), collectively referred to as FeFETs 1402. Each FeFET within the 1402 series, such as 1402a, 1402b, 1402c, 1402d, etc., is a constituent memory cell of the 3D memory column 1400. These FeFETs are utilized for their ability to retain data in a non-volatile manner due to the ferroelectric properties of their gate material, which allows for data retention without continuous power supply for a time.

[0280] Each FeFET in the series 1402 includes a source, exemplified by source 1404a for FeFET 1402a. The source 1404 for each FeFET is either coupled to a bit line, illustrated as bit line 1410 for FeFET 1402a, or is connected to the drain of the preceding FeFET in the series. For instance, source 1404b of FeFET 1402b isAttorney Docket: P25-061-SEC-W001electrically coupled to drain 1408a of FeFET 1402a. This serial connection forms the basis for the daisy-chain configuration, which is used in NAND architectures, allowing for sequential access to the array of FeFETs.

[0281] Furthermore, each FeFET within the FeFETs 1402 is equipped with a gate terminal, such as gate 1406a for FeFET 1402a. The gates of the FeFETs are connected to their respective read / write enable lines, which are depicted as element 1414 in the figure. For example, gate 1406a of FeFET 1402a is influenced by read / write enable line 1414a. These enable lines control the application of appropriate voltages for the reading and writing of data.

[0282] Additionally, each FeFET in the FeFETs 1402 series includes a drain, such as drain 1408a for FeFET 1402a. This drain is connected to the source of the subsequent FeFET in the series, thus establishing the continuity for the columnar structure of the 3D memory stack.

[0283] In some embodiments, each FeFET of the FeFETs 1402 incorporates a pass gate, for example, pass gate 1418a, which is connected to a pass gate line, represented by 1416 in the figure. The pass gate line 1416 is a conductive pathway that provides electrical signals to control the pass gates 1418 of the FeFETs. The inclusion of pass gates in the FeFETs may allow for improved isolation between memory cells during operation, thereby reducing interference and potentially enhancing the reliability of data storage and retrieval.

[0284] The 3D memory column 1400, as depicted in Fig. 14 also encompasses a diverse range of materials and parameters that could be utilized to optimize its performance in various embodiments. Each FeFET 1402 within the column could be fabricated using a variety of semiconductor materials. For instance, the channel layer of the FeFETs could be formed from materials such as Indium Gallium Zinc Oxide (IGZO).

[0285] The ferroelectric layer, which is a defining characteristic of the FeFETs, may be composed of materials like Hafnium Zirconium Oxide (HfZrO2) or other perovskite materials, which are known for their remanent polarization. This property determines the data retention capabilities of the FeFETs. The coercive voltage of this layer, which affects the energy required to switch the polarization state, is another critical parameter that can be adjusted according to the requirements of the specific application, with a range in one embodiment being between -3 Volts to 3 Volts.Attorney Docket: P25-061-SEC-W001

[0286] The source and drain terminals of the FeFETs, which include elements 1404 and 1408, respectively, could be composed of conductive materials such as Tungsten or Titanium Nitride. These materials provide pathways for current flow, which is for switching. The read / write enable lines 1414, which control the gates 1406 of the FeFETs, could also be fabricated from similar materials, ensuring consistent electrical characteristics throughout the device.

[0287] In terms of the physical parameters, the channel layer thickness may be less than 30 nm in thickness. The electron mobility within these channel layers may be maintained at a predetermined level even when the layer is less than 30nm in thickness

[0288] The pass gates 1418 may be manufactured using low-resistance materials to enable quick switching times, which is beneficial when the memory column is accessed frequently during operation.

[0289] Fig. 15 illustrates a three-dimensional (3D) memory column 1500, which may be configured as either a 3D-NOR or a 3D-AND structure with independent Read / Write enable capabilities, in accordance with an embodiment of the present disclosure. This memory column encompasses a series of vertically aligned FeFETs 1502, such as FeFETs 1502a, 1502b, 1502c, 1502d, and so forth, each integrated with a source 1504 (e.g., source 1504a for FeFET 1502a) linked to a respective read enable line 1520 (e.g., read enable line 1520a for FeFET 1502a), and a gate 1506 (e.g., gate 1506a for FeFET 1502a) connected to a corresponding write enable line 1522 (e.g., write enable line 1522a for FeFET 1502a). All FeFETs within the column share a common bit line 1510 connected to their drains 1508, enabling the column to perform coordinated memory operations.

[0290] Fig. 15 presents a detailed depiction of a three-dimensional (3D) memory column 1500, which can be configured as a 3D-NOR or 3D-AND structure with independent Read / Write enable functionalities. This memory column is an assembly of Field-Effect Transistors with ferroelectric gate layers, commonly referred to as FeFETs 1502, which are individually identified, for example, as 1502a, 1502b, 1502c, 1502d, etc., each representing a memory cell within the column.

[0291] In the illustrated embodiment, each FeFET 1502 includes a source 1504, such as source 1504a corresponding to FeFET 1502a. The source 1504 is designed to be electrically coupled to a respective read enable line 1520, such as read enable line 1520a which is dedicated to FeFET 1502a. The read enable line 1520 functions toAttorney Docket: P25-061-SEC-W001selectively activate the FeFET 1502 for reading operations, allowing the readout of stored data from the memory cell.

[0292] Additionally, each FeFET 1502 is equipped with a gate 1506, exemplified by gate 1506a for FeFET 1502a. The gate 1506 is connected to a respective write enable line 1522, such as write enable line 1522a, which is specific to FeFET 1502a. The write enable line 1522 serves to selectively activate the FeFET 1502 for writing operations, enabling the storage of data within the memory cell.

[0293] Furthermore, each FeFET 1502 includes a drain 1508, for instance, drain 1508a affiliated with FeFET 1502a. The drain 1508 is connected to a common bit line 1510. The bit line 1510 acts as a conduit for transferring data to and from the memory cells during read and write operations. The commonality of the bit line 1510 across multiple FeFETs 1502 signifies that data from any activated memory cell can be routed through this shared path.

[0294] In some embodiments of the memory column 1500, the configuration of the FeFETs 1502 allows for a high density of memory cells vertically stacked within a compact footprint.

[0295] The ferroelectric material utilized in the gate 1506 of the FeFETs 1502 may comprise various compositions, such as hafnium oxide-based materials, which can be deposited using atomic layer deposition techniques. The ferroelectric property of the material allows for data retention, enabling the memory cells to maintain stored information even when power is not supplied.

[0296] The source 1504, gate 1506, and drain 1508 of each FeFET 1502 can be fabricated from materials that provide predetermined electrical performance. These materials may include metals such as tungsten or copper, or metal nitrides such as titanium nitride.

[0297] The read enable lines 1520 and write enable lines 1522 can be designed to minimize crosstalk and interference between adjacent lines, in some embodiments.In some specific embodiments, shielding layers or insulating materials may be included to further isolate the signal paths.

[0298] Furthermore, the described memory column 1500 may be integrated within a larger semiconductor device, such as a processor or a storage module. It may form part of a system-on-chip (SoC) or be included in a multi-chip module (MCM), contributing to a data storage and retrieval system.Attorney Docket: P25-061-SEC-W001

[0299] The materials that constitute the FeFETs 1502 within the memory column 1500 are selected to provide specific electrical and physical properties to optimize the performance of the integrated circuit. For instance, the channel layer in each FeFET may be formed from advanced semiconductor materials, such as Indium Gallium Zinc Oxide (IGZO) or other Amorphous Oxide Semiconductors (AOS) like Zinc Tin Oxide or Cadmium Oxide. These materials are chosen for their excellent electron mobility characteristics and stability.

[0300] The ferroelectric layer, integral to the FeFETs 1502, may be fabricated from various ferroelectric materials that exhibit suitable polarization properties.Materials such as Hafnium Zirconium Oxide (HfZrO2) or Lead Zirconate Titanate (PZT) could be utilized. These materials can be doped with elements such as Lanthanum, Yttrium, or other suitable dopants to modify their ferroelectric properties, such as coercive voltage, remanent polarization, and crystallization temperature. The ferroelectric layer's thickness and material composition may be adjusted to achieve desired memory characteristics, such as write endurance and retention time, while ensuring the layer remains compatible with the overall semiconductor manufacturing process, or other considerations, etc.

[0301] The source 1504, gate 1506, and drain 1508 terminals of the FeFETs 1502 may be composed of conductive materials like Tungsten, Titanium Nitride, Nickel, or Molybdenum. Connections to the read enable lines 1520 and the write enable lines 1522 may be facilitated through conductive vias or contacts.

[0302] The read enable lines 1520 and write enable lines 1522, along with the common bit line 1510, may be patterned using lithographic techniques to achieve the predetermined precision and alignment for proper functionality. These lines may be insulated from one another using dielectric materials like Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), or low-k dielectrics to reduce parasitic capacitance and crosstalk.

[0303] Each element within the memory column 1500 may consider factors such as line width, spacing, and aspect ratio to ensure manufacturability, functionality, and / or other goals or characteristics. The materials and processes used in the construction of the memory column 1500 are chosen to ensure compatibility with standard semiconductor fabrication techniques, such as photolithography, etching, deposition, and annealing, while also enabling the integration of materials and structures.Attorney Docket: P25-061-SEC-W001

[0304] The fabrication of the FeFETs 1502 within the memory column 1500 may involve deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) to create uniform and / or non-uniform layers.

[0305] Fig. 16 presents a cross-sectional view of a 3D memory structure, designated as 1600, configured as a single -port 3D NAND, in accordance with an embodiment of the present disclosure. The structure includes a first vertical structure 1608a and a second identical vertical structure 1608b, each comprising a dielectric column 1610a, 1610b, a channel column 1612a, 1612b disposed around the dielectric column, and a ferroelectric column 1614a, 1614b disposed around the channel column.A series of horizontal gate-electrode layers 1606a-c are disposed at predetermined distances from each other, adjacent to the ferroelectric column along the length of the vertical structures. The assembly further includes a drain select layer 1602 and a source select layer 1604, with respective end dielectric columns 1618a, 1618b, and 1616a, 1616b positioned at the interfaces with the vertical structures, illustrating a detailed and intricate design for high-density data storage.

[0306] Thus, Fig. 16 provides a cross-sectional view of a three-dimensional (3D) memory structure, designated as 1600, which is configured as a single -port 3D NAND architecture. This structure incorporates a pair of vertical structures, 1608a and 1608b, which may be fabricated to be substantially identical, as indicated by their respective subscripts a and b, suggesting the potential for a modular and scalable memory array design.

[0307] Each vertical structure, exemplified by the first vertical structure 1608a, includes a dielectric column 1610a. The dielectric column may adopt various geometric forms — it can be cylindrical, substantially cylindrical, or feature curves. Additionally, it may present a tapered form, having different diameters at each end, implying a design that narrows towards the top. Both solid and hollow configurations of the dielectric column are contemplated within the scope of the disclosure, offering design flexibility for different electrical and structural requirements.

[0308] Surrounding the dielectric column 1610a is a channel column 1612a, which is the locus for charge earners during device operation. The channel column is also described as potentially cylindrical, substantially cylindrical, or feature curves and / or and may exhibit similar variations in diameter along its length as the dielectric column.Attorney Docket: P25-061-SEC-W001

[0309] Enveloping the channel column 1612a is a ferroelectric column 1614a, which extends along the length of the channel column but may recede at the ends, thereby meaning the ferroelectric column 1614 does not extend the entire length of the channel column 1612a.

[0310] Intersecting with the vertical structures is a series of horizontal gateelectrode layers, 1606a-c, which are positioned at predetermined distances from one another. These layers play a role in controlling the operational states of the device by influencing the electric field within the ferroelectric column.

[0311] Atop the 3D memory structure 1600 sits a drain select layer 1602, parallel to the horizontal gate-electrode layers 1606. Where the drain select layer 1602 meets the vertical structures 1608a, 1608b, end dielectric columns, 1618a and 1618b, are discernible. These end dielectric columns 1618 interface with the channel column 1612 and the drain select layer 1602, contributing to the isolation and control of the charge carriers within the channel column. They may contact the ferroelectric layer 1614, as they envelop the channel column 1612 at different positions along its length.

[0312] Similarly, a source select layer 1604 is situated at the bottom of the structure 1600, again parallel to the horizontal gate-electrode layers 1606.Corresponding end dielectric columns, 1616a and 1616b, are present where the source select layer 1604 interfaces with the vertical structures, serving analogous functions to the end dielectric columns 1618 near the drain select layer 1602.

[0313] The horizontal gate -electrode 1606 layers could be constructed from a range of conductive materials, including metals and metal compounds, which may offer different work functions, conductivity, and compatibility with other materials in the structure. Similarly, the ferroelectric column 1614 might incorporate a variety of ferroelectric materials each with its unique polarization characteristics, coercive fields, and dielectric constants, affecting the device's memory retention and switching behaviors.

[0314] The channel column 1612 materials can be chosen based on their electronic properties, such as carrier mobility and bandgap, to achieve the desired levels of on-state and off-state current. The dielectric column 1610 provides the electrical insulation necessary to prevent leakage currents and ensure the proper functioning of the device.

[0315] The dielectric column, such as 1610a for the first vertical structure, may be constructed from materials that offer insulating properties to mitigate any potentialAttorney Docket: P25-061-SEC-W001leakage currents. Choices for the dielectric material may be Hafnium Oxide (HfO2) or Silicon Dioxide (SiO2).

[0316] Surrounding the dielectric column, the channel column (1612a) has channel material can be selected from a wide range of semiconducting materials that offer predetermined carrier mobility. For example, Indium Gallium Zinc Oxide (IGZO) can be used for its electrical properties. The channel layer's thickness may vary, with some embodiments considering a thickness less than 30 nm. This thickness is chosen to achieve a predetermined electrical performance. The ferroelectric column, like 1614a, may include perovskite structures, such as Lead Zirconate Titanate (PZT).

[0317] The horizontal gate-electrode layers, represented by 1606a-c, are composed of conductive materials that facilitate the application of an electric field to the ferroelectric column, such as Tungsten or Titanium Nitride, which may be chosen for their electrical behavior. The selection of gate-electrode materials also takes into consideration factors such as work function, thermal stability, and ease of integration with the existing semiconductor manufacturing processes.

[0318] The drain and source select layers, 1602 and 1604 respectively, are incorporated to enable the addressing of individual memory cells within the array. The materials used for these layers are chosen for their conductive properties and compatibility with the channel and ferroelectric materials. The design of these layers may also incorporate considerations for reducing parasitic capacitance and ensuring swift data access.

[0319] The end dielectric columns, like 1618a and 1616a, provide electrical insulation at the ends of the channel column, where the ferroelectric material does not extend.

[0320] The disclosed embodiments within the 3D memory structure 1600 outline an assembly capable of providing data storage. The design allows for variations in structural dimensions, such as the diameter of the cylindrical columns, which can be uniform or tapered. Additionally, the option for solid or hollow configurations may be used.

[0321] Fig. 17 shows a 3D memory structure that is a dual-port 3D NAND arrangement in accordance with an embodiment of the present disclosure. The three-dimensional (3D) memory structure illustrated in Fig. 17, referred to as 3D memory structure 1700, exemplifies a dual-port 3D NAND arrangement to provide a memory functionality. This structure is characterized by two primary vertical formations,Attorney Docket: P25-061-SEC-W001designated as the first vertical structure 1708a and the second vertical structure 1708b, which may be identical or near identical, as evidenced by the designating subscripts ‘a’ and ‘b’.

[0322] The first vertical structure 1708a includes a hollow or solid, tapered pass-gate electrode column 1718a that is substantially cylindrical in shape. The passgate electrode column 1718a may be made of titanium nitride and may have a larger diameter at the bottom end compared to the top end.

[0323] Surrounding the pass-gate electrode column 1718a is a dielectric column 1710a that may be made of hafnium oxide. The dielectric column 1710a is also substantially cylindrical with a slightly tapered shape, having a marginally larger diameter at the top. The dielectric column 1710a provides electrical isolation between the pass-gate electrode and subsequent layers.

[0324] Disposed around the dielectric column 1710a is a cylindrical channel column 1712a that may be made of IGZO semiconductor material. The channel column 1712a features curves along its length and has a uniform diameter throughout. The thickness of the channel column may be less than 30 nm.

[0325] Enclosing the channel column 1712a is a PZT ferroelectric column 1714a that covers most of the length of the channel column 1712a but recedes at the ends, leaving a portion of the channel column 1712a uncovered. The ferroelectric column 1714a is substantially cylindrical and contains lead, zirconium and titanium as key elemental constituents.

[0326] The vertical structures 1708a and 1708b traverse through several horizontal gate-electrode layers 1706a, 1706b and 1706c that may be made of tungsten, which are positioned at fixed intervals to form an interconnected grid layout. These layers influence the electric field within the ferroelectric column 1714a during memory operations.

[0327] At the top of the memory structure 1700, a drain select layer 1702 (e.g., titanium nitride ) runs parallel to the horizontal gate-electrode layers 1706. Where the drain select layer 1702 intersects the vertical structures 1708a and 1708b, end dielectric columns 1718a and 1718b are visible. These end columns (e.g., made of HfO2 ) touch the ferroelectric column 1714a on one end and surround the uncovered portion of channel column 1712a, providing insulation.

[0328] Similarly at the bottom of the structure 1700, a source select layer 1704 (e.g., made of tungsten), also parallel to the electrode layers 1706, interfaces with theAttorney Docket: P25-061-SEC-W001vertical structures. End dielectric columns 1716a and 1716b can be observed at these intersection points, enclosing the open ends of the channel columns 1712a and 1712b.

[0329] Within the hollow region of the pass-gate electrode columns 1718a and 1718b at the ends, a thin dielectric horizontal layers 1720a and 1720b may be placed near the bottom terminals (e.g., HfO2). These layers seal off the bottom open ends of the vertical hollow voids.

[0330] Fig. 18 illustrates a 3D memory structure 1800 that can be configured as a 3D NOR Vertical Transistor memory array. The 3D memory structure 1800 comprises a first vertical structure 1808a and an identical (or substantially identical) second vertical structure 1808b arranged adjacent to one another.

[0331] The first vertical structure 1808a includes a vertical plug column 1802a that provides an electrical connection to the lower portions of the 3D memory structure.The vertical plug column 1802a may have a uniform diameter along its entire length or may have a larger diameter on its lower end than on its upper end. The plug column 1802a can be fabricated as a solid column or as a hollow column in various embodiments.

[0332] Disposed adjacent to the vertical plug column 1802a is a source electrode column 1804a and a drain electrode column 1816a. The source electrode column 1804a and drain electrode column 1816a provide electrical connections to the source and drain nodes of the vertical transistors formed along the vertical structure 1808a. The source electrode column 1804a and drain electrode column 1816a may be comprised of various conducting materials including, but not limited to, tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AICu and TiW, and conducting polymers.

[0333] Surrounding the vertical plug column 1802a, source electrode column 1804a, and drain electrode column 1816a is a channel column 1812a that provides the semiconductor channel region for the vertical transistors along the first vertical structure 1808a. The channel column 1812a may be formed from materials including, but not limited to, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), hafnium indium oxide (HIO), cadmium oxide (CdO), polysilicon,Attomey Docket: P25-061-SEC-W001polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon, crystalline germanium, gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT, polythiophene, PPV, graphene, carbon nanotubes (CNTs), methylammonium lead halides, cesium lead halides, lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), and other semiconducting materials.

[0334] Surrounding the channel column 1812a is a ferroelectric column 1814a that provides the gate dielectric for the vertical transistors along the first vertical structure 1808a. The ferroelectric column 1814a may be comprised of ferroelectric materials including, but not limited to, perovskite oxides, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), bismuth zinc niobate (Bi(Znl / 2Til / 2)O3), bismuth lanthanum titanate (BiLaTiO3), bismuth nickel titanate (BiNiTiO3), PMN-PT, PLZT, neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), hafnium-based oxides like hafnium oxide (HfO2) and doped hafnium oxide, tungsten bronze structure materials, barium strontium niobate (BSN), lead barium niobate (PBN), potassium tantalate niobate (KTN), bismuth titanate (Bi4Ti3O12), strontium bismuth tantalate (SBT), calcium bismuth niobate (CBN), organic ferroelectrics like PVDF, TrFE and P(VDF-TrFE) copolymers, aurivillius phase oxides, rare earth manganites like YMnO3, lanthanum-modified PLZT, nickel manganese oxide (NiMnO3), relaxor ferroelectrics like PMN, PST and PIN, multiferroic materials like TbMnO3, EuTiO3, SbSI, GeTe, SnTe, PZT thin films, SBT thin films, HfO2-based thin films, layered superlattices, and PbTiO3 / SrTiO3.

[0335] The 3D memory structure 1800 further comprises multiple horizontal gate electrode layers 1806 including layers 1806a, 1806b, 1806c etc. The horizontal gate electrode layers 1806 are disposed at regular intervals along the vertical structures 1808 and provide the gate electrodes for the vertical transistors. The gate electrode layers 1806 may be formed from materials such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-Attorney Docket: P25-061-SEC-W001doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AICu and TiW, and conducting polymers.

[0336] Each of the horizontal gate electrode layers 1806 may be surrounded by an oxide / nitride / oxide (ONO) stack 1810, such as 1810a surrounding gate electrode layer 1806a, to provide insulation between the gate electrodes.

[0337] The second vertical structure 1808b in the 3D memory structure 1800 is identically configured as the first vertical structure 1808a. The two vertical structures 1808a and 1808b are arranged horizontally adjacent to each other with a spacing that allows integration of the gate electrode layers 1806 and ONO stacks 1810. Together, the first and second vertical structures 1808a, 1808b along with the horizontal gate electrode layers 1806 can be configured as a 3D NOR memory architecture.

[0338] Fig. 19 illustrates an embodiment of a planar FeFET 1900. The FeFET 1900 comprises a substrate 1910 upon which various layers and components are formed. The substrate 1910 may be comprised of silicon or other suitable semiconductor materials. Disposed on top of the substrate 1910 is a layer of TiN 1912.The TiN layer 1912 may act as an electrode and can be deposited by sputtering or other suitable deposition techniques.

[0339] On top of the substrate 1910 and TiN layer 1912, a layer of HZO 1908 is disposed. HZO 1908 comprises hafnium, zirconium, and oxygen and can exhibit ferroelectric properties. The HZO 1908 may be deposited by ALD, CVD, PVD or other suitable deposition methods and can have a thickness in the range of 5-50 nm. Acting as a ferroelectric layer, the HZO 1908 enables the non-volatile storage of data in the FeFET 1900.

[0340] Deposited conformally on top of the HZO 1908 is a layer of IWO 1906.IWO 1906 comprises indium, tungsten, and oxygen. It can be deposited by sputtering or other suitable techniques and may have a thickness in various ranges. The IWO 1906 layer serves as a control oxide layer in the FeFET 1900.

[0341] On top of the IWO 1906 layer, a drain contact 1904 and source contact 1914 are formed. The drain contact 1904 and source contact 1914 may comprise metals such as copper, aluminum, or alloys thereof and can be deposited by PVD, CVD or other suitable methods. The drain contact 1904 and source contact 1914 allow electrical connection to the FeFET 1900. They may have thicknesses in the range of 50-500 nm.

[0342] In operation, a voltage applied to the drain 1904, source 1914, and TiN gate contact 1912 can control the ferroelectric polarization of the HZO 1908 layer. TheAttorney Docket: P25-061-SEC-W001polarization state can be used to store information in a non-volatile manner, enabling memory storage capabilities. The IWO 1906 layer helps improve the switching speed and endurance of the FeFET 1900. Overall, the layered structure shown in Fig. 19 enables a FeFET 1900 suitable for non-volatile memory applications.

[0343] Fig. 20 presents the transfer characteristics of a Ferroelectric FET (FeFET) device, illustrating the relationship between the gate voltage (V_GS) on the x-axis and the resulting drain current (I_D) on the y-axis. Fig. 20 may show the characteristics of a FeFET as disclosed herein. The x-axis spans from -IV to IV, while the y-axis, on a logarithmic scale, displays current values from 10A- 12 A / pm to 10A-4A / pm

[0344] Two distinct curves represent the drain current behavior under clockwise (CW) and counterclockwise (MW) polarization of the FeFET. The blue curve (CW) starts at approximately I ()A- 1 I A / pm at -IV and exhibits a steep increase around -1 V, reaching just above 10A-5 A / pm at IV. This demonstrates the rapid increase in drain current exhibited by the FeFET under forward bias in the clockwise polarization state.

[0345] Conversely, the red curve (MW) starts at approximately 10A- 11 A / pm at -IV and increases more gradually as it approaches 0V. At around IV, it then follows closely with the blue curve past IV. This demonstrates comparable drain current behavior under reverse bias conditions regardless of the polarization state.

[0346] Notably, the separation between the red and blue curves spans several orders of magnitude in the negative voltage range near -IV. This substantial difference in off-state current highlights the non-volatile memory effect achievable with the FeFET depending on its polarization direction. This large memory window is explicitly called out in the green box labeled “Large Memory Window” at the top left.

[0347] Additional key details provided include the FeFET device dimensions, with a width / length ratio of lpm / 50nm specified. The drain voltage is also fixed at 0.05V. Specific points along the curves are annotated, such as “MW @5e-7A / pm =1V” on the red MW curve denoting the IV memory window at 5xlOA-7A / pm drain current.Another point marked is “CW @-0.5V = lxlOA6” on the blue CW curve, highlighting the clockwise current value of lxlO-6A / pm at -0.5V gate voltage.

[0348] In summary, Fig. 20 comprehensively depicts the bidirectional transfer characteristics of the FeFET device, highlighting the large memory window achievable through polarization switching and providing detailed voltage, current, and dimensionalAttorney Docket: P25-061-SEC-W001specifications to fully convey the measurement conditions and transistor performance.The paired curves effectively compare the clockwise and counterclockwise operation modes over the full gate voltage range.

[0349] Fig. 21 illustrates an assembly 2100, representing a semiconductor device with a unified read / write periphery 2102, in accordance with an embodiment of the present disclosure. The assembly 2100 comprises a read / write periphery 2102, which integrates both read and write functionalities into a single module.

[0350] The read / write periphery 2102 is responsible for handling the data transactions of the memory bit cells 2106. The read data 2104 and write data 2110 flow through this unified periphery, which simplifies the design by consolidating the data paths. This integration allows for streamlined operations, reducing latency and improving the overall performance of the memory device.

[0351] Address and read / write enable lines, along with clocks 2112, are routed through the read / write periphery 2102, ensuring control and synchronization of data access operations. This configuration supports the efficient management of memory transactions, allowing for high-speed data processing and retrieval.

[0352] The clock address bus 2114 and the read / write data bus 2108 are components of the assembly 2100. The clock address bus 2114 provides timing signals and address information, enabling accurate data access and storage. The read / write data bus 2108 facilitates the transfer of data to and from the memory bit cells 2106, ensuring seamless communication within the semiconductor device.

[0353] The integrated design of the assembly 2100, with its unified read / write periphery 2102, offers significant advantages in terms of power efficiency, speed, and scalability. This innovative approach allows for the development of more compact and versatile semiconductor devices, meeting the demands of modem computing applications.

[0354] The bit cells 2106 may be a microvault and may be in a 3D configuration as described previously. Each microvault within the assembly may be equipped with a dedicated read and write periphery, ensuring precise data handling and storage capabilities.

[0355] The read / write periphery 2102 depicted in Fig. 21 is integrated to include a read / write address decoder, which is responsible for decoding both read and write addresses. The read / write address decoder may be further enhanced with a senseAttorney Docket: P25-061-SEC-W001amplifier, which amplifies the signals read from the memory cells, ensuring accurate data retrieval.

[0356] The assembly 2100 may be designed with programmable read and write clock cycle lengths, allowing for flexible operation tailored to specific application requirements. The programmable nature of these clock cycles may enable the integrated circuit to adapt to varying processing speeds and power consumption needs, thereby enhancing its versatility for different use cases.

[0357] In some embodiments, the assembly 2100 includes an interlock mechanism configured to prevent simultaneous read and write operations within the same microvault. This feature ensures data integrity and prevents potential conflicts during memory access, which is crucial for maintaining reliable performance in highspeed applications.

[0358] The circuit assembly 2100 also supports multiple bonding areas, including a primary bonding area that facilitates communication between the microvaults and external components. These bonding areas are strategically placed on the primary surface and may include read / write ports, data ports, and address ports, enabling seamless integration with other semiconductor devices or chiplets.

[0359] Furthermore, the assembly 2100 can incorporate a multiplexer system, enabling selective addressing of different microvaults. This system can include read, write, or read / write multiplexers, providing flexible access control to the memory cells.The multiplexer configuration enhances the scalability of the integrated circuit, allowing it to efficiently manage data flow across multiple memory modules.

[0360] Fig. 22 shows an assembly of semiconductor devices including a semiconductor device with a system-on-chip 2214 and another semiconductor 2206 with microvaults disposed on top in accordance with an embodiment of the present disclosure. The assembly 2200 integrates a semiconductor device 2206 and a semiconductor device 2214, which may be implemented as separate chiplets bonded together. The semiconductor device 2214 includes various components to facilitate bidirectional data communication with the microvaults on the semiconductor device 2206, such as a read / write address register input interconnect 2224, read / write data register 2222, and read / write data register output interconnect 2250. These components pass the read / write address to the microvaults on semiconductor device 2206 and return the read / write data back to the semiconductor device 2214.Attorney Docket: P25-061-SEC-W001

[0361] Specifically, the read / write address enters via interconnect 2224 into the read / write address register 2226. The output of this register 2262 connects through interconnects and bumpless bonds to another read / write address register 2238 on the semiconductor device 2206, which then addresses the target microvault 2236. The micro vault 2236 outputs read / write data via interconnect 2240 to a read / write data register 2242, which passes the data back through bumpless bonds 2210, 2218 to read / write data register 2222 on semiconductor device 2214. This data can then be accessed externally via the read / write data register output interconnect 2250.Additionally, the semiconductor device 2214 and 2206 have interconnected Through-Silicon Vias 2216 and 2244 to allow bidirectional communication with devices potentially stacked above semiconductor device 2206.

[0362] The semiconductor device 2206 features various memory structures to provide data storage capabilities. This includes a microvault 2236, which offers high-density, low-latency data storage, along with other peripheral memory components like read / write data register 2242 and read / write address register 2238 to facilitate bidirectional data access. The microvault 2236 resides on the BEOL portion of the chiplet, allowing dense 3D integration of memory layers. In some implementations, the microvault utilizes non-volatile memory technologies like FeFET or STT-MRAM for data retention without power.

[0363] The semiconductor device 2214 comprises processing elements and data routing circuitry to retrieve and manipulate data stored in semiconductor device 2206.Components like read / write address register 2226 and read / write data register 2222 handle sending read / write addresses and receiving data from the microvault 2236 respectively. The device 2214 also includes interconnects 2224, 2250 and Through-Silicon Via 2216 to communicate externally.

[0364] The two devices 2206 and 2214 integrate via fine-pitch interconnects like bumpless hybrid bonds 2208, 2210, 2218, 2220, 2230 and 2232. This allows direct bidirectional data transfer pathways between processing components in device 2214 and memory structures in device 2206. Alignment during bonding ensures dedicated access - for instance, read / write data register output interconnect 2250 on 2214 links directly to read / write data register 2222 to receive requested data.

[0365] The pathways facilitating bidirectional data flow can be summarized as follows: A read / write address enters through interconnect 2224 into read / write address register 2226 on device 2214. This gets communicated via interconnects and bumplessAttorney Docket: P25-061-SEC-W001bonds to read / write address register 2238 on device 2206, which then addresses microvault 2236. Requested data gets passed via interconnect 2240 to read / write data register 2242, then transfers through bonds back to read / write data register 2222 on 2214, where it becomes available externally via interconnect 2250.

[0366] The assembly 2200 exemplifies a modular, high-density architecture optimized for data-centric applications like Al inferencing. Tight integration of processing and storage dies via advanced packaging techniques allows localized data access with minimal latency and power. Scalability is also enabled by incorporating multiple chiplets, in this case devices 2206 and 2214. The assembly 2200 illustrates a potential configuration suited for space-constrained, high-performance computing systems.

[0367] The Through-Silicon Via (TSV) 2216 is an electrical connection that passes vertically through the semiconductor device 2214. Its purpose is to provide a pathway for signals to travel bidirectionally between the top and a processing element within the semiconductor device 2214. This allows the device to be stacked and interconnected with other components in a vertical configuration. The TSV 2216, along with other TSVs on the device, facilitates high-density 3D integration and heterogeneous stacking of multiple devices like chiplets.

[0368] The TSV 2216 interacts with several other components within the system. On the top side of semiconductor device 2214, it connects to interconnect 2212, which couples it to bumpless bonds 2218. These bonds interface with complementary bumpless bonds 2210 on the bottom side of semiconductor device 2206 when the two devices are stacked. This allows signals to travel bidirectionally from device 2214 to device 2206 through the TSV 2216. The route continues as signals go through interconnect 2202 to TSV 2244 on device 2206. TSV 2244 provides a vertical signal pathway to the top surface of device 2206 where additional devices could be stacked.In the reverse direction, signals can travel from TSV 2244 down through device 2206, back up TSV 2216, and down into device 2214. So the TSV 2216 provides bidirectional vertical communication across device boundaries.

[0369] There are a few possible variations for the TSV 2216 implementation.First, multiple TSVs arranged in an array could be used instead of a single via to increase throughput and redundancy. Second, the dimensions and materials of the TSV could be optimized — for example, smaller TSV diameters using denser materials like tungsten could be advantageous. Additionally, the interface circuitry driving signalsAttorney Docket: P25-061-SEC-W001into the TSV, like interconnects 2212 and 2202. could employ variable line drivers to support different voltage levels or signal integrity enhancements. Further embodiments may include integrated monitoring circuitry within TSV 2216 to track metrics like temperature and link utilization. And alternative signaling schemes besides electrical signals could be employed in future cases. For instance, integrated silicon photonics utilizing modulated light to convey data through the TSVs could enable very high bandwidth and low latency connectivity. There are multiple avenues to further develop the capabilities of TSV-based vertical links like TSV 2216 within these complex 3D integrated architectures.

[0370] There are several variations and alternatives for the interconnect 2212 implementation. For example, different conductive materials such as copper or aluminum may be utilized to fabricate the pathways forming interconnect 2212 and optimize for conductivity or thermal dissipation. Additionally, interconnect 2212 may feature redundant signal paths or self-repair capabilities using spare interconnect lines to improve reliability and resilience. The bumpless bonds 2218 and 2210 connecting devices 2206 and 2214 could also be replaced with other high-density bonding approaches like hybrid bonding or Through-Silicon Vias. Furthermore, alternate signaling schemes besides simple digital logic could be employed on interconnect 2212, such as analog signaling or multi-level digital waveforms to enhance data transmission capabilities. The routing and dimensions of interconnect 2212 can also be adapted according to bandwidth requirements or circuit layout considerations. Overall, many structural and functional alternatives exist for crafting interconnect 2212 to meet application needs.

[0371] The bumpless bonds 2218 are electrical connections located on the semiconductor device 2214 between an interconnect 2212 and bumpless bonds 2210 of the semiconductor device 2206. The bumpless bonds 2218 provide an electrical pathway for signals to travel bidirectionally between the semiconductor device 2214 and any additional semiconductor devices, such as the semiconductor device 2206, stacked on top of the assembly 2200. The signals communicated over the bumpless bonds 2218 can include data signals, control signals, address signals, or any other signals needed to coordinate operations between the multiple semiconductor devices.

[0372] There are several possible variations for the bumpless bonds 2218. The number of individual bond sites can range from just a few to hundreds, depending on signal bandwidth requirements. The bonding method can utilize techniques like directAttorney Docket: P25-061-SEC-W001bonding, plasma-activated bonding, adhesive bonding, or compression bonding. Hybrid bonding approaches are also possible, combining direct wafer bonds with intermediate metal bonds. The size and pitch of each bond site can vary and may use pitches under 10 micrometers to enable high-density connections. Redundant bonds can provide backup pathways. Shielding structures may surround bonds for noise immunity.Overall, many embodiments of bumpless bonds 2218 are possible to meet cost, reliability, and performance needs.

[0373] The bumpless bonds 2210 provide an interface for communicating signals between the semiconductor device 2206 and semiconductor device 2214.Specifically, the bumpless bonds 2210 of the semiconductor device 2206 are electrically coupled to the complementary bumpless bonds 2218 of the semiconductor device 2214. This allows signals like read / write data and addresses to be transmitted bidirectionally between the two devices. The bumpless nature of the bonds allows for a low-profile, high-density interconnection.

[0374] The bumpless bonds 2210 interact with other components in the system to facilitate bidirectional data transfer operations. For writes, data enters the semiconductor device 2214 via the Through-Silicon Via 2216, passes through interconnect 2212 and bumpless bonds 2218 before reaching bumpless bonds 2210 of device 2206. For reads, addresses flow from the read / write address register 2226 of device 2214 through interconnects 2228, 2230 and bumpless bonds 2232 into the read / write address register 2238 on device 2206. Read data then returns through bumpless bonds 2208 and 2220 back to device 2214. So the bumpless bonds 2210 provide key bidirectional data and address routing between the devices.

[0375] Possible variations of the bumpless bonds 2210 include using different bond densities, materials, or electrical contact configurations to optimize performance.The bonds can use alloying or doping techniques to improve conductivity. Additionally, the routing of signals can be changed, for example by using separate ports for input and output instead of shared ports. More bumpless bonds can be added to increase bandwidth between devices. Shielding may be added around the bonds to reduce interference. Overall, many modifications to the bumpless bonds 2210 are possible within the scope of electrically interconnecting multiple devices.

[0376] The Through-Silicon Via (TSV) 2244 is an electrical connection that passes vertically through the semiconductor device 2206 from the top surface to the bottom surface. Its purpose is to facilitate bidirectional communication of signals andAttorney Docket: P25-061-SEC-W001data between the semiconductor device 2206 and any additional semiconductor devices potentially stacked on top of it in a 3D integrated circuit configuration. The TSV 2244 enables high-density interconnections between multiple stacked semiconductor layers, providing an efficient means for data routing and signaling.

[0377] The TSV 2244 interfaces with surrounding circuitry within the semiconductor device 2206, allowing signals to be transmitted bidirectionally depending on the system configuration. On one end, the TSV 2244 couples to the read / write data register 2242 via interconnect 2246. The read / write data register 2242 can use the TSV 2244 path to transfer read / write data from the microvault 2236 to external semiconductor devices. This enables efficient data offloading from the on-chip memory. On the other end, the TSV 2244 continues through to the top surface of semiconductor device 2206, where it may interface with complementary contacts or interconnects on the bonded semiconductor above it. This facilitates the vertical transfer of signals and data along the assembly 2200.

[0378] There can be many variations in the specific implementation of the TSV 2244. Its dimensions can range from a few microns to tens of microns to match pitch requirements. The TSV 2244 can be tapered, straight, or have non-uniform crosssections. It may utilize different conductive materials as liners and fills, including metals like copper, tungsten, or alloys. Insulating liners made of materials like silicon dioxide can separate the conductive fill from the substrate. The contacts and interconnects coupling into the TSV 2244 can also have diverse layouts. Multiple TSVs can be placed adjacent to each other in a high-density array configuration if desired.Overall, many architectural optimizations in the design and fabrication process of the TSV 2244 are possible within the scope of the present disclosure.

[0379] Fig. 23 shows a semiconductor assembly 2300 incorporating a daisy-chained configuration of microvaults 2336, 2358, operatively connected to a multiplexer 2360 and managed by a counter 2362 for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure. This assembly 2300 is designed to carry out data processing tasks, potentially for applications such as artificial intelligence (Al) and machine learning, where high-speed data access and processing are utilized.

[0380] The assembly 2300 comprises two primary semiconductor devices: semiconductor device 2306 and semiconductor device 2314. Semiconductor device 2314 is depicted as containing several interfaces and registers for data communication,Attorney Docket: P25-061-SEC-W001including a read / write address register input interconnect 2324. This interconnect 2324 facilitates the delivery of read / write addresses to a read / write address register 2326, which temporarily holds these addresses before they are transmitted to corresponding microvaults 2336, 2358 in semiconductor device 2306 for data retrieval and writing operations.

[0381] In semiconductor device 2314, interconnect 2328 serves as a pathway for read / write addresses from the read / write address register 2326 to transition to bumpless bonds 2330. Bumpless bonds 2330 and 2332 represent high-density, low-profile electrical connections between semiconductor device 2314 and semiconductor device 2306, ensuring the transmission of read / write addresses with minimal signal loss and physical space requirements.

[0382] Through interconnect 2334, the received addresses reach the read / write address register 2338 in semiconductor device 2306, which then directs the microvault 2336 to output the requested read / write data. Microvault 2336, a memory storage unit, may encompass a variety of memory technologies, such as FeFETs and / or 3D-NAND structures as described herein, to facilitate the storage and rapid retrieval of data.

[0383] The multiplexer 2360 selects the appropriate data stream from multiple microvault 2336, 2358 outputs. Controlled by a counter 2362, which may operate according to a predefined sequence or be driven by external control signals, the multiplexer 2360 arbitrates between the outputs of microvault 2336 and another microvault, denoted as microvault 2358. Microvault 2358, similar in function and potential memory technology to microvault 2336, provides an additional source of data for the multiplexer 2360 to select from.

[0384] Once the desired data is selected by the multiplexer 2360, it is temporarily stored in a read / write data register 2342, also located within semiconductor device 2306. This register 2342 acts as a buffer, holding the data for subsequent processing or transmission. The read / write data is then routed via interconnect 2304 to bumpless bonds 2308, which facilitate the transfer of data to the semiconductor device 2314.

[0385] Bumpless bonds 2310, 2318 facilitate the continued data's journey through the assembly 2300, ensuring data transfer from semiconductor device 2306 to semiconductor device 2314. Once the read / write data arrives at semiconductor device 2314, it is channeled via interconnect 2348 to a read / write data register, specifically read / write data register 2322, where it can be accessed by external systems, such as anAttorney Docket: P25-061-SEC-W001application-specific integrated circuit (ASIC) or a system-on-chip (SoC), via the read / write data register output interconnect 2350.

[0386] Additionally, the assembly 2300 encompasses Through-Silicon Vias (TSVs) 2316 and 2344, providing vertical electrical connections through the semiconductor devices 2314 and 2306, respectively. These TSVs enable the stacking of additional semiconductor devices or chiplets atop the assembly 2300, thus allowing for vertical expansion of the system's capabilities. Interconnects 2312 and 2346 serve as horizontal pathways for signals to travel to and from the TSVs 2316 and 2344, respectively.

[0387] Although the description presents a specific configuration, the assembly 2300 may be subject to various modifications and alternative embodiments. For example, the number and arrangement of microvaults, the specific types of memory technologies employed within the microvaults, and the configuration of interconnects and bonding areas may be tailored to meet the requirements of different applications.

[0388] In some embodiments, the semiconductor devices 2306 and 2314 may be designed to accommodate additional functionality, such as thermal management layers for heat dissipation, hardware-based encryption modules for data security, or power management circuits to optimize energy consumption. The detailed structure of Fig. 23, therefore, serves as a foundation upon which a variety of sophisticated semiconductor systems can be constructed, each tailored to the specific needs of its intended application.

[0389] In the configuration of assembly 2300 as depicted in Fig. 23, the microvaults, exemplified by microvaults 2336 and 2358, present a daisy-chaining configuration that allows for an expandable and flexible memory architecture within the semiconductor device 2306. This daisy-chaining is facilitated through a series of interconnected pathways and controlled by the multiplexer 2360 in coordination with the counter 2362.

[0390] Each microvault, such as 2336 and 2358, is designed to hold and provide rapid access to data, which may be in the form of stored charge, magnetic states, ferroelectric material states, or other physical embodiments of binary information. The microvaults are interconnected such that the output of one microvault can be routed to the input of another, creating a chain of memory elements. This is achieved through a series of interconnects, such as interconnect 2334 for microvault 2336 and interconnectAttorney Docket: P25-061-SEC-W0012356 for microvault 2358, which serve as conduits for the read / write data signals emanating from the micro vaults.

[0391] The multiplexer 2360 manages the flow of data from this daisy chain of microvaults. It is designed with multiple inputs, each connected to the output of a micro vault via respective interconnects. In the example provided, interconnect 2340 carries the read / write data from microvault 2336, and interconnect 2356 carries the read / write data from microvault 2358 to the multiplexer 2360. The multiplexer 2360 is capable of selecting which input to connect to its output at any given time, thus controlling which microvault's data is forwarded to the read / write data register 2342.

[0392] The counter 2362 orchestrates the operation of the multiplexer 2360. It may be a binary counter or any form of sequential logic circuit that produces a series of output states in response to a clock signal. The counter 2362 progresses through its states with each tick of the clock, which may be provided by an external clock source or generated internally within the semiconductor device 2306. As the counter 2362 advances, it outputs a control signal that instructs the multiplexer 2360 on which input to select.

[0393] For instance, at the first clock pulse, the counter 2362 may instruct the multiplexer 2360 to connect the output from microvault 2336 to the read / write data register 2342. At the next clock pulse, the counter may switch the connection to microvault 2358's output, and so on, cycling through the available microvaults in a predefined order. The counter's sequence and timing can be configured based on the desired data access patterns and the specific requirements of the processing tasks at hand.

[0394] This clock-driven coordination allows for an efficient and organized retrieval of data from a potentially large array of microvaults. It ensures that each microvault has an equal opportunity to present its data for processing, and it simplifies the control scheme by reducing it to a predictable, rhythmic progression of states. This is particularly advantageous in systems where a large volume of data must be processed in parallel, as it provides a systematic method for accessing and utilizing the stored information.

[0395] It should be noted that while Fig. 23 illustrates only two microvaults, the described daisy-chaining mechanism can be extended to accommodate any arbitrary number of microvaults. Additional microvaults can be added to the chain, with each new microvault connected to the multiplexer via an additional input line. TheAttorney Docket: P25-061-SEC-W001multiplexer 2360 and counter 2362 would be scaled accordingly to manage the increased number of inputs, maintaining the same clock-driven, sequential data retrieval process across the expanded memory architecture.

[0396] This daisy-chaining of microvaults, in conjunction with the multiplexing and counter-driven control system, exemplifies a modular and scalable approach to memory design in semiconductor devices. It allows for the customization of memory arrays to match the capacity and performance needs of a wide range of applications, from embedded systems to large-scale data centers, providing a versatile solution for modem computing challenges.

[0397] Fig. 24 shows a semiconductor assembly 2400 incorporating a daisy-chained configuration of microvaults in multiple semiconductor devices 2406, 2416 that are operatively connected to multiplexers and managed by counters for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure.

[0398] The present detailed description relates to Fig. 24 of the accompanying drawings, which illustrates an embodiment of an assembly 2400 as part of an integrated circuit. The assembly 2400 may be seen as a hierarchical structure that includes a bottom semiconductor device 2422, a middle semiconductor device 2416, and a top semiconductor device 2406 (each of these may be chiplets). Each semiconductor device is configured to interface with the others through a series of bumpless bonds, such as bumpless bonds 2428, 2429, 2458, 2459, 2460, 2461, 2462, and 2463, which facilitate electrical connectivity without the added profile of traditional bonding methods, thus enabling a compact and dense stacking of semiconductor layers.

[0399] The bottom semiconductor device 2422 includes a read / write address register 2426, which may be configured to store and communicate read and write addresses to microvaults located across the assembly 2400. The read / write address register 2426 communicates via an interconnect 2474, which serves as a conduit for signals directed to bumpless bonds 2428. These bonds in turn engage with bumpless bonds 2429 of the middle semiconductor device 2416, thus transferring the read and write addresses into the middle semiconductor device. The bottom semiconductor device 2422 also comprises a read / write data register 2424, which may serve as a repository for read and write data received. Read and write data is received through an interconnect 2476 that connects to bumpless bonds 2458, which are in communication with bumpless bonds 2459 of the middle semiconductor device 2416.Attorney Docket: P25-061-SEC-W001

[0400] The middle semiconductor device 2416 serves as an intermediary layer within the assembly 2400, housing microvaults such as microvault 2432 and microvault 2418, each of which may be designed to store and rapidly provide access to data. These microvaults are linked to other components within the device via interconnects, such as interconnect 2430 and interconnect 2434, which guide the flow of read and write addresses and read and write data, respectively. The middle semiconductor device 2416 also features a read / write address register 2446, which receives read and write addresses from interconnect 2430, and a read / write data register 2454, which collects read and write data from TSV 2452.

[0401] The multiplexer 2414, within the middle semiconductor device 2416, selects between various data streams. This multiplexer is controlled by a phase counter 2410, which determines the sequence of data selection based on the input received from the top semiconductor device 2406 via the TSV 2452. The read / write data register 2412 serves as a holding area for the selected data stream from the multiplexer 2414.

[0402] The top semiconductor device 2406 features a phase counter 2402 and a read / write data register 2404, which are used for coordinating data flow within the assembly 2400. The phase counter 2402, in conjunction with multiplexer 2450, dictates the output of read and write data from microvaults 2438 and 2464 based on the selected phase. The read / write data register 2404 captures the output from the multiplexer 2450, which is then relayed through interconnect 2408 to bumpless bonds 2462, facilitating communication with the middle semiconductor device 2416.

[0403] The assembly 2400 illustrates the integration of multiple microvaults across different semiconductor devices. For example, the microvault 2432 on the middle semiconductor device 2416 may receive read and write addresses from read / write address register 2446 via an interconnect 2434, path "1". Similarly, microvault 2418 may receive read and write addresses from the same register via an interconnect 2456, path "2". Microvaults 2438 and 2464 on the top semiconductor device 2406 receive read and write addresses via interconnect 2440 and paths "3" and "4", respectively, from read / write address register 2442, which is in communication with the middle semiconductor device 2416 via TSV 2436 and bumpless bonds 2460 and 2461.

[0404] Each microvault, such as 2432, 2418, 2438, and 2464, can potentially output read and write data to the multiplexer 2414 or 2450, where the data is then selected based on the configuration of the respective phase counter, 2410 or 2402. TheAttorney Docket: P25-061-SEC-W001selected data is temporarily stored in a read / write data register, either 2412 or 2404, before being transmitted down the assembly 2400 through the respective bumpless bonds and interconnects, ultimately reaching the read / write data register 2424 of the bottom semiconductor device 2422. This arrangement allows for a synchronized readout of data from all microvaults, which may be essential in applications requiring parallel processing and high-speed data access.

[0405] The TSVs, such as 2436 and 2452, provide vertical connectivity across the semiconductor devices, enabling the integration of additional layers or functionalities atop the existing assembly 2400. These TSVs are coupled to various interconnects and bumpless bonds that establish the necessary pathways for signal transmission both within and between the semiconductor devices.

[0406] In some embodiments, the microvaults within the assembly 2400 may include various memory technologies, such as 3D-NAND or 3D-NOR structures, and are arranged to facilitate parallel processing and efficient data retrieval. Each microvault may include additional features, such as thermal management layers for heat dissipation, hardware-based encryption modules for data security, or power management circuits to optimize energy consumption.

[0407] Datapath 1 within the assembly 2400 exemplifies a route through which read and write addresses and corresponding read and write data are transmitted across the assembly, specifically directing operations from the read / write address register 2426 located on the bottom semiconductor device 2422 to the read / write data register 2424 within the same device.

[0408] The process begins with the read / write address register 2426 holding a specific read and write address. This address is sent through interconnect 2474, which acts as a channel for the signal. The read and write address is then transmitted to bumpless bonds 2428, which are meticulously designed to create a reliable electrical connection without the physical protrusion associated with traditional bonding methods. These bonds ensure a low-profile interface that preserves the compactness of the semiconductor stack.

[0409] The signal continues from bumpless bonds 2428 to engage with bumpless bonds 2429 of the middle semiconductor device 2416. The read and write address is carried forward by interconnect 2430, which delivers the address to the read / write address register 2446 of the middle semiconductor device. Read / writeAttorney Docket: P25-061-SEC-W001address register 2446, in turn, propagates the read and write address through interconnect 2434, designated as path "1" guiding the signal to the microvault 2432.

[0410] Upon receiving the read and write address, microvault 2432 accesses the requested data. This data is then outputted through interconnect 2470 and directed to the multiplexer 2414. In some embodiments, multiplexer 2414 functions as a selective switch that chooses between data streams based on the configuration determined by phase counter 2410. This phase counter may be designed to cycle through a sequence that dictates the timing and selection of data streams, ensuring that each microvault is read and written to in a coordinated manner.

[0411] The selected data from multiplexer 2414 is then captured by read / write data register 2412, which holds the data momentarily. The data is subsequently sent via interconnect 2420, which carries the signal to bumpless bonds 2459. These bonds are part of a sophisticated electrical interconnection system that, along with bumpless bonds 2458 on the bottom semiconductor device 2422, enables vertical and horizontal integration within the semiconductor stack.

[0412] The signal, now in the form of read and write data, traverses from bumpless bonds 2459 to bumpless bonds 2458 and is finally introduced into interconnect 2476. This interconnect completes the connection to read / write data register 2424, which is configured to receive and hold the read and write data. The read / write data register 2424 may be equipped to retain the data for subsequent processing or external communication.

[0413] Datapath 2 within the assembly 2400 delineates a route specifically designed for the transmission of read and write addresses from the read / write address register 2426 on the bottom semiconductor device 2422 to the microvault 2418 located on the middle semiconductor device 2416 and the subsequent transfer of read and write data back to the read / write data register 2424 on the bottom device.

[0414] The journey commences at the read / write address register 2426, where a read and write address is held in preparation for dispatch. This register is part of the semiconductor device's control mechanism, orchestrating the retrieval of data by issuing specific addresses to the memory units. From the read / write address register 2426, the read and write address is sent through the interconnect 2474, which provides a secure and reliable pathway for electrical signals within the integrated circuit.

[0415] The read and write address continues from the interconnect 2474 to bumpless bonds 2428, which offer a seamless and low-profile connection to the middleAttorney Docket: P25-061-SEC-W001semiconductor device 2416 via the corresponding bumpless bonds 2429. These bonds maintain the signal's integrity during inter-layer communication and are designed to accommodate the requirements of modem semiconductor architectures.

[0416] The signal is then channeled via interconnect 2430 to the read / write address register 2446 within the middle semiconductor device 2416. The read / write address register 2446 acts as a secondary store and hold register. From there, the read and write address is directed down interconnect 2456, labeled as path "2," which terminates at the microvault 2418.

[0417] Upon receipt of the read and write address, microvault 2418 accesses the corresponding data. This data retrieval process is facilitated by the microvault's internal architecture, which may comprise an array of memory cells optimized for rapid access and data stability. The read and write data is outputted from microvault 2418 and travels through interconnect 2472, which leads to the multiplexer 2414.

[0418] Multiplexer 2414 determines which data stream to forward based on input from the phase counter 2410. The phase counter 2410 operates in synchronization with the system clock or an external control signal, cycling through various states to control the selection process of the multiplexer 2414 in a precise and predictable manner.

[0419] The output of the multiplexer 2414, now carrying the selected read and write data, is conveyed to read / write data register 2412. This register temporarily stores the read and write data, acting as a buffer. The read and write data is then dispatched via interconnect 2420 towards bumpless bonds 2459.

[0420] Bumpless bonds 2459 form the interface with bumpless bonds 2458 on the bottom semiconductor device 2422, where the signal is transmitted downward through the assembly. The read and write data then traverses the interconnect 2476 to reach its final destination, the read / write data register 2424. The read / write data register 2424 captures the read and write data, holding it in readiness for further processing or transmission to external circuits.

[0421] Datapath 3 within the assembly 2400 is another communication route that illustrates the data transfer sequence from the read / write address register 2426 on the bottom semiconductor device 2422, through various components, ultimately to the microvault 2438 on the top semiconductor device 2406, and then back to the read / write data register 2424 on the bottom device.Attorney Docket: P25-061-SEC-W001

[0422] The sequence initiates at the read / write address register 2426, which serves as the origin point for read and write addresses. The register 2426 securely holds the address before it is dispatched through the interconnect 2474. Interconnect 2474 acts as a dedicated channel, ensuring that the read and write address is conveyed with precision to the bumpless bonds 2428. These bumpless bonds 2428 facilitate a streamlined connection to the bumpless bonds 2429 of the middle semiconductor device 2416, preserving the integrity and compactness of the signal pathway.

[0423] Upon reaching the middle semiconductor device 2416, the read and write address is relayed through interconnect 2430 to the read / write address register 2446. The read / write address register 2446 acts as a juncture that further propagates the address signal through the Through-Silicon Via (TSV) 2436. The TS V 2436 is a vertical interconnect that pierces through the semiconductor substrate, providing a direct link from the middle semiconductor device 2416 to the top semiconductor device 2406, thus exemplifying the 3D integration capabilities of semiconductor design.

[0424] The read and write address ascends from TSV 2436 and emerges onto bumpless bonds 2460 on the middle semiconductor device 2416. The bumpless bonds 2460 are connected to the bumpless bonds 2461 of the top semiconductor device 2406.The address signal is conducted through interconnect 2440 to the read / write address register 2442 on the top device 2406.

[0425] The read / write address register 2442, upon receiving the read and write address, directs the signal along interconnect 2444. This path, denoted as "3," leads the address to the microvault 2438. Microvault 2438, designed for data storage, retrieves the requested information in response to the read and write address. The read and write data is outputted through interconnect 2466, which feeds the data into the multiplexer 2450.

[0426] The multiplexer 2450 in the top semiconductor device 2406 is governed by the phase counter 2402, which dictates the selection of the data stream to be channeled to the read / write data register 2404. The chosen data stream is temporarily housed in the read / write data register 2404, where it awaits downstream transmission.

[0427] The read and write data departs from the read / write data register 2404 via interconnect 2408, which connects to bumpless bonds 2462. These bonds 2462 engage with the corresponding bumpless bonds 2463 on the middle semiconductor device 2416, transferring the read and write data to TSV 2452.Attorney Docket: P25-061-SEC-W001

[0428] TSV 2452 operates as a vertical conduit, allowing the read and write data to traverse down into the middle semiconductor device 2416, where it is received by the read / write data register 2454. The read / write data register 2454 holds the read and write data momentarily before it is directed to the multiplexer 2414 through interconnect 2456.

[0429] The multiplexer 2414 in the middle semiconductor device 2416, coordinated by the phase counter 2410, selects the appropriate data for output. The read and write data is then channeled to the read / write data register 2412, where it is briefly stored. Following this, the read and write data travels via interconnect 2420 to bumpless bonds 2459.

[0430] The bumpless bonds 2459 form an interface with bumpless bonds 2458 on the bottom semiconductor device 2422. The read and write data signal is then carried through interconnect 2476, culminating its journey at the read / write data register 2424 on the bottom device.

[0431] Datapath 4 within the assembly 2400 is a path that establishes the flow of read and write addresses from the read / write address register 2426 on the bottom semiconductor device 2422 to the microvault 2464 located on the top semiconductor device 2406, and subsequently facilitates the movement of read and write data back down to the read / write data register 2424 on the bottom device.

[0432] This datapath begins at the read / write address register 2426, which is responsible for holding and issuing the read and write addresses necessary for data retrieval from the microvaults. The read and write address is sent from the register 2426 through interconnect 2474, a pathway that maintains signal integrity and facilitates electrical communication.

[0433] From interconnect 2474, the read and write address is directed to bumpless bonds 2428. These bonding areas create an interconnection between the bottom semiconductor device 2422 and the middle semiconductor device 2416 through bumpless bonds 2429. The design of these bumpless bonds facilitates data transmission.

[0434] Once the read and write address reaches the middle semiconductor device 2416, it is carried forward by interconnect 2430 to the read / write address register 2446. This register acts as an intermediary, preparing the address for its vertical ascent through the device stack. The address is then transmitted via the Through-Silicon Via (TSV) 2436 that facilitates vertical integration by providing a direct electrical link through the semiconductor substrate.Attorney Docket: P25-061-SEC-W001

[0435] After ascending through TSV 2436, the read and write address emerges onto bumpless bonds 2460, which are aligned to connect with bumpless bonds 2461 on the top semiconductor device 2406. The read and write address then proceeds along interconnect 2440 to the read / write address register 2442 located on the top device.

[0436] The read / write address register 2442 serves to forward the read and write address to its final destination, the microvault 2464, through interconnect 2448, labeled as path "4". Microvault 2464, upon receiving the read and write address, retrieves the requested data, which is then outputted through interconnect 2468. This data is directed to the multiplexer 2450, which is under the control of phase counter 2402.

[0437] The phase counter 2402 determines which data stream is selected by the multiplexer 2450, which then sends the read and write data to the read / write data register 2404. The read / write data register 2404 acts as a temporary repository, holding the data until it can be sent downwards through the device stack.

[0438] The data leaves the read / write data register 2404 and travels via interconnect 2408 to bumpless bonds 2462. These bonds maintain a connection to bumpless bonds 2463 on the middle semiconductor device 2416. The read and write data is then transferred to TSV 2452, which carries the data vertically down to the read / write data register 2454 on the middle semiconductor device 2416.

[0439] The read / write data register 2454 temporarily holds the read and write data before it is fed into the multiplexer 2414 via interconnect 2456. The multiplexer 2414, coordinated by the phase counter 2410, channels the appropriate data stream to the read / write data register 2412. This register serves as a staging area for the read and write data, which is then sent through interconnect 2420 to bumpless bonds 2459.

[0440] Bumpless bonds 2459 interface with bumpless bonds 2458 on the bottom semiconductor device 2422 to provide a downward transmission of the read and write data. Finally, the signal is routed through interconnect 2476 and arrives at read / write data register 2424, where the data is made available for subsequent processing or external communication.

[0441] Various alternatives and modifications can be devised by those skilled in the art without departing from the disclosure. Accordingly, the present disclosure is intended to embrace all such alternatives, modifications, and variances. Additionally, while several embodiments of the present disclosure have been shown in the drawings and / or discussed herein, it is not intended that the disclosure be limited thereto, as it is intended that the disclosure be as broad in scope as the art will allow and that theAttorney Docket: P25-061-SEC-W001specification be read likewise. Therefore, the above description should not be construed as limiting, but merely as exemplifications of particular embodiments. And those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto. Other elements, steps, methods, and techniques that are insubstantially different from those described above and / or in the appended claims are also intended to be within the scope of the disclosure.

[0442] The embodiments shown in the drawings are presented only to demonstrate certain examples of the disclosure. And the drawings described are only illustrative and are non-limiting. In the drawings, for illustrative purposes, the size of some of the elements may be exaggerated and not drawn to a particular scale.Additionally, elements shown within the drawings that have the same numbers may be identical elements or may be similar elements, depending on the context.

[0443] Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun, e.g., "a," "an," or "the,” this includes a plural of that noun unless something otherwise is specifically stated. Hence, the term "comprising" should not be interpreted as being restricted to the items listed thereafter; it does not exclude other elements or steps, and so the scope of the expression "a device comprising items A and B" should not be limited to devices consisting only of components A and B. This expression signifies that, with respect to the present disclosure, the only relevant components of the device are A and B.

[0444] Furthermore, the terms "first," "second," "third," and the like, whether used in the description or in the claims, are provided for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances (unless clearly disclosed otherwise) and that the embodiments of the disclosure described herein are capable of operation in other sequences and / or arrangements than are described or illustrated herein.

Claims

Attorney Docket: P25-061-SEC-W001What is Claimed is:

1. An integrated circuit comprising :a plurality of microvaults, each of the plurality of microvaults is disposed in spaced relation relative to each other and adjacent to a first surface, each respective microvault of the plurality of microvaults has a respective read periphery and a respective write periphery; anda plurality of bonding areas including a first bonding area, each of the plurality of bonding areas is disposed on the first surface.

2. The integrated circuit according to claim 1, wherein the respective read periphery has a programmable read-clock cycle length.

3. The integrated circuit according to claim 1 or 2, wherein the respective write periphery has a programmable write-clock cycle length.

4. The integrated circuit according to claim 3 when depending from claim 2, wherein the read-clock cycle length is based off of a first clock.

5. The integrated circuit according to claim 4, wherein the write-clock cycle length is based off of the first clock.

6. The integrated circuit according to claim 4, wherein the write-clock cycle length is based off of a second clock being different from the first clock.

7. The integrated circuit according to any one of claims 1 to 6, further comprising an interlock configured to prevent simultaneous read and write operation of the respective microvault.

8. The integrated circuit according to any one of claims 1 to 7, wherein the write periphery writes to the respective microvault using a first voltage.

9. The integrated circuit according to any one of claims 1 to 8, wherein the read periphery reads the respective microvault using a second voltage.Attorney Docket: P25-061-SEC-W00110. The integrated circuit according to claim 8 or 9, wherein the first voltage is programmable.

11. The integrated circuit according to claims 9 or 10, wherein the second voltage is programmable.

12. The integrated circuit according to claim 1, wherein the respective read periphery and the respective write periphery are integrated together to form an integrated read / write periphery.

13. The integrated circuit according to claim 2, wherein the integrated read / write periphery includes a read / write address decoder.

14. The integrated circuit according to claim 3, wherein the read / write address decoder is configured to decode read addresses and write addresses.

15. The integrated circuit according to claim 2, wherein the read / write address periphery includes a sense amplifier.

16. The integrated circuit according to claim 2, wherein the read / write periphery is disposed adjacent the respective microvault at a side opposite to the first surface.

17. The integrated circuit according to claim 2, wherein the read / write periphery is disposed adjacent the respective microvault in a front-end-of-the-line layer of the integrated circuit.

18. The integrated circuit according to claim 17, wherein the respective microvault is disposed on a back-end-of-the-line layer of the integrated circuit.

19. The integrated circuit according to claim 2, further comprising an address port configured to decode one of a read address and a write address.Attorney Docket: P25-061-SEC-W00120. The integrated circuit according to claim 1, wherein the read periphery is disposed adjacent to the write periphery.

21. The integrated circuit according to claim 20, wherein:the read periphery includes a read address decoder configured to decode a read address, andthe write periphery includes a write address decoder configured to decode a write address.

22. The integrated circuit according to claim 20, wherein the read periphery and the write periphery are disposed adjacent the respective microvault adjacent to a side opposite to the first surface.

23. The integrated circuit according to claim 22, wherein the read periphery and the write periphery are disposed adjacent the respective microvault in a front-end-of-the-line layer of the integrated circuit.

24. The integrated circuit according to claim 23, wherein the respective micro vault is disposed on a back-end-of-the-line layer of the integrated circuit.

25. The integrated circuit according to claim 1, further comprising an application programming interface.

26. The integrated circuit according to claim 1, wherein the plurality of microvaults includes a first microvault and a second microvault.

27. The integrated circuit according to claim 26, further comprising a multiplexer configured to address the first microvault and the second microvault.

28. The integrated circuit according to claim 27, wherein the multiplexer is a read multiplexer.

29. The integrated circuit according to claim 26, wherein the multiplexer is a write multiplexer.Attorney Docket: P25-061-SEC-W00130. The integrated circuit according to claim 26, wherein the multiplexer is a read / write multiplexer.

31. The integrated circuit according to claim 26, wherein the first bonding area is operatively coupled to the first and second microvaults.

32. The integrated circuit according to claim 31, wherein the first bonding area includes a read / write port.

33. The integrated circuit according to claim 31, wherein the first bonding area includes a read / write data port.

34. The integrated circuit according to claim 31, wherein the first bonding area includes a read / write address port.

35. The integrated circuit according to claim 31, wherein the first bonding area includes a read address port and a write address port.

36. The integrated circuit according to claim 31, wherein the first bonding area includes a read data port and a write data port.

37. The integrated circuit according to claim 31, wherein the first and second microvaults are disposed in a first chiplet.

38. The integrated circuit according to claim 37, further comprising a second chiplet diposed on the first chiplet.

39. The integrated circuit according to claim 38, further comprising a third and fourth microvault disposed in the second chiplet.

40. The integrated circuit according to claim 38, wherein the first and second chiplets are coupled together via a first complementary bonding area of the first chiplet and a second complementary bonding area of the second chiplet.Attorney Docket: P25-061-SEC-W00141. The integrated circuit according to claim 40, wherein the first bonding area is in operative communication with the first and second microvaults.

42. The integrated circuit according to claim 41, wherein the first bonding area is in operative communication with the third and fourth microvaults via the first complementary bonding area of the first chiplet and the second complementary bonding area of the second chiplet.

43. The integrated circuit according to claim 1, further comprising:a face-to-face bonded chiplet, wherein at least one of the plurality of microvaults is implemented as a 3D memory module within the face-to-face bonded chiplet.

44. The integrated circuit according to claim 43, wherein the face-to-face bonded chiplet is connected to the first surface via the first bonding area.

45. The integrated circuit according to claim 44, wherein the first bonding area includes bump-less bonds.

46. The integrated circuit according to claim 1, further comprising:a plurality of registers configured to facilitate data transfer between the plurality of microvaults and the first bonding area.47 The integrated circuit according to claim 1, wherein at least two micro vaults of the plurality of microvaults are disposed adjacent to each.

48. The integrated circuit according to claim 47, further comprising:a counter circuit configured to control access to the at least two microvaults in a multi-cycled pipelined configuration.

49. The integrated circuit according to claim 1, further comprising:a plurality of microvaults arranged in at least two chiplets; anda through-silicon via (TSV) connecting the at least two chiplets.Attorney Docket: P25-061-SEC-W00150. The integrated circuit according to claim 49, further comprising:a first phase counter associated with a first chiplet of the at least two chiplets; anda second phase counter associated with a second chiplet of the at least two chiplets,wherein the first and second phase counters are configured to coordinate multicycled pipelined access to the plurality of micro vaults.

51. The integrated circuit according to claim 50, further comprising:a plurality of registers configured to facilitate data transfer between the microvaults in different chiplets of the at least two chiplets.

52. The integrated circuit according to claim 1, further comprising:an application System-on-Chip (SoC) disposed adjacent to the first surface, the application SoC configured to interface with the plurality of microvaults via bump-less bonds.

53. The integrated circuit according to claim 1, further comprising a SRAM vault disposed adjacent to the first microvault.

54. The integrated circuit according to claim 53, wherein the first bonding area is in operative communication with the SRAM vault.

55. The integrated circuit according to claim 53, further comprising a second bonding area disposed on the first surface and in operative communication with the SRAM vault.

56. The integrated circuit according to claim 53, wherein the plurality of microvaults is formed on a first die and the SRAM vault is formed on a second die, wherein the first and second dies are bonded together.

57. The integrated circuit according to claim 1, further comprising an address register operatively coupled to the first bonding area, the address register configured to hold and communicate an address to a first microvault of the plurality of microvaults.Attorney Docket: P25-061-SEC-W00158. The integrated circuit according to claim 57, wherein the address register is a read address register.

59. The integrated circuit according to claim 57, wherein the address register is a write address register.

60. The integrated circuit according to claim 57, wherein the address register is a read / write address register.

61. The integrated circuit according to claim 1, further comprising a data register operatively coupled to the first bonding area, the data register configured to hold and communicate data to a first microvault of the plurality of microvaults.

62. The integrated circuit according to claim 61, wherein the data register is a read data register.

63. The integrated circuit according to claim 61 , wherein the data register is a write data register.

64. The integrated circuit according to claim 61, wherein the data register is a read / write data register.

65. The integrated circuit according to claim 1 , wherein a first microvault comprises at least one column of 3D-NORs formed from a plurality transistors, wherein each transistor includes a gate coupled to a read-write enable, a source coupled to a bit line, and a drain coupled to a select line.

66. The integrated circuit according to wherein 1, wherein a first micro vault comprises a column of 3D-NANDs formed from a plurality of transistors, each transistor having a gate coupled to a read / write enable line, a source coupled to a bit line, and a drain coupled to a source of a second transistor.Attorney Docket: P25-061-SEC-W00167. The integrated circuit according to claim 1, wherein a first microvault comprises a column of 3D-NANDs with a pass gate formed from a plurality of transistors, each transistor having a gate coupled to a read / write enable line, a source coupled to a bit line, a drain coupled to a source of a second transistor, and a pass gate coupled to all of the plurality of transistors.

68. The integrated circuit according to claim 1 , wherein a first microvault comprises a column of 3D-NORs with independent read and write enables formed from a plurality of transistors, wherein each transistor includes a source coupled to a bit line, a drain coupled to a read enable line, and a gate coupled to a write enable line.

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