A stacked structure cascaded GaN-based power device and packaging method thereof

Abstract

The present invention provides a stacked cascade GaN-based power device and a packaging method thereof. The device structure is a DBC double-sided ceramic substrate with through holes and grooves bonded on a TO-220 frame, a GaN-based chip bonded in the groove of the DBC ceramic substrate, and a vertically structured silicon-based MOSFET stacked on the source of the GaN-based chip to form a Cascode cascade structure. The present invention realizes the Cascode cascade structure by rationally arranging the GaN-based chip and the silicon-based MOSFET chip, thereby reducing the area of ​​the frame occupied by the chip, reducing the volume of the package body and improving the selectivity of the packaging form; the high thermal conductivity DBC double-sided ceramic substrate with through holes and groove structures increases the contact area between the chip and the high thermal conductivity material, improves the heat dissipation performance of the chip, optimizes the process steps, and improves the reliability and practicality of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a GaN-based power device and a packaging method thereof. Background Art

[0002] Since the 20th century, the fields of mobile communications, electronic automobiles, large-scale automated industrial production have flourished, and higher requirements have been placed on the corresponding electronic systems. As an indispensable core component in electronic systems, power electronic devices are one of the main directions for improving system performance. In order to meet the requirements of electronic system applications, power devices are developing in the direction of high voltage, high current, high frequency, high integration and intelligence. GaN power devices have become a hot spot in the field of power electronic devices due to their large bandgap width, high saturated electron mobility, high thermal conductivity and other excellent properties. The most mature of these is the HEMT (high electron mobility transistor) made based on GaN materials.

[0003] GaN HEMT mainly has two working modes: enhancement mode and depletion mode. Among them, the current preparation process of high-voltage GaN HEMT in single-cell enhancement mode is not mature, and the prepared devices still have many problems, such as small gate voltage swing and unstable threshold voltage, which affect the reliability of the device and its large-scale use. The single-cell depletion mode is a mode naturally formed in the preparation process of GaNHEMT, which has good stability and mature preparation process. Moreover, the single-cell depletion mode GaN HEMT can easily achieve a high voltage with a breakdown voltage of more than 600V and has the characteristics of a wide range of driving power supplies. Therefore, single-cell depletion mode GaN HEMT has more advantages in high-voltage and high-power applications. However, the depletion mode is turned on when the gate is not biased, causing the system to continuously consume energy, which greatly increases the static power consumption of the system compared to the enhancement mode. Therefore, it is very necessary to form an enhancement mode by cascading a high-voltage depletion mode GaN HEMT with a low-voltage enhancement mode silicon-based MOS tube.

[0004] Figure 1 The schematic diagram of a hybrid tube with forward turn-on voltage enhancement mode formed by cascading GaN HEMT and silicon-based MOS tube. The left side is a low-voltage silicon-based MOS tube, which controls the conduction and shutdown of the entire hybrid tube; the right side is a high-voltage depletion GaN-based HEMT chip, which plays a role in withstanding high voltage when the hybrid tube is turned off.

[0005] Figure 2 yes Figure 1One of the commonly used implementation methods in the prior art. For example, in an existing invention patent: A GaN-based cascade power device and its packaging method (application number: 201810953473.1), this technology uses a TO-220FL copper frame as a packaging frame, and the high-voltage depletion-type GaN HEMT and the silicon-based MOSFET are respectively bonded to the right and left sides of the frame base island through insulating glue. The GaN HEMT gate (G2) and the silicon-based MOSFET source (S1) are directly electrically connected to the frame base island through copper wires and aluminum wires, respectively. Since the frame base island is the source (S) of the hybrid tube and the drain (D1) of the low-voltage MOS tube with a vertical structure is at the bottom of the chip, according to Figure 1 Circuit connection method: the drain of the silicon-based MOS tube (D1) cannot be directly bonded to the frame base island. This technology uses a silver paste process to bond the MOS tube to a metal substrate and then uses insulating glue to bond the metal plate to the frame base island, so as to lead out the drain of the MOS tube without being electrically connected to the source (S) of the hybrid tube.

[0006] The disadvantages of the above technologies are:

[0007] 1. The high-voltage depletion-mode GaN HEMT and silicon-based MOSFET are placed on the right and left sides of the frame base island respectively. This arrangement requires the area of ​​two chips. In addition, the GaN chip is a high-power device with a relatively large chip area. This often leads to problems such as limited design of package layout and wiring, limited frame selection, and a large package volume that does not meet application requirements.

[0008] 2. The vertical structure MOS tube is bonded to the small copper substrate through silver paste, and the small copper substrate is bonded to the frame base island through insulating glue. This method has many process steps and low reliability. When the insulating glue is insufficient or unevenly distributed, it is easy to cause a short circuit between the metal substrate and the frame base island.

[0009] 3. The gate of the MOS tube is far away from the frame gate pin, and the copper wire has a small diameter, which may cause problems during the wire bonding process. In addition, wire punching or even wire breakage may occur during the subsequent plastic encapsulation process, leading to device failure.

[0010] 4. The small copper substrate used is prone to oxidation during the curing process of silver paste and insulating glue, which reduces the subsequent conductive performance and bonding stability.

[0011] 5. When using a copper frame for packaging, the frame is easily oxidized during high-temperature curing after using the insulating glue process and the silver paste process. In addition, when bonding the gate copper wire, preheating in the rail of the pressure welding machine will also cause frame oxidation. After the frame is oxidized, copper oxide is generated on the surface, making it difficult to bond the copper wires connecting the silicon-based MOS tube to the gate of the GaN power device and the copper wires connecting the source of the silicon-based MOS tube to the frame base island. The second solder joint will become cold or desoldering, causing the device to fail. Summary of the invention

[0012] In view of the above problems, the present invention provides a stacked structure cascaded GaN-based power device and a packaging method thereof. The method uses a smaller frame base island area to achieve cascade structure packaging, which provides more options for packaging frame and chip layout and wiring.

[0013] The stacked structure cascaded GaN-based power device provided by the present invention comprises a GaN-based high-voltage depletion-mode HEMT chip, a vertical low-voltage enhanced silicon-based MOSFET, a TO-220 frame, a DBC double-sided ceramic substrate with through holes and grooves, and a high thermal conductivity plastic packaging material. The DBC double-sided ceramic substrate with through holes and grooves is bonded on the TO-220 frame, the GaN-based chip is bonded in the groove of the DBC ceramic substrate, and the vertical silicon-based MOSFET is stacked on the source of the GaN-based chip to form a cascode cascade structure.

[0014] The present invention is achieved through the following technical solutions.

[0015] The present invention provides a stacked structure cascaded GaN-based power device, which comprises a GaN-based chip, a silicon-based MOSFET chip, a TO-220 frame and a DCB double-sided ceramic substrate provided with through holes and grooves.

[0016] The stacked structure refers to stacking the silicon-based MOSFET chip on the GaN-based chip in a cascade manner, which plays a role in reducing chip layout space and reducing the use of internal leads.

[0017] The DBC double-sided copper-clad ceramic substrate with through holes and grooves has copper clad on the entire back surface, and two copper-clad conductive substrates are provided on the front surface. One of the copper-clad conductive substrates is electrically connected to the copper-clad layer on the back of the substrate through the through hole; the groove is placed on the front surface of the DBC ceramic substrate, the depth of the groove is shallower than the thickness of the DBC substrate and is not electrically connected to the copper-clad plate on the back surface.

[0018] The base island of the TO-220 frame is connected to the middle pin and is set as the source pin of the GaN-based power device, the left pin is set as the gate pin of the GaN-based power device, and the right pin is set as the drain pin of the GaN-based power device.

[0019] The two copper-clad conductive substrates are respectively a first copper-clad conductive substrate and a second copper-clad conductive substrate; the first copper-clad conductive substrate is electrically connected to the back copper-clad substrate through a through hole, and is connected to the source of the silicon-based MOSFET chip and the gate of the GaN chip through an inner lead; the second copper-clad conductive substrate is connected to the gate of the MOSFET chip and the gate pin of the TO-220 frame through an inner lead; and the drain pin of the TO-220 frame is directly connected to the drain of the GaN chip through an inner lead.

[0020] Preferably, the GaN-based HEMT chip is a horizontal structure high voltage depletion type n-channel HEMT (high electron mobility transistor) chip, the top surface of which includes a gate, a source, and a drain. The GaN-based HEMT has a size of 5000μm * 2400μm~6700μm * 3000μm and a thickness of 400μm~700μm.

[0021] Preferably, the silicon-based MOSFET is a vertical low-voltage enhancement type n-channel MOS tube, the gate and source are on the top surface of the chip, and the drain is on the bottom surface of the chip. The specific size of the silicon-based MOSFET is 1500μm * 1000μm~2500μm * 1500μm, and the thickness is 200μm~400μm.

[0022] Preferably, the DBC double-sided copper-clad ceramic substrate provided with through holes and grooves has the same size as the frame base island, with specific dimensions of 6000μm * 5000μm ~7300μm * 6300μm, and a thickness of 600μm-800μm, which includes the thickness of the back copper-clad plate and the front conductive substrate; the through holes are filled with copper metal, and electrically connect the back copper-clad layer where the through holes of the DBC ceramic substrate are located and the first copper-clad conductive substrate.

[0023] Preferably, the surfaces of the first copper-clad conductive substrate and the second copper-clad conductive substrate on the front side of the DBC ceramic substrate are immersion gold or silver plated.

[0024] The packaging method of the stacked structure cascaded GaN-based power device provided by the present invention comprises the following steps:

[0025] (1) Bond the DBC ceramic substrate to the frame base island through conductive solder, with the back side facing down and the front side facing up, so that the copper clad plate on the back of the substrate is electrically connected to the frame base island;

[0026] (2) Bonding the GaN HEMT chip to the groove of the DBC ceramic substrate through an insulating adhesive process;

[0027] (3) Place the silicon-based MOSFET with the front side facing up and the back side facing down, and bond it to the GaN source electrode using a high-conductivity silver paste to form a stacked cascade structure;

[0028] (4) The drain of the GaN HEMT chip is electrically connected to the drain pin of the frame through an aluminum wire, the gate of the silicon-based MOSFET is electrically connected to the second copper-clad conductive substrate through a copper wire, the second copper-clad conductive substrate is electrically connected to the source pin of the frame through an aluminum wire, the source of the silicon-based MOSFET is electrically connected to the first copper-clad conductive substrate through an aluminum wire, and finally the stacked structure cascaded GaN-based power device is obtained by plastic encapsulation.

[0029] Preferably, the conductive solder is solder paste or lead-tin-silver solder with a thickness of 30-50 μm, and the insulating glue and high-conductivity silver paste have a thickness of 20-40 μm.

[0030] Preferably, the copper wire has a diameter of 25 μm-50 μm, and the aluminum wire has a diameter of 100 μm-200 μm.

[0031] Compared with the prior art, the present invention has the following beneficial effects and advantages:

[0032] (1) The present invention provides a new chip layout method, which can stack silicon-based MOS tubes on the source of GaN HEMT chips in a cascade manner. Compared with the prior art, GaN chips and silicon-based MOSFET chips of the same size are laid out on the same plane, which greatly saves chip layout space, makes the packaging form more selective, and further reduces the volume of the package body;

[0033] (2) The DBC ceramic substrate used in the present invention is a material with high thermal conductivity. A groove is dug in the middle of the ceramic substrate and the chip is placed in the groove so that the chip can fully contact with the ceramic material, thereby forming good heat diffusion;

[0034] (3) The present invention uses a DBC double-sided copper-clad ceramic substrate with through holes, and a partial electrode copper-clad layer has been made on the ceramic base island, which reduces the complexity of the process steps in the packaging process and reduces the precision requirements for the pressure welding machine; and the surface of the copper-clad conductive substrate is silver-plated to increase solderability and prevent the copper-clad board from being unable to be bonded due to oxidation, thereby further improving product reliability.

[0035] (4) The gate lead of the present invention is first led out through a conductive substrate and then electrically connected to the pin using an aluminum inner lead, thereby shortening the length of the inner lead and making it less likely for the gate lead to break during punching in subsequent processes, thereby increasing device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is the circuit schematic diagram of the cascade connection of HEMT chip and silicon-based MOSFET chip;

[0037] Figure 2 A schematic diagram of an existing cascade GaN packaging technology;

[0038] Figure 3 A schematic top view of a stacked structure cascaded GaN-based power device according to an example of the present invention;

[0039] Figure 4 , Figure 5 , Figure 6 They are respectively a top view, a front view, and a left view of a DBC ceramic substrate used in an example of the present invention;

[0040] Figure 7 , Figure 8 It is a schematic diagram of the preparation process of the stacked cascade structure GaN-based power device in the example of the present invention;

[0041] The figure shows: a DCB double-sided ceramic substrate 1, a first conductive copper-clad substrate 2, a through hole 3, a second conductive copper-clad substrate 4, a groove 5, a back copper-clad substrate 6, an aluminum oxide insulating layer 7, a GaN HEMT 8, a silicon-based MOSFET 9, an aluminum inner lead 10, and a copper inner lead 11. DETAILED DESCRIPTION

[0042] The specific implementation of the present invention is further described below in conjunction with examples, but the implementation and protection of the present invention are not limited thereto. It should be noted that if there are processes that are not particularly described in detail below, they can be implemented or understood by those skilled in the art with reference to the prior art.

[0043] Example 1

[0044] like Figure 3 As shown, a stacked cascade structure GaN-based power device includes: a GaN HEMT (high-voltage depletion-mode GaN-based HEMT chip) 8, a silicon-based MOSFET chip 9, a TO-220 frame and a DCB double-sided ceramic substrate 1 with through holes 3 and grooves 5.

[0045] The stacked structure refers to the silicon-based MOSFET chip 8 Figure 1 The circuit schematic diagram uses a cascode cascade method to stack on a GaN-based HEMT chip 8. Compared with the conventional method of placing two chips on the same horizontal plane, this stacked chip layout method can significantly reduce the space required for chip layout, leaving more room for the selection of chip packaging frame and chip layout and wiring.

[0046] The GaN-based HEMT8 chip is a horizontally structured high-voltage depletion-type n-channel HEMT (high electron mobility transistor) chip. The top surface includes a gate (G2), a source (S2), and a drain (D2), and the bottom surface is a silicon substrate. Its specific dimensions are 5000μm * 2400μm, with a thickness of 400μm. The source (S2) size is approximately 4300μm * 1200μm, the drain (D2) size is approximately 4800μm * 650μm, and the gate (G2) size is approximately 300μm * 500μm.

[0047] The silicon-based MOSFET 9 is a vertical low-voltage enhancement type n-channel MOS tube, with the gate (G1) and source (S1) on the top surface of the chip, and the drain (D1) on the bottom surface of the chip. Its specific size is 1900μm * 1100μm, the thickness is 240μm, the source (S1) size is about 1450μm * 960μm, the drain (D1) size is about 1760μm * 960μm, and the gate (G1) size is about 250μm * 300μm.

[0048] like Figure 4 , Figure 5 , Figure 6 As shown, the back of the DBC double-sided copper-clad ceramic substrate 1 with through holes and grooves is covered with copper 6. The existence of the copper-clad layer greatly improves the conductivity of the through holes connected to the frame base island; in addition, two copper-clad electrode pads are provided on the front of the ceramic substrate, namely the first conductive copper-clad substrate 2 and the second conductive copper-clad substrate 4. The first conductive copper-clad substrate is electrically connected to the back of the substrate through the through hole, which facilitates the subsequent silicon-based MOSFET to connect the source (S1) to the frame base island through the inner lead; the surfaces of the first conductive copper-clad substrate 2 and the second conductive copper-clad substrate 4 are both silver-plated, so that the substrate has anti-oxidation ability and increases solderability; there is also a groove on the front of the DBC ceramic substrate, the depth of which is shallower than the thickness of the DBC substrate and is not electrically connected to the back copper-clad substrate. The size of the DBC ceramic substrate is 6000μm * 5000μm * 800μm, of which the thickness of the DBC ceramic substrate is 800μm, including a 100μm copper clad layer on the back, a 600μm alumina ceramic layer (alumina insulating layer 7,), and two conductive copper clad electrodes on the front with a thickness of 100μm; the size of the groove is 5100μm * 2500μm * 400μm. Specifically, according to the calculation results of the fuse current, the size of the first copper clad conductive substrate 2 is designed to be 4400μm * 400μm * 100μm, of which the thickness is 100μm; the size of the second copper clad conductive substrate 4 is 400μm * 2250μm * 100μm, of which the thickness is 100μm; the aperture size of the through hole 3 is 200μm, and the copper metal is filled inside, and the size of the back copper clad board 6 is 6000μm * 5000μm * 100μm.

[0049] The selected TO-220 frame has a base island size of 6000μm * 5000μm. The base island is connected to the middle pin and is set as the source (S) pin of the GaN-based power device. The left pin is set as the gate (G) pin of the GaN-based power device, and the right pin is set as the drain (D) pin of the GaN-based power device.

[0050] Specifically, the first conductive copper-clad substrate 2 is connected to the source (S1) of the silicon-based MOSFET chip 9 and the gate of the GaN chip 8 through inner leads; the second conductive copper-clad substrate 4 is connected to the gate (G1) of the MOSFET chip 9 and the gate (G) pin of the TO-220 frame through inner leads; and the drain (D) pin of the TO-220 frame is directly connected to the drain (D2) of the GaN chip 8 through inner leads.

[0051] Figure 7 , Figure 8 This is a schematic diagram of a manufacturing process of a stacked cascade structure GaN-based power device in an example of the present invention, comprising the following steps:

[0052] 1) Fix the HEMT wafer and silicon-based MOSFET wafer with a blue film and an iron ring frame, and then send them to a dicing machine to separate them into single chips; the HEMT wafer material is relatively hard and the cutting line is 100μm, so a dicing knife with high hardness is required for cutting, while the silicon-based MOSFET wafer material is relatively soft and the cutting line is 60μm, so a normal specification blade can be used for cutting.

[0053] 2) The DBC ceramic substrate is bonded to the frame base island through solder paste at a temperature of 370°C, with the back side facing down and the front side facing up, so that the copper clad plate on the back of the substrate is electrically connected to the frame base island.

[0054] 3) Place the GaN chip through the insulating glue Figure 7 As shown, it is bonded to the groove of the DBC ceramic substrate, and the thickness of the insulating glue is about 20-40μm.

[0055] 4) Silicon-based MOSFETs Figure 8 The front side faces up and the back side faces down, and is bonded to the GaN source electrode through high-conductivity silver paste to form a stacked cascade structure. The thickness of the silver paste is about 20-40μm.

[0056] 5) After the bonding is completed, put it into the oven for 3 hours at a baking temperature of 175°C. During the baking process, keep the oven in a nitrogen environment and ensure that the oxygen content in the oven is below 100ppm. After baking, wait until it cools down to room temperature before taking it out.

[0057] 6) After setting the ultrasonic, pressure, time and temperature of the welding machine, send the chip to be welded into the guide rail and then Figure 3The lead connection method shown is used for welding. Specifically, the GaN drain (D2) is electrically connected to the frame drain (D) pin through four aluminum wires with a wire diameter of 150 μm; the silicon-based MOSFET gate (G1) is electrically connected to the second conductive substrate 4 through a copper inner lead 11 with a wire diameter of 25 μm, the second conductive substrate 4 is electrically connected to the frame gate (G) pin through an aluminum inner lead 10 with a wire diameter of 150 μm, and the silicon-based MOSFET source (S) is electrically connected to the first conductive substrate (2) through four aluminum wires with a wire diameter of 150 μm, completing the pressure welding.

[0058] 7) The chip after steps 1-6 is further subjected to injection molding, packaging, overflow removal, tinning, and separation to obtain a finished product.

[0059] The above embodiments are only preferred implementation modes of the present invention and are only used to explain the present invention rather than to limit the present invention. Any changes, substitutions, modifications, etc. made by those skilled in the art without departing from the spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A stacked structure cascaded GaN-based power device, characterized in that: The invention comprises a GaN-based chip, a silicon-based MOSFET chip, a TO-220 frame and a DBC double-sided copper-clad ceramic substrate provided with through holes and grooves; the silicon-based MOSFET chip is stacked on the GaN-based chip in a cascade manner; the back surface of the DBC double-sided copper-clad ceramic substrate provided with through holes and grooves is entirely copper-clad, and two copper-clad conductive substrates are provided on the front surface; wherein the first copper-clad conductive substrate is electrically connected to the back surface of the DBC double-sided copper-clad ceramic substrate through the through holes; the groove is placed on the front surface of the DBC double-sided copper-clad ceramic substrate, the depth of the groove is shallower than the thickness of the DBC double-sided copper-clad ceramic substrate and is not electrically connected to the back copper-clad substrate; the TO-220 frame The base island is connected to the middle pin and is set as the source pin of the GaN-based power device, the left pin is set as the gate pin of the GaN-based power device, and the right pin is set as the drain pin of the GaN-based power device; the two copper-clad conductive substrates are respectively the first copper-clad conductive substrate and the second copper-clad conductive substrate; the first copper-clad conductive substrate is electrically connected to the back copper-clad substrate through a through hole, and is connected to the source of the silicon-based MOSFET chip and the gate of the GaN chip through an inner lead; the second copper-clad conductive substrate is connected to the gate of the MOSFET chip and the gate pin of the TO-220 frame through an inner lead; the drain pin of the TO-220 frame is directly connected to the drain of the GaN chip through an inner lead; The preparation of the stacked structure cascaded GaN-based power device comprises the following steps: (1) Bond the DBC double-sided copper-clad ceramic substrate to the frame base island through conductive solder, with the back side facing down and the front side facing up, so that the copper-clad plate on the back of the substrate is electrically connected to the frame base island; (2) The GaN-based chip is bonded to the groove of the DBC double-sided copper-clad ceramic substrate through an insulating adhesive process; (3) Place the silicon-based MOSFET with the front side facing up and the back side facing down, and bond it to the GaN source electrode using a high-conductivity silver paste to form a stacked cascade structure; (4) The drain of the GaN-based chip is electrically connected to the drain pin of the frame through an aluminum wire, the gate of the silicon-based MOSFET is electrically connected to the second copper-clad conductive substrate through a copper wire, the second copper-clad conductive substrate is electrically connected to the source pin of the frame through an aluminum wire, the source of the silicon-based MOSFET is electrically connected to the first copper-clad conductive substrate through an aluminum wire, and finally the stacked structure cascaded GaN-based power device is obtained by plastic encapsulation.

2. The stacked structure cascaded GaN-based power device according to claim 1, characterized in that: The GaN-based chip is a horizontally structured high-voltage depletion-type n-channel HEMT chip; the top surface of the GaN-based chip includes a gate, a source and a drain; the size of the GaN-based chip is 5000μm*2400μm~6700μm*3000μm, and the thickness is 400μm~700μm.

3. The stacked structure cascaded GaN-based power device according to claim 1, characterized in that: The silicon-based MOSFET is a vertical low-voltage enhancement type n-channel MOS tube; the gate and source are on the top surface of the chip, and the drain is on the bottom surface of the chip. The size of the silicon-based MOSFET is 1500μm*1000μm~2500μm*1500μm, and the thickness is 200μm~400μm.

4. The stacked structure cascaded GaN-based power device according to claim 1, characterized in that: The size of the DBC double-sided copper-clad ceramic substrate with through holes and grooves is the same as that of the TO-220 frame base island; the size of the DBC double-sided copper-clad ceramic substrate with through holes and grooves is 6000μm * 5000μm~7300μm * 6300μm, and the thickness is 600μm-800μm; the thickness includes the thickness of the back copper-clad board and the front conductive substrate; the through holes are filled with copper metal, and electrically connect the back copper-clad layer and the first copper-clad conductive substrate where the through holes of the DBC double-sided copper-clad ceramic substrate are located.

5. The stacked structure cascaded GaN-based power device according to claim 4, characterized in that: The surfaces of the first copper-clad conductive substrate and the second copper-clad conductive substrate on the front side of the DBC double-sided copper-clad ceramic substrate are immersion gold or silver plated.

6. A packaging method for a stacked structure cascaded GaN-based power device according to any one of claims 1 to 5, characterized in that: The steps include: (1) Bond the DBC double-sided copper-clad ceramic substrate to the frame base island through conductive solder, with the back side facing down and the front side facing up, so that the copper-clad plate on the back of the substrate is electrically connected to the frame base island; (2) The GaN-based chip is bonded to the groove of the DBC double-sided copper-clad ceramic substrate through an insulating adhesive process; (3) Place the silicon-based MOSFET with the front side facing up and the back side facing down, and bond it to the GaN source electrode using a high-conductivity silver paste to form a stacked cascade structure; (4) The drain of the GaN-based chip is electrically connected to the drain pin of the frame through an aluminum wire, the gate of the silicon-based MOSFET is electrically connected to the second copper-clad conductive substrate through a copper wire, the second copper-clad conductive substrate is electrically connected to the source pin of the frame through an aluminum wire, the source of the silicon-based MOSFET is electrically connected to the first copper-clad conductive substrate through an aluminum wire, and finally the stacked structure cascaded GaN-based power device is obtained by plastic encapsulation.

7. The packaging method according to claim 6, characterized in that: The conductive solder in step (1) is solder paste or lead-tin-silver solder with a thickness of 30-50 μm; the thickness of the insulating glue in step (2) is 20-40 μm; the thickness of the high-conductivity silver paste in step (3) is 20-40 μm.

8. The packaging method according to claim 6, characterized in that: In step (4), the wire diameter of the copper wire is 25 μm-50 μm, and the wire diameter of the aluminum wire is 100 μm-200 μm.

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