Charge pump and active loop filter with shared unity-gain buffer

Abstract

The present invention discloses a unity gain buffer shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses a unity gain buffer to reduce current mismatch in the charge pump, while the active loop filter uses a unity gain buffer in the circuit, which increases the effective capacitance of the active loop filter.

Description

Technical Field

[0001] The present disclosure relates to generating clock signals, and more particularly, to generating clock signals in a phased-locked loop (PLL) with different power and jitter settings. Background Art

[0002] Analog-to-digital converters (ADCs) based on continuous-time delta-sigma modulators are widely used in radio frequency (RF) receiver (RX) applications. Typically, a high-order delta-sigma modulator-based ADC using a reference clock (e.g., a crystal oscillator) or a less complex low-order delta-sigma ADC with a higher clock rate is used. For the second case, one solution generates the ADC clock from a divided local oscillator (LO) clock. However, the LO clock signal can vary depending on the tuning channel, causing the ADC sampling frequency to vary, complicating the modem design. Another approach uses a phased-locked loop (PLL) circuit as the ADC's clock multiplier. These PLLs are typically not optimized for delta-sigma ADCs, and therefore consume high power and occupy a large die area, increasing cost. Summary of the Invention

[0003] A phase-locked loop (PLL) can be used to independently provide a fixed-rate clock to the ADC in the RX signal chain, simplifying the modem design and advantageously reducing the power consumption in the dedicated PLL.

[0004] In one embodiment, a phase-locked loop (PLL) includes a charge pump that provides charge based on a difference between a reference signal and a feedback signal provided by a phase and frequency detector. An active loop filter is coupled to an output node of the charge pump. A unity-gain buffer is coupled for use in the charge pump and the active loop filter.

[0005] In another embodiment, a method for operating a phase-locked loop (PLL) includes generating a signal indicative of a difference between a reference signal and a feedback signal in a phase and frequency detector, and providing the signal indicative of the difference to a charge pump. The method also includes using a unity gain buffer in the charge pump and a unity gain buffer in an active loop filter, and generating a filtered oscillator control signal using the charge pump and the active loop filter.

[0006] In another embodiment, a phase-locked loop (PLL) includes a phase and frequency detector (PFD) configured to provide a PFD signal indicating a difference between a reference signal and a feedback signal. A charge pump provides a current to an output node of the charge pump based on the PFD signal. An active loop filter is coupled to the output node of the charge pump, the active loop filter increasing the effective capacitance of a capacitor in the active loop filter. A unity gain buffer is coupled as part of the charge pump to reduce mismatch in the charge pump, and the unity gain buffer is further coupled as part of the active loop filter. The charge pump includes a first transistor coupled between a first current source and the output node of the charge pump; a second transistor coupled between a second current source and the output node of the charge pump; a third transistor coupled between the first current source and a fourth transistor; and a fourth transistor coupled between the third transistor and the second current source. A positive input terminal of the unity gain buffer is coupled to the output node of the charge pump via a first resistor of the active loop filter. A second resistor of the active loop filter is coupled between the output node of the charge pump and an output terminal of the unity gain buffer. The capacitor of the active loop filter is connected between the positive input terminal of the unity gain buffer and ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0008] Figure 1a A PLL is shown providing a clock signal to the ADC operating in full rate mode.

[0009] Figure 1b A PLL is shown providing a clock signal to an ADC operating in less than full rate mode.

[0010] Figure 2a A PLL with a full-rate voltage control oscillator (VCO) is shown providing a full-rate clock signal to the ADC.

[0011] Figure 2b A PLL with a full-rate VCO and a divider on the PLL output to provide a lower rate clock signal to the ADC is shown.

[0012] Figure 2c A PLL with a lower rate VCO is shown, which provides a lower rate clock signal to the ADC without using a divider.

[0013] Figure 3aAn RX signal chain including an amplifier and an ADC is shown, where the PLL providing the clock signal to the ADC is configured to set the amplifier gain to maximum.

[0014] Figure 3b An RX signal chain including an amplifier and an ADC is shown, wherein the PLL providing the clock signal to the ADC is configured to set the amplifier gain to less than a maximum value.

[0015] Figure 4 A block diagram of a PLL with multiple VCOs is shown according to one embodiment.

[0016] Figure 5 A portion of a PLL is shown showing control signals for a plurality of VCOs.

[0017] Figure 6a Shown is a block diagram of one of the PLL VCOs implemented as a ring oscillator according to an embodiment.

[0018] Figure 6b Shown is a block diagram of another one of the PLL VCOs implemented as a ring oscillator according to an embodiment.

[0019] Figure 7 Shown Figure 6a and 6b Various possible settings of the VCO are shown.

[0020] Figure 8 A conventional loop filter topology is shown.

[0021] Figure 9a A passive loop filter is shown.

[0022] Figure 9b An active loop filter is shown.

[0023] Figure 10a A conventional charge pump is shown.

[0024] Figure 10b The charge pump and active loop filter are shown.

[0025] Figure 11 A charge pump and loop filter topology with a shared unity gain buffer is shown according to an embodiment.

[0026] Figure 12 The use of a charge pump and loop filter topology in an embodiment of a PLL with multiple VCOs is shown.

[0027] Figure 13 The use of a charge pump and loop filter topology in an embodiment of a PLL with a single VCO is shown.

[0028] The use of the same reference numbers in different drawings indicates similar or identical items. Specific embodiments

[0029] Embodiments described herein provide a phase-locked loop (PLL) specifically for clock generation of a continuous time delta-sigma modulator (ADC) in a radio frequency receiver (RF RX) signal chain. For a given power budget, the PLL minimizes far-end phase noise at the expense of a looser closure in the phase noise. The PLL may also be used in other applications. Embodiments provide a variable power PLL in which the PLL power consumption is selected based on the requirements of the ADC. For example, the PLL power may be scaled based on the input signal strength to the RX signal chain and / or based on the clock rate required by the ADC. Embodiments provide a fixed rate clock to the ADC, thereby avoiding the complexity of using a divided LO clock, thereby simplifying the design of the modem.

[0030] In one embodiment, for a 2 MHz bandwidth, the ADC clock rate is approximately 307.2 MHz. The integrated 2 MHz ADC noise bandwidth is primarily used in Zigbee applications. The 1 MHz bandwidth, for an ADC clock rate of approximately 153.6 MHz, is primarily used in Bluetooth applications; however, both bandwidth settings are generally usable over a wide range of data rates, e.g., 100 kbps to 2 Mbps FSK modulated signals or lower. Some embodiments assume a crystal frequency of 38.4 MHz. Due to high-frequency jitter, the jitter-limited signal-to-noise ratio (SNR) depends primarily on in-band quantization noise folding. As is known in the art, jitter is the deviation of a clock signal edge from its ideal position. Higher clock rates require lower jitter in the PLL (e.g., doubling the frequency requires less than a factor of two reduction in jitter, assuming the shape of the noise transfer function (NTF) simply scales with frequency—e.g., by doubling the size of the loop filter capacitor, the NTF is reduced by a factor of two). Note that for a PLL used for clock generation of a continuous-time delta-sigma modulator, minimizing the PLL high-frequency jitter is more important than optimizing the overall jitter, so embodiments can focus on an efficient voltage-controlled oscillator (VCO) design, keeping the charge pump (CP), loop filter, phase frequency detector (PFD), and feedback divider area and / or power consumption low. Thus, embodiments are motivated to reduce high-frequency jitter because low-frequency jitter is not as critical for some applications. Embodiments utilize a clock frequency scaling scheme for both full-rate and half-rate ADC operation. In half-rate mode, the ADC clock frequency is scaled by a factor of two compared to full-rate mode. However, the frequency adjustment is not accomplished via the VCO output divider. Instead, the feedback division ratio is reduced by a factor of two, and a lower-power VCO is used instead of the VCO used for full-rate operation. Because the jitter requirements of the ADC are relaxed in half-rate mode, this approach results in lower overall total power consumption.

[0031] In addition, in principle, the jitter number can be relaxed when the input signal power is higher, for example, by RX gain compensation. Low jitter is required especially when the input signal level is close to the sensitivity level. The sensitivity level is the level at which acceptable signal detection occurs. For larger input signals (higher SNR), the allowed jitter may be higher. Therefore, an embodiment uses a PLL power scaling technique based on the received signal power. When the signal chain gain falls back from its maximum value to or below the threshold gain setting, the full-rate VCO will be replaced by a low-power version (which has higher jitter). When the signal power is higher, using a lower-power VCO with higher jitter can save power.

[0032] If the ADC noise transfer function scales 1-1 when the clock frequency is reduced (e.g., fclk = 320 MHz to fclk = 160 MHz), the jitter specification can be relaxed by the same or similar amount. That is, twice as much jitter can be tolerated at the lower clock frequency. This allows the use of a lower power PLL to produce an output signal with higher jitter content. See Figure 1a Assuming that ADC 101 is in full-rate state, PLL 103 (also called clock multiplier unit (CMU) because it scales up the input reference clock) has a power utilization of P1 and a jitter specification of Jitter1, and PLL 103 provides ADC clock 105 with a frequency of fclk1. PLL 103 multiplies the reference clock signal CLKin with a frequency of fref to obtain ADC clock 105 with a frequency of fclk1. The PLL multiplies the reference clock CLKin by N based on the feedback divider. Therefore, the frequency of the ADC clock (fclk) = N × fref. Figure 1b If the clock frequency requirement of ADC 107 is reduced (e.g., from 320 MHz to 160 MHz), the lower-power PLL 109 provides an ADC clock 111 (ADCclk2) having a frequency of fclk2. PLL 109 multiplies the reference clock signal CLKin having a frequency of fref to obtain ADC clock 111 having a frequency of fclk2. PLL 109 has a power utilization of P2 and a jitter specification of Jitter2. The frequency fclk2 < fclk1, and the power utilization P2 < P1. Therefore, a lower-power PLL can be used, which provides a lower-frequency ADC clock with a higher jitter component. As described above, the jitter still meets the ADC requirements.

[0033] Reference Figure 2a, the illustrated embodiment utilizes a PLL 201 with a full-rate VCO to provide a full-rate ADC clock (ADCclk1 ) 203 to an ADC 205 . Figure 2b It is shown that the output divider 207 can be used in conjunction with the PLL 201 having a full rate VCO to provide an ADC clock (ADclk2) 209 having a lower frequency than the ADC clock (ADCclk1) 203. However, Figure 2b The method requires the use of PLL 201 with a full-rate VCO and divider 207, which consumes unnecessary power. Figure 2c An embodiment is shown in which the lower rate clock 215 is provided to the ADC 217 directly from a PLL 219 using a lower rate VCO. The PLL 219 uses a lower power VCO specifically designed to provide a lower rate ADC clock. The PLL 219 uses less power than the PLL 201 and is Figure 2c In the embodiment shown, the divider 207 is omitted entirely, thereby saving additional power.

[0034] In an embodiment, PLL power scaling is performed based on the power of the input signal. Figure 3a , PLL 301 and ADC 303 are used as part of the RX signal chain. The signal chain includes a receive amplifier 305, whose gain setting is set by a gain control signal 307. Note that gain block 305 represents the various gain blocks (e.g., the gains of the front-end passive network, low noise amplifier (LNA), and programmable gain amplifier (PGA)) in a typical receiver as a single block for illustration. The gain setting provides information indicating whether the power level of input signal 309 is close to the sensitivity level Psens. That is, if the input signal power Pin causes the input signal to approach the minimum signal power sensitivity level Psens required for accurate sensing of the input signal, the gain setting of amplifier 301 is set to the maximum gain factor G1 (G1=Gmax). When the gain factor is set to G1 (which corresponds to maximum gain), the system consumes power P1 using PLL 301 and generates a clock signal with jitter Jitter1.

[0035] However, if Pin > Psens (e.g., at least a few dB greater), the amplifier gain signal 307 is decreased to reduce the gain of the amplifier 305. The decreased gain setting indicates that the jitter specification can be relaxed as the overall quantization + thermal noise limited SNR increases. This means that the ADC can tolerate a clock signal with a larger jitter component. In this case, the system will switch to a lower power VCO. Figure 3bIf the gain of amplifier 305 is set to G2 < Gmax, the system uses PLL 315 with a power utilization of P2 and jitter equal to Jitter2, Jitter2 > Jitter1. In addition, the power of the input signal Pin2 > Pin1, which allows a smaller gain factor G2 < Gmax. A smaller gain factor means that PLL 315 can use a VCO that generates a clock signal with a higher jitter component. Therefore, PLL 315 provides a clock signal with a higher jitter component than clock signal 311 ( Figure 3a ) a clock signal 317 of the same frequency (fclk) as that of the first embodiment, but with greater jitter. Using a higher jitter clock signal allows the use of a lower power PLL.

[0036] Figure 4 A block diagram of a PLL (or CMU) 400 according to an embodiment is shown. PLL 400 includes a phase and frequency detector (PFD) 401, which compares a reference clock 403 with a feedback clock 405 and, based on the comparison, provides an UP or DN signal to a charge pump 407. The charge pump provides a loop filter 409, which provides an oscillator control signal 411 to a low-jitter oscillator (VCO1) 415 and a low-power oscillator (VCO2) 417. A selector circuit 419 selects the output of either VCO1 415 or VCO2 417 as the output clock signal 421 of PLL 400. Thus, a single PLL is selected between the VCOs to achieve the desired power and jitter, rather than using separate PLLs. The output clock signal 421 is fed back to PFD 401 via a feedback divider 423. Feedback divider 423 divides the PLL output signal by N and provides the divided signal 405 to PFD 401. The choice of VCO1 415 or VCO2 417 as the output clock signal depends on the proximity of the input signal power to the sensitivity level and / or whether the ADC is running at half rate or full rate.

[0037] Despite Figure 4 In the embodiment shown, two VCOs are shown, but other embodiments may use additional VCOs. For example, in one embodiment, a third VCO has power consumption and jitter specifications between those of VCO1 and VCO2. For example, when the input signal power is above a predetermined level, but the dB above the sensitivity level (sufficiently high SNR) is not sufficient to warrant higher jitter in the low-power VCO2, but can still tolerate higher jitter than the low-jitter VCO1, the third VCO is selected, thereby achieving some power savings. For example, in embodiments where the ADC operates at a rate between full rate and half rate, the third VCO is also selected. In an embodiment, one or more VCOs that are not in use are powered down. For example, when VCO2 is in use, VCO1 is powered down, and when VCO1 is in use, VCO2 is powered down.

[0038] Figure 5 A high-level block diagram of a portion of a PLL 500 according to one embodiment is shown. The loop filter provides an oscillator control signal 501 to VCO1 515 and VCO2 517. A selector circuit 519 selects the output signal from one of the multiple VCOs as the PLL output signal based on a select signal Sel 520. The oscillator receives a mode signal 531, VCO1 receives a select signal Sel 532, and VCO2 receives the inverse of Sel 533. The select signals 532 and 533 can be independent of or dependent on the select signal 520. Although in Figure 5 Two VCOs are shown in FIG, but other embodiments may use other numbers of VCOs to suit a particular application. Thus, an embodiment may select between three VCOs with different power and jitter specifications.

[0039] Figure 6a An exemplary block diagram of VCO1 515 is shown. Oscillator 515 is a ring oscillator-based VCO with a programmable number of inverter stages. Mode signal 531 selects the delay through the ring oscillator by selecting the number of inverter stages. When the mode signal is 1, stage N1 is selected by multiplexer 601. When the mode signal is 0, stage N2 is selected, where N1 and N2 are integers. For a given control voltage Vctl, the number of stages selected by the mode signal determines the frequency of the output signal provided by VCO1. Select signal 532 determines whether the ring oscillator is active. If the select signal is zero, NAND gate 602 prevents the oscillator from oscillating. If the select signal is 1, the feedback signal controls the output of NAND gate 602, and the ring oscillator oscillates.

[0040] VCO1 utilizes an inverter chain with a larger device aspect ratio (width / length (W / L)) to provide lower jitter and phase noise. Using an inverter with a larger W / L aspect ratio causes VCO1 to consume more power compared to VCO2. VCO1 is used in higher ADC clock rate modes and lower jitter. For a given ADC SNR requirement, lower jitter is required in high-rate (full-rate) ADC mode. VCO1 is also selected when the RX chain input power approaches the sensitivity level.

[0041] Figure 6bAn exemplary block diagram of oscillator VCO2 517 is shown. Oscillator 517 is a ring oscillator-based VCO with a programmable number of inverter stages. Mode signal 531 selects a certain number of inverter stages. When the mode signal is 1, stage M1 is selected via multiplexer 603. When the mode signal is 0, stage M2 is selected, where M1 and M2 are different integers. Note that depending on the specific embodiment, M1 and N1 can be the same or different, and M2 and N2 can be the same or different. For a given control voltage Vctl, the number of stages selected by the mode signal determines the frequency of the output signal provided by VCO2. Signal 533 (selb) determines whether the ring oscillator is active. The signal is zero, then the NAND gate 604 prevents the oscillator from oscillating. It should be noted that if If the signal is zero, select 532 to 1, thus enabling VCO1. If the signal is 1, the feedback signal controls the output of the NAND gate 604 and the ring oscillator oscillates. In one embodiment, the unused oscillator is powered down to save power, rather than just preventing the oscillator from oscillating.

[0042] Compared to VCO1, VCO2 utilizes an inverter chain with a smaller device aspect ratio (W / L). This reduces power consumption compared to VCO1, but at the expense of higher jitter. VCO2 is used in lower clock rate ADC modes. For a given ADC SNR requirement, higher jitter can be tolerated at lower clock rates. Therefore, when higher jitter is tolerated and a lower power VCO can be utilized, VCO2517 is used in half-rate ADC mode. VCO2517 is also used when the RX chain input power is high (dB threshold above the sensitivity level).

[0043] although Figure 6a and 6b A ring oscillator is shown, but other embodiments may use different types of oscillators for VCO 1 and VCO 2. For example, in another embodiment, the oscillators are LC oscillators, which provide different power consumption and jitter levels.

[0044] Figure 7 Shown Figure 6a and 6bVarious possible settings for the VCO are shown. Asserting the select signal (Sel) 532 selects VCO1. In the case of mode = 0, VCO1 is configured to have more inverter stages, resulting in a lower oscillation frequency for a given control voltage Vctl. When a low rate is selected, the control voltage variation between two different frequency settings can be reduced by increasing the number of inverter stages. This mode and select setting (1, 0) is suitable for low-rate, low-jitter applications. The mode and select setting (1, 1) selects fewer inverter stages for VCO1 and is suitable for high-rate, low-jitter applications. Not asserting the select signal (Sel) 532 selects VCO2. In the case of mode = 0, VCO2 selects more inverter stages, resulting in a lower oscillation frequency for a given control voltage Vctl. Increasing the number of stages keeps the control voltage offset between the two oscillation frequencies small. This mode and select setting (0, 0) is suitable for low-rate, low-power, higher-jitter applications. The mode and select settings (0, 1) configure VCO2 to have a smaller inverter stage (higher frequency) and are suitable for high-speed, higher-jitter, low-power applications. For example, if the input power is sufficiently above the sensitivity level, a higher jitter level can be tolerated and a low-power VCO can be used.

[0045] Reference back Figure 4 , components of PLL 400 include a charge pump 407 and a loop filter 409 . Figure 8 A conventional loop filter topology for a Type II PLL is shown, which also includes higher order electrodes. The area of ​​capacitor Cz 801 is typically large, and therefore occupies a larger area. Additional circuitry 803 is included to provide higher order filtering.

[0046] Figure 9a shows an input impedance Z in (s)=R z +1 / sC z Passive loop filter 900. Figure 9b An active loop filter 902 with capacitor multiplication is shown, which reduces the size of capacitor Cz by a factor of N. The size of resistor 903 is set to R1 = NRz, where Rz is Figure 9a The active loop filter 902 further includes a unity gain buffer 905. A unity gain buffer is an amplifier for making the output voltage equal to the input voltage, that is, a unity gain buffer is an amplifier with a gain of 1. In the active filter 902, the size of the resistor 907 is set to The active loop filter and the passive loop filter have the same input impedance. That is, the active loop filter also has an input impedance Z in (s)=R z +1 / sC zUsing an active loop filter reduces the size of capacitor Cz to Cz / N. Therefore, the effective capacitance of an active loop filter with capacitor C increases by C eff = C(1+R1 / R2). For active filter implementations, larger N (e.g., N=10) requires smaller capacitors, resulting in significant savings in capacitor area at the expense of additional area and power consumption due to the unity gain buffer, additional resistor 907, and larger resistor 903. However, since the area of ​​the resistors in loop filter implementations is much smaller than the area of ​​capacitor Cz, the additional area penalty for the resistors is minimal. In various embodiments, PLL 400 includes loop filter 800 ( Figure 8 ), loop filter 900, or loop filter 902, or any suitable loop filter, to generate a control signal to control the VCO according to the requirements of a specific application.

[0047] In addition to the loop filter, Figure 4 The illustrated PLL 400 also includes a charge pump 407 . Figure 10a FIG4 shows a conventional implementation of a push-pull charge pump 1000 used in an embodiment of the PLL 400. Current sources 1001 and 1003 increase or decrease the charge provided according to the UP and DN signals provided from the PFD 401 (see FIG4 ). Figure 4 ). The UP and DN signals, and their complements, are provided as dnb, dn, up, and upb, respectively, to control transistors M1, M2, M3, and M4, respectively. Transistors M4 and M2 control the charging or discharging of charge stored in the loop filter capacitor of loop filter 900, respectively. It should be noted that transistor pair M4 and M3 are PMOS transistors controlled by an active-low gate control signal. Transistor pair M1 and M2 are NMOS transistors controlled by a higher active-gate control signal. When one transistor in the pair is off, the other transistor in the pair is on. Thus, for example, when both upb are high and both dn are low, and upb is low and dnb is high, transistors M3 and M1 are on, thereby providing a path between nodes 1002 and 1004. When only upb is asserted (active-low), loop filter capacitor Cz is charged through M4, and transistor M1 is on, thereby providing a path between nodes 1006 and 1004. When only dn is asserted, the loop filter capacitor Cz discharges through M2 and transistor M3 turns on to provide a path between nodes 1002 and 1006. Unity gain buffer 1005 forces the voltage Vx at node 1006 to follow the voltage on CPout node 1007, thereby helping to minimize offset current. Figure 10a A simple passive loop filter 900 is shown, but other embodiments use higher order loop filters (e.g., Figure 8Although passive loop filters are used in various embodiments, Figure 10b An embodiment is shown in which an active loop filter 1011 is used in conjunction with a unity gain buffer 1015. This allows the use of smaller capacitors (Cz / N).

[0048] Figure 11 An embodiment is shown having a new charge pump and active loop filter topology 1100 that has a lower overhead in terms of power and area. The topology can be used in various embodiments described herein, but can also be used in PLLs intended for other applications to save area and power. The new charge pump and loop filter implementation can reduce the area of ​​the loop filter while keeping the overall charge pump and active loop filter current low due to the shared use of unity gain buffers, as described below. Figure 11 The embodiment includes a charge pump and an active loop filter 1100, wherein a unity gain buffer 1105 is shared by the charge pump and the loop filter, thereby reducing the area required for the charge pump and the loop filter and the power consumed. In the charge pump and loop filter 1100 (also refer to Figure 9b and 10b ), resistor 1133 is used as loop filter resistor R1 = NRz. Resistor 1135 is used as resistor and capacitor 1131 is Cz / N. Thus, the unity gain amplifier 1105 acts as part of an active loop filter, allowing for a reduction in the capacitance area of ​​capacitor 1131, compared to a passive loop filter implementation. The unity gain buffer 1105 also forces the voltage at node 1137 to follow the output voltage CPout on node 1134, thereby minimizing the offset current in the charge pump. Note that Figure 11 and Figure 10b For example, in Figure 10b In FIG, there is no series resistor (e.g., resistor 1133) between the passive input of the unity gain buffer and CPout. However, for the intended purpose (node ​​1137 along with node 1134), Figure 11 The circuit is valid. At DC, the capacitor is an open circuit, so at low frequencies, the two methods are the same. The average Vx (node ​​1137) needs to follow the output (CPout, node 1134), which is Figure 11 can be realized.

[0049] Figure 12 An embodiment of a PLL 1250 is shown, wherein Figure 4The charge pump 407 and loop filter 409 are replaced by a charge pump / loop filter topology 1200 with a shared unity gain buffer 1201. Filter 1200 is identical to charge pump / loop filter 1100 except that current sources 1203 and 1205 are more symbolically shown in charge pump / loop filter 1200. Figure 12 In an embodiment of the present invention, the loop filter includes a higher order filtering component 1260. Charge pump / loop filter 1200 provides VCO control signal 1209 to VCOs 1215 and 1217, and multiplier 1221 selects one of VCOs 1215 and 1217 to provide the PLL output signal.

[0050] Figure 13 An embodiment is shown in which a charge pump / loop filter 1300 with a shared unity gain buffer 1301 controls a single VCO 1315 in a PLL 1350 .

[0051] Thus, various aspects have been described related to a unity gain buffer shared by a charge pump and an active loop filter, the PLL utilizing VCOs having different jitter and power specifications. The description of the invention herein is illustrative and is not intended to limit the scope of the invention as set forth in the appended claims. Other variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A phase-locked loop, comprising: a charge pump coupled to provide charge based on a difference between a reference signal and a feedback signal provided by the phase and frequency detector; an active loop filter coupled to an output node of the charge pump; as well as a unity gain buffer coupled for use in the charge pump in the feedback path and in the active loop filter, The active loop filter provides an effective capacitance greater than a capacitor in the active loop filter, and the active loop filter further comprises: a first resistor coupled between an output terminal of the charge pump and an output terminal of the unity gain buffer, the output terminal of the unity gain buffer being coupled to an internal node of the charge pump; a second resistor coupled between the positive input terminal of the unity gain buffer and the output terminal of the charge pump; wherein the capacitor is connected between the positive input terminal of the unity gain buffer and ground; wherein the effective capacitance of the capacitor is C(1+R1 / R2), wherein C represents the capacitance of the capacitor, R1 represents the resistance of the second resistor, and R2 represents the resistance of the first resistor; and The positive input terminal of the unity gain buffer is coupled to the output node of the charge pump via the second resistor.

2. The phase-locked loop according to claim 1, wherein: The charging pump further comprises: a first current source coupled between a power supply voltage and a first node of the charge pump to provide charge to an output node of the charge pump through a first transistor, wherein a gate of the first transistor is coupled to a first control signal; a second current source coupled between a ground voltage and a second node of the charge pump, the second current source removing charge from a capacitor coupled to the output node, the charge being removed via a second transistor coupled between the output node and a second node, the gate terminal of the second transistor being coupled to a second control signal; a third transistor coupled between the first node and an output terminal of the unity gain buffer, a gate terminal of the third transistor coupled to a complementary signal of the first control signal; and A fourth transistor is coupled between the second node and an output terminal of the unity gain buffer, a gate terminal of the fourth transistor being coupled to a complementary signal of the second control signal.

3. The phase-locked loop according to claim 2, further comprising: in, The third transistor and the fourth transistor provide a path between the first node of the charge pump and the second node of the charge pump when the first transistor and the second transistor are turned off.

4. The phase-locked loop according to any one of claims 1 to 2, further comprising: A first voltage controlled oscillator is coupled to an output node of the charge pump.

5. The phase-locked loop according to claim 4, further comprising: A second voltage controlled oscillator is coupled to the output node of the charge pump.

6. A method for operating a phase-locked loop, comprising: In a phase and frequency detector, a signal indicative of a difference between a reference signal and a feedback signal is generated; providing a signal indicative of the difference to a charge pump; Using a unity gain buffer in a charge pump and using the unity gain buffer in an active loop filter; as well as Uses a charge pump and active loop filter to generate a filtered oscillator control signal, and Using the unity gain buffer in the active loop filter, the active loop filter increases an effective capacitance of a capacitor of the active loop filter, the effective capacitance being based on a ratio between a first resistor coupled between a positive input terminal of the unity gain buffer and an output node of the charge pump and a second resistor coupled between the output node of the charge pump and an output node of the unity gain buffer, and wherein the capacitor is coupled between the positive input terminal of the unity gain buffer and ground.

7. The method according to claim 6, further comprising: asserting a first control signal to turn on the first transistor to provide charge to an output node of the charge pump through a first charge pump node and through the first transistor; asserting a second control signal to turn on the second transistor when the first transistor is turned off to remove charge from the capacitor coupled to the output node, the charge being removed through the second transistor and the second charge pump node; controlling a third transistor using a complement of the first control signal to provide a path from the first charge pump node to a third charge pump node, which is an output node of the unity gain buffer, in response to the third transistor being turned on; controlling a fourth transistor using a complement of the second control signal to provide a path from the third charge pump node to the second charge pump node in response to the third transistor being turned on; as well as The unity gain buffer coupled between the output node and the third charge pump node via a first resistor is used to cause a voltage on the third charge pump node to track a voltage on the output node.

8. The method according to claim 7, further comprising: The third transistor and the fourth transistor are used to provide a path between the first charge pump node and the second charge pump node when the first transistor and the second transistor are turned off.

9. The method according to any one of claims 6 to 8, further comprising: Based on the filtered oscillator control signal, the first voltage controlled oscillator is controlled.

10. The method according to claim 9, further comprising: The second voltage controlled oscillator is selectively controlled based on the filtered oscillator control signal.

11. A phase-locked loop, comprising: a phase and frequency detector for providing a phase and frequency detector signal indicative of a difference between a reference signal and a feedback signal; a charge pump that provides current to an output node of the charge pump based on the phase and frequency detector signals; an active loop filter coupled to an output node of the charge pump, the active loop filter providing an increased effective capacitance of a capacitor in the active loop filter; as well as a unity gain buffer coupled as part of the charge pump, wherein the unity gain buffer is further coupled as part of an active loop filter; Wherein, the charging pump comprises: a first transistor coupled between a first current source and an output node of the charge pump; a second transistor coupled between a second current source and an output node of the charge pump; a third transistor coupled between the first current source and an output terminal of the unity gain buffer; a fourth transistor coupled between the output terminal of the unity gain buffer and the second current source; wherein the positive input terminal of the unity gain buffer is coupled to the output node of the charge pump through the first resistor of the active loop filter; A second resistor of the active loop filter is coupled between an output node of the charge pump and an output terminal of the unity gain buffer; and The capacitor of the active loop filter is coupled between the positive input terminal of the unity gain buffer and ground.

12. The phase-locked loop according to claim 11, further comprising: A first voltage controlled oscillator is coupled to an output node of the charge pump.

13. The phase-locked loop according to claim 12, further comprising: A second voltage controlled oscillator is coupled to the output node of the charge pump.

14. The phase-locked loop according to any one of claims 11 to 13, wherein: the first transistor coupled to receive a first gate control signal; the second transistor coupled to receive a second gate control signal; the third transistor being coupled to receive a complementary signal of the first gate control signal; as well as The fourth transistor is coupled between the third transistor and the second current source and is coupled to receive a complementary signal of the second gate control signal.

15. The phase-locked loop according to any one of claims 11 to 13, further comprising: in, The third transistor and the fourth transistor provide a path between the first current source and the second current source when the first transistor and the second transistor are turned off.

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