System and method for addressing data in memory

Abstract

The present application is entitled "System and Method for Addressing Data in Memory". A digital signal processor 100 having a CPU (110) with a program counter register (121) and optionally an event context stack pointer register (122) for saving and restoring event handler context when a higher priority event preempts a lower priority event handler is disclosed. The CPU (110) is configured to use a minimized set of addressing modes, including using the event context stack pointer register (122) and the program counter register (121) to calculate addresses for storing data in memory (112, 114). The CPU (110) can also eliminate post-decrement addressing, pre-increment addressing, and post-decrement addressing, and rely only on post-increment addressing.

Description

Background Art

[0001] Modern digital signal processors (DSPs) face multiple challenges. Increasing workloads demand ever-increasing bandwidth. System-on-a-chip (SoCs) continue to grow in size and complexity. Memory system latency severely impacts certain classes of algorithms. Furthermore, the patterns used to address data in memory can be complex and / or inadequate for many DSPs. Summary of the Invention

[0002] The example described herein includes a method for addressing data in a memory. The method includes using an event context stack pointer as a base address. Other examples described herein include a digital signal processor. The digital signal processor includes a CPU. The CPU includes a program counter register, wherein the CPU is configured to be used as a base address for storing data in the memory. The CPU is additionally configured to address the memory using post-incremental addressing, and is not configured to address the memory using pre-incremental addressing, pre-decremental addressing, or post-decremental addressing. The CPU may also include an event context stack pointer register, which is used to save and restore an event handler context when a higher priority event preempts a lower priority event handler. The CPU may alternatively use an event context stack pointer register as a base address for storing data in the memory.

[0003] Other examples described herein include a digital signal processor system. The digital signal processor system includes a memory and a digital signal processor. The digital signal processor includes a CPU. The CPU includes a program counter register, wherein the CPU is configured to serve as a base address for storing data in the memory. The CPU is further configured to address the memory using post-incremental addressing, rather than using pre-incremental addressing, pre-decremental addressing, or post-decremental addressing. The CPU may also include an event context stack pointer register for saving and restoring an event handler context when a higher priority event preempts a lower priority event handler. The CPU may alternatively use the event context stack pointer register as a base address for storing data in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0005] Figure 1 shows a DSP according to embodiments described herein; and

[0006] Figure 2 An exemplary event context stack pointer register is shown. DETAILED DESCRIPTION

[0007] Figure 1 1 shows a block diagram of a DSP 100 including a vector CPU core 110. Figure 1 As shown, the vector CPU 110 includes an instruction fetch unit 141, an instruction dispatch unit 142, an instruction decode unit 143, and a control register 144. The vector CPU 110 further includes a 64-bit register file 150 (e.g., designated registers A0 to A15 and D0 to D15) for receiving and processing 64-bit scalar data from the level 1 data cache (L1D) 112 and a 64-bit functional unit 151. The vector CPU 110 also includes a 512-bit register file 160 and a 512-bit functional unit 161 for receiving and processing 512-bit vector data from the level 1 data cache (L1D) 112 and / or from the stream engine 113. The vector CPU 110 may also include a debug unit 171 and an interrupt logic unit 172.

[0008] DSP 100 also includes a stream engine 113. As described in U.S. Patent No. 9,606,803 (hereinafter referred to as the "803 patent", the entire contents of which are incorporated herein by reference), a stream engine such as stream engine 113 can increase the available bandwidth of the CPU, reduce the number of cache misses, reduce scalar operations, and allow multi-dimensional memory access. DSP 100 also includes stream address generators 180, 181, 182, 183 in vector CPU 110. As described in U.S. patent application entitled "Streaming Address Generation" filed concurrently with this document and incorporated herein by reference (hereinafter referred to as the "Streaming Address Generation application"), stream address generator 180 generates offsets for addressing streaming data. Although Figure 1 Four stream address generators are shown, but as described in the concurrently filed application, there may be one, two, three, or four stream address generators, and in other examples there may be more than four stream address generators. As described in the Streaming Address Generation application, the offsets generated by stream address generators 180, 181, 182, 183 are stored in stream address offset registers SA0 190, SA1 191, SA2 192, and SA3 193, respectively.

[0009] The control registers 144 include a program counter (PC) register 121 and optionally one or more event context stack pointers (ECSP) 122. The DSP uses the ECSP register 122 to save and restore event handler context when a higher priority event preempts a lower priority event handler. The ECSP register 122 preserves context in the event of an interrupt and contains the address used to stack machine state when an event is detected. Figure 2 An exemplary ECSP register is shown including an address 21 and a nested interrupt counter 22 .

[0010] To write data from the CPU, a store operation is typically used. To read data into the CPU, a load operation is typically used. To indicate an address in memory for reading or writing data, a base address is typically provided as an operand and optionally an offset.

[0011] The base address register can be any of the 64-bit scalar registers A0-A15 (preferably A0-A15) or D0-D15. These registers are collectively referred to as "baseR" hereinafter. The program counter (PC) register or the event context stack pointer (ECSP) control register can also be used as the base address register.

[0012] The base address register can also be a 64-bit register. In this case, since the virtual address size is typically 49 bits, the address generation logic or uTLB lookup does not use the remaining high bits of the register (e.g., bit 15). However, these bits are checked to ensure they are all 0 or all 1; otherwise, an address exception may be generated.

[0013] The constant offset can be a scaled 5-bit unsigned constant or an unscaled 32-bit signed constant. The value can be scaled by the data type, such as the element size (shifted by 0, 1, 2, or 3 if the element size is byte, halfword, word, or doubleword, respectively) and the result (up to 35 bits after the shift) can be sign-extended to 49 bits. This offset can then be added to the base register. When no bracketed register or constant is specified, the offset value can default to 0.

[0014] Load instructions and store instructions may use offsets, such as A0-A15 (preferably A8-A15), D0-D15 registers. ADDA / SUBA instructions that perform linearly scaled address calculations by adding a base address operand to a shifted offset value operand may use, for example, A0-A15, D0-D15 registers. In general, the effective register offset is represented as offsetR32. Streaming address offset registers SA0 190, SA1 191, SA2 192, and SA3 193 may also be used for offsets for load instructions, store instructions, ADDA instructions, or SUBA instructions. Streaming address offset registers SA0 190, SA1 191, SA2 192, and SA3 193 may or may not be used for advancement. As described in the Streaming Address Generation application, an exemplary syntax for advancing the streaming address offset register SA0 is "SA0++," which will advance the offset after being used for the next offset.

[0015] Post-increment addressing updates the base register by a specified amount after address calculation. With post-increment addressing, the value of the base register before the addition is the address to be accessed from memory. The post-increment operation on the base register is denoted as baseR++. After accessing the value, this operation increments the base register by one element.

[0016] Using program counter 121 as the base address may be referred to as a PC-relative addressing mode. A PC-relative reference may be relative to the PC of the fetch packet containing the reference. This also holds true for execute packets that span fetch packets, where the PC reference may be relative to a fetch packet containing an instruction with PC-relative addressing mode. Specifically, in at least one example, the address used for the base address when using PC-relative addressing mode is the address of the fetch packet containing the .D unit instruction with PC-relative addressing mode.

[0017] For example, for this code sequence:

[0018] LDW.D1*PC[0x30],A0

[0019] ||LDW.D2*PC[0x34],A1

[0020] If the instruction on .D1 and the instruction on .D2 are in different fetch packets due to expansion, they will end up with different values ​​for the PC.

[0021] use Figure 2 The illustrated ECSP 122 as a base address provides the advantage that the address will be preserved in the event of an interrupt, even nested interrupts.

[0022] Table 1 shows the addressing modes for load and store operations according to the above example:

[0023]

[0024] By limiting the addressing modes to only a few options and including only post-increment (ie, no pre-increment or pre / post-decrement), the design verification space is reduced and fewer opcode bits are required.

[0025] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A method for addressing data in a memory, the method comprising: Maintains the event context stack pointer register that stores the address; To preempt a lower priority event handler in response to a higher priority event: Using the event context stack pointer register to save and restore event handler context; as well as The memory is accessed using the address stored in the event context stack pointer register as a base address. 2 . The method of claim 1 , further comprising offsetting the address stored in the event context stack pointer register by an offset. The method of claim 2 , wherein the offset is an unsigned 5-bit constant. The method of claim 2 , wherein the offset is a 32-bit constant.

5. A digital signal processor comprising: A central processing unit, or CPU, is configured to be coupled to a memory, wherein: The CPU includes a program counter register and an event context stack pointer register for saving and restoring an event handler context when a higher priority event preempts a lower priority event handler, and The CPU is configured to: receiving an instruction specifying a memory location in the memory based on the event context stack pointer register; determining the memory location using the value of the event context stack pointer register as a base address; and In response to the instruction, data is loaded or stored at the memory location in the memory.

6. The digital signal processor of claim 5, wherein the CPU adds an offset to a value stored in the event context stack pointer register. The digital signal processor of claim 6 , wherein the offset is an unsigned 5-bit constant. The digital signal processor of claim 6 , wherein the offset is a 32-bit constant.

9. A digital signal processor system comprising: Memory; a digital signal processor coupled to the memory, the digital signal processor comprising: a central processing unit, i.e., a CPU, comprising a program counter register and an event context stack pointer register for saving and restoring event handler context when a higher priority event preempts a lower priority event handler, and The CPU is configured to use the value of the event context stack pointer register as a base address for loading or storing data in a memory.

10. The digital signal processor system of claim 9, wherein the CPU adds an offset to a value stored in the event context stack pointer register to calculate the memory address. The digital signal processor system of claim 10 , wherein the offset is an unsigned 5-bit constant.

12. The digital signal processor system of claim 10, wherein the offset is a 32-bit constant.

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