analog-to-digital converter

Abstract

A kind of analog-digital converter is disclosed.The analog-digital converter includes: comparator, is configured to: input signal is compared with reference signal, and output comparison signal indicating corresponding comparison result;Control logic is configured to output control signal for adjusting reference signal based on comparison signal;And reference signal adjusting circuit is configured to adjust reference signal based on control signal.Comparator includes: first preamplifier, is configured to: using first transistor with first size, the difference between input signal and reference signal is amplified;Second preamplifier, is configured to: using second transistor with second size different from first size, the difference between input signal and reference signal is amplified;And latch, is configured to: using at least one of the output of first preamplifier and the output of second preamplifier, comparison signal is generated.First preamplifier and second preamplifier share latch.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0115468, filed on September 19, 2019, the disclosure of which is fully incorporated herein by reference. Technical Field

[0002] Exemplary embodiments of the present invention relate to analog-to-digital converters and methods for performing analog-to-digital conversion using analog-to-digital converters. Background Technology

[0003] An analog-to-digital converter (ADC) is used to generate a sequence of digital codes that indicate each signal level of an analog signal.

[0004] One type of analog-to-digital converter is the successive approximation register analog-to-digital converter (SARADC). The SAR ADC repeatedly performs analog-to-digital conversion, compares the data, and determines the bits of the digital code.

[0005] Because a large amount of electrical power is consumed in the process of converting signals using such analog-to-digital converters, research is underway to reduce power consumption. Summary of the Invention

[0006] An aspect of the present invention provides an analog-to-digital converter with reduced operating power consumption.

[0007] The present invention also provides a method for performing analog-to-digital conversion using an analog-to-digital converter with reduced operating power consumption.

[0008] According to an exemplary embodiment, an analog-to-digital converter includes: a comparator configured to compare an input signal with a reference signal and output a comparison signal indicating a corresponding comparison result; control logic configured to output a control signal for adjusting the reference signal based on the comparison signal; and a reference signal adjustment circuit configured to adjust the reference signal based on the control signal. The comparator includes: a first preamplifier configured to amplify the difference between the input signal and the reference signal using a first transistor having a first size; a second preamplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size; and a latch configured to generate the comparison signal using at least one of the outputs of the first and second preamplifiers. The first and second preamplifiers share the latch.

[0009] According to an exemplary embodiment, an analog-to-digital converter includes: a comparator configured to: compare an input signal with a reference signal and output a first comparison signal and a second comparison signal indicating a corresponding comparison result; and control logic configured to: determine a first bit value based on the first comparison signal, determine a second bit value based on the second comparison signal, and determine a third bit value corresponding to the input signal based on the first bit value and the second bit value. The comparator includes: a first preamplifier configured to amplify the difference between the input signal and the reference signal; a second preamplifier configured to amplify the difference between the input signal and the reference signal; and a latch configured to: generate the first comparison signal and the second comparison signal using at least one of the outputs of the first preamplifier and the second preamplifier. The dimensions of the first preamplifier and the second preamplifier are different from each other. The control logic controls the first preamplifier and the second preamplifier such that the first comparison signal is generated using the first preamplifier, and the second comparison signal is generated using the second preamplifier.

[0010] According to an exemplary embodiment, an analog-to-digital converter includes: a comparator configured to: compare an input signal with a reference signal and output a comparison signal indicating a corresponding comparison result; control logic configured to: output a control signal for adjusting the reference signal based on the comparison signal and determine a digital signal corresponding to the input signal based on the comparison signal; and a reference signal adjustment circuit configured to adjust the reference signal based on the control signal. The comparator includes: a first preamplifier configured to: amplify the difference between the input signal and the reference signal using a first transistor having a first size; a second preamplifier configured to: amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size; and a latch configured to: generate a comparison signal using at least one of the outputs of the first and second preamplifiers. The latch includes: a first reset circuit configured to receive the output of a first preamplifier and reset a first output node and a second output node using a third transistor having a third size; a second reset circuit configured to receive the output of a second preamplifier and reset the first output node and the second output node using a fourth transistor having a fourth size different from the third size; and an amplifier circuit configured to amplify the voltage level of the first output node and the voltage level of the second output node using at least one of the outputs of the first and second preamplifiers. Attached Figure Description

[0011] The above and other features of the present invention will become clearer from a detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of a semiconductor device according to an exemplary embodiment.

[0013] Figure 2 yes Figure 1 An exemplary block diagram of a comparator.

[0014] Figure 3 yes Figure 2 Exemplary circuit diagrams of the first and second preamplifiers.

[0015] Figure 4 yes Figure 2 An exemplary circuit diagram of a shared latch.

[0016] Figures 5 to 13 This is a diagram used to explain the operation of a semiconductor device according to an exemplary embodiment.

[0017] Figure 14 and Figure 15 This is a diagram used to explain the effects of a semiconductor device according to an exemplary embodiment.

[0018] Figure 16 This is a block diagram of a semiconductor device according to an exemplary embodiment.

[0019] Figure 17 This is a block diagram of a semiconductor device according to an exemplary embodiment.

[0020] Figure 18 yes Figure 17 Exemplary circuit diagrams of the first and second preamplifiers.

[0021] Figure 19 yes Figure 17 An exemplary circuit diagram of a shared latch.

[0022] Figure 20 and Figure 21 This is a diagram used to explain the operation of a semiconductor device according to an exemplary embodiment.

[0023] Figure 22 This is a block diagram of a semiconductor device according to an exemplary embodiment. Detailed Implementation

[0024] In the following description, exemplary embodiments of the invention will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may denote the same elements.

[0025] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an exemplary embodiment may be described as a “second” element in another exemplary embodiment.

[0026] It should also be understood that, unless the context clearly indicates otherwise, the description of a feature or aspect within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments.

[0027] As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0028] Figure 1 This is a block diagram of a semiconductor device according to an exemplary embodiment.

[0029] Reference Figure 1 The semiconductor device 10 may include a sampling circuit (S / H) 100, a comparator 200, control logic 300, and a reference signal conditioning circuit 400.

[0030] In an exemplary embodiment, the semiconductor device 10 may be, for example, an analog-to-digital converter that converts an analog input signal IS into a digital signal corresponding to the analog input signal IS. For example, the semiconductor device 10 may be a successive approximation register analog-to-digital converter (SAR ADC) that converts the provided analog input signal IS into a q-bit (q is a positive integer) digital output signal by successive approximation. The analog-to-digital converter may also be referred to herein as an analog-to-digital converter circuit.

[0031] In the following description, although the technical concept of the present invention will be described as an example of a SAR ADC for the semiconductor device 10, exemplary embodiments of the present invention are not limited thereto. For example, in exemplary embodiments, the semiconductor device 10 may be implemented as an analog-to-digital converter of a type other than a SAR ADC, and may also be implemented as a semiconductor device 10 of a type other than an analog-to-digital converter.

[0032] Reference Figure 1 The sampling circuit 100 receives the input signal IS and can sample and hold the input signal. For example, the sampling circuit 100 can use a predetermined storage element to store the input signal IS, so that the input signal IS can be provided to the comparator 200. Therefore, the sampling circuit 100 can provide the sampled input signal IS to the comparator 200.

[0033] Comparator 200 compares the input signal IS with the reference signal RS and can output a comparison signal CS based on the comparison result. For example, comparator 200 can compare the voltage level of the input signal IS with the voltage level of the reference signal RS and output the comparison signal CS based on the comparison result. For example, the comparison signal CS can indicate the corresponding comparison result based on the comparison between the input signal IS and the reference signal RS.

[0034] If the voltage level of the input signal IS is greater than the voltage level of the reference signal RS, the comparator 200 can output a comparison signal CS with a first voltage level. If the voltage level of the input signal IS is less than the voltage level of the reference signal RS, the comparator 200 can output a comparison signal CS with a second voltage level different from the first voltage level. The detailed configuration of the comparator 200 will be described more fully below.

[0035] Control logic 300 may receive a comparison signal CS from comparator 200 and determine the bit value of the digital signal corresponding to the input signal IS based on the comparison signal CS. Furthermore, control logic 300 may output a first control signal RCON to reference signal conditioning circuit 400 based on the comparison signal CS. In one exemplary embodiment, control logic 300 may generate the first control signal RCON based on a plurality of generated comparison signals, which will be further described below. Control logic 300 may also be referred to herein as control logic circuitry.

[0036] The reference signal conditioning circuit 400 can adjust the reference signal RS to be provided to the comparator 200 according to the first control signal RCON provided from the control logic 300. For example, the reference signal conditioning circuit 400 can adjust the voltage level of the reference signal RS to be provided to the comparator 200 according to the first control signal RCON provided from the control logic 300.

[0037] In an exemplary embodiment, if the semiconductor device 10 is a SAR ADC, the reference signal conditioning circuit 400 may include a digital-to-analog converter (DAC) that adjusts the voltage level of the reference signal RS according to a first control signal RCON, which is a digital signal. For example, when the semiconductor device 10 is a SAR ADC, the reference signal conditioning circuit 400 may include a DAC that adjusts an externally supplied reference voltage RV according to the first control signal RCON and outputs the reference voltage as the reference signal RS. For example, if the semiconductor device 10 is a SAR ADC, the reference signal conditioning circuit 400 may include a DAC that controls a plurality of capacitors and a plurality of switches disposed therein according to the first control signal RCON to generate the reference signal RS from the reference voltage RV and output the reference signal RS to the comparator 200.

[0038] On the other hand, control logic 300 may provide comparator 200 with a second control signal PCON for controlling the operation of comparator 200. A further description of the second control signal PCON will be provided below.

[0039] In an exemplary embodiment, while control logic 300 may include SAR logic, reference signal conditioning circuit 400 may include a digital-to-analog converter that generates a reference voltage based on a first digital control signal RCON provided from the SAR logic. However, the exemplary embodiment is not limited thereto.

[0040] Figure 2 yes Figure 1 An exemplary block diagram of a comparator.

[0041] Reference Figure 2 The comparator 200 may include a first preamplifier 210, a second preamplifier 220, and a shared latch 230.

[0042] The first preamplifier 210 and the second preamplifier 220 can receive an input signal IS and a reference signal RS. For example, the first preamplifier 210 and the second preamplifier 220 can receive the input signal IS through input node IN1 and the reference signal RS through input node IN2. In an exemplary embodiment, the first preamplifier and the second preamplifier can be dynamic preamplifiers.

[0043] The first preamplifier 210 and the second preamplifier 220 can be connected to the shared latch 230. That is, the output of the first preamplifier 210 and the output of the second preamplifier 220 can be sent to the shared latch 230.

[0044] In one exemplary embodiment, the first preamplifier 210 and the second preamplifier 220 may share a latch for generating the comparison signal CS. For example, whether the comparison signal CS is generated using the first preamplifier 210 or the comparison signal CS is generated using the second preamplifier 220, the comparator 200 can use the shared latch 230 instead of a separate latch (e.g., a separate first latch and a separate second latch) to generate the comparison signal CS. Therefore, the size of the comparator 200 can be reduced compared to the case where a separate latch is used.

[0045] The first preamplifier 210 and the second preamplifier 220 may have different dimensions from each other. For example, if the first preamplifier 210 has a first size N, then the second preamplifier 220 may have a second size M greater than the first size N, where M and N are positive integers. In an exemplary embodiment, the dimensions of the transistors constituting the first preamplifier 210 and the dimensions of the transistors constituting the second preamplifier 220 may be different from each other. Therefore, the first preamplifier 210 and the second preamplifier 220 may have different dimensions from each other. Furthermore, in an exemplary embodiment, the number of transistors constituting the first preamplifier 210 and the number of transistors constituting the second preamplifier 220 may be different from each other. Therefore, the first preamplifier 210 and the second preamplifier 220 may have different dimensions from each other. However, the exemplary embodiment is not limited to this, and the configuration in which the first preamplifier 210 and the second preamplifier 220 have different dimensions from each other can be implemented with various modifications.

[0046] Because the first preamplifier 210 is relatively smaller than the second preamplifier 220, the current flowing in the first preamplifier 210 can be relatively smaller when the difference between the input signal IS and the reference signal RS is amplified. Therefore, the power consumption required for amplification in the first preamplifier 210 is less than the power consumption required for amplification in the second preamplifier 220. In other words, when the first preamplifier 210 is operating, the comparator 200 can operate in a low-power mode.

[0047] On the other hand, in the case of the first preamplifier 210, when the difference between the input signal IS and the reference signal RS is amplified, the magnitude of the current flowing in the first preamplifier 210 is relatively small compared to the second preamplifier 220. Therefore, the amplification amplitude of the first preamplifier 210 in amplifying the difference between the input signal IS and the reference signal RS can be smaller than that of the second preamplifier 220. Therefore, when the comparison signal CS is generated using the second preamplifier 220, the comparison accuracy can be further improved compared to the case where the comparison signal CS is generated using the first preamplifier 210. That is, when the second preamplifier 220 is operating, the comparator 200 can operate in a low-noise mode. Due to these characteristics, the first preamplifier 210 has characteristics relatively suitable for coarse comparison, and the second preamplifier 220 can have characteristics relatively suitable for fine comparison. However, the exemplary embodiments are not limited thereto.

[0048] In one exemplary embodiment, the first preamplifier 210 may amplify the difference between the input signal IS and the reference signal RS before the second preamplifier 220 amplifies the difference between the input signal IS and the reference signal RS.

[0049] The first clock signal Q can be provided to the first preamplifier 210. Therefore, the first preamplifier 210 can operate synchronously with the first clock signal Q.

[0050] A second clock signal QLN can be provided to the second preamplifier 220. Therefore, the second preamplifier 220 can operate synchronously with the second clock signal QLN. The second clock signal QLN can determine whether the second preamplifier 220 is enabled. The second clock signal QLN can also be referred to as a control signal and can be different from the first control signal RCON and the second control signal PCON. That is, the second clock signal QLN can control whether the second preamplifier 220 is enabled or disabled. For example, in an exemplary embodiment, when the signal level of the second clock signal QLN does not change, the second preamplifier 220 does not amplify the difference between the input signal IS and the reference signal RS. Therefore, the second clock signal QLN can be used as an enable signal to determine whether the second preamplifier 220 is enabled.

[0051] A first enable signal EN_LN may be provided to the shared latch 230. The first enable signal EN_LN determines whether the shared latch 230 is enabled. For example, the first enable signal EN_LN may determine whether a specific circuit region of the shared latch 230 is enabled. This will be described in more detail below.

[0052] In an exemplary embodiment, the control logic ( Figure 1 The second control signal generated by (300) Figure 1 The PCON (control logic) may include a first clock signal Q, a second clock signal QLN, and a first enable signal EN_LN. In other words, the control logic ( Figure 1 The 300) can generate a second clock signal QLN to be provided to the second preamplifier 220 and a first enable signal EN_LN to be provided to the shared latch 230, and can output these signals.

[0053] On the other hand, in an exemplary embodiment, the control logic ( Figure 1 The second control signal generated by (300) Figure 1 The PCON may only include the first enable signal EN_LN. That is, the control logic ( Figure 1 The 300) can generate and output a first enable signal EN_LN that will be provided to the shared latch 230, and a second clock signal QLN that will be provided to the second preamplifier 220 can also be generated by another device using the first clock signal Q.

[0054] In the following text, reference will be made to Figure 3 An exemplary configuration of the first preamplifier 210 and the second preamplifier 220 is described in more detail below.

[0055] Figure 3 yes Figure 2 Exemplary circuit diagrams of the first and second preamplifiers.

[0056] Reference Figure 3 The first preamplifier 210 may include multiple transistors SP1, SP2, SN1, SN2 and SN3.

[0057] Transistor SP1 is connected between the power supply voltage VDD and the output node VOM1, and can supply the power supply voltage VDD to the output node VOM1 based on the first clock signal Q input to node A1. Node A1 is connected to the gate of transistor SP1. Transistor SP2 is connected between the power supply voltage VDD and the output node VOP1, and can supply the power supply voltage VDD to the output node VOP1 based on the first clock signal Q input to node A1. Node A1 is connected to the gate of transistor SP2.

[0058] Transistor SN1 is connected between transistors SP1 and SN3, and its output node VOM1 can be connected to the drain of transistor SN3 based on the input signal IS provided through input node IN1. Input node IN1 is connected to the gate of transistor SN1. Transistor SN2 is connected between transistors SP2 and SN3, and its output node VOP1 can be connected to the drain of transistor SN3 based on the reference signal RS provided through input node IN2. Input node IN2 is connected to the gate of transistor SN2. Transistor SN3 is connected between transistors SN1 and SN2 and ground voltage, and its output nodes VOP1 and VOM1 can be grounded based on the first clock signal Q provided to the gate of transistor SN3.

[0059] Although transistors SP1 and SP2 are configured as, for example, P-type transistors, and transistors SN1, SN2 and SN3 may be configured as, for example, N-type transistors, the exemplary embodiments are not limited thereto.

[0060] The second preamplifier 220 may include multiple transistors BP1, BP2, BN1, BN2 and BN3.

[0061] Transistor BP1 is connected between the power supply voltage VDD and the output node VOM2, and can supply the power supply voltage VDD to the output node VOM2 based on the second clock signal QLN input to node A2. Node A2 is connected to the gate of transistor BP1. Transistor BP2 is connected between the power supply voltage VDD and the output node VOP2, and can supply the power supply voltage VDD to the output node VOP2 based on the second clock signal QLN input to node A2. Node A2 is connected to the gate of transistor BP2.

[0062] Transistor BN1 is connected between transistors BP1 and BN3, and its output node VOM2 can be connected to the drain of transistor BN3 based on the input signal IS provided through input node IN1. Input node IN1 is connected to the gate of transistor BN1. Transistor BN2 is connected between transistors BP2 and BN3, and its output node VOP2 can be connected to the drain of transistor BN3 based on the reference signal RS provided through input node IN2. Input node IN2 is connected to the gate of transistor BN2. Transistor BN3 is connected between transistors BN1 and BN2 and ground voltage, gated by the second clock signal QLN provided to the gate of transistor BN3, and its output nodes VOM2 and VOP2 can be grounded.

[0063] Although transistors BP1 and BP2 may be configured as, for example, P-type transistors, and transistors BN1, BN2 and BN3 may be configured as, for example, N-type transistors, the exemplary embodiments are not limited thereto.

[0064] In an exemplary embodiment, the dimensions of the plurality of transistors SP1, SP2, SN1, SN2 and SN3 included in the first preamplifier 210 may be different from the dimensions of the plurality of transistors BP1, BP2, BN1, BN2 and BN3 included in the second preamplifier 220.

[0065] For example, when each of the plurality of transistors SP1, SP2, SN1, SN2, and SN3 included in the first preamplifier 210 has a first size, each of the plurality of transistors BP1, BP2, BN1, BN2, and BN3 included in the second preamplifier 220 may have a second size larger than the first size. Therefore, the size of the second preamplifier 220 may be larger than the size of the first preamplifier 210.

[0066] Next, we will refer to Figure 4 A more complete description of shared latches ( Figure 2 Example configuration of 230).

[0067] Figure 4 yes Figure 2 An exemplary circuit diagram of a shared latch.

[0068] Reference Figure 4 The shared latch 230 may include low-noise reset circuits LNRC1 and LNRC2 and amplifier circuit AC. Transistors SP3, SP4, SN4, SN5, SN6 and SN7 perform the function of a low-power reset circuit.

[0069] The amplifier circuit AC amplifies the voltage levels of output nodes VOM and VOP. In one exemplary embodiment, the amplifier circuit AC amplifies the voltage level difference between output nodes VOM and VOP. For this purpose, the amplifier circuit AC may include multiple transistors MP1, MP2, MN1, and MN2.

[0070] Transistor MP1 supplies power supply voltage VDD to output node VOP based on the voltage level of output node VOM, and transistor MP2 supplies power supply voltage VDD to output node VOM based on the voltage level of output node VOP.

[0071] Transistor MN1 grounds output node VOP based on the voltage level of output node VOM, and transistor MN2 grounds output node VOM based on the voltage level of output node VOP.

[0072] When the first preamplifier ( Figure 3 When 210 is enabled and in operation or when the second preamplifier ( Figure 3 When 220 is enabled and in operation, the amplifier circuit AC can operate continuously to generate a comparison signal. Figure 2 The CS). That is to say, the first preamplifier ( Figure 3 210) and the second preamplifier ( Figure 3 The 220) can share the amplifier circuit AC.

[0073] Transistor SP3 can be based on the first preamplifier ( Figure 3 The voltage level of the output node VOM1 of transistor SP4 (210) supplies the power supply voltage VDD to transistor MP1. Transistor SP4 can be based on the first preamplifier ( Figure 3 The voltage level of the output node VOP1 of the 210) provides the power supply voltage VDD to the transistor MP2.

[0074] Transistor SN4 can be based on the first preamplifier ( Figure 3 The voltage level of the output node VOM1 of the 210) provides the ground voltage to transistor MP1. Transistor SN5 can be based on the first preamplifier ( Figure 3 The voltage level of the output node VOP1 of the 210) provides the ground voltage to the transistor MP2.

[0075] Transistor SN6 can be based on the first preamplifier ( Figure 3 The voltage level of the output node VOM1 of transistor SN7 will ground the output node VOP. Transistor SN7 can be based on the first preamplifier (…). Figure 3 The voltage level of output node VOP1 of (210) will ground output node VOM.

[0076] As previously mentioned, when the first preamplifier ( Figure 3 When 210 is enabled and in operation, transistors SP3, SP4, SN4, SN5, SN6 and SN7 can perform the function of a low-power reset circuit to reset the output nodes VOM and VOP.

[0077] When the second preamplifier ( Figure 3 When 220 is enabled and in operation, the low-noise reset circuits LNRC1 and LNRC2 can perform the function of resetting the output nodes VOM and VOP. For this purpose, the low-noise reset circuits LNRC1 and LNRC2 may include multiple transistors BP3, BP4, BN4, BN5, BN6 and BN7.

[0078] Transistor BP3 can be based on a second preamplifier ( Figure 3 The voltage level of the output node VOM2 of the 220) supplies the power supply voltage VDD to transistor MP1. Transistor BP4 can be based on the second preamplifier ( Figure 3 The voltage level of the output node VOP2 of the 220) supplies the power supply voltage VDD to the transistor MP2.

[0079] Transistor BN4 can be based on a second preamplifier ( Figure 3 The voltage level of the output node VOM2 of transistor 220 provides ground voltage to transistor MP1. However, transistor BN4 can only provide ground voltage to transistor MP1 when the switch is turned on by the first enable signal EN_LN.

[0080] Transistor BN5 can be based on a second preamplifier ( Figure 3 The voltage level of the output node VOP2 of transistor 220 provides ground voltage to transistor MP2. However, transistor BN5 can only provide ground voltage to transistor MP2 when the switch is turned on by the first enable signal EN_LN.

[0081] Transistor BN6 can be based on a second preamplifier ( Figure 3 The voltage level of output node VOM2 of transistor 220 will ground output node VOP. However, transistor BN6 can only ground output node VOP when the switch is turned on by the first enable signal EN_LN.

[0082] Transistor BN7 can be based on a second preamplifier ( Figure 3 The voltage level of output node VOP2 of transistor 220 will ground output node VOM. However, transistor BN7 can only ground output node VOM when the switch is turned on by the first enable signal EN_LN.

[0083] In other words, when the switch is turned on by the first enable signal EN_LN, transistors BN4 to BN7 perform the same function as transistors SN4 to SN7. However, when the switch is turned off by the first enable signal EN_LN, transistors BN4 to BN7 do not perform the same function as transistors SN4 to SN7. For example, when the switch is turned off by the first enable signal EN_LN, transistors BN4 to BN7 do not participate in increasing or decreasing the voltage levels of output nodes VOM and VOP.

[0084] In the exemplary embodiments, although transistors SP3, SP4, BP3, BP4, MP1 and MP2 are configured as, for example, P-type transistors, and transistors SN4 to SN7, BN4 to BN7, MN1 and MN2 may be configured as, for example, N-type transistors, the exemplary embodiments are not limited thereto.

[0085] In an exemplary embodiment, the dimensions of the plurality of transistors SP3 to SP4 and SN4 to SN7, as well as the plurality of transistors BP3 to BP4 and BN4 to BN7, may be different from each other.

[0086] For example, when each of transistors SP3 to SP4 and SN4 to SN7 has a third size, each of transistors BP3 to BP4 and BN4 to BN7 may have a fourth size that is larger than the third size.

[0087] In an exemplary embodiment, the comparison signal can be determined based on at least one of the voltage levels of output node VOP and output node VOM. Figure 2 The signal level of CS. Refer to the following... Figures 5 to 13 The operation of a semiconductor device according to an exemplary embodiment is described.

[0088] Figures 5 to 13 This is a diagram used to explain the operation of a semiconductor device according to an exemplary embodiment.

[0089] First, refer to Figure 1 and Figure 5 Describe the operation of a semiconductor device in determining the digital signal corresponding to an analog input signal.

[0090] Reference Figure 1 and Figure 5In the first time period T1, comparator 200 compares the input signal IS with the reference signal RS to generate a comparison signal CS1 based on the comparison result. Comparison signal CS1 may be referred to as the first comparison signal, and it can be generated using a first preamplifier 210 and a shared latch 230. In an exemplary embodiment, as described further below, comparison signal CS1 can be generated without using a second preamplifier 220. Furthermore, control logic 300 can determine a first bit value B1 of the digital signal corresponding to the analog input signal IS based on the signal level of comparison signal CS1. Here, the statement "determining bit value B1" does not mean that the bit value B1 to be included in the final digital signal output by control logic 300 is finally decided at the end of the first time period T1, but rather that bit value B1 is temporarily determined. The value of the temporarily determined bit value B1 can be changed according to subsequent operations of control logic 300 and can be determined as the bit value of the final digital signal.

[0091] If the first bit value B1 of the digital signal corresponding to the analog input signal IS is determined according to the signal level of the comparison signal CS1, then the control logic 300 outputs a control signal RCON1 based on the determined result. The reference signal conditioning circuit 400, to which the control signal RCON1 is provided, can adjust the reference signal RS to be provided to the comparator 200. Here, each adjusted reference signal RS corresponding to different control signals (e.g., RCON1, RCON2, etc.) can be referred to as a first reference signal, a second reference signal, etc.

[0092] For example, if the input signal IS (e.g., the input signal IS can be an input voltage, and for convenience, the input voltage will be described as an example below) is greater than the reference signal RS (e.g., the reference signal RS can be a reference voltage, and for convenience, the reference voltage will be described as an example below), then the control logic 300 can output a control signal RCON1 that increases the magnitude of the reference voltage. Conversely, if the input voltage is less than the reference voltage, then the control logic 300 can output a control signal RCON1 that decreases the magnitude of the reference voltage.

[0093] In the next second time period T2, comparator 200 compares the input signal IS with the reference signal RS, which is now regulated by the control signal RCON1, to generate a comparison signal CS2 based on the comparison result. Comparison signal CS2 may be referred to as the second comparison signal, and it can be generated using the second preamplifier 220 and the shared latch 230. Comparison signal CS1 may be generated before comparison signal CS2, and comparison signal CS2 may be output after comparison signal CS1. In an exemplary embodiment, as described in more detail below, comparison signal CS2 can be generated using the first preamplifier 210 and the second preamplifier 220, or it can be generated without using the first preamplifier 210. In an exemplary embodiment, comparator 200 can output comparison signal CS1 using the first preamplifier 210, the low-noise reset circuit LNRC1, and the amplifier circuit AC, without using the second preamplifier 220 and the low-noise reset circuit LNRC2. In an exemplary embodiment, comparator 200 may use a first preamplifier 210 and a second preamplifier 220, low-noise reset circuits LNRC1 and LNRC2, and amplifier circuit AC to output a comparison signal CS2. Furthermore, control logic 300 may determine the second bit value B2 of the digital signal corresponding to the analog input signal IS based on the signal level of the comparison signal CS2. If the second bit value B2 of the digital signal corresponding to the analog input signal IS is determined based on the signal level of the comparison signal CS2, control logic 300 outputs a control signal RCON2 based on the determined result. The reference signal conditioning circuit 400, to which control signal RCON2 is provided, may readjust the reference signal RS to be provided to comparator 200. This operation may continue until the redundant bit is determined.

[0094] Next, during the nth time period Tn and the (n+1)th time period T(n+1) (where n is a positive integer greater than 3) where the bit values ​​corresponding to the redundant bits need to be determined, the control logic 300 determines the nth bit value Bn and the (n+1)th bit value B(n+1) through the above operations, performs a preset redundancy operation, and can determine the bit value of the redundant bit based on the nth bit value Bn and the (n+1)th bit value B(n+1). In an exemplary embodiment, previously determined bit values ​​(e.g., B1, B2, etc.) can be changed in this process. In an exemplary embodiment, subsequent bit values ​​corresponding to the input signal IS can be determined by performing predetermined operations as described herein based on previously determined bit values ​​(e.g., B1, B2).

[0095] In the following text, reference will be made to Figures 6 to 13 The process of determining bit values ​​is described in more detail.

[0096] Reference Figure 6In the first part T11, which includes the first time period T1, the first clock signal Q is logic low (hereinafter referred to as L), and the second clock signal QLN and the first enable signal EN_LN are also logic low L.

[0097] Reference Figure 7 Since the first clock signal Q is logic low (L), transistors SP1 and SP2 are turned on, and transistor SN3 is turned off. As a result, the voltage levels of output nodes VOM1 and VOP1 increase (as shown by the bracketed arrows in the diagram).

[0098] On the other hand, since the second clock signal QLN is also logic low (L), transistors BP1 and BP2 are turned on, and transistor BN3 is turned off. As a result, the voltage levels at output nodes VOM2 and VOP2 increase.

[0099] Now refer to Figure 8 As the voltage levels of output nodes VOM1, VOP1, VOM2, and VOP2 increase, transistors SN6, SN7, BN6, and BN7 turn on. Therefore, transistors SN6 and SN7 ground output nodes VOM and VOP, and the voltage levels of output nodes VOM and VOP decrease. Although transistors BN6 and BN7 are turned on, due to the first enable signal (… Figure 6 When EN_LN is logic low (L) and the switch is off, output nodes VOM and VOP are not grounded. That is, transistors BN6 and BN7 do not participate in reducing the voltage levels of output nodes VOM and VOP. In other words, low-noise reset circuits LNRC1 and LNRC2 are disabled. Therefore, the first enable signal EN_LN, which can be included in the second control signal PCON, can determine whether low-noise reset circuits LNRC1 and LNRC2 are enabled.

[0100] Refer again Figure 6 In Part 1-2, following Part 1-1 T11, the first clock signal Q is logic high (hereinafter referred to as H), but the second clock signal QLN and the first enable signal EN_LN remain logic low L.

[0101] Next, refer to Figure 9 Since the first clock signal Q is logic high H, transistors SP1 and SP2 are turned off and transistor SN3 is turned on. Therefore, the voltage levels of output nodes VOM1 and VOP1 are determined by the input signal (IS, which will be described as input voltage below for convenience) and the reference signal (RS, which will be described as reference voltage below for convenience).

[0102] For example, assuming the input voltage IS is greater than the reference voltage RS, the voltage level of the output node VOM1 can be relatively reduced by transistors SN1, SN2 and SN3 (as shown by the bracketed arrows in the figure), and the voltage level of the output node VOP1 can be relatively increased.

[0103] On the other hand, since the second clock signal QLN remains at logic low level L, transistors BP1 and BP2 remain on, and transistor SN3 remains off. The voltage levels of output nodes VOM2 and VOP2 remain unchanged at the current supply voltage VDD level (as shown by the horizontal line in brackets in the figure). That is, the voltage levels of output nodes VOM2 and VOP2 remain constant regardless of the magnitude of the input voltage IS or the reference voltage RS. In other words, the second preamplifier 220 is disabled.

[0104] Now refer to Figure 10 As the voltage level of output node VOM1 decreases, the supply voltage VDD is provided to output node VOP, and the voltage level of output node VOP increases. Furthermore, as the voltage level of output node VOP1 increases, ground voltage is provided to output node VOM, and the voltage level of output node VOM decreases. The amplifier circuit AC further amplifies the voltage level difference between output node VOM and output node VOP, ultimately causing the voltage level of output node VOM to become logic low (L) and the voltage level of output node VOP to become logic high (H). For example, assuming the voltage level of output node VOP becomes the comparator signal (... Figure 2 When the signal level of the CS signal is reached, if the input voltage IS is greater than the reference voltage RS, then the comparison signal ( Figure 2 The signal level of the comparison signal (CS) becomes logic high (H). Conversely, if the input voltage IS is less than the reference voltage RS, the comparison signal (CS) becomes logic high (H). Figure 2 The signal level of CS changes to logic low level L.

[0105] In an exemplary embodiment, the comparison signal can be determined based on at least one of the voltage levels of output node VOP and output node VOM. Figure 2 The signal level of CS.

[0106] On the other hand, due to the first enable signal ( Figure 6 Since EN_LN is still logic low (L), the switch is in the off state. Therefore, the low-noise reset circuits LNRC1 and LNRC2 do not involve generating a comparison signal ( Figure 2 (CS). In other words, the low-noise reset circuits LNRC1 and LNRC2 remain disabled.

[0107] Reference Figure 6 and Figure 11 In the second time period T2 and the third time period T3 following the first time period T1, the input signal IS and the reference signal RS are compared to generate a comparison signal, which can be used to determine the bit value of the digital signal (e.g., Figure 5 (B1, B2, and B3). This operation can continue until control logic 300 determines the time period Tn for determining some of the bit values ​​Bn among the aforementioned redundant bits.

[0108] In other words, such as Figure 11 As shown, comparator 200 can generate the comparison signal CS from the first time period T1 to the nth time period Tn using only the first preamplifier 210 and the shared latch 230. At this time, the second preamplifier 220 is disabled by the second clock signal QLN, and the low-noise reset circuit of the shared latch 230 (…) Figure 4 LNRC1 and LNRC2 can be disabled by the first enable signal EN_LN. Therefore, comparator 200 can operate in a low-power mode that minimizes power consumption from the first time period T1 to the nth time period Tn.

[0109] Refer again Figure 6 In the (n+1)th time period T(n+1) after the nth time period Tn, similar to the above operation, the first clock signal Q changes from logic low level L to logic high level H, and the second clock signal QLN also changes from logic low level L to logic high level H. In addition, the first enable signal EN_LN remains at logic high level H.

[0110] Therefore, as Figure 12 As shown, all switches of the shared latch 230 are turned on. That is, the low-noise reset circuits LNRC1 and LNRC2 are enabled. On the other hand, since the second clock signal QLN is also input in the same way as the first clock signal Q, the second preamplifier 220 also amplifies the difference between the input voltage IS and the reference voltage RS and provides it to the shared latch 230.

[0111] In other words, such as Figure 13 As shown, starting from the (n+1) time period T(n+1), comparator 200 uses all of the first preamplifier 210, the second preamplifier 220, and the shared latch 230 to generate the comparison signal CS. Therefore, starting from the (n+1) time period T(n+1), comparator 200 can operate in a low-noise mode with further improved comparison accuracy.

[0112] In summary, in the semiconductor device according to the exemplary embodiment, the control logic 300 uses only the first preamplifier ( Figure 2 210) and shared latch ( Figure 2 (230) to generate comparison signal ( Figure 2 The CS), until some of the bit values ​​used to determine the aforementioned redundant bits ( Figure 5 The time period of Bn) Figure 6 Tn). Furthermore, the remaining bit values ​​from the bit values ​​used to determine the redundant bits (Tn). Figure 5 The time period of B(n+1)) Figure 6 Starting from T(n+1)), control logic 300 uses the first preamplifier ( Figure 2 210), second preamplifier ( Figure 2 220) and shared latch ( Figure 2 All of the 230) are used to generate the comparison signal ( Figure 2 (CS).

[0113] The above has described an example of comparator 200 operating in a low-power mode that minimizes power consumption, and then, after a certain period of time, operating in a low-noise mode that further improves comparison accuracy. However, the exemplary embodiments are not limited thereto. For example, in an exemplary embodiment, when the accuracy of bit value determination is not relatively important (i.e., when low-resolution ADC operation is required), comparator 200 may operate only in low-power mode until all bit values ​​are determined. That is, comparator 200 may use only the first preamplifier ( Figure 2 210) and the second preamplifier ( Figure 2 The first preamplifier in (220) Figure 2 (210) to determine the input signal ( Figure 2 The values ​​of all bits of IS are determined until all bits are determined.

[0114] Figure 14 and Figure 15 This is a diagram used to explain the effects of a semiconductor device according to an exemplary embodiment.

[0115] Figure 14 This is a graph showing the power consumption ratio of each functional block in the SARADC. A represents the power consumption of the comparator, B represents the power consumption of the SAR logic, C represents the power consumption of the sampling circuit, D represents the power consumption of the clock generation circuit, E represents the power consumption of the reference signal conditioning circuit, and AU represents any unit.

[0116] Reference Figure 14 As can be seen, the comparator's power consumption is close to about 70% of the total power consumption in recently used SAR ADCs. In other words, it can be seen that when the comparator's power consumption is reduced, the overall power consumption of the SAR ADC is significantly reduced.

[0117] Figure 15 This illustrates the design of the first preamplifier with a 1:3 ratio. Figure 2 The size of the 210) and the second preamplifier ( Figure 2 A graph comparing the power consumption of each functional module when the comparator operates in the manner described above (size 220). Here, the first preamplifier ( Figure 2 The size of the 210) and the second preamplifier ( Figure 2 The configuration of the 220's dimensions in a 1:3 ratio indicates that it constitutes the first preamplifier ( Figure 2 The size and configuration of the 210 transistor in the second preamplifier ( Figure 2 The size of the 220 transistors was designed to be in a 1:3 ratio.

[0118] In low-power mode, only the first preamplifier is used. Figure 2 210) and shared latch ( Figure 2 (230) to generate comparison signal ( Figure 2 CS). In low-noise mode, the first preamplifier is used ( Figure 2 210), second preamplifier ( Figure 2 220) and shared latch ( Figure 2 All of the 230) are used to generate the comparison signal ( Figure 2 (CS).

[0119] Reference Figure 15 Even assuming that the power consumption of the latch module and the buffer (BUF) module remains the same, if the preamp module operates in low power mode, the power consumption of the preamp module is reduced to almost 1 / 4 level, and the total power consumption can be reduced to 1 / 2 level.

[0120] Figure 16 This is a block diagram of a semiconductor device according to an exemplary embodiment.

[0121] For ease of explanation, repeated descriptions of previously described elements and aspects may be omitted in the following text.

[0122] Reference Figure 16 The comparator 600 of the semiconductor device according to an exemplary embodiment includes a first preamplifier 610, a second preamplifier 620, and a shared latch 630. However, unlike the previous exemplary embodiment, the same second clock signal QLN can be provided to the second preamplifier 620 and the shared latch 630, instead of different signals ( Figure 2The QLN and EN_LN are provided to the second preamplifier 620 and the shared latch 630. As a result, in low-power mode, the comparator 600 uses only the preamplifier 610 and the shared latch 630 to generate the comparison signal CS until it is used to determine some of the bit values ​​used to determine redundant bits. Figure 5 The time period of Bn) Figure 6 Up to Tn). Furthermore, from the remaining bit values ​​(used to determine the bit values ​​used to determine redundant bits) Figure 5 The time period of B(n+1)) Figure 6 Starting from T(n+1), comparator 600 can use all of the first preamplifier 610, the second preamplifier 620 and the shared latch 630 to generate the comparison signal CS.

[0123] Figure 17 This is a block diagram of a semiconductor device according to an exemplary embodiment. Figure 18 yes Figure 17 Exemplary circuit diagrams of the first and second preamplifiers. Figure 19 yes Figure 17 An exemplary circuit diagram of a shared latch.

[0124] For ease of explanation, further descriptions of the previously described elements and aspects may be omitted in the following text.

[0125] Reference Figure 17 The comparator 700 of the semiconductor device according to an exemplary embodiment includes a first preamplifier 710, a second preamplifier 720, and a shared latch 730. A third clock signal QLP is provided to the first preamplifier 710, a second clock signal QLN is provided to the second preamplifier 720, and a first enable signal EN_LN and a second enable signal EN_LP are provided to the shared latch 730.

[0126] Reference Figure 18 The third clock signal QLP is provided to node A1 of the first preamplifier 710, and transistor SN3 can be gated by the signal level of the third clock signal QLP.

[0127] Reference Figure 19 The shared latch 730 may also include multiple switches controlled by a second enable signal EN_LP. For example, the multiple switches controlled by the second enable signal EN_LP may also be located at the sources of transistors SN4 to SN7.

[0128] Figure 20 and Figure 21 This is a diagram used to explain the operation of a semiconductor device according to an exemplary embodiment.

[0129] First, refer to Figure 20 In low-power mode, for example, control logic ( Figure 1 The 300) switches the signal level of the third clock signal QLP to repeat logic low level L and logic high level H, and can keep the signal level of the second clock signal QLN at logic low level L. Furthermore, in low power mode, the control logic ( Figure 1 (300) can keep the signal level of the first enable signal EN_LN at logic low level L and the signal level of the second enable signal EN_LP at logic high level H.

[0130] As a result, the first preamplifier 710 is enabled, the second preamplifier 720 is disabled, and the comparison signal CS can be generated via the shared latch 730. At this time, when the switches controlled by the second enable signal EN_LP and set at the sources of transistors SN4 to SN7 are in the ON state, Figure 19 The transistors SN4 to SN7 of the shared latch 730 can supply ground voltage to the output nodes VOM and VOP. However, in an exemplary embodiment, when the switches set at the sources of transistors BN4 to BN7 are in the off state, controlled by the first enable signal EN_LN, transistors BN4 to BN7 do not supply ground voltage to the output nodes VOM and VOP. That is, the low-noise reset circuits LNRC1 and LNRC2 can be disabled.

[0131] Next, refer to Figure 21 In low-noise mode, for example, control logic ( Figure 1 The 300) keeps the signal level of the third clock signal QLP at logic low level L, and can switch the signal level of the second clock signal QLN to repeat logic low level L and logic high level H. Furthermore, in low-noise mode, the control logic ( Figure 1 (300) can keep the signal level of the first enable signal EN_LN at a logic high level H and the signal level of the second enable signal EN_LP at a logic low level L.

[0132] Therefore, the first preamplifier 710 is disabled, the second preamplifier 720 is enabled, and the comparison signal CS can be generated by the shared latch 730. That is, in an exemplary embodiment, in low-noise mode, not both the first preamplifier 710 and the second preamplifier 720 are enabled, but only the second preamplifier 720 is enabled.

[0133] At this time, when the switches controlled by the first enable signal EN_LN and set at the sources of transistors BN4 to BN7 are in the ON state, Figure 19The transistors BN4 to BN7 of the shared latch 730 can provide ground voltage to the output nodes VOM and VOP. However, in an exemplary embodiment, when the switches set at the sources of transistors SN4 to SN7 are in the off state, controlled by the second enable signal EN_LP, transistors SN4 to SN7 do not provide ground voltage to the output nodes VOM and VOP. That is, the low-noise reset circuits LNRC1 and LNRC2 can be enabled to generate the comparison signal CS.

[0134] Figure 22 This is a block diagram of a semiconductor device according to an exemplary embodiment.

[0135] Reference Figure 22 The comparator 800 of the semiconductor device according to an exemplary embodiment may include a plurality of preamplifiers 810-1 to 810-k (where k is a positive integer greater than 2). Different clock signals Q1 to Qk may be provided to each of the preamplifiers 810-1 to 810-k.

[0136] Multiple preamplifiers 810-1 to 810-k can be connected to a shared latch 830. That is, multiple preamplifiers 810-1 to 810-k can share a single latch to generate a comparison signal CS. Multiple enable signals EN_1 to EN_k can be provided to the shared latch 830 to determine whether the functional circuitry located in the shared latch 830 is enabled.

[0137] As is customary in the field of the inventive concept, exemplary embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) formed using semiconductor-based or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or the like, they can be programmed with software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Optionally, each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry).

[0138] Although the invention has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. An analog-to-digital converter, comprising: The comparator is configured to compare the input signal with a reference signal and output a comparison signal indicating the corresponding comparison result. The control logic is configured to output a control signal for adjusting the reference signal based on the comparison signal; as well as The reference signal conditioning circuit is configured to condition the reference signal based on a control signal. The comparator includes: A first preamplifier is configured to amplify the difference between an input signal and a reference signal using a first transistor having a first size. The second preamplifier is configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size; and The latch is configured to generate a comparison signal using at least one of the outputs of a first preamplifier and a second preamplifier. The first preamplifier and the second preamplifier share a latch.

2. The analog-to-digital converter according to claim 1, wherein, The latch uses a third transistor with a third size and a fourth transistor with a fourth size different from the third size to generate a comparison signal.

3. The analog-to-digital converter according to claim 2, wherein, The latch includes: The first reset circuit is configured to reset the first and second output nodes of the latch using a third transistor. The second reset circuit is configured to: reset the first output node and the second output node using a fourth transistor; and The amplifier circuit is configured to amplify the voltage levels of the first output node and the second output node using at least one of the outputs of the first preamplifier and the second preamplifier.

4. The analog-to-digital converter according to claim 3, wherein, Control signals include: The first control signal is provided to the reference signal conditioning circuit; and The second control signal determines whether the second reset circuit is enabled.

5. The analog-to-digital converter according to claim 1, wherein, The latch includes: The first reset circuit is configured to receive the output of the first preamplifier and use a third transistor of a third size to reset the first output node and the second output node of the latch. The second reset circuit is configured to: receive the output of the second preamplifier and use a fourth transistor having a fourth size different from the third size to reset the first and second output nodes; and The amplifier circuit is configured to amplify the voltage levels of the first output node and the second output node using at least one of the outputs of the first preamplifier and the second preamplifier.

6. The analog-to-digital converter according to claim 5, wherein, Control signals include: The first control signal is provided to the reference signal conditioning circuit; and The second control signal determines whether the second reset circuit is enabled. The second reset circuit includes a switch controlled by a second control signal and connected to the first output node and ground, and a switch controlled by the second control signal and connected to the second output node and ground.

7. The analog-to-digital converter according to claim 5, wherein, Control signals include: The first control signal is provided to the reference signal adjustment circuit; The second control signal determines whether the second reset circuit is enabled; and The third control signal determines whether the second preamplifier is enabled, and is different from the second control signal.

8. The analog-to-digital converter according to any one of claims 1 to 7, wherein, The comparison signals include: The first comparison signal is generated using a first preamplifier and a latch; and The second comparison signal is generated using a second preamplifier and a latch. The control logic converts the input signal into a digital signal that includes a first bit and a second bit. The value of the first bit is determined using a first comparison signal, and the value of the second bit is determined using a second comparison signal.

9. The analog-to-digital converter according to claim 8, wherein, The first comparison signal is generated before the second comparison signal, and The first dimension is smaller than the second dimension.

10. The analog-to-digital converter according to claim 8, wherein, The first comparison signal is generated before the second comparison signal. The first comparison signal is generated without using a second preamplifier, and The second comparison signal is generated using a first preamplifier and a second preamplifier.

11. The analog-to-digital converter according to claim 8, wherein, The first comparison signal is generated before the second comparison signal. The first comparison signal is generated without using a second preamplifier, and The second comparison signal is generated without using the first preamplifier.

12. The analog-to-digital converter according to any one of claims 1 to 7, further comprising: The sampling circuit is configured to: receive the input signal, sample and hold the input signal, and provide the sampled input signal to the comparator. The reference signal conditioning circuit adjusts the voltage level of the reference signal according to the control signal.

13. The analog-to-digital converter according to claim 12, wherein, The analog-to-digital converter is a successive approximation register analog-to-digital converter.

14. An analog-to-digital converter, comprising: The comparator is configured to compare an input signal with a reference signal and output a first comparison signal and a second comparison signal indicating the corresponding comparison result. as well as The control logic is configured to: determine a first bit value based on a first comparison signal, determine a second bit value based on a second comparison signal, and determine a third bit value corresponding to the input signal based on the first bit value and the second bit value. The comparator includes: The first preamplifier is configured to amplify the difference between the input signal and the reference signal; The second preamplifier is configured to amplify the difference between the input signal and the reference signal; and The latch is configured to generate a first comparison signal and a second comparison signal using at least one of the outputs of a first preamplifier and a second preamplifier. in, The dimensions of the first preamplifier and the second preamplifier are different from each other, and The control logic controls the first preamplifier and the second preamplifier, such that the first comparison signal is generated using the first preamplifier and the second comparison signal is generated using the second preamplifier.

15. The analog-to-digital converter according to claim 14, wherein, The first comparison signal is output before the second comparison signal, and The size of the first preamplifier is smaller than the size of the second preamplifier.

16. The analog-to-digital converter according to claim 15, wherein, The control logic controls the first preamplifier and the second preamplifier such that the first comparison signal is generated using the first preamplifier but not the second preamplifier, and the second comparison signal is generated using both the first and second preamplifiers.

17. The analog-to-digital converter according to claim 15, wherein, The control logic controls the first preamplifier and the second preamplifier such that the first comparison signal is generated using the first preamplifier but not the second preamplifier, and the second comparison signal is generated using the second preamplifier but not the first preamplifier.

18. The analog-to-digital converter according to any one of claims 14 to 17, further comprising: The reference signal conditioning circuit is configured to condition the reference signal. Specifically, the control logic generates a control signal for adjusting the reference signal based on the first comparison signal and the second comparison signal, and provides the control signal to the reference signal adjustment circuit. The reference signal conditioning circuit adjusts the reference signal based on the control signal.

19. An analog-to-digital converter, comprising: The comparator is configured to compare the input signal with a reference signal and output a comparison signal indicating the corresponding comparison result. The control logic is configured to: output a control signal for adjusting a reference signal based on a comparison signal, and determine a digital signal corresponding to the input signal based on the comparison signal; as well as The reference signal conditioning circuit is configured to condition the reference signal based on a control signal. The comparator includes: A first preamplifier is configured to amplify the difference between an input signal and a reference signal using a first transistor having a first size. The second preamplifier is configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size; and The latch is configured to generate a comparison signal using at least one of the outputs of a first preamplifier and a second preamplifier. The latch includes: The first reset circuit is configured to receive the output of the first preamplifier and use a third transistor of a third size to reset the first output node and the second output node of the latch. The second reset circuit is configured to: receive the output of the second preamplifier and use a fourth transistor having a fourth size different from the third size to reset the first and second output nodes; and The amplifier circuit is configured to amplify the voltage level of the first output node and the voltage level of the second output node using at least one of the outputs of the first preamplifier and the second preamplifier.

20. The analog-to-digital converter according to claim 19, wherein, The comparison signals include a first comparison signal and a second comparison signal that is output later than the first comparison signal. The comparator uses a first preamplifier, a first reset circuit, and an amplifier circuit, but not a second preamplifier and a second reset circuit, to output a first comparison signal. The comparator uses a first preamplifier, a second preamplifier, a first reset circuit, a second reset circuit, and an amplifier circuit to output a second comparison signal. The first dimension is smaller than the second dimension, and The third dimension is smaller than the fourth dimension.

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