Chip-to-wafer bonding structure and semiconductor package using the same

Abstract

According to one aspect of the present invention, a wafer-to-wafer bonding structure is provided, comprising a wafer having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, wherein the first bonding pad penetrates the first insulating layer. The structure may further comprise a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, wherein the second bonding pad penetrates the second insulating layer. The structure may further comprise a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the wafer and the wafer. In addition, the wafer and the wafer may be bonded together.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0123973, filed on October 7, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a wafer-to-wafer bonding structure and a semiconductor package using the same, and more particularly, to a wafer-to-wafer bonding structure including a polymer layer and a semiconductor package using the same. Background Art

[0004] Recently, in response to the rapid development of the electronics industry and user demands, electronic devices have become more compact and lightweight. Semiconductor packages used in these devices are being required to achieve high performance and large capacity, as well as miniaturization and lightweighting. In response to these demands, research and development are underway into semiconductor packages in which multiple semiconductor chips are combined to achieve these performance, large capacity, miniaturization, and lightweighting. Summary of the Invention

[0005] The inventive concept provides a wafer-to-wafer bonding structure having excellent bonding reliability between directly bonded (direct bonding) bonding pads and a semiconductor package using the same.

[0006] Problems to be solved by the technical ideas of the present invention are not limited to the above problems, and those skilled in the art can clearly understand other unmentioned problems from the following description.

[0007] According to one aspect of the present invention, a wafer-to-wafer bonding structure is provided, comprising a wafer having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, wherein the first bonding pad penetrates the first insulating layer. The structure may further comprise a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, wherein the second bonding pad penetrates the second insulating layer. The structure may further comprise a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the wafer and the wafer. In addition, the wafer and the wafer may be bonded together.

[0008] According to another aspect of the present invention, a wafer-to-wafer bonding structure is provided, comprising a wafer having a first integrated circuit layer on a first substrate, a first metal wiring layer connected to the first integrated circuit layer, a plurality of first test pads on the first metal wiring layer, a first insulating layer, and a plurality of first bonding pads formed on the plurality of first test pads, the plurality of first bonding pads penetrating the first insulating layer. The structure may also include a wafer having a second integrated circuit layer on a second substrate, a second metal wiring layer connected to the second integrated circuit layer, a plurality of second test pads on the second metal wiring layer, a second insulating layer, and a plurality of second bonding pads formed on the plurality of second test pads, the plurality of second bonding pads penetrating the second insulating layer. The structure may also include a polymer layer surrounding all side surfaces of the first bonding pads and all side surfaces of the second bonding pads, the polymer layer being arranged between the wafer and the wafer. In addition, an uneven portion may be formed on a surface of at least one of the plurality of first test pads, and the plurality of first bonding pads and the plurality of second bonding pads face each other and are bonded to each other.

[0009] According to another aspect of the present invention, a semiconductor package is provided, comprising a first metal wiring layer on a first substrate, a first test pad on the first metal wiring layer, a first insulating layer on the first test pad, a polymer layer on the first test pad and the first insulating layer, a second insulating layer on the polymer layer, and a second test pad on the polymer layer and the second insulating layer. The structure may further include a second metal wiring layer on the second test pad, a second substrate on the second metal wiring layer, and a bonding pad that penetrates the polymer layer and connects the first test pad and the second test pad, the bonding pad being surrounded by the polymer layer.

[0010] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, the method comprising: preparing a first wafer, the first wafer comprising a first metal wiring layer on a first substrate, a first test pad on the first metal wiring layer, and a first insulating layer on the first test pad, the first wafer comprising a plurality of separate wafers. The method may further comprise: patterning the first insulating layer to expose the top surface of the first test pad; performing a test by contacting the exposed first test pad with a test pin of a test device; forming a mask pattern on the first insulating layer and the first test pad; and forming a first bonding pad on a surface of the first test pad where the mask pattern is not formed. The method may further comprise: removing the mask pattern; forming a first polymer layer covering all of the first insulating layer, the first test pad, and the first bonding pad; exposing the first bonding pad by polishing the first polymer layer; separating the first wafer into separate wafers by cutting the first wafer; and bonding the separated wafers to a second wafer. In addition, each wafer may comprise at least one first bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view illustrating a bonding portion of a wafer-to-wafer bonding structure according to an embodiment of the inventive concept;

[0013] Figures 2A to 2C It shows the manufacturing Figure 1 A cross-sectional view of a portion of a process for a wafer-to-wafer bonding structure;

[0014] Figures 3 to 5 is a cross-sectional view illustrating a bonding portion of a wafer-to-wafer bonding structure according to an embodiment of the inventive concept;

[0015] Figure 6 is a perspective view illustrating a die-to-wafer bonding process according to an embodiment of the present inventive concept;

[0016] Figure 7 is a cross-sectional view illustrating a wafer-to-wafer bonding structure according to an embodiment of the inventive concept;

[0017] Figures 8A to 8I It shows the manufacturing Figure 7 A cross-sectional view of a process of a wafer-to-wafer bonding structure;

[0018] Figure 9 is a cross-sectional view illustrating a wafer-to-wafer bonding structure according to an embodiment of the inventive concept;

[0019] Figure 10A and Figure 10B It shows the manufacturing Figure 9 A cross-sectional view of a portion of a process for a wafer-to-wafer bonding structure;

[0020] Figure 11 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept;

[0021] Figure 12 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a cross-sectional view illustrating a bonding portion of a wafer-to-wafer bonding structure 10 according to an embodiment of the inventive concept.

[0024] Reference Figure 1, the wafer-to-wafer bonding structure 10 may have a structure in which a wafer 100 - 1 is bonded to a wafer 100 - 2 .

[0025] Wafer 100-1 may refer to a separate semiconductor wafer or a separate semiconductor chip. Wafer 100-1 may include a first test pad 110-1, a first insulating layer 120-1, a first bonding pad 130-1, a first polymer layer 140-1, and a first interlayer insulating layer 150-1. For ease of description, the surface of wafer 100-1 that contacts wafer 100-2 may be referred to as the top surface of wafer 100-1, and the surface of wafer 100-1 opposite to the top surface of wafer 100-1 may be referred to as the bottom surface of wafer 100-1. For example, the top surface of wafer 100-1 may contact wafer 100-2, and the bottom surface of wafer 100-1 may be opposite to the top surface of wafer 100-1 and not in direct contact with wafer 100-2. In addition, the top surface and the bottom surface may extend in a horizontal direction.

[0026] Wafer 100-2 may refer to a substrate in which multiple semiconductor wafers are not individually separated or a substrate in which multiple semiconductor chips are not individually separated. For example, a wafer may include a substrate on which multiple semiconductor wafers and / or multiple semiconductor chips are arranged. Wafer 100-2 may include a second test pad 110-2, a second insulating layer 120-2, a second bonding pad 130-2, a second polymer layer 140-2, and a second interlayer insulating layer 150-2. For convenience of description, the surface of wafer 100-2 that contacts wafer 100-1 may be referred to as the top surface of wafer 100-2, and the surface of wafer 100-2 opposite to the top surface of wafer 100-2 may be referred to as the bottom surface of wafer 100-2. For example, the top surface of wafer 100-2 may contact wafer 100-1, and the bottom surface of wafer 100-2 may be opposite to the top surface of wafer 100-2 and not in direct contact with wafer 100-1. It will be understood that when an element is referred to as being in "contact" with another element, it can be directly in contact with, connected to, or coupled to the other element or to another element, or intervening elements may be present. In contrast, when an element is referred to as being in "direct contact" with another element, there are no intervening elements.

[0027] For example, the first test pad 110-1 may have a dual inlay pattern. The dual inlay pattern may be a pattern having a structure with a narrow bottom and a wide top, and may be formed by a dual inlay process. For example, the material constituting the first test pad 110-1 may include aluminum (Al). The material constituting the first test pad 110-1 may include a metal having relatively low hardness and strength compared to the material constituting the first bonding pad 130-1. For example, the top surface of the first test pad 110-1 may have a rectangular shape. However, the shape of the top surface of the first test pad 110-1 may not be limited to a rectangular shape. For example, the top surface of the first test pad 110-1 may have various shapes such as a circular shape, an elliptical shape, and a polygonal shape.

[0028] The first test pad 110-1 may be configured as a plurality, for example, a plurality of first test pads 110-1. The first bonding pad 130-1 may be formed on a portion (or a subgroup) of the plurality of first test pads 110-1, and the first bonding pad 130-1 may not be formed on the remaining portion of the plurality of first test pads 110-1. For example, the first bonding pad 130-1 may be formed only on a subgroup of the plurality of first test pads 110-1, and may not be formed on every bonding pad in the plurality of first bonding pads 130-1. The first insulating layer 120-1, the first bonding pad 130-1, and the first polymer layer 140-1 may contact the top surface of the first test pad 110-1 on which the first bonding pad 130-1 is formed. In addition, the first insulating layer 120-1 and the first polymer layer 140-1 may contact the top surface of the first test pad 110-1 on which the first bonding pad 130-1 is not formed.

[0029] When viewed from a side view, the maximum width of the first test pad 110-1 in the horizontal direction may be greater than the maximum width of the first bonding pad 130-1 in the horizontal direction. In addition, when viewed in a plan view, the surface area of ​​the first test pad 110-1 may be greater than the surface area of ​​the first bonding pad 130-1.

[0030] For example, the first insulating layer 120-1 may include silicon oxide, silicon nitride, and / or silicon oxynitride. The first insulating layer 120-1 may include a single layer of a single material, or may include multiple layers of different materials. For example, when the first insulating layer 120-1 includes multiple layers, the first insulating layer 120-1 may include a first silicon nitride carbon (SiCN) layer, a tetraethyl orthosilicate (TEOS) layer, and a second SiCN layer. In addition, the first insulating layer 120-1 may include a first SiCN layer, a first TEOS layer, a second SiCN layer, and a second TEOS layer.

[0031] The first bonding pad 130-1 may be arranged on some of the plurality of first test pads 110-1. The first bonding pad 130-1 may be arranged so that the bottom surface of the first bonding pad 130-1 contacts the top surface of the first test pad 110-1 without passing through a vertical contact. For example, the bottom surface of the first bonding pad 130-1 may directly contact the top surface of the first test pad 110-1. In addition, all side surfaces of the first bonding pad 130-1 may be surrounded by the first polymer layer 140-1.

[0032] The first bonding pad 130-1 may be formed by, for example, a plating process or a physical vapor deposition (PVD) process. The first bonding pad 130-1 may have, for example, a cylindrical shape. However, the shape of the first bonding pad 130-1 is not limited thereto. For example, the first bonding pad 130-1 may have various shapes such as an elliptical column, a square column, and a polygonal column.

[0033] The first bonding pad 130-1 may have various sizes. For example, the width of the first bonding pad 130-1 in the horizontal direction may be about 1 μm to about 20 μm. For example, the thickness of the first bonding pad 130-1 in the vertical direction may be about 15% to about 50% of its width. In addition, as the width of the first bonding pad 130-1 increases, the ratio of thickness to width may decrease relatively. For example, when the width of the first bonding pad 130-1 is about 1 μm, its thickness may be about 1 μm to about 201 μm. When the width of the first bonding pad 130-1 is about 201 μm, its thickness may be about 31 μm to about 51 μm. Of course, the width and thickness of the first bonding pad 130-1 are not limited to the above values.

[0034] The first polymer layer 140-1 may be formed on the first test pad 110-1 and the first insulating layer 120-1 and may have a structure surrounding the side surface of the first bonding pad 130-1. The first polymer layer 140-1 may have a structure surrounding all side surfaces and the top surface of the first insulating layer 120-1 and the side surface of the first bonding pad 130-1. In addition, the top surface S1 of the first bonding pad 130-1 may be coplanar with the top surface S2 of the first polymer layer 140-1.

[0035] For example, the first polymer layer 140-1 may include a polymer material having relatively high heat resistance and high bonding strength. The first polymer layer 140-1 may include a material that is easily reflowed by heat treatment or easily combined with another polymer (e.g., the second polymer layer 140-2 of the wafer 100-2) by heat treatment. In addition, the first polymer layer 140-1 may include a material that is cured by heat treatment and maintains strong bonding due to the curing.

[0036] In some embodiments, for example, the first polymer layer 140-1 may include any one of polyimide, polyamide, polyacrylate, and polyaramid. Of course, the material of the first polymer layer 140-1 is not limited thereto. In other embodiments, when the first polymer layer 140-1 has the aforementioned properties (e.g., heat resistance, reflowability, higher bonding strength through curing, etc.), the first polymer layer 140-1 may include other types of materials besides the aforementioned materials.

[0037] The structure, material, etc. of the elements constituting the wafer 100 - 2 may be substantially the same as or similar to the structure, material, etc. of the elements constituting the wafer 100 - 1 described above. Therefore, a detailed description of the wafer 100 - 2 is omitted.

[0038] In some embodiments, the first test pad 110-1 may include some other characteristics compared to the second test pad 110-2. An uneven portion 110-1G (non-planar portion) may be formed in at least one first test pad 110-1. For example, Figure 1 As shown, a left first test pad 110-1 (marked) and a right first test pad 110-1 (unmarked) are shown, and the uneven portion 110-1G may correspond to a protrusion and / or depression (protrusion and / or indentation) that is non-planar and not coplanar with the other test pads 110-1. For another example, the right first test pad 110-1 (unmarked) is not coplanar with the left first test pad 110-1 (marked). The uneven portion 110-1G of the first test pad 110-1 may be formed by a test process for screening the wafer 100-1. The test process may be performed to verify the functionality and electrical connections of the wafer 100-1. The uneven portion 110-1G may be formed by placing a test device (see Figure 8C TA) test pin (see Figure 8C The test process is performed by physically contacting the first test pad 110-1 with the TP in the first test pad 110-1. Compared with the non-contact test process, the contact test process can have relatively high test performance, and thus the contact test process can have advantages over the non-contact test process. However, the contact test process may be accompanied by a shape that reduces surface uniformity, such as the uneven portion 110-1G of the first test pad 110-1.

[0039] Despite Figure 11 and 13. The first bonding pad 130-1 and the second bonding pad 130-2 and the first polymer layer 140-1 and the second polymer layer 140-2 are distinguished from each other by dot-dash lines, but the illustration is intended to indicate that the first bonding pad 130-1 and the first polymer layer 140-1 originate from the wafer 100-1, and the second bonding pad 130-2 and the second polymer layer 140-2 originate from the wafer 100-2. Therefore, those skilled in the art will understand that the first bonding pad 130-1 and the second bonding pad 130-2 can be bonded to each other to form the integrated bonding pad 130A, and the first polymer layer 140-1 and the second polymer layer 140-2 can be bonded to each other to form the polymer layer 140A in an integral configuration.

[0040] The wafer-to-wafer bonding structure 10 may have a structure in which the wafer 100-1 and the wafer 100-2 are bonded to each other through heat treatment. For example, the first bonding pad 130-1 and the second bonding pad 130-2 may be bonded by heat treatment, and the first polymer layer 140-1 and the second polymer layer 140-2 may be bonded by heat treatment. Here, the heat treatment may be performed at a temperature at which a bonded coupling is formed between the first bonding pad 130-1 and the second bonding pad 130-2. In some embodiments, for example, the heat treatment temperature may be about 180°C to about 300°C.

[0041] As described above, the first polymer layer 140-1 and the second polymer layer 140-2 have fluidity due to reflow when heated within the heat treatment temperature range disclosed above, and thus can fill unwanted gaps. In addition, since the first polymer layer 140-1 and the second polymer layer 140-2 maintain strong bonding due to curing through heat treatment, the possibility of bonding failure (which may occur in bonding between conventional silicon-on-insulator layers) can be prevented and / or suppressed.

[0042] Furthermore, the first polymer layer 140-1 and the second polymer layer 140-2 may be cured by heat treatment to have a degree of curing of approximately 90% or higher. Generally, curing may refer to crystallization of a polymer material above its glass transition temperature. For example, a degree of curing of approximately 90% or higher may mean that approximately 90% or more of the polymer material crystallizes above its glass transition temperature, and this crystallization allows for very strong bonding.

[0043] As a result, in the wafer-to-wafer bonding structure 10 according to the technical concept of the present invention, the reflow of the polymer layer 140A can be used to fill unwanted voids, and defects caused by this phenomenon can be prevented and / or suppressed. In addition, by bonding the polymer layer 140A with a degree of cure of approximately 90% or higher, a very strong bonding force can be maintained. For example, when a reflow process is used in which the first polymer layer 140-1 and the second polymer layer 140-2 are heated to an appropriate heat treatment temperature, the resulting polymer layer 140A can have a degree of cure of approximately 90% or higher, thereby forming a relatively strong bonding force between the wafer 100-1 and the wafer 100-2.

[0044] Furthermore, by filling the uneven portion 110-1G with a material having good fluidity like the first polymer layer 140-1, the wafer-to-wafer bonding structure 10 according to the technical concept of the present invention can form a reliable bonding structure that is not affected by the surface uniformity of the first test pad 110-1. For example, when the test equipment (see Figure 8C When the uneven portion 110-1G is formed in the first test pad 110-1 due to the TA in FIG, the uneven portion 110-1G can be reliably filled by the reflow process as described above.

[0045] Finally, since the tested known good die (KGD) 100 - 1 can be mounted on the wafer 100 - 2 in a reliable bonding structure, the wafer-to-wafer bonding structure 10 according to the technical concept of the present invention can increase the yield and reliability of semiconductor packages.

[0046] Figures 2A to 2C It shows the manufacturing Figure 1 FIG. 1 is a cross-sectional view of a portion of a process for a wafer-to-wafer bonding structure 10 .

[0047] Reference Figure 2A , a first insulating layer 120 - 1 including a first opening 120 - 1H may be formed on the first interlayer insulating layer 150 - 1 and the first test pad 110 - 1 .

[0048] After forming a preliminary insulating layer on the first interlayer insulating layer 150-1 and the first test pad 110-1, the first insulating layer 120-1 having the first opening 120-1H exposing the central portion of the first test pad 110-1 may be formed by patterning the preliminary insulating layer through phototreatment and etching processes.

[0049] In the test process for screening the wafer 100-1, the uneven portion 110-1G of the first test pad 110-1 may be formed. Figure 8C TA) test pin (see Figure 8CThe TP in FIG. 1 is in physical contact with the first test pad 110-1 to perform a test process. In this way, a shape that reduces surface uniformity, such as an uneven portion 110-1G of the first test pad 110-1, may be included.

[0050] Reference Figure 2B , the preliminary bonding pads 130 - 1P may be arranged on some of the plurality of first test pads 110 - 1 .

[0051] The preliminary bonding pad 130-1P may be arranged so that its bottom surface contacts the top surface of the first test pad 110-1. The preliminary bonding pad 130-1P may be formed only on the first test pad 110-1 that does not include the uneven portion 110-1G among the plurality of first test pads 110-1. For example, the preliminary bonding pad 130-1P may be formed only on the test pin TP (see FIG. Figure 8C ) is not in contact with and / or will not contact the corresponding first test pad 110-1. For another example, the preliminary bonding pad 130-1P may be formed only on the untested pin TP (see Figure 8C ) on a subset of the first test pads 110-1 that are in contact with and / or deformed, and may not be formed on the tested pins TP (see Figure 8C ) on the remaining first test pad 110 - 1 that is in contact with and / or deformed.

[0052] The preliminary bonding pad 130-1P may be formed, for example, by a plating process or a physical vapor deposition (PVD) process. For example, the material constituting the preliminary bonding pad 130-1P may include copper (Cu). The material constituting the preliminary bonding pad 130-1P may include a metal having relatively higher hardness and strength than the material constituting the first test pad 110-1.

[0053] The preliminary bonding pad 130-1P may have, for example, a cylindrical shape. The thickness of the preliminary bonding pad 130-1P in the vertical direction may be greater than the thickness of the first insulating layer 120-1 in the vertical direction. In addition, the width of the preliminary bonding pad 130-1P in the horizontal direction may be smaller than the width of the first opening 120-1H in the horizontal direction.

[0054] Reference Figure 2C , a first polymer layer 140 - 1 may be formed on the first insulating layer 120 - 1 and the first test pad 110 - 1 to cover side surfaces of the first bonding pad 130 - 1 .

[0055] The first polymer layer 140-1 may have a structure that surrounds all side surfaces and the top surface of the first insulating layer 120-1 and the side surface of the first bonding pad 130-1. This structure can reduce defects that occur at the contact area between different materials by reducing the types of materials that contact the first bonding pad 130-1. In some embodiments, the first polymer layer 140-1 may not contact the top surface of the bonding pad 130-1.

[0056] The first polymer layer 140-1 may include a polymer material having relatively high heat resistance and high bonding strength. The first polymer layer 140-1 may include a material that is easily reflowed by heat treatment and is also easily bonded to other polymer layers and / or materials by heat treatment. In addition, the first polymer layer 140-1 may include a material that is cured by heat treatment and maintains strong bonding due to the curing.

[0057] When viewed from the side, the maximum width 110-1W of the first test pad 110-1 in the horizontal direction may be greater than the maximum width 130-1W of the first bonding pad 130-1 in the horizontal direction. In addition, when viewed in a plan view, the surface area of ​​the first test pad 110-1 may be greater than the surface area of ​​the first bonding pad 130-1. Therefore, not only the first bonding pad 130-1, but also the first insulating layer 120-1 and the first polymer layer 140-1 may contact the top surface of the first test pad 110-1.

[0058] The thickness 120-1T of the first insulating layer 120-1 in the vertical direction may be approximately 0.5 μm to approximately 10 μm. In addition, the thickness 140-1T of the first polymer layer 140-1 in the vertical direction may be approximately 1 μm to approximately 20 μm. The thickness 140-1T of the first polymer layer 140-1 in the vertical direction may be approximately two times or more the thickness 120-1T of the first insulating layer 120-1 in the vertical direction. In some embodiments, the increase in the exposed surface of the first polymer layer 140-1 and the increase in its thickness may intentionally maintain a strong bonding force in the chip-to-wafer bonding structure 10. In addition, the thickness of the polymer layer 140A in the vertical direction may be approximately two times the thickness 140-1T of the first polymer layer 140-1 in the vertical direction, and may be approximately 2 μm to approximately 40 μm.

[0059] In addition, the thickness 140-1T of the first polymer layer 140-1 in the vertical direction may be substantially the same as the thickness of the first bonding pad 130-1 in the vertical direction. For example, the top surface of the first polymer layer 140-1 may be coplanar with the top surface of the first bonding pad 130-1. This may be because the first polymer layer 140-1 is planarized together with the first bonding pad 130-1.

[0060] The chip 100-1 manufactured in this process is mounted on the wafer 100-2 (see Figure 1 ), a wafer-to-wafer bonding structure 10 according to an example embodiment of the inventive concept may be manufactured.

[0061] Figures 3 to 5 are cross-sectional views illustrating bonding portions of a wafer-to-wafer bonding structure 10 according to example embodiments of the inventive concepts.

[0062] Most of the components constituting each of the wafer-to-wafer bonding structures (20, 30, 40) and the materials included in the components described below can be compared with those in the reference Figure 1 Therefore, for the convenience of description, the following description will mainly focus on the above-mentioned chip-to-wafer bonding structure 10 (refer to Figure 1 ) is different.

[0063] Reference Figure 3 , the wafer-to-wafer bonding structure 20 may have a structure in which the wafer 100 - 3 is bonded to the wafer 100 - 4 .

[0064] The wafer 100 - 3 may include a third test pad 110 - 3 , a third insulating layer 120 - 3 , a third bonding pad 130 - 3 , a third polymer layer 140 - 3 , and a third interlayer insulating layer 150 - 3 .

[0065] The third bonding pad 130-3 may be formed on all of the plurality of third test pads 110-3. For example, the third bonding pad 130-3 may be formed on each of the plurality of third test pads 110-3. The third bonding pad 130-3 may be arranged so that the bottom surface of the third bonding pad 130-3 contacts the top surface of the third test pad 110-3. All side surfaces of the third bonding pad 130-3 may be surrounded by the third polymer layer 140-3.

[0066] The wafer 100-4 may have substantially the same or similar configuration as the die 100-3 and may include a fourth test pad 110-4, a fourth insulating layer 120-4, a fourth bonding pad 130-4, a fourth polymer layer 140-4, and a fourth interlayer insulating layer 150-4.

[0067] In some embodiments, the third test pad 110-3 may include some other characteristics compared to the fourth test pad 110-4. For example, an uneven portion 110-3G may be formed in at least one of the third test pads 110-3. As explained above, the uneven portion 110-3G of the third test pad 110-3 may be formed during the test process for screening the wafer 100-3. In contrast, the uneven portion may not be formed in the fourth test pad 110-4.

[0068] The third bonding pad 130-3 may fill the uneven portion 110-3G of the third test pad 110-3. Thus, the third bonding pad 130-3 may be formed on the third test pad 110-3 including the uneven portion 110-3G. Figure 3 The surface profile of the bottom surface of the third bonding pad 130-3 (on the right side in FIG. 1 ) may have a shape according to (defined by) the shape of the top surface of the third test pad 110-3. In contrast, the surface profile of the bottom surface of the third test pad 110-3 (on the right side in FIG. 1 ) formed on the third test pad 110-3 without the uneven portion 110-3G may have a shape according to (defined by) the shape of the top surface of the third test pad 110-3. Figure 3 The bottom surface of the third bonding pad 130-3 (left side in FIG) may be a flat surface (eg, a planar surface). As a result, the thickness of some bonding pads 130B among the plurality of bonding pads 130B may be greater than the thickness of other bonding pads 130B among the plurality of bonding pads 130B.

[0069] By having the uneven portion 110 - 3G of the third test pad 110 - 3 filled by the third bonding pad 130 - 3 , the wafer-to-wafer bonding structure 20 according to the technical idea of ​​the present inventive concept may form a reliable structure that is not affected by the surface uniformity of the third test pad 110 - 3 .

[0070] Reference Figure 4 , the wafer-to-wafer bonding structure 30 may have a structure in which the wafer 100 - 1 is bonded to the wafer 100 - 2 .

[0071] The wafer 100-1 may be formed in a structure in which the first barrier metal layer 131-1 surrounds the bottom surface and side surfaces of the first bonding pad 130-1. The first barrier metal layer 131-1 may face the first test pad 110-1 so that the bottom surface of the first barrier metal layer 131-1 contacts the first test pad 110-1 and the side surface of the first barrier metal layer 131-1 contacts the first polymer layer 140-1.

[0072] In substantially the same manner, the wafer 100-2 may be formed in a structure in which the second barrier metal layer 131-2 surrounds the lower surface and side surfaces of the second bonding pad 130-2. The second barrier metal layer 131-2 may face the structure of the second bonding pad 130-2 such that the bottom surface of the second barrier metal layer 131-2 contacts the second test pad 110-2 and the side surface of the second barrier metal layer 131-2 contacts the second polymer layer 140-2.

[0073] The first barrier metal layer 131-1 can prevent the diffusion of Cu (which can be a material constituting the first bonding pad 130-1) and can include a stacked structure including, for example, one or more of titanium (Ti) and tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). However, the material of the first polymer layer 140-1 is not limited thereto.

[0074] The first bonding pads 130-1 and the first barrier metal layer 131-1 may be formed on some portions of the plurality of first test pads 110-1, and may not be formed on other portions of the plurality of first test pads 110-1. For example, the first bonding pads 130-1 and the first barrier metal layer 131-1 may be formed only on some (a subset) of the first test pads 110-1, and may not be formed on the remaining first test pads 110-1 (the remaining subset).

[0075] The first polymer layer 140-1 may be formed on the first test pad 110-1 and the first insulating layer 120-1 and may have a structure surrounding the side surface of the first barrier metal layer 130-1. The first polymer layer 140-1 may have a structure surrounding all side surfaces and the top surface of the first insulating layer 120-1 and the side surface of the first barrier metal layer 131-1. In addition, the top surface S1 of the first bonding pad 130-1, the top surface S11 of the first barrier metal layer 131-1, and the top surface S2 of the first polymer layer 140-1 may be coplanar with each other. This may be, for example, the result of the first bonding pad 130-1, the first barrier metal layer 131-1, and the first polymer layer 140-1 being planarized relative to each other.

[0076] Despite Figure 4 In the figure, the first bonding pad 130-1 and the second bonding pad 130-2, the first barrier metal layer 131-1 and the second barrier metal layer 131-2, and the first polymer layer 140-1 and the second polymer layer 140-2 are distinguished from each other by dot-dash lines, but this illustration is intended to indicate that the first bonding pad 130-1, the first barrier metal layer 131-1, and the first polymer layer 140-1 originate from the wafer 100-1, and the second bonding pad 130-2, the second barrier metal layer 131-2, and the second polymer layer 140-2 originate from the wafer 100-2. Therefore, the first bonding pad 130-1 and the second bonding pad 130-2 may be directly bonded to each other to form an integrated bonding pad 130C, the first barrier metal layer 131-1 and the second barrier metal layer 131-2 may be directly bonded to each other to form an integrated barrier metal layer 131C, and the first polymer layer 140-1 and the second polymer layer 140-2 may be directly bonded to each other to form an integrated polymer layer 140C.

[0077] Reference Figure 5, the wafer-to-wafer bonding structure 40 may have a structure in which the wafer 100 - 3 is bonded to the wafer 100 - 4 .

[0078] The wafer-to-wafer bonding structure 40 can be conceptually considered to be similar to the wafer-to-wafer bonding structure 20 (see FIG. Figure 3 ) characteristics and the chip-to-wafer bonding structure 30 (refer to Figure 4 ) have essentially the same feature combination.

[0079] Therefore, those skilled in the art will understand the wafer-to-wafer bonding structure 40 by referring to the description of the wafer-to-wafer bonding structures 20 and 30 given above. Therefore, a detailed description of the wafer-to-wafer bonding structure 40 is omitted.

[0080] In addition, the third barrier metal layer 131-3 may fill the uneven portion 110-3G of the third test pad 110-3. Therefore, the third test pad 110-3 including the uneven portion 110-3G may be formed on the third test pad 110-3 (located at Figure 5 The surface profile of the bottom surface of the third barrier metal layer 131-3 on the right side of the figure may have a surface profile according to (defined by) (also located at Figure 5 On the contrary, the top surface of the third test pad 110-3G (located at the right side of the figure) is formed without the uneven portion 110-3G. Figure 5 On the left side of the third test pad 110-3 (also located on Figure 5 A bottom surface of the third barrier metal layer 131-3 (on the left side in FIG) may be a flat surface.

[0081] Figure 6 is a perspective view illustrating a wafer-to-wafer bonding process according to an embodiment of the inventive concept.

[0082] Reference Figure 6 , the wafer-to-wafer bonding process can mount multiple wafers 100 - 1 on one wafer 100 - 2 .

[0083] First, a single wafer 100-2 is loaded into the wafer holding portion WP of the wafer table WT. Next, multiple wafers 100-1 can be sequentially mounted on the single wafer 100-2. Finally, the single wafer 100-2 can be unloaded onto the wafer table WT, and the mounting process of the multiple wafers 100-1 can be completed. The above operations can be performed in a different order as needed.

[0084] exist Figure 6 , a state in which three chips 100 - 1 are mounted on one wafer 100 - 2 is shown, but this is only an example of a bonding process, and a larger number of chips 100 - 1 may be sequentially mounted on the wafer 100 - 2 .

[0085] In the bonding process, since the tested and screened chip 100-1 (known good chip KGD) is mounted on one wafer 100-2 in a reliable bonding structure, the chip-to-wafer bonding structure according to the technical concept of the present invention can increase the yield and reliability of semiconductor packages.

[0086] In some embodiments, at least one of the plurality of wafers 100-1 mounted on a single wafer 100-2 may be a dummy wafer. In other words, the plurality of selected wafers 100-1 and at least one dummy wafer may be mounted together on a single wafer 100-2. In other embodiments, no dummy wafer is present, and only the plurality of selected wafers 100-1 may be mounted on a single wafer 100-2.

[0087] Figure 7 is a cross-sectional view illustrating a wafer-to-wafer bonding structure 1100 according to an embodiment of the inventive concept.

[0088] Reference Figure 7 The wafer-to-wafer bonding structure 1100 may show in detail the first interlayer insulating layer 150-1 and the second interlayer insulating layer 150-2, the first metal wiring layer 160-1 and the second metal wiring layer 160-2, the first integrated circuit layer 103-1 and the second integrated circuit layer 103-2, and the first integrated circuit layer 105-1 and the second integrated circuit layer 105-2.

[0089] Hereinafter, the wafer 100 - 1 disposed on top of the wafer-to-wafer bonding structure 1100 is described.

[0090] The wafer 100-1 may include a first substrate 101-1, first integrated circuit layers 103-1 and 105-1, a first test pad 110-1, a first insulating layer 120-1, a first bonding pad 130-1, a first polymer layer 140-1, a first interlayer insulating layer 150-1, and a first metal wiring layer 160-1.

[0091] The first substrate 101-1 may include Si. In some embodiments, the first substrate 101-1 may include a semiconductor element such as germanium (Ge), or a compound semiconductor element such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the first substrate 101-1 may have a silicon-on-insulator (SOI) structure. For example, the first substrate 101-1 may include a buried oxide (BOX) layer. In addition, the first substrate 101-1 may include a conductive region, for example, a well doped with impurities, or a structure doped with impurities. In addition, the first substrate 101-1 may have various device isolation structures such as a shallow trench isolation (STI) structure.

[0092] The first integrated circuit layers 103 - 1 and 105 - 1 may be formed on the first substrate 101 - 1 and may include, for example, various semiconductor devices such as transistors, diodes, resistors, and capacitors. Figure 7 A transistor is shown as a representative integrated circuit. For example, the transistor may include source / drain regions and a channel region formed in a first substrate 101 - 1 , and a gate structure formed on the first substrate 101 - 1 .

[0093] In some embodiments, for example, including (located at Figure 7 The transistors in the first integrated circuit layer 103-1 (on the left side of FIG) may be transistors used in a memory device, and may be included in the transistors in the first integrated circuit layer 103-1 (on the left side of FIG). Figure 7 The transistors in the first integrated circuit layer 105-1 (on the right side in FIG) may be logic devices or transistors used in a ferry region.

[0094] The first integrated circuit layer (103-1 and 105-1) can be electrically connected to the first metal wiring layer 160-1 through the first contact 161-1, and can exchange electrical signals with the outside through the first metal wiring layer 160-1. Here, for example, the electrical signal may include a power supply voltage, a ground voltage, a signal voltage, etc. The first metal wiring layer 160-1 may include a plurality of wiring layers. The first metal wiring layer 160-1 may include Cu, but example embodiments are not limited thereto.

[0095] The first interlayer insulating layer 150-1 may be formed on the first substrate 101-1 and cover the first integrated circuit layer (103-1 and 105-1) and the first metal wiring layer 160-1. The first interlayer insulating layer 150-1 may include a plurality of layers corresponding to the number of wiring layers constituting the first metal wiring layer 160-1. When the first interlayer insulating layer 150-1 includes a plurality of layers, the first interlayer insulating layer 150-1 may include a plurality of layers of the same single material, or may include at least two layers having different material layers.

[0096] The first test pad 110-1 may be configured in a plurality, for example, a plurality of first test pads 110-1. The first bonding pad 130-1 may be formed on a portion (subgroup) of the plurality of first test pads 110-1, and the first bonding pad 130-1 may not be formed on the remaining portion (remaining subgroup) of the plurality of first test pads 110-1. The first insulating layer 120-1, the first bonding pad 130-1, and the first polymer layer 140-1 may contact the top surface of the first test pad 110-1 on which the first bonding pad 130-1 is formed. In addition, the first insulating layer 120-1 and the first polymer layer 140-1 may contact the top surface of the first test pad 110-1 on which the first bonding pad 130-1 is not formed.

[0097] Details of the first insulating layer 120 - 1 , the first bonding pad 130 - 1 , and the first polymer layer 140 - 1 may be similar to those described in reference Figure 1 Those described are substantially the same or similar, so detailed descriptions thereof are omitted here.

[0098] The distinction between the first bonding pad 130-1 and the second bonding pad 130-2 and between the first polymer layer 140-1 and the second polymer layer 140-2 may be merely for convenience of description and for understanding their respective origins. Therefore, the first bonding pad 130-1 and the second bonding pad 130-2 may be inseparably bonded (directly bonded) to each other to form an integrated bonding pad 130A, and the first polymer layer 140-1 and the second polymer layer 140-2 may be inseparably bonded (directly bonded) to each other to form an integrated polymer layer 140A.

[0099] Furthermore, although wafer 100-2 and die 100-1 are shown as having the same size, wafer 100-2 may have a size sufficient to mount a plurality of die 100-1. In other words, wafer 100-2 may include a substrate before dicing, and die 100-1 may represent a substrate after dicing.

[0100] As mentioned above Figure 6 As described, since the tested and screened chip 100-1 (known good chip KGD) is mounted on a wafer 100-2 in a reliable bonding structure, the chip-to-wafer bonding structure 1100 according to the technical concept of the present invention can increase the yield and reliability of semiconductor packages.

[0101] Figures 8A to 8I It shows the manufacturing Figure 7 FIG. 1 is a cross-sectional view of a process of a wafer-to-wafer bonding structure 1100 .

[0102] Reference Figure 8A , showing that a first integrated circuit layer (103-1 and 105-1), a first interlayer insulating layer 150-1, and a first metal wiring layer 160-1 are formed on a first substrate 101-1. In addition, a first test pad 110-1 electrically connected to the first metal wiring layer 160-1 is formed, and a preliminary insulating layer 120-1P is formed on the first test pad 110-1 and the first interlayer insulating layer 150-1.

[0103] The preliminary insulating layer 120-1P may be formed to cover both the top surface of the first test pad 110-1 and the top surface of the first interlayer insulating layer 150-1 at its uppermost layer. For example, the preliminary insulating layer 120-1P may include silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the preliminary insulating layer 120-1P may be formed as a single layer as shown, or may be formed as a plurality of layers.

[0104] Reference Figure 8B , showing that the preliminary insulating layer 120-1P (refer to Figure 8A ) is patterned to form a first insulating layer 120-1 including a first opening 120-1H exposing the top surface 110-1T of the first test pad 110-1.

[0105] The preliminary insulating layer 120-1P (refer to Figure 8A ) is formed on a photomask pattern (not shown), and the first insulating layer 120-1P can be etched by using the photomask pattern as an etching mask and etching the first insulating layer 120-1P (refer to Figure 8A ) to form a preliminary insulating layer 120-1P including a first opening 120-1H. After forming the first insulating layer 120-1, the photomask pattern may be removed by, for example, an ashing process and a stripping process.

[0106] The first insulating layer 120-1 may cover a portion of the top surface 110-1T of the first test pad 110-1. In other words, the first insulating layer 120-1 may not completely expose the top surface 110-1T of the first test pad 110-1, but may still cover the edge portion. For example, the first insulating layer 120-1 may partially expose the center portion of the top surface 110-1T of the first test pad 110-1 and cover the remaining edge portion of the top surface 110-1T of the first test pad 110-1.

[0107] Reference Figure 8C By using the test equipment TA, the wafer 100-1 (refer to Figure 8A ) perform the test process.

[0108] A test process may be performed to verify the wafer 100-1 (refer to Figure 8A )'s functionality and electrical connection characteristics.

[0109] The test device TA may include a needle-shaped test pin TP, and the test pin TP may make physical contact with the first test pad 110-1 to perform a test process. For example, compared to a non-contact test process such as Figure 8C The contact testing process shown can have a relatively high testing performance.

[0110] For example, the test pin TP may be part of a probe card connected to the test equipment TA. In addition, a plurality of test pins TP may be located on the probe card.

[0111] Reference Figure 8D , using the test equipment TA (refer to Figure 8C ) may include first to sixth operations T110 to T160.

[0112] Those skilled in the art will readily appreciate that, when a particular embodiment is implemented differently, specific operations may be performed differently from the order described. For example, two operations described in succession may be performed substantially simultaneously, or in an order different from the order described or in a reverse order.

[0113] A first operation T110 of testing the wafer may be performed. The wafer test may include, for example, a DC test, an AC test, and / or a functional test. These tests may be contact test processes as described above. However, the test types and methods are not limited thereto.

[0114] A second operation T120 may be performed to verify whether the test result passes. After passing the test, the wafer may be moved to a third operation T130 of screening the wafer. On the other hand, if the wafer does not pass the test, it may be moved to a fourth operation T140 of determining the wafer as defective.

[0115] If the wafer is determined to be good in the third operation T130, a fifth operation T150 may be performed in which the good wafer is bonded to a wafer in a subsequent process. On the other hand, if the wafer is determined to be defective in the fourth operation T140, a sixth operation T160 may be performed in which the defective wafer is repaired or discarded in a subsequent process.

[0116] As a result, die selected as “passed” and / or deemed qualified through the test process T100 may be mounted on the wafer in a reliable direct bonding structure.

[0117] Reference Figure 8E , illustrating the shape of the mask pattern M1 formed to cover the first insulating layer 120 - 1 and a portion of the top surface 110 - 1T of the first test pad 110 - 1 .

[0118] The mask pattern M1 may be formed in a pattern having a second opening M1H exposing a portion of the top surface 110 - 1T of the first test pad 110 - 1. For example, the mask pattern M1 may be a photomask pattern or a hardmask pattern.

[0119] although Figure 8E Only one second opening M1H is shown in the figure, but a plurality of second openings M1H may be formed. In other words, since the portion of the top surface 110-1T of the first test pad 110-1 exposed by the second opening M1H of the mask pattern M1 corresponds to the portion where the preliminary bonding pad 130-1P is formed in a subsequent process (refer to Figure 8F ) part, so when the initial bonding pad 130-1P (refer to Figure 8F ) is formed in plural, the second opening M1H of the mask pattern M1 may be formed in plural to be aligned with each preliminary bonding pad 130-1P (refer to Figure 8FFor example, in an embodiment having a plurality of first test pads 110 - 1 , a corresponding second opening M1H may exist for each corresponding first test pad 110 - 1 in the plurality of first test pads 110 - 1 .

[0120] Reference Figure 8F , a preliminary bonding pad 130-1P may be formed to fill the second opening M1H of the mask pattern M1 (refer to Figure 8E For example, the preliminary bonding pad 130 - 1P may at least partially fill the second opening M1H.

[0121] To form the preliminary bonding pad 130-1P, for example, a plating process may be performed on the first substrate 101-1 on which the mask pattern M1 is formed. In some embodiments, for example, a seed layer (not shown) may be first formed on the first test pad 110-1, and then the preliminary bonding pad 130-1P may be formed using the seed layer through a plating process.

[0122] For example, the preliminary bonding pad 130-1P may include a metal formed of copper (Cu), nickel (Ni), and gold (Au), or an alloy thereof, or a multilayer structure of multiple metals of Cu, Ni, and Au. Here, the preliminary bonding pad 130-1P is described as including Cu.

[0123] The preliminary bonding pad 130-1P may be formed to fill only a portion of the mask pattern M1 without completely filling the second opening M1H of the mask pattern M1 (refer to FIG. Figure 8E In other words, the top surface of the preliminary bonding pad 130-1P may be lower than the top surface of the mask pattern M1. For example, when viewed in a cross-sectional view, the top surface of the preliminary bonding pad 130-1P may be lower than the top surface of the mask pattern M1.

[0124] Reference Figure 8G , the mask pattern M1 can be removed (refer to Figure 8F ), and a preliminary polymer layer 140-1P may be formed to completely cover the first test pad 110-1, the first insulating layer 120-1, and the preliminary bonding pad 130-1P.

[0125] The preliminary polymer layer 140-1P may fill a gap between a sidewall of the first insulating layer 120-1 and a sidewall of the preliminary bonding pad 130-1P. In addition, the preliminary polymer layer 140-1P may fill an uneven portion 110-1G formed in the at least one first test pad 110-1.

[0126] The preliminary polymer layer 140-1P may be initially formed to a thickness greater than its final design thickness because some of the preliminary polymer layer 140-1P may be removed by subsequent processes. Figure 8GThe preliminary polymer layer 140-1P is Figure 8H In addition, the material constituting the preliminary polymer layer 140-1P may be appropriately adjusted in consideration of a ratio or amount of removal of the preliminary polymer layer 140-1P by a subsequent process.

[0127] Reference Figure 8H The preliminary polymer layer 140-1P (see Figure 8G ) is polished so that the top surface of the first bonding pad 130-1 is exposed.

[0128] The first bonding pad 130-1 and the first polymer layer 140-1 may be formed by the CMP process. The thickness of the first bonding pad 130-1 may be smaller than that of the preliminary bonding pad 130-1P (refer to FIG. Figure 8G ) thickness. In addition, the thickness of the first polymer layer 140-1 may be smaller than that of the preliminary polymer layer 140-1P (refer to Figure 8G ) thickness.

[0129] The top surface of the first bonding pad 130-1 and the top surface of the first polymer layer 140-1 may be formed on the same plane to be coplanar. This characteristic may be a result of the planarization characteristic of the CMP process.

[0130] Reference Figure 8I , ( Figure 8I The wafer 100-2 may have the same Figure 8I ) wafer 100-1 has a similar structure.

[0131] The chip 100-1 can be placed on the wafer 100-2 so that the first bonding pad 130-1 faces the second bonding pad 130-2, and the position of the chip 100-1 can also be accurately aligned. For example, the top surface of the first bonding pad 130-1 can be aligned to accurately match the top surface of the second bonding pad 130-2.

[0132] Return to reference Figure 7 , the first bonding pad 130-1 and the second bonding pad 130-2 may be bonded to each other to form a bonding pad 130A, and the chip 100-1 and the wafer 100-2 may be bonded by bonding the first polymer layer 140-1 to the second polymer layer 140-2 to form a polymer layer 140A.

[0133] By combining the wafer 100 - 1 and the wafer 100 - 2 , a wafer-to-wafer bonding structure 1100 according to the technical concept of the present inventive concept may be realized.

[0134] Furthermore, the manufacturing process of the wafer-to-wafer bonding structure 1100 may be substantially the same as or similar to the manufacturing process of the semiconductor package. Therefore, one of ordinary skill in the art may understand the manufacturing process of the semiconductor package from the manufacturing process of the wafer-to-wafer bonding structure 1100 described above.

[0135] Figure 9 is a cross-sectional view illustrating a wafer-to-wafer bonding structure 1200 according to an embodiment of the inventive concept.

[0136] Most of the components constituting the wafer-to-wafer bonding structure 1200 and the materials included therein, which will be described below, may be similar to those described in reference to FIG. Figure 7 Therefore, for the convenience of description, the following mainly describes the above-mentioned chip-to-wafer bonding structure 1100 (refer to Figure 7 ) is different.

[0137] Reference Figure 9 , the wafer-to-wafer bonding structure 1200 may show in detail the third and fourth interlayer insulating layers 150-3 and 150-4, the third and fourth metal wiring layers 160-3 and 160-4, and the third and fourth integrated circuit layers (103-3 and 105-3) and (103-4 and 105-4).

[0138] The third bonding pad 130-3 may be formed on each of the plurality of third test pads 110-3. The third bonding pad 130-3 may be arranged so that the bottom surface of the third bonding pad 130-3 contacts the top surface of the third test pad 110-3. All side surfaces of the third bonding pad 130-3 may be surrounded by the third polymer layer 140-3.

[0139] Compared to the fourth test pad 110-4, the third test pad 110-3 may include some other characteristics. For example, an uneven portion 110-3G may be formed in at least one of the third test pads 110-3. The uneven portion 110-3G of the third test pad 110-3 may be formed in a contact test process for screening the wafer 100-3 (see FIG. Figure 8D In some embodiments, the uneven portion may not be formed in the fourth test pad 110-4. In addition, some embodiments may include a third test pad 110-3 having an uneven portion 110-3G and a third test pad 110-3 not having an uneven portion 110-3G.

[0140] The third bonding pad 130-3 may fill the uneven portion 110-3G of the third test pad 110-3. Thus, the third bonding pad 130-3 may be formed on the third test pad 110-3 including the uneven portion 110-3G. Figure 9The surface profile of the bottom surface of the third bonding pad 130-3 (on the right side in the figure) may have a shape according to the shape of the top surface of the third test pad 110-3. For example, the surface profile of the bottom surface of the third bonding pad 130-3 may be defined by the shape of the top surface of the third test pad 110-3. In contrast, the surface profile of the bottom surface of the third bonding pad 130-3 (located on the right side in the figure) may have a shape according to the shape of the top surface of the third test pad 110-3. Figure 9 The bottom surface of the third bonding pad 130-3 (left side in FIG) may be a flat surface. As a result, some of the plurality of bonding pads 130B may be thicker in the vertical direction than other bonding pads 130B.

[0141] Figure 10A and Figure 10B It shows the manufacturing Figure 9 FIG. 1 is a cross-sectional view of a portion of a process for a wafer-to-wafer bonding structure 1200 .

[0142] Most of the manufacturing operations constituting the manufacturing method of the wafer-to-wafer bonding structure described below are similar to those described above with reference to Figures 8A to 8I The above-described wafer-to-wafer bonding structure is substantially the same or similar. In addition, there is a difference in the process of forming the third bonding pad 130-3 on the third test pad 110-3 including the uneven portion 110-3G. Therefore, for the sake of convenience, the following will mainly describe the differences from the above-described wafer-to-wafer bonding structure.

[0143] Reference Figure 10A , a third bonding pad 130 - 3 may be formed on the third test pad 110 - 3 .

[0144] The third bonding pad 130-3 may be formed on all the test pads among the plurality of third test pads 110-3. The third bonding pad 130-3 may be arranged so that the bottom surface of the third bonding pad 130-3 contacts the top surface of the third test pad 110-3. All side surfaces of the third bonding pad 130-3 may be surrounded by the third polymer layer 140-3.

[0145] For example, the third bonding pad 130 - 3 may be formed by polishing a preliminary bonding pad (not shown) through a CMP process, and the third polymer layer 140 - 3 may be formed by polishing a preliminary polymer layer (not shown) through a CMP process.

[0146] The top surface of the third bonding pad 130 - 3 and the top surface of the third polymer layer 140 - 3 may be formed on the same plane and thus be considered coplanar. This characteristic may be a result of the planarization characteristic of the CMP process.

[0147] Figure 10B It is shown that a wafer 100 - 4 having a structure similar to that of the wafer 100 - 1 is prepared.

[0148] The chip 100-3 can be placed on the wafer 100-4 so that the third bonding pad 130-3 faces the fourth bonding pad 130-4. In addition, the position of the chip 100-3 can also be precisely aligned. For example, the top surface of the third bonding pad 130-3 can be aligned to precisely match the top surface of the fourth bonding pad 130-4.

[0149] Return to reference Figure 9 , the third bonding pad 130-3 and the fourth bonding pad 130-4 may be bonded to each other to form a bonding pad 130B, and the chip 100-3 and the wafer 100-4 may be bonded by bonding the third polymer layer 140-3 and the fourth polymer layer 140-4 to form a polymer layer 140B.

[0150] By combining the wafer 100 - 3 and the wafer 100 - 4 , a wafer-to-wafer bonding structure 1200 according to the technical concept of the present inventive concept may be realized.

[0151] Figure 11 is a cross-sectional view illustrating a semiconductor package 1100P according to a technical idea of ​​the present inventive concept.

[0152] Reference Figure 11 , the semiconductor package 1100P may form a direct bonding structure using the semiconductor chip 1100 - 1 , the second semiconductor chip 1100 - 2 , the bonding pad 130A, and the polymer layer 140A.

[0153] The first semiconductor chip 1100-1 may be manufactured from the wafer 100-1 described above, and the second semiconductor chip 1100-2 may be manufactured from the wafer 100-2 described above. Therefore, since most of the components constituting the first and second semiconductor chips 1100-1 and 1100-2 are the same or similar to those described above, only the differences are described below.

[0154] The first semiconductor chip 1100-1 and the second semiconductor chip 1100-2 included in the semiconductor package 1100P may be logic chips or memory chips, respectively. For example, the first semiconductor chip 1100-1 and the second semiconductor chip 1100-2 may be memory chips of the same type, or one of the first semiconductor chip 1100-1 and the second semiconductor chip 1100-2 may be a memory chip and the other may be a logic chip. For example, the first semiconductor chip 1100-1 may be a memory chip and the second semiconductor chip 1100-2 may be a logic chip.

[0155] For example, the memory chip may be a volatile memory semiconductor chip such as a dynamic random access memory (RAM) (DRAM) and a static RAM (SRAM), or a non-volatile memory chip such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM), and a resistive RAM (RRAM). In addition, the logic chip may include, for example, a microprocessor, an analog element, or a digital signal processor.

[0156] The second semiconductor chip 1100-2 may include a through electrode 170-2 penetrating the second substrate 101-2. A bump pad 180-2 may be on the bottom surface 101-2B of the second substrate 101-2 so that the bottom surface 101-2B is connected to the through electrode 170-2. The bump pad 180-2 may include at least one of Al, Cu, Ni, tungsten (W), platinum (Pt), and Au, but is not limited thereto.

[0157] A passivation layer 190-2 may be formed on the bottom surface 101-2B of the second substrate 101-2. The passivation layer 190-2 may expose the bump pad 180-2.

[0158] The through electrode 170-2 may penetrate the second substrate 101-2, extend from the top surface 101-2T toward the bottom surface 101-2B of the second substrate 101-2, and be connected to the second metal wiring layer 160-2. The through electrode 170-2 may have a cylindrical shape. For example, the through electrode 170-2 may include a through silicon via (TSV).

[0159] The bump structure BS may contact the bump pad 180-2. The semiconductor package 1100P may receive control signals, power signals, and ground signals for the operation of the first semiconductor chip 1100-1 and the second semiconductor chip 1100-2 through the bump structure BS, or receive data signals to be stored in the first semiconductor chip 1100-1 and the second semiconductor chip 1100-2, or may provide data stored in the first semiconductor chip 1100-1 and the second semiconductor chip 1100-2 to the outside. For example, the bump structure BS may have a pillar structure, a ball structure, or a solder layer.

[0160] In some embodiments, the semiconductor package 1100P may include a bump structure BS for connection with an external device (eg, a printed circuit board or an interposer).

[0161] The first semiconductor chip 1100-1 may be arranged such that a top surface of the first semiconductor chip 1100-1 faces a top surface of the second semiconductor chip 1100-2. The first semiconductor chip 1100-1 may be electrically connected to the second semiconductor chip 1100-2 via bonding pads 130A.

[0162] Furthermore, a polymer layer 140A may be interposed between the first semiconductor chip 1100-1 and the second semiconductor chip 1100-2, so that the first semiconductor chip 1100-1 and the second semiconductor chip 1100-2 can be combined (coupled) with each other while maintaining a very strong bonding force. As shown, the polymer layer 140A may surround the bonding pads 130A.

[0163] Figure 12 is a cross-sectional view illustrating a semiconductor package 1200P according to a technical idea of ​​the present inventive concept.

[0164] Most of the components constituting the semiconductor package 1200P and the materials included in the components to be described below can be compared with those in the reference Figure 11 Therefore, for the convenience of description, the following will mainly describe the semiconductor package 1100P (refer to Figure 11 ) is different.

[0165] Reference Figure 12 , the semiconductor package 1200P may form a direct bonding structure using the third semiconductor chip 1200 - 3 , the fourth semiconductor chip 1200 - 4 , the bonding pads 130B, and the polymer layer 140B.

[0166] The third semiconductor chip 1200-3 may be manufactured from the wafer 100-3, and the fourth semiconductor chip 1200-4 may be manufactured from the wafer 100-4. Therefore, since most of the components constituting the third and fourth semiconductor chips 1200-3 and 1200-4 are the same or similar to those described above, only the differences are described below.

[0167] The fourth semiconductor chip 1200-4 may include a through electrode 170-4 passing through the fourth substrate 101-4. The bottom bonding pad 180-4 may contact the bottom surface 101-4B of the fourth substrate 101-4 to be connected to the through electrode 170-4. The bottom bonding pad 180-4 may include Cu, but is not limited thereto.

[0168] The semiconductor package 1200P can receive control signals, power signals, and ground signals for the operation of the third semiconductor chip 1200-3 and the fourth semiconductor chip 1200-4 through the bottom bonding pads 180-4, or receive data signals to be stored in the third semiconductor chip 1200-3 and the fourth semiconductor chip 1200-4, or can provide data stored in the third semiconductor chip 1200-3 and the fourth semiconductor chip 1200-4 to the outside. For example, the bottom bonding pads 180-4 can form a direct bonding structure similar to the bonding pads 130B.

[0169] In some embodiments, the semiconductor package 1200P may include bottom bonding pads 180 - 4 for direct bonding with other semiconductor chips.

[0170] The third semiconductor chip 1200-3 may be arranged such that a top surface of the third semiconductor chip 1200-3 faces a top surface of the fourth semiconductor chip 1200-4. The third semiconductor chip 1200-3 may be electrically connected to the fourth semiconductor chip 1200-4 through bonding pads 130B.

[0171] Furthermore, a polymer layer 140B may be interposed between the third semiconductor chip 1200-3 and the fourth semiconductor chip 1200-4, so that the third semiconductor chip 1200-3 and the fourth semiconductor chip 1200-4 may be combined (coupled) with each other while maintaining a very strong bonding force. As shown, the polymer layer 140B may surround the bonding pads 130B.

[0172] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A wafer-to-wafer bonding structure, comprising: A wafer comprising a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, wherein the first bonding pad penetrates the first insulating layer; a wafer comprising a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, wherein the second bonding pad penetrates the second insulating layer; as well as a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being disposed between the die and the wafer, wherein the wafer and the chip are combined together, Wherein, the structure further includes: a plurality of first test pads including the first test pad, Wherein, at least one of the plurality of first test pads has no corresponding first bonding pad formed thereon, wherein an uneven portion is formed on a surface of the at least one first test pad on which a corresponding first bonding pad is not formed, and The polymer layer fills the uneven portion.

2. The structure according to claim 1, wherein The polymer layer includes a first polymer layer on the wafer and a second polymer layer on the die, wherein the first polymer layer and the second polymer layer are directly bonded together.

3. The structure according to claim 1, wherein When viewed from a cross-section, The horizontal width of the first test pad is greater than the horizontal width of the first bonding pad, and A horizontal width of the second test pad is greater than a horizontal width of the second bonding pad.

4. The structure according to claim 1, wherein A material constituting the first test pad and the second test pad is different from a material constituting the first bonding pad and the second bonding pad.

5. The structure according to claim 1, wherein A side surface of the first insulating layer, a side surface of the second insulating layer, and horizontal surfaces of the first insulating layer and the second insulating layer facing each other are surrounded by a polymer layer. 6 . The structure of claim 1 , further comprising a barrier metal layer surrounding the first bonding pad and the second bonding pad.

7. A wafer-to-wafer bonding structure, comprising: A wafer comprising a first integrated circuit layer on a first substrate, a first metal wiring layer connected to the first integrated circuit layer, a plurality of first test pads on the first metal wiring layer, a first insulating layer, and a plurality of first bonding pads formed on the plurality of first test pads, the plurality of first bonding pads penetrating the first insulating layer; a wafer comprising a second integrated circuit layer on a second substrate, a second metal wiring layer connected to the second integrated circuit layer, a plurality of second test pads on the second metal wiring layer, a second insulating layer, and a plurality of second bonding pads formed on the plurality of second test pads, the plurality of second bonding pads penetrating the second insulating layer; as well as a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being disposed between the chip and the wafer, wherein the plurality of first bonding pads and the plurality of second bonding pads face each other and are bonded to each other, Wherein, at least one of the plurality of first test pads has no corresponding first bonding pad formed thereon, wherein an uneven portion is formed on a surface of the at least one first test pad on which a corresponding first bonding pad is not formed, and The polymer layer fills the uneven portion.

8. The structure according to claim 7, wherein The polymer layer includes at least one of polyimide, polyamide, polyacrylate, and polyaramid.

9. The structure according to claim 7, wherein The first test pad and the second test pad include aluminum, and The first bonding pad and the second bonding pad include copper.

10. The structure according to claim 7, wherein When viewed from a cross-section, The vertical thicknesses of the first insulating layer and the second insulating layer are 0.5 μm to 10 μm respectively. The maximum vertical thickness of the polymer layer is 2 μm to 40 μm, and The maximum vertical thickness of the polymer layer is two or more times the sum of vertical thicknesses of the first insulating layer and the second insulating layer.

11. The structure according to claim 7, further comprising: a plurality of wafers comprising said wafer, and At least one of the plurality of wafers is a virtual wafer.

12. A semiconductor package, comprising: a first metal wiring layer on a first substrate; a first test pad on the first metal wiring layer; a first insulating layer on the first test pad; a polymer layer on the first test pad and the first insulating layer; a second insulating layer on the polymer layer; a second test pad on the polymer layer and the second insulating layer; a second metal wiring layer on the second test pad; a second substrate on the second metal wiring layer; as well as a bonding pad that penetrates the polymer layer and connects the first test pad and the second test pad, the bonding pad being surrounded by the polymer layer, The semiconductor package further comprises: a plurality of first test pads including the first test pad, Wherein, at least one of the plurality of first test pads has no corresponding bonding pad formed thereon, wherein an uneven portion is formed on a surface of the at least one first test pad on which a corresponding bonding pad is not formed, and The polymer layer fills the uneven portion. 13 . The semiconductor package according to claim 12 , further comprising a through electrode penetrating the second substrate and connecting the second metal wiring layer. 14 . The semiconductor package according to claim 13 , further comprising an external connection terminal electrically connected to the through-electrode on the second substrate. 15 . The semiconductor package of claim 13 , further comprising a bottom bonding pad electrically connected to the through electrode on the second substrate.

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