Multi-bit digital-to-analog converter and continuous-time sigma-delta modulator

Abstract

The present disclosure relates to multi-bit digital-to-analog converters and continuous-time sigma-delta modulators. A four-way signal generator circuit generates four 2 N -bit control signals in response to a sampling clock and a 2 N -bit thermometer-coded signal. A digital-to-analog converter circuit has 2 N -bit unit resistor elements, where each unit resistor element includes four switching circuits controlled by corresponding bits of the four 2 N -bit control signals. Outputs of the 2 N -bit unit resistor elements are summed to generate an analog output signal. The four-way signal generator circuit controls generation of the four 2 N -bit control signals so that all logic states of the bits of the four 2 N -bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal can be a feedback signal in a sigma-delta analog-to-digital converter circuit that includes a multi-bit quantization circuit that operates to quantize a filtered loop signal to generate a 2 N -bit thermometer-coded signal.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 948,929, filed December 17, 2019, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present invention relates generally to a digital-to-analog converter (DAC) circuit, and in particular to a multi-bit DAC circuit for use in a continuous-time (CT) sigma-delta (SD) modulator circuit. BACKGROUND

[0004] Figure 1 A time-domain block diagram of a conventional continuous-time (CT) sigma-delta (SD) analog-to-digital converter (ADC) circuit 10 is shown. Circuit 10 includes a continuous-time sigma-delta modulator circuit 12 (illustrated here as a first-order circuit) having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B consisting of a pulse-density-modulated pulse stream of 1-bit codes. The instantaneous amplitude of input signal A is represented by a ratio formed by a count of the number of pulses in the pulse stream of signal B divided by the total number of samples (set by a sampling clock at a sampling rate fs) of input signal A over a known time interval. Circuit 10 also includes a decimator circuit 14 that accumulates and averages the pulses in the pulse stream of digital output signal B to generate a digital signal C consisting of a stream of multi-bit (M-bits, where M » 1) digital words at an output word rate fd set by a decimation factor (where fd « fs).

[0005] A first-order implementation of the sigma-delta modulator circuit 12 includes a differential amplifier 20 (or summing circuit) having a first (non-inverting) input that receives an analog input signal A and a second (inverting) input that receives an analog feedback signal D. The differential amplifier 20 outputs an analog difference signal vdif in response to a difference between the analog input signal A and the analog feedback signal D (i.e., vdif(t) = A(t) - D(t)). The analog difference signal vdif is integrated by an integrator circuit 22 (a first-order loop filter) to generate a change signal vc having a slope and magnitude that depend on the sign and magnitude of the analog difference signal vdif. A comparator circuit 24 samples the change signal vc at a sampling rate fs in response to a sampling clock and compares each sample of the change signal vc to a reference signal vref to generate a corresponding single-bit pulse of a digital output signal B (the single-bit has a first logic state if vc ≥ vref and a second logic state if vc < vref). The comparator circuit 24 effectively operates as a single-bit quantization circuit for quantizing the change signal vc. A single-bit digital-to-analog converter (DAC) circuit 26 in the feedback loop then converts the logic state of the digital output signal B to a corresponding analog signal level for the analog feedback signal D.

[0006] The sigma-delta modulator circuit 12 can be implemented instead with multi-bit quantization (e.g., N bits, where 1 < N < < M) as shown by Figure 2 The circuit implementation requires a multi-bit (e.g., N-bit) quantization circuit 24' and a multi-bit DAC circuit 26' in the feedback loop. The quantization circuit 24' samples the change signal vc at a sampling rate fs set by the sampling clock CLK and generates a 2 N -1 bit thermometer-coded output word for each sample. The use of multi-bit quantization has multiple advantages over the single-bit implementation of Figure 1 including permitting the modulator's operation to achieve a given resolution using a lower sampling rate fs or to achieve a higher resolution for a given sampling rate fs. The DAC circuit 26' is a resistive circuit that includes 2 N -1 unit resistance DAC elements (UEs) driven by the 2 N -1 bits of the thermometer code word of the digital output signal B, respectively, with the current outputs from the driven unit resistance DAC elements summed at the DAC circuit output to generate the analog signal level for the analog feedback signal D. The decimator circuit 14 operates to low-pass filter and down-sample the 2 N -1 bit thermometer code words in the stream of the digital output signal B to generate a digital signal C that consists of a stream of multi-bit (M-bit, resolution desired, where M > > N) digital words at an output word rate fd set by the decimation factor.

[0007] A key feature of sigma-delta modulator circuit 12 is its ability to push quantization noise due to the operation of quantization circuit 24, 24' to higher frequencies away from the signal of interest. This is known in the art as noise shaping. Decimator circuit 14 can then be implemented with a low-pass filtering feature (i.e., frequency response) to substantially remove the high frequency components of the shaped quantization noise.

[0008] However, because of inherent mismatches present in the 2 N -1 unit resistor DAC elements in the feedback loop, it is difficult to use multi-bit quantization in a sigma-delta modulator circuit; this mismatch translates directly into non-linearity of the overall modulator 12. This non-linearity is due to, for example, the presence of unequal analog signal output steps of the multi-bit DAC circuit (i.e., due to mismatch between the 2 N -1 unit resistor DAC elements).

[0009] As a result of the non-linearity introduced in the analog output of DAC circuit 26' due to the mismatch between the unit resistor DAC elements, the noise floor will increase with respect to the modulator output spectrum, and the harmonic distortion within the signal band of interest will also increase. The DAC non-linearity also modulates the quantization noise of quantization circuit 24' into the signal band, resulting in a reduction in signal-to-noise ratio (SNR) and signal-to-noise distortion ratio (SNDR).

[0010] Referring now to Figure 3 It is known in the art to address the DAC non-linearity problem by employing circuit 102 in the feedback loop that implements a data weighted averaging (DWA) algorithm to achieve first order dynamic element matching (DEM) with respect to the 2 N -1 unit resistor DAC elements. Circuit 102 receives the series of 2 N -1 bit thermometer code words output from quantization circuit 24' and generates a series of 2 N -1 bit control words to actuate the 2 N -1 unit resistor DAC elements of DAC circuit 26' such that over time all of the 2 N -1 unit resistor DAC elements will be actuated relatively equally in generating the analog feedback signal D.

[0011] The execution of the DWA algorithm introduces processing delays into the signal processing loop in addition to the quantization delay. Importantly, the total delay (referred to as the excessive loop delay (ELD)) must not exceed one cycle Ts of the sampling clock CLK, as this can lead to modulator instability. Ideally, ELD should satisfy the constraint: 0.5Ts < ELD < 0.75Ts. However, despite the existence of calibration 2... N The advantage of a single-resistance DAC element and acceptable ELD due to DWA operation, but Figure 3 The performance of modulator 10' is unacceptable. This is attributed to one or more issues with the following: a) switching of DAC circuit 26' at each edge of the sampling clock in response to the DWA algorithm. N -1 unit resistance DAC element; b) modification of the number of conversions via the DWA algorithm, which causes a sharp change in the spectrum; c) presence of nonlinear short-time pulse wave interference energy (dynamic nonlinearity); and d) a sharp increase in harmonic distortion due to data-dependent switching (in response to DWA) inter-symbol interference (ISI).

[0012] Therefore, there is a need in the art to address the aforementioned problems by implementing improved DAC circuitry in the feedback path of a continuous-time sigma-delta modulator. Summary of the Invention

[0013] In one embodiment, a circuit includes: a digital-to-analog converter (DAC) circuit having 2 N -1 unit resistance DAC element, wherein each unit resistance DAC element comprises four 2 N The four switching circuits controlled by the corresponding bit of the -1 bit control signal, among which the 2 N The outputs of -1 unit resistance DAC elements are summed to generate an analog output signal; and a four-channel signal generator circuit is configured to respond to a sampling clock and 2 N -1 bit thermometer encoded input signal to generate four 2 N -1 bit control signal, where the four signal generator circuits control four 2 N -1 bit control signal generation, so that four 2 N All logic states of the -1 bit control signal remain constant for at least one cycle of the sampling clock.

[0014] In one embodiment, a sigma-delta analog-to-digital converter (ADC) circuit includes: a summing circuit configured to receive an analog input signal and an analog feedback signal and generate a differential signal; a loop filter circuit configured to filter the differential signal and generate a variable signal; and a multi-bit quantization circuit configured to quantize the variable signal and generate a 2-bit quantization signal. N- 1-bit thermometer-coded signals; a four-way signal generator circuit configured to generate four 2 N - 1-bit control signals in response to the sampling clock and the 2 N - 1-bit control signals; a digital-to-analog converter (DAC) circuit having 2 N - 1 unit-resistor DAC elements, wherein each unit-resistor DAC element comprises four 2 N - 1-bit control signals; a digital-to-analog converter (DAC) circuit having 2 N - 1-bit control signals; a digital-to-analog converter (DAC) circuit having 2 N - 1-bit control signals in response to the sampling clock and the 2 N - 1-bit control signals in response to the sampling clock and the 2

[0015] In an embodiment, a sigma-delta analog-to-digital converter (ADC) circuit comprises a loop filter configured to receive an analog input signal and an analog feedback signal, and the loop filter is configured to generate an integrated signal; a multi-bit quantization circuit configured to quantize the integrated signal and generate 2 N - 1-bit thermometer-coded signals; a four-way signal generator circuit configured to generate four 2 N - 1-bit control signals in response to the sampling clock and the 2 N - 1-bit control signals; a digital-to-analog converter (DAC) circuit having 2 N - 1 unit-resistor DAC elements, wherein each unit-resistor DAC element comprises four 2 N - 1-bit control signals; a digital-to-analog converter (DAC) circuit having 2 N - 1-bit control signals; a digital-to-analog converter (DAC) circuit having 2 N - 1-bit control signals in response to the sampling clock and the 2 N - 1-bit control signals in response to the sampling clock and the 2 BRIEF DESCRIPTION OF DRAWINGS

[0016] For a better understanding of the embodiments, reference will now be made, purely by way of example, to the accompanying drawings in which:

[0017] Figure 1 is a time-domain diagram of a conventional sigma-delta analog-to-digital converter circuit with single-bit quantization;

[0018] Figure 2is a time-domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi-bit quantization;

[0019] Figure 3 is a time-domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi-bit quantization and data weighted averaging;

[0020] Figure 4A is a time-domain block diagram of a continuous-time sigma-delta analog-to-digital converter circuit with multi-bit quantizer, data weighted averaging, and a four-path signal generator controlling a four-path switched digital-to-analog converter;

[0021] Figure 4B illustrates in more detail the circuit of Figure 4A in a differential signal implementation;

[0022] Figure 5 is a block diagram of a digital-to-analog converter (DAC) circuit as used in the circuit of Figure 4B ;

[0023] Figure 6 is a block diagram of a four-path signal generator circuit as used in the circuit of Figure 4B ;

[0024] Figure 7 shows a timing diagram for the operation of the four-path signal generator circuit. DETAILED DESCRIPTION

[0025] Reference is now made to Figure 4A , which shows a time-domain block diagram of a continuous-time sigma-delta analog-to-digital converter (modulator) circuit 100 with multi-bit quantizer, data weighted averaging, and a four-path signal generator controlling a four-path switched digital-to-analog converter. The circuit 100 includes a continuous-time sigma-delta modulator circuit 12 (illustrated here as a first-order circuit, but it is understood that the loop filter of the modulator can be of any order suitable for the circuit application requirements; see, for example, the third-order continuous-time sigma-delta modulator circuit of Figure 4B ), having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B consisting of a stream of multi-bit thermometer-coded data words. The thermometer-coded values in the pulse stream of signal B at a sampling rate of fs are processed in decimator circuit 14 (comprising a low-pass filter and a down-sampler) to generate an equivalent digital signal C of input signal A having a desired resolution and a desired output word rate fd set by a decimation factor, where fd « fs.

[0026] The first order sigma-delta modulator circuit 12 includes a differential amplifier 20 (or summing circuit) having a first (non-inverting) input that receives an analog input signal A and a second (inverting) input that receives an analog feedback signal D. The differential amplifier 20 outputs an analog difference signal vdif in response to the difference between the analog input signal A and the analog feedback signal D (i.e., vdif(t) = A(t) - D(t)). The analog difference signal vdif is integrated by an integrator circuit 22 (of a loop filter, here of the first order type, but not limited thereto) to generate a change signal vc having a slope and a magnitude that depend on the sign and magnitude of the analog difference signal vdif. An N-bit quantization circuit 24' samples the change signal vc in response to a clock CLK at a sampling rate fs and generates for each sample a digital output signal B that is a 2 N -1 bit thermometer-coded output word. The use of multi-bit quantization presents multiple advantages, including: permitting the operation of the modulator to be implemented with a lower sampling rate fs for a given resolution; or permitting the operation of the modulator to achieve a higher resolution for a given sampling rate fs. A circuit 102 implementing a data weighted averaging (DWA) algorithm receives the 2 N -1 bit thermometer-coded output word and outputs a 2 N -1 bit output DWA word, thereby providing first order dynamic element matching (DEM). A four-way signal generator circuit 104 receives the 2 N -1 bit output DWA word and the sampling clock CLK and generates four 2 N -1 bit control words DP1, DP2, DM1 and DM2, the data values of which 2 N -1 bit control words change at the same rate as the rate of the sampling clock CLK. A DAC circuit 126 includes 2 N -1 unit resistance DAC elements that are driven by corresponding bits in the 2 N -1 bit of the control words DP1, DP2, DM1 and DM2, respectively, to generate currents that are summed at the output of the DAC circuit to produce an analog signal for the analog feedback signal D. A decimator circuit 14 low-pass filters and down-samples the 2 N -1 bit code words in the stream of digital output signal B to generate a digital signal C that consists of a stream of multi-bit (M-bit, resolution desired, where M » N) digital words at an output word rate fd set by the decimation factor.

[0027] The implementation illustrated in Figure 4A is a simplified scheme. In a preferred implementation, the circuit is fully differential and includes a higher order sigma-delta modulator. Figure 4B An implementation using a third order modulator is shown in Figure 4Aof a differential signal implementation of the circuit. The loop filter is formed by operational amplifiers OP1, OP2 and OP3 to provide differential amplifier 20 and integrator circuit 22 for a third order implementation of sigma-delta modulator circuit 12 in a configuration with cascaded integrators with feed-forward and feedback (CIFF-FB). Because of the selection of a third order implementation with CIFF-FB, two DACs 126 are required. Each DAC 126 receives 2 N bits of control words DPl, DP2, DMI and DM2 output from four-way signal generator circuit 104 and provides differential output signals D(Outm and Outp). Operational amplifier OP1 receives signals A(Inm and Inp) and Dl (Outml and Outpl from one of the DACs) as a differential signal. Operational amplifier OP3 receives signals D2 (Outm2 and Outp2 from the other of the DACs) as a differential signal combined with the differential signal output from operational amplifier OP2 and the differential input signal A(Inp and Inm). Quantization circuit 24' receives signal vc output from integrator circuit 22 as a differential signal.

[0028] Reference is now made to Figure 5 which shows a block diagram of DAC circuit 126. DAC circuit 126 includes 2 N -1 unit resistance DAC elements (UEs) 110(1) through 110(2 N -1) that are selectively actuated in response to control word outputs of four-way signal generator circuit 104 to generate an analog feedback signal. Each unit resistance DAC element 110 receives a corresponding bit from each of control words DPl<2 N -1:1>, DP2<2 N -1:1>, DMI<2 N -1:1> and DM2<2 N -1:1>. For example, unit resistance DAC element 110(1) receives first bits DPl(l), DP2(l), DMI(l) and DM2(l); unit resistance DAC element 110(2) receives second bits DPl(2), DP2(2), DMI(2) and DM2(2); and so on; and unit resistance DAC element 110(2 N -1) receives 2 N -1 bits DPl(2 N -1), DP2(2 N -1), DMI(2 N -1) and DM2(2 N -1). Four-way signal generator circuit 104 generates the control words from 2 N-1 bit output DWA word to generate control word DP1<2 N -1 : 1>, DP2<2 N -1 : 1>, DM1<2 N -1 : 1> and DM2<2 N -1 : 1> bits. Control word DP1<2 N -1 : 1>, DP2<2 N -1 : 1>, DM1<2 N -1 : 1> and DM2<2 N -1 : 1> bits change at the same rate as the rate of the sampling clock CLK.

[0029] For each given one X (where X is 1 to 2 N -1), unit resistance DAC element 110(X) includes a first CMOS inverter (switching) circuit formed by pMOS transistor 142 and nMOS transistor 144, a source-drain path of which is coupled in series between a first reference voltage Vrefp and a second reference voltage Vrefm. The switching circuit switches between the first and second reference voltages in response to certain ones of the control words, where: a gate of pMOS transistor 142 receives a bit DP1B(X) that is a logical inversion (generated by inverter 146) of a bit DP1(X) of control word DP1<2 N -1 : 1>. A gate of nMOS transistor 144 receives a bit DM1(X) of control word DM1<2 N -1 : 1>. Unit resistance DAC element 110(X) also includes a second CMOS inverter (switching) circuit formed by pMOS transistor 152 and nMOS transistor 154, a source-drain path of which is coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The switching circuit switches between the first and second reference voltages in response to certain ones of the control words, where: a gate of pMOS transistor 152 receives a bit DP2B(X) that is a logical inversion (generated by inverter 146) of a bit DP2(X) of control word DP2<2 N -1 : 1>. A gate of nMOS transistor 124 receives a bit DM2(X) of control word DM2<2 N -1 : 1>. A common drain terminal of transistors 142 and 144 is connected at node 160 to a common drain terminal of transistors 152 and 154. Resistor 162 is coupled between node 160 and a first output node 164 of unit resistance DAC element 110(X) that produces an output current signal.

[0030] The unit-resistance DAC element 110(X) also includes a third CMOS inverter (switching) circuit formed by a pMOS transistor 172 and an nMOS transistor 174, a source-drain path of which is coupled in series between a first reference voltage Vrefp and a second reference voltage Vrefm. The switching circuit switches between the first and second reference voltages in response to certain ones of the control words, where: a gate of the pMOS transistor 172 receives a logically inverted bit DM1B(X) (generated by an inverter 176) of a bit DM1(X) of the control word DM1<2 N -1:1>. A gate of the nMOS transistor 174 receives a bit DP1(X) of the control word DP1<2 N -1:1>. The unit-resistance DAC element 110(X) also includes a fourth CMOS inverter (switching) circuit formed by a pMOS transistor 182 and an nMOS transistor 184, a source-drain path of which is coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The switching circuit switches between the first and second reference voltages in response to certain ones of the control words, where: a gate of the pMOS transistor 182 receives a logically inverted bit DM2B(X) (generated by an inverter 186) of a bit DM2(X) of the control word DM2<2 N -1:1>. A gate of the nMOS transistor 184 receives a bit DP2(X) of the control word DP2<2 N -1:1>. Common drain terminals of the transistors 172 and 174 are connected at a node 190 to common drain terminals of the transistors 182 and 184. A resistor 192 is coupled between the node 190 and a second output node 194 of the unit-resistance DAC element 110(X) that produces a current output signal.

[0031] The first reference voltage Vrefp and the second reference voltage Vrefm are selected by a circuit designer based on a design voltage of the circuit. In an embodiment, for example, the first reference voltage Vrefp = 1.1 V, and the second reference voltage Vrefm = 0 V. Any suitable regulator voltage generator circuit can be used to provide the first reference voltage Vrefp and the second reference voltage Vrefm.

[0032] The current output signals generated at the first output nodes 164 of the unit-resistance DAC elements 110(1) through 110(2 N -1) are connected together at a summing node to generate a net output DAC current that provides a first component Outp of an analog feedback signal D. The current output signals generated at the second output nodes 166 of the unit-resistance DAC elements 110(1) through 110(2 NThe current output signals at the second output nodes 194 of the second current output stages of the -1) are connected together at a summing node to generate a net output DAC current that provides a second component Outm of the analog feedback signal D. In this implementation, the analog feedback signal D is a differential current signal formed from the Outp component and the Outm component. The Outp component and the Outm component are input to the amplifier OP input terminal.

[0033] It should be noted that although the circuit 10 is preferably implemented in differential form, the circuit can be implemented in single-ended form.

[0034] Reference is now made to Figure 6 which shows a block diagram of the four-way signal generator circuit 104. A frequency divider circuit 200 is used to divide by two the sample clock CLK input to the four-way signal generator circuit 104 to output a divided-by-two clock (DCLK) and a logical inversion of the divided-by-two clock (i.e., phase shifted by 180 degrees) (DCLKB). The 2 N -1 bit output DWA word (DWAout<2 N -1:1) is logically inverted by the circuit 202 to generate an inverted 2 N -1 bit output DWA word (DWAoutB<2 N -1:1). A logic delay circuit 204 receives the sample clock CLK and outputs a phase delayed sample clock DlyCLK. As described below, the four-way control words DP1<2N-1:1>, DP2<2N-1:1>, DM1<2N-1:1> and DM2<2N-1:1> are generated by logically combining the DWAout<2 N -1:1> words and the DCLK clock, and then latching the result of the logical ANDing operation in a latch circuit 212 in response to the DlyCLK clock to generate the control word DP1<2 N -1:1>. The control word DP2<2 N -1:1> is generated by logically ANDing 214 the DWAoutB<2 N -1:1> words and the DCLKB clock, and then latching the result of the logical ANDing operation in a latch circuit 216 in response to the DlyCLK clock. The control word DP2<2 N -1:1> is generated by logically ANDing 218 the DWAoutB<2 N -1:1> words and the DCLK clock, and then latching the result of the logical ANDing operation in a latch circuit 220 in response to the DlyCLK clock to generate the control word DM1<2 N-1:1> word and DCLKB clock logic AND (222) then latches the result of the logical AND operation in latch circuit 224 in response to the DlyCLK clock to generate control word DM2<2 N -1:1>.

[0035] Figure 7 A timing diagram showing the operation of the four-way signal generator circuit 104 is shown. It should be noted that the changes in the logic state of the control signals DP1(X), DP2(X), DM1(X), and DM2(X) occur in response to the same edge (in this case, the trailing edge) of the sampling clock CLK. Thus, the changes in the logic state of the control signals DP1(X), DP2(X), DM1(X), and DM2(X) occur at the same rate as the sampling clock CLK. In other words, the logic state of the control signals DP1(X), DP2(X), DM1(X), and DM2(X) remains constant for at least as long as the duration of one period of the sampling clock CLK. This operation occurs because the DCLK clock and the DCLKB clock (at one-half the rate of the sampling clock CLK) control the logical combination function through an AND operation that generates the control signals DP1(X), DP2(X), DM1(X), and DM2(X) from the DWAout(X) bits and the DWAoutB(X) bits.

[0036] Although disclosed herein in the context of a continuous-time delta-sigma modulator, it should be understood that the disclosed circuits and operations herein can also be applied to a discrete-time modulator.

[0037] While the application has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered illustrative or exemplary only; the application is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed application, from an study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: Digital-to-analog converter (DAC) circuit with 2 N -1 unit resistance DAC element, wherein each unit resistance DAC element comprises four 2 N The four switching circuits controlled by the corresponding bit of the -1 bit control signal, wherein the 2 N The outputs of -1 unit resistance DAC elements are summed to generate an analog output signal; as well as A four-channel signal generator circuit is configured to respond to a sampling clock and 2 N The four 2-bit thermometer-encoded input signals are generated by the -1-bit thermometer encoding input signal. N -1 bit control signal, wherein the four-way signal generator circuit controls the four 2 N -1 bit control signal generation, so that the four 2 N The logic state of all bits of the -1 control signal remains constant for at least the duration of one cycle of the sampling clock. Where N is the number of bits in the multi-bit quantization circuit.

2. The circuit according to claim 1, wherein the four-channel signal generator circuit controls the four 2 N -1 bit control signal generation, so that in the four 2 N All changes in the logic state of the -1 bit control signal occur in response to the same leading or trailing edge of the period of the sampling clock.

3. The circuit according to claim 1, wherein the four-channel signal generator circuit comprises: A frequency divider circuit is configured to divide the sampling clock and generate a divided sampling clock, wherein the four-channel signal generator circuit controls the four 2 N -1 bit control signal generation, so that in the four 2 N All changes in the logic state of the -1 bit control signal occur in response to the edge of the divided sampling clock.

4. The circuit of claim 1, wherein the four switching circuits for each unit-resistance DAC element comprise: The first switching circuit is configured to respond to the four 2 N The logical inversion of the second control signal in the -1 bit control signal and the four 2 N The first control signal in the -1 bit control signal, while switching the first common node between the first reference voltage and the second reference voltage; The second switching circuit is configured to respond to the four 2 N The logical inversion of the fourth control signal in the -1 bit control signal and the four 2 N The third control signal in the -1 bit control signal, and the first common node is switched between the first reference voltage and the second reference voltage; The third switching circuit is configured to respond to the four 2 N The logical inversion of the first control signal in the -1 bit control signal and the four 2 N The second control signal in the -1 bit control signal, while switching the second common node between the first reference voltage and the second reference voltage; as well as The fourth switching circuit is configured to respond to the four 2 N The logical inversion of the third control signal in the -1 bit control signal and the four 2 N The fourth control signal in the -1 bit control signal, while switching the second common node between the first reference voltage and the second reference voltage.

5. The circuit according to claim 4, further comprising: A first resistor circuit is coupled between the first common node and the first summation output node, the first summation output node being used to provide a first component of the analog output signal; as well as A second resistor circuit is coupled between the second common node and the second summation output node, the second summation output node being used to provide a second component of the analog output signal.

6. The circuit according to claim 5, wherein the first component and the second component are differential currents of the analog output signal.

7. The circuit according to claim 4, wherein the four-channel signal generator circuit comprises: The frequency divider circuit is configured to divide the sampling clock and generate the divided sampling clock. The first logic circuit is configured to... N Each bit of the input signal encoded by the -1-bit thermometer is logically combined with the frequency-divided sampling clock to generate the corresponding bit of the second control signal; The second logic circuit is configured to... N Each bit of the input signal encoded by the -1-bit thermometer is combined with the inverted logic of the frequency-divided sampling clock to generate the corresponding bit of the fourth control signal; The third logic circuit is configured to convert the 2 N Each bit of the logically inverted input signal encoded by the -1-bit thermometer is combined with the frequency-divided sampling clock logic to generate the corresponding bit of the first control signal; as well as The fourth logic circuit is configured to... N Each bit of the -1-bit thermometer-encoded input signal, inverted by logic, is combined with the inverted logic of the frequency-divided sampling clock to generate the corresponding bit of the third control signal.

8. The circuit according to claim 7, wherein the four-channel signal generator circuit further comprises: Latch circuit, used for the four 2 N -1 control signal, each 2 N -1 bit control signal, the latch circuit is configured to latch the four 2-bit control signals in response to a delayed sampling clock generated by applying a delay to the sampling clock. N -1 bit of the control signal.

9. The circuit according to claim 1, wherein the 2 N The input signal encoded by the -1-bit thermometer is generated using a data weighted average (DWA).

10. The circuit of claim 9, further comprising a DWA circuit configured to transmit data to the received 2 N The -1 bit thermometer-encoded signal is applied to a data-weighted average to generate the 2 N -1 bit thermometer encoded input signal.

11. The circuit of claim 10, further comprising the multi-bit quantization circuit configured to generate the 2 N -1 bit thermometer encoded signal.

12. A sigma-delta analog-to-digital converter (ADC) circuit, comprising: A loop filter circuit is configured to generate a difference signal based on the difference between an analog input signal and an analog feedback signal, and to filter the difference signal to generate a changing signal. A multi-bit quantization circuit is configured to quantize the changing signal and generate 2 N -1 bit thermometer encoded signal, wherein N is the number of bits of the multi-bit quantization circuit; The four-channel signal generator circuit is configured to respond to the sampling clock and the 2 N -1 bit thermometer encoded signal to generate four 2 N -1 bit control signal; Digital-to-analog converter (DAC) circuit with 2 N -1 unit resistance DAC element, wherein each unit resistance DAC element comprises four 2 N The four switching circuits controlled by the corresponding bit of the -1 bit control signal; Among them, for the 2 N The outputs of -1 unit resistance DAC elements are summed to generate the analog feedback signal; and The four-channel signal generator circuit controls the four 2 N -1 bit control signal generation, so that the four 2 N All logic states of the -1 bit control signal remain constant for at least the duration of one cycle of the sampling clock.

13. The circuit according to claim 12, wherein the 2 N The -1 bit thermometer-encoded signal is generated using a data weighted average (DWA).

14. The circuit of claim 13, further comprising a DWA circuit configured to transmit 2 from the multi-bit quantization circuit. N The output signal encoded by the -1-bit thermometer is applied using a data-weighted average to generate the 2 N -1 bit thermometer encoded signal.

15. The circuit of claim 12, wherein the four-channel signal generator circuit controls the four 2 N -1 bit control signal generation, so that in the four 2 N All changes in the logic state of the -1 bit control signal occur in response to the same leading or trailing edge of the period of the sampling clock.

16. The circuit of claim 12, wherein the four-channel signal generator circuit comprises: A frequency divider circuit is configured to divide the sampling clock and generate a divided sampling clock, wherein the four-channel signal generator circuit controls the four 2 N -1 bit control signal generation, so that in the four 2 N All changes in the logic state of the -1 bit control signal occur in response to the edge of the divided sampling clock.

17. The circuit of claim 12, wherein the four switching circuits for each unit-resistance DAC element comprise: The first switching circuit is configured to respond to the four 2 N The logical inversion of the second control signal in the -1 bit control signal and the four 2 N The first control signal in the -1 bit control signal, while switching the first common node between the first reference voltage and the second reference voltage; The second switching circuit is configured to respond to the four 2 N The logical inversion of the fourth control signal in the -1 bit control signal and the four 2 N The third control signal in the -1 bit control signal, and the first common node is switched between the first reference voltage and the second reference voltage; The third switching circuit is configured to respond to the four 2 N The logical inversion of the first control signal in the -1 bit control signal and the four 2 N The second control signal in the -1 bit control signal, while switching the second common node between the first reference voltage and the second reference voltage; as well as The fourth switching circuit is configured to respond to the four 2 N The logical inversion of the third control signal in the -1 bit control signal and the four 2 N The fourth control signal in the -1 bit control signal, while switching the second common node between the first reference voltage and the second reference voltage.

18. The circuit according to claim 17, further comprising: A first resistor circuit is coupled between the first common node and the first summation output node, the first summation output node being used to provide a first component of the analog output signal; as well as A second resistor circuit is coupled between the second common node and the second summation output node, the second summation output node being used to provide a second component of the analog output signal.

19. The circuit of claim 18, wherein the first component and the second component are differential currents of the analog output signal.

20. The circuit of claim 17, wherein the four-channel signal generator circuit comprises: The frequency divider circuit is configured to divide the sampling clock and generate a frequency-divided sampling clock. The first logic circuit is configured to... N Each bit of the signal encoded by the -1-bit thermometer is logically combined with the frequency-divided sampling clock to generate the corresponding bit of the second control signal; The second logic circuit is configured to... N Each bit of the signal encoded by the -1-bit thermometer is combined with the inverted logic of the frequency-divided sampling clock to generate the corresponding bit of the fourth control signal; The third logic circuit is configured to convert the 2 N Each bit of the signal encoded by the -1-bit thermometer is logically inverted and combined with the frequency-divided sampling clock logic to generate the corresponding bit of the first control signal; as well as The fourth logic circuit is configured to... N Each bit of the -1-bit thermometer encoded signal, inverted by logic, is combined with the inverted logic of the frequency-divided sampling clock to generate the corresponding bit of the third control signal.

21. The circuit of claim 20, wherein the four-channel signal generator circuit further comprises: Latch circuit, used for the four 2 N -1 control signal, each 2 N -1 bit control signal, the latch circuit is configured to latch the four 2-bit control signals in response to a delayed sampling clock generated by applying a delay to the sampling clock. N -1 bit of the control signal.

22. A sigma-delta analog-to-digital converter (ADC) circuit, comprising: The loop filter is configured to receive an analog input signal and a first analog feedback signal and generate an integral signal; A multi-bit quantization circuit is configured to quantize the integrated signal and generate 2 N -1 bit thermometer encoded signal, wherein N is the number of bits of the multi-bit quantization circuit; The four-channel signal generator circuit is configured to respond to the sampling clock and the 2 N -1 bit thermometer encoded signal to generate four 2 N -1 bit control signal; The first digital-to-analog converter (DAC) circuit has 2 N -1 unit resistance DAC element, wherein each unit resistance DAC element comprises four 2 N The four switching circuits controlled by the corresponding bit of the -1 bit control signal; Among them, the 2 of the first DAC circuit N The outputs of -1 unit resistance DAC elements are summed to generate the first analog feedback signal; and The four-channel signal generator circuit controls the four 2 N -1 bit control signal generation, so that the four 2 N All logic states of the -1 bit control signal remain constant for at least the duration of one cycle of the sampling clock.

23. The circuit of claim 22, wherein the loop filter is at least third order, and the loop filter further receives a second analog feedback signal to generate the integral signal, and the circuit further comprises: The second digital-to-analog converter (DAC) circuit has 2 N -1 unit resistance DAC element, wherein each unit resistance DAC element comprises four 2 N The four switching circuits controlled by the corresponding bit of the -1 bit control signal; and Among them, the second DAC circuit of the 2 N The outputs of -1 unit resistance DAC elements are summed to generate the second analog feedback signal.

24. The circuit of claim 22, further comprising a data weighted average (DWA) circuit configured to feed data from the multi-bit quantization circuit into the 2... N The output signal encoded by the -1-bit thermometer is applied using a data-weighted average to generate the 2 N -1 bit thermometer encoded signal.

25. The circuit of claim 22, wherein the four switching circuits for each unit-resistance DAC element comprise: The first switching circuit is configured to respond to the four 2 N The logical inversion of the second control signal in the -1 bit control signal and the four 2 N The first control signal in the -1 bit control signal, while switching the first common node between the first reference voltage and the second reference voltage; The second switching circuit is configured to respond to the four 2 N The logical inversion of the fourth control signal in the -1 bit control signal and the four 2 N The third control signal in the -1 bit control signal, and the first common node is switched between the first reference voltage and the second reference voltage; The third switching circuit is configured to respond to the four 2 N The logical inversion of the first control signal in the -1 bit control signal and the four 2 N The second control signal in the -1 bit control signal, while switching the second common node between the first reference voltage and the second reference voltage; as well as The fourth switching circuit is configured to respond to the four 2 N The logical inversion of the third control signal in the -1 bit control signal and the four 2 N The fourth control signal in the -1 bit control signal, while switching the second common node between the first reference voltage and the second reference voltage.

26. The circuit according to claim 25, further comprising: A first resistor circuit is coupled between the first common node and the first summation output node, the first summation output node being used to provide a first component of the analog output signal; as well as A second resistor circuit is coupled between the second common node and the second summation output node, the second summation output node being used to provide a second component of the analog output signal.

27. The circuit of claim 26, wherein the first component and the second component are differential currents of the analog output signal.

28. The circuit of claim 25, wherein the four-channel signal generator circuit comprises: The frequency divider circuit is configured to divide the sampling clock and generate a frequency-divided sampling clock. The first logic circuit is configured to... N Each bit of the signal encoded by the -1-bit thermometer is logically combined with the frequency-divided sampling clock to generate the corresponding bit of the second control signal; The second logic circuit is configured to... N Each bit of the signal encoded by the -1-bit thermometer is combined with the inverted logic of the frequency-divided sampling clock to generate the corresponding bit of the fourth control signal; The third logic circuit is configured to convert the 2 N Each bit of the signal encoded by the -1-bit thermometer is logically inverted and combined with the frequency-divided sampling clock logic to generate the corresponding bit of the first control signal; as well as The fourth logic circuit is configured to... N Each bit of the -1-bit thermometer encoded signal, inverted by logic, is combined with the inverted logic of the frequency-divided sampling clock to generate the corresponding bit of the third control signal.

29. The circuit of claim 28, wherein the four-channel signal generator circuit further comprises: Latch circuit, used for the four 2 N -1 control signal, each 2 N -1 bit control signal, the latch circuit is configured to latch the four 2-bit control signals in response to a delayed sampling clock generated by applying a delay to the sampling clock. N -1 bit of the control signal.

Images