Apparatus for parallel generation of syndrome in a lookup table-based synchronization byte decoder

Abstract

The present invention relates to a parallel syndrome generation device for a MPEG-2 synchronization byte decoder based on a lookup table, applicable to the digital multi-program system B recommended by ITU-T J.83. The device is characterized in that it mainly consists of a 1504-bit memory, 15 registers R0 to R 14 , 128 two-input AND gates and 128 two-input XOR gates. The syndrome generation device provided by the present invention inputs the received data of 188 bytes in a 16-bit parallel manner and outputs 1-byte syndrome in an 8-bit parallel manner, which can effectively reduce the logical resource requirements while increasing the processing speed by 16 times, and has the advantages of fast running speed and less consumption of logical resources.

Description

Technical Field

[0001] The present invention relates to the field of wired digital television, and particularly to a parallel generation technology of the syndrome of an MPEG-2 synchronization byte decoder based on a lookup table in Digital Multiprogram System B recommended by ITU-T J.83. Background Art

[0002] The MPEG-2 transport packet has a length of 188 bytes and consists of a 1-byte "synchronization" field, a 3-byte "header" field, and a 184-byte "payload" field. For the sake of description, we will collectively refer to the 3-byte "header" field and the 184-byte "payload" field as 187-byte information.

[0003] ITU-T J.83 recommends 4 digital multiprogram systems for the wired distribution of television, voice, and data services, one of which is Digital Multiprogram System B. This system removes the "synchronization" field based on the MPEG-2 transport packet format and adds a 1-byte "checksum" field after the "payload" field to form a codeword with a length still remaining 188 bytes. The checksum can be calculated by a FIR parity-check linear block code for the 187-byte information and can be used for synchronization and error detection to provide enhanced packet division function and error detection ability independent of the FEC layer. If the transmitting end uses a serial method to transmit the codeword, then the most significant bit (MSB) of the byte is transmitted first, and the least significant bit (LSB) is transmitted last. The receiving end uses a syndrome generation device to determine whether the received data is a valid codeword.

[0004] Digital Multiprogram System B gives the circuit model of the syndrome generation device of the MPEG-2 synchronization byte decoder, as Figure 1 shown. This circuit model consists of two functional modules, an Infinite Impulse Response (IIR) filter and a Finite Impulse Response (FIR) filter, and includes 1512 registers and 8 two-input exclusive-OR gates. In this device, all the registers are initialized to '0'. This device serially inputs the received data of 188 bytes and serially outputs 1 byte of syndrome after 1504 clock cycles.

[0005] The syndrome generation device given by Digital Multiprogram System B uses 1512 registers and 8 two-input exclusive-OR gates, consuming a lot of logic resources. It takes 1504 clock cycles to calculate a syndrome once, and the running speed is slow. Summary of the Invention

[0006] Aiming at the disadvantages of the syndrome generation scheme given for ITU-T J.83 digital multi-program system B, such as high consumption of logic resources and slow operation speed, the present invention provides a scheme for parallelly generating syndromes based on a look-up table, and gives the corresponding circuit model to reduce the logic resource requirements and improve the processing speed.

[0007] As Figure 3 shown, the syndrome parallel generation device in the MPEG-2 synchronization byte decoder based on the look-up table mainly consists of a 1504-bit memory, 15 registers R0 to R 14 , 128 two-input AND gates and 128 two-input XOR gates. The memory stores the look-up table of the combined filter coefficients, and its address corresponds to the index j of the look-up table, and outputs e 1481-16j ~e 1496-16j through a 16-bit data bus, where 0 ≤ j < 94. Registers R0 to R6 are respectively used to store the coefficients e 1497-16j ~e 1503-16j of the combined filter. Registers R7 to R 14 are respectively used to store d 1496 ~d 1503 and their intermediate operation results. 128 two-input AND gates and 128 two-input XOR gates are used to calculate d 1496 ~d 1503 . The device inputs the received data of 188 bytes in a 16-bit parallel manner and outputs 1 byte of syndrome in an 8-bit parallel manner. Calculating a syndrome is completed in 5 steps: (1) Initialize j = 0, and registers R0 to R 14 are all initialized to 0, where registers R0 to R6 are equivalently initialized to e 1497 ~e 1503 ; (2) Input the bits a 16j ~a 16j+15 of the data segment vector, the memory outputs e 1481-16j ~e 1496-16j , registers R0 to R6 output e 1497-16j ~e 1503-16j , and they jointly output e 1481-16j ~e 1503-16j ; (3) The continuous 16 bits in e 1481-16j ~e 1503-16j form 8 different vectors, and 128 two-input AND gates and 128 two-input XOR gates perform vector multiplication operations, and the products are accumulated into registers R7 to R 14 ; (4) e 1481-16j ~e 1487-16j are saved into registers R0 to R6; (5) j is incremented by 1. If j < 94, jump to step (2); otherwise, the content in registers R7 to R 14 is the d 1496~d 1503 The calculation of the syndrome is completed this time.

[0008] The syndrome generation device based on the lookup table provided by the present invention inputs the received data in parallel and outputs the syndrome in parallel. At the cost of adding a small amount of memory, it can significantly improve the processing speed while effectively reducing the demand for logic resources.

[0009] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. Description of the Drawings

[0010] Figure 1 It is a circuit model for generating the syndrome by the MPEG-2 synchronization byte decoder;

[0011] Figure 2 It is a polynomial model for generating the syndrome by the MPEG-2 synchronization byte decoder;

[0012] Figure 3 It is a circuit model for parallelly generating the syndrome by the MPEG-2 synchronization byte decoder based on the lookup table;

[0013] Figure 4 The specific content of the lookup table made from some coefficients of the joint filter is given. Detailed Embodiments

[0014] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but it is not intended to limit the present invention.

[0015] In Figure 1 , the received data sequence and the output sequence are respectively labeled as a i and d i , and their values are '0' or '1'. Among them, 0 ≤ i < 1504, and d 1496 ~d 1503 constitute a 1-byte syndrome.

[0016] Figure 1 The corresponding polynomial model is as Figure 2 shown, and its input and output are respectively

[0017]

[0018]

[0019] When 0 ≤ i < 1504, the coefficients a i and d i in the above formula are exactly the same as a Figure 1 and d i in i In Figure 2Among them, the IIR filter completes the division operation of the generating polynomial g(x), and the FIR filter completes the multiplication operation of the polynomial [1 + x 1497 b(x)], where g(x) = 1 + x + x 5 + x 6 + x 8 , b(x) = 1 + x + x 3 + x 7 . The IIR filter and the FIR filter form a combined filter, and its characteristic polynomial is

[0020]

[0021] The coefficients of the combined filter are e i , when 0 ≤ i ≤ 1496, e i = 0 or 1, when i < 0 or i > 1496, e i = 0. Obviously, this combined filter is a FIR filter, and its input and output satisfy the following relationship

[0022] d(x) = a(x)e(x) (4)

[0023] Substituting equations (1) - (3) into the above formula and sorting it out, the 8 - bit syndrome can be obtained

[0024]

[0025] From equation (3), it can be seen that when i < 0, e i = 0. Therefore, equation (5) can be rewritten as

[0026]

[0027] There are 1504 terms on the right side of the above equation, and 1504÷16 = 94. Since 1504 is an integer multiple of 16, the received data sequence can be divided into equal - length segments, each segment being 16 bits, and they form a data - segment vector [a 16j+15 a 16j+14 … a 16j , where 0 ≤ j < 94. The continuous 16 - bit coefficients of the combined filter can form a column vector, and thus equation (6) can be rewritten in the following form of vector multiplication

[0028]

[0029] Among them, the superscript TDenotes the vector transpose. In the above formula, the row vectors in each equation are exactly the same, all being data segment vectors, and the 8 column vectors are slightly different: the column vectors in adjacent equations differ by only 1 bit, and the column vector in the following equation is obtained by shifting the column vector in the previous equation one bit to the left and updating 1 bit at the least significant bit. Therefore, each column vector in Equation (7) can be regarded as being taken from the column vector [e 1481-16j e 1482-16j … e 1503-16j T for 16 consecutive bits.

[0030] Based on the above analysis, we can obtain a circuit model of the syndrome parallel generation device in the MPEG-2 synchronization byte decoder based on the lookup table, as Figure 3 shown. This device inputs the received data of 188 bytes in a 16-bit parallel manner and outputs 1 byte of syndrome in an 8-bit parallel manner. This device mainly consists of a 1504-bit memory, 15 registers R0 to R 14 , 128 two-input AND gates, and 128 two-input XOR gates. The lookup table is made from the partial coefficients of the combined filter, and the range of its index j is 0 ≤ j < 94. Each item contains 16 coefficients, corresponding to e 1481-16j to e 1496-16j from the most significant bit to the least significant bit. The specific content in hexadecimal representation is as Figure 4 shown. The memory stores the lookup table composed of the combined filter coefficients, and its address corresponds to the index j of the lookup table, and outputs e 1481-16j to e 1496-16j using a 16-bit data bus. Registers R0 to R6 are respectively used to store the coefficients e 1497-16j to e 1503-16j of the combined filter. Among them, when j = 0, it can be seen from Equation (3) that e 1497 to e 1503 are all 0. Therefore, registers R0 to R6 need to be initialized to all zeros. Registers R7 to R 14 are respectively used to store d 1496 to d 1503 and their intermediate operation results, and they also need to be initialized to all zeros. 128 two-input AND gates and 128 two-input XOR gates are used to calculate d 1496 to d 1503 . 128 two-input AND gates are used to complete the element multiplication operation of the vector multiplication in Equation (7), and 128 two-input XOR gates are used to complete the element modulo 2 addition operation of the vector multiplication in Equation (7) and accumulate the product into registers R7 to R 14 .

[0031] ​For the digital multi-program system B recommended by ITU-T J.83, the present invention provides a method for parallel generation of syndromes in an MPEG-2 synchronization byte decoder based on a lookup table. The steps for calculating a syndrome are as follows:

[0032] (1) Initialize j = 0, and registers R0 to R 14 are all initialized to 0, where registers R0 to R6 are equivalently initialized to e 1497 to e 1503 ;

[0033] (2) Input the bits a 16j to a 16j+15 of the data segment vector, the memory outputs e 1481-16j to e 1496-16j , and registers R0 to R6 output e 1497-16j to e 1503-16j . They jointly output e 1481-16j to e 1503-16j ;

[0034] (3) The consecutive 16 bits in e 1481-16j to e 1503-16j form 8 different vectors. 128 two-input AND gates and 128 two-input XOR gates perform vector multiplication operations, and the products are accumulated into registers R7 to R 14 ;

[0035] (4) e 1481-16j to e 1487-16j are saved into registers R0 to R6;

[0036] (5) Increment j by 1. If j < 94, jump to step (2); otherwise, the contents in registers R7 to R 14 are the syndromes d 1496 to d 1503 , and the calculation of the syndrome for this time is completed.

[0037] If the syndrome bits d 1496 to d 1503 are respectively equal to '0', '1', '0', '0', '0', '1', '1', and '1', that is, combined into one byte equal to the hexadecimal number 0x47, it is considered that the received data is a valid codeword; otherwise, it is considered that the received data is incorrect.

[0038] The present invention requires a 1504-bit memory, 15 registers, 128 two-input AND gates, and 128 two-input XOR gates, and generates a syndrome result after 94 clock cycles. Compared with the syndrome generation device given in ITU-T J.83 Digital Multiprogram System B, the processing speed of the present invention is increased by 16 times. Although 128 two-input AND gates and 120 two-input XOR gates are used more, the consumption of registers is less than 1% of the former. Generally speaking, very few logic resources are consumed. The disadvantage of the present invention is that it requires a 1504-bit memory. In summary, compared with the syndrome generation device given in ITU-T J.83 Digital Multiprogram System B, the present invention has the advantages of fast operation speed and less consumption of logic resources.

[0039] The present invention has been described in detail above through specific embodiments and examples. For those skilled in the art, without departing from the principle of the present invention, several modifications and improvements can still be made, which should also be regarded as the protection scope of the present invention.

Claims

1. A syndrome parallel generation device in a lookup table-based synchronization byte decoder, applicable to the digital multi-program system B recommended by ITU-T J.

83. This device inputs the received data of 188 bytes in a 16-bit parallel manner and outputs 1-byte syndrome in an 8-bit parallel manner. The received data sequence a i is divided into segments of equal length, each segment being 16 bits, which form the data segment vector [a 16j+15 a 16j+14 … a 16j , where 0 ≤ i < 1504, 0 ≤ j < 94, and the 8 bits of the syndrome are d 1496 ~d 1503 , and the coefficients of the joint filter are e i , when 0 ≤ i ≤ 1496, e i = 0 or 1, when i < 0 or i > 1496, e i = 0. The lookup table is made from partial coefficients of the joint filter, and the range of its index j is 0 ≤ j < 94. Each item contains 16 coefficients, corresponding to e 1481-16j ~e 1496-16j , and it is characterized in that the device comprises the following components: A 1504-bit memory stores a look-up table composed of combined filter coefficients, whose address corresponds to the index j of the look-up table, and outputs e using a 16-bit data bus 1481-16j ~e 1496-16j ; 15 registers R0 to R 14 , registers R0 to R6 are respectively used to store the coefficients e 1497-16j ~e 1503-16j , where when j = 0, e 1497 ~e 1503 are all 0, and registers R7 to R 14 are respectively used to store d 1496 ~d 1503 and their intermediate operation results; 128 two-input AND gates and 128 two-input XOR gates are used to calculate d 1496 ~d 1503 , 128 two-input AND gates are used to perform element-wise multiplication operations of vector multiplication, and 128 two-input XOR gates are used to perform element-wise modulo-2 addition operations of vector multiplication and accumulate the products into registers R7~R 14 .

2. A method for parallel generation of syndrome in a lookup table-based synchronous byte decoder, applicable to the digital multi-program system B recommended by ITU-T J.

83. This method inputs the received data of 188 bytes in a 16-bit parallel manner and outputs 1-byte syndrome in an 8-bit parallel manner. The received data sequence a i is divided into segments of equal length, each segment being 16 bits, which form the data segment vector [a 16j+15 a 16j+14 … a 16j , where 0 ≤ i < 1504, 0 ≤ j < 94, and the 8 bits of the syndrome are d 1496 ~d 1503 , and the coefficients of the combined filter are e i , when 0 ≤ i ≤ 1496, e i = 0 or 1, when i < 0 or i > 1496, e i = 0. The look-up table is made up of partial coefficients of the combined filter, where the index j ranges from 0 ≤ j < 94, and each item contains 16 coefficients corresponding to e from the most significant bit to the least significant bit 1481-16j ~e 1496-16j , characterized in that the generating method calculates the syndrome once as follows: (1) Initialize j = 0, and registers R0 to R 14 are all initialized to 0. Among them, registers R0 to R6 are equivalently initialized to e 1497 ~e 1503 ; (2) Bit a of the input data segment vector 16j ~a 16j+15 , memory output e 1481-16j ~e 1496-16j , register R0 to R6 output e 1497-16j ~e 1503-16j , they jointly output e 1481-16j ~e 1503-16j ; (3)e 1481-16j ~e 1503-16j The consecutive 16 bits in form 8 different vectors, and 128 two-input AND gates and 128 two-input XOR gates perform vector multiplication operations, and the products are accumulated into registers R7 to R 14 ; (4)e 1481-16j ~e 1487-16j are stored in registers R0 to R6; (5)Increment j by 1. If j < 94, jump to step (2); otherwise, the content in registers R7 to R 14 is d 1496 to d 1503 , and the calculation of the syndrome for this time is completed.

3. The method for parallel generation of syndromes in a look-up table-based synchronization byte decoder as claimed in claim 2, wherein, Calculate the 8-bit d of the syndrome 1496 ~d 1503 Follow the following vector multiplication: Among them, the superscript T represents the vector transpose.

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