A compression type power chip packaging structure

Abstract

The present invention provides a compression-type power chip packaging structure, comprising: a first electrode layer and a second electrode layer; a power chip; a composite connection plate located between the first electrode layer and the second electrode layer and located on the side of the power chip, the composite connection plate comprising: a first insulating plate, a first conductive layer located on one side of the first insulating plate, and a second conductive layer located on the side of the first insulating plate facing away from the first conductive layer, the first conductive layer and the second conductive layer are respectively spaced from the first electrode layer and the second electrode layer; a gate is electrically connected to the first conductive layer through a first bonding wire; and an emitter is electrically connected to the second conductive layer through a second bonding wire. The compression-type power chip packaging structure has an increased switching speed and reduced switching loss.

Description

Technical Field

[0001] The invention relates to the technical field of power semiconductor devices, and in particular to a compression-type power chip packaging structure. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor), also known as insulated gate bipolar transistor, is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar junction transistor) and MOS (insulated gate field effect transistor). The packaged IGBT module is directly used in inverters, UPS uninterruptible power supplies and other equipment to play the role of a switch.

[0003] Currently, power IGBT devices can be divided into two types according to the packaging process: welding type and crimping type.

[0004] High-power crimp-type IGBT devices combine the advantages of both IGBT and GTO, and have the characteristics of double-sided heat dissipation, easy series connection, high reliability, short-circuit failure, and large current capacity. The crimp-type IGBT device connects multiple IGBT chips in parallel and multiple diode chips in anti-parallel to obtain the high current capacity of the device. Due to its advantages of high voltage, high current, low control power, high switching speed, and double-sided heat dissipation, it is very suitable for high-power applications such as electric locomotive traction and high-current pulse generators. In addition, the crimp-type IGBT device also has the characteristics of short-circuit failure, which is particularly suitable for redundant design. Therefore, the crimp-type IGBT device is an ideal device for high-voltage DC transmission.

[0005] However, the switching speed of existing press-fit IGBT devices needs to be improved and the switching loss needs to be reduced. Summary of the invention

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the problem of how to increase the switching speed and reduce the switching loss of the press-fit IGBT device in the prior art, thereby providing a press-fit power chip packaging structure.

[0007] The present invention provides a compression-type power chip packaging structure, comprising: a first electrode layer and a second electrode layer arranged opposite to each other; a power chip located between the first electrode layer and the second electrode layer, a collector is arranged on a surface of the power chip facing the first electrode layer, a gate and an emitter are arranged on a surface of the power chip facing the second electrode layer, and the emitter is electrically connected to the second electrode layer; a composite connecting plate located between the first electrode layer and the second electrode layer and located on the side of the power chip, the composite connecting plate comprising: a first insulating plate, a first conductive layer located on one side of the first insulating plate, and a second conductive layer located on a surface of the first insulating plate facing away from the first conductive layer, the first conductive layer and the second conductive layer are respectively spaced apart from the first electrode layer and the second electrode layer; the gate is electrically connected to the first conductive layer through a first bonding wire; the emitter is electrically connected to the second conductive layer through a second bonding wire.

[0008] Optionally, it further includes: a gate terminal, one end of which is connected to the first conductive layer; and an auxiliary emitter terminal, one end of which is connected to the second conductive layer.

[0009] Optionally, it also includes: an elastic conductive component located between the power chip and the second electrode layer, the elastic conductive component electrically connects the emitter and the second electrode layer, and the elastic conductive component is separate from the gate.

[0010] Optionally, the elastic conductive component is electrically connected to the emitter via a third conductive layer, and a thermal expansion coefficient of the third conductive layer is greater than a thermal expansion coefficient of the power chip and smaller than a thermal expansion coefficient of the elastic conductive component.

[0011] Optionally, the elastic conductive component includes: a conductive pin, the conductive pin includes a pin base and a protrusion protruding from the surface of the pin base, the pin base is located between the protrusion and the emitter and is electrically connected to the emitter; a conductive guide, the conductive guide includes a first guide and a second guide connected to the first guide, the second guide is connected to the second electrode layer, and a portion of the side wall of the first guide is slidably connected to the side wall of the protrusion; an elastic member, the elastic member is sleeved on the outer wall of the first guide, one end of the elastic member is abutted against the second guide member, and the other end of the elastic member is abutted against the pin base.

[0012] Optionally, the first conductive layer is located between the first insulating plate and the first electrode layer, and the second conductive layer is located between the first insulating plate and the second electrode layer; the composite connecting plate also includes a second insulating plate and a third insulating plate; the second insulating plate is located between the first conductive layer and the first electrode layer, and the first conductive layer is also in contact with a surface of the second insulating plate facing away from the first electrode layer; the third insulating plate is located between the second conductive layer and the second electrode layer, and the second conductive layer is also in contact with a surface of the third insulating plate facing away from the second electrode layer.

[0013] Optionally, the surface area of ​​the second insulating plate facing away from the first electrode layer is larger than the surface area of ​​the first insulating plate facing the first electrode layer, the portion of the first conductive layer in contact with the second insulating plate is located outside the first insulating plate, and the first bonding wire is in contact with the first conductive layer located outside the first insulating plate and on the surface of the second insulating plate; the surface area of ​​the first insulating plate facing the second electrode layer is larger than the surface area of ​​the third insulating plate facing away from the second conductive layer, the portion of the second conductive layer in contact with the first insulating plate is located outside the third insulating plate, and the second bonding wire is in contact with the second conductive layer located outside the third insulating plate and on the surface of the first insulating plate.

[0014] Optionally, the second insulating plate is fixedly connected to the first electrode layer via a first welding layer; and the third insulating plate is fixedly connected to the second electrode layer via a second welding layer.

[0015] Optionally, it also includes: a tube shell, wherein the tube shell is located between the first electrode layer and the second electrode layer, one end of the tube shell is fixedly connected to the first electrode layer, and the other end of the tube shell can be separated from the second electrode layer; the gate terminal is led out from the tube shell at one end away from the first conductive layer; and the auxiliary emitter terminal is led out from the tube shell at one end away from the second conductive layer.

[0016] Optionally, the first insulating plate includes a ceramic insulating plate, the first conductive layer includes a copper conductive layer, the second conductive layer includes a copper conductive layer, and the first electrode layer includes a molybdenum electrode layer.

[0017] The technical solution of the present invention has the following beneficial effects:

[0018] 1. The present invention provides a compression-type power chip packaging structure, in which the gate is electrically connected to the first conductive layer through a first bonding wire, the emitter is electrically connected to the second conductive layer through a second bonding wire, the first conductive layer is spaced apart from the first electrode layer and the second electrode layer, and the second conductive layer is spaced apart from the first electrode layer and the second electrode layer. A gate drive circuit formed by the first conductive layer, the first bonding wire, the gate, the emitter, the second bonding wire and the second conductive layer and a collector-emitter power circuit formed by the first electrode layer, the collector, the emitter and the second electrode layer form a parallel structure. The gate drive circuit, as an auxiliary circuit connecting the emitter and the gate, realizes a Kelvin connection, so that the gate drive circuit and the collector-emitter power circuit are decoupled, and the influence of the common-emitter stray inductance on the power chip is eliminated, thereby improving the switching speed of the power chip and reducing the switching loss of the power chip.

[0019] 2. Furthermore, the elastic conductive component is located between the power chip and the second electrode layer. The power chip and the second electrode layer are in elastic contact. The elastic conductive component adjusts the pressure difference between the power chip and the composite connecting plate so that the surface of the power chip is evenly stressed, thereby avoiding damage to the power chip due to hard contact with the first electrode layer and the second electrode layer under the action of external pressure.

[0020] 3. Furthermore, even if the power chip generates a lot of heat during operation, causing the volume of the power chip to expand thermally, the elastic conductive component is electrically connected to the emitter through the third conductive layer. The thermal expansion coefficient of the third conductive layer is greater than the thermal expansion coefficient of the power chip and less than the thermal expansion coefficient of the elastic conductive component. The thermal expansion coefficient of the third conductive layer is similar to that of the power chip, thereby avoiding the mismatch in thermal expansion coefficients between the power chip and the elastic conductive component, which causes a large shear force to wear the power chip, and avoiding failure of the power chip after multiple thermal expansion and contraction.

[0021] 4. Furthermore, the second insulating plate is located between the first conductive layer and the first electrode layer, and plays a role in supporting the first conductive layer and the first electrode layer, so that the first conductive layer and the first electrode layer are insulated. The third insulating plate is located between the second conductive layer and the second electrode layer, and plays a role in supporting the second conductive layer and the second electrode layer, so that the second conductive layer and the second electrode layer are insulated.

[0022] 5. Furthermore, the first insulating plate includes a ceramic insulating plate, the first conductive layer includes a copper conductive layer, the second conductive layer includes a copper conductive layer, and the composite connecting plate uses a copper-clad ceramic substrate, which has the characteristics of high thermal conductivity, high electrical insulation, high mechanical strength, and low expansion of ceramics, and also has the high conductivity and excellent welding performance of copper; the first electrode layer includes a molybdenum electrode layer, and the thermal expansion coefficient of molybdenum is similar to that of the power chip, thereby avoiding the mismatch in the thermal expansion coefficients of the power chip and the first electrode layer, which generates a large shear force to cause wear on the power chip, and avoiding failure of the power chip after multiple thermal expansion and contraction. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 An equivalent circuit diagram of a press-fit power chip packaging structure provided by the prior art;

[0025] Figure 2 A schematic diagram of an equivalent circuit of a compression-type power chip packaging structure provided by the present invention;

[0026] Figure 3 A schematic structural diagram of a compression-type power chip packaging structure provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] The inventor of the present application has found through research that as the current level of the IGBT device increases, a larger di / dt will be generated during the switching transient process. In the traditional packaging form, the emitter parasitic inductance is included in both the collector-emitter power circuit and the gate drive circuit, becoming the common emitter stray inductance. Figure 1 As shown, Figure 1 In the figure, "E" represents the emitter of the IGBT device, "C" represents the collector of the IGBT device, "G" represents the gate of the IGBT device, "Lg" represents the stray inductance of the drive circuit, "Le" represents the common emitter stray inductance, and "Lc" represents the collector inductance. The large di / dt of the switching transient will produce a large voltage drop on the common emitter stray inductance, which will have a great impact on the gate drive circuit, not only limiting the switching speed, but also causing more switching losses. In addition, the oscillation in the power circuit will also affect the drive circuit, increasing the probability of gate oscillation.

[0028] In order to avoid the common common emitter stray inductance, an auxiliary emitter connection, i.e. a Kelvin connection, is usually used in power modules, such as Figure 2 As shown, Figure 2In the figure, "E" represents the emitter of the IGBT device, "C" represents the collector of the IGBT device, "G" represents the gate of the IGBT device, "Lg" represents the stray inductance of the drive loop, and "Lc" represents the collector inductance. The Kelvin connection decouples the gate drive loop and the collector-emitter power loop, eliminating the influence of the common emitter stray inductance commonly found on a single chip, thereby increasing the switching speed and reducing the switching loss. The reduction of these losses substantially improves the thermal performance and system efficiency of the device. In addition, increasing the switching speed by using the Kelvin connection is better than reducing the gate resistance, because the latter will increase the gate current and cause additional gate oscillations.

[0029] However, currently, the packaging form that can realize Kelvin connection is only used in welding modules, and the gate of the press-fit IGBT device still adopts the traditional common emitter connection method. Therefore, the present invention provides a press-fit power chip packaging structure that can realize Kelvin connection, so that the switching speed of the press-fit power chip packaging structure is improved and the switching loss is reduced.

[0030] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] An embodiment of the present invention provides a compression-type power chip packaging structure, please refer to Figure 3 ,include:

[0035] A first electrode layer 1 and a second electrode layer 2 arranged opposite to each other;

[0036] A power chip 3 located between the first electrode layer 1 and the second electrode layer 2, wherein a collector (not shown) is disposed on a surface of the power chip 3 facing the first electrode layer 1, and a gate 3a and an emitter 3b are disposed on a surface of the power chip 3 facing the second electrode layer 2, and the emitter 3b is electrically connected to the second electrode layer 2;

[0037] A composite connecting plate 4 located between the first electrode layer 1 and the second electrode layer 2 and on the side of the power chip 3, the composite connecting plate 4 comprising: a first insulating plate 401, a first conductive layer 402 located on one side of the first insulating plate 401, and a second conductive layer 403 located on the surface of the first insulating plate 401 on the side facing away from the first conductive layer 402, the first conductive layer 402 and the second conductive layer 403 being spaced apart from the first electrode layer 1 and the second electrode layer 2, respectively;

[0038] The gate electrode 3 a is electrically connected to the first conductive layer 402 via a first bonding wire 5 ; the emitter electrode 3 b is electrically connected to the second conductive layer 403 via a second bonding wire 6 .

[0039] The power chip 3 includes an insulated gate bipolar transistor (IGBT). Specifically, in one embodiment, the power chip 3 is a high-voltage chip with a voltage level of ≥4500V.

[0040] Please continue to refer to Figure 3 The press-fit power chip packaging structure further includes: a gate terminal 7 , one end of which is connected to the first conductive layer 402 ; and an auxiliary emitter terminal 8 , one end of which is connected to the second conductive layer 403 .

[0041] Please continue to refer to Figure 3 The compression-type power chip packaging structure further includes: an elastic conductive component 9 located between the power chip 3 and the second electrode layer 2, the elastic conductive component 9 electrically connects the emitter 3b and the second electrode layer 2, and the elastic conductive component 9 is separate from the gate 3a. The elastic pressure provided by the elastic conductive component 9 to the power chip 3 is less than the bearing pressure of the power chip 3.

[0042] The elastic conductive component 9 is located between the power chip 3 and the second electrode layer 2. The power chip 3 and the second electrode layer 2 are in elastic contact. The elastic conductive component 9 adjusts the pressure difference between the power chip 3 and the composite connecting plate 4, so that the surface of the power chip 3 is evenly stressed, thereby avoiding damage to the power chip 3 due to hard contact with the first electrode layer 1 and the second electrode layer 2 under the action of external pressure.

[0043] Please continue to refer to Figure 3 The elastic conductive component 9 includes: a conductive pin 901, the conductive pin 901 includes a pin base 901a and a protrusion 901b protruding from the surface of the pin base 901a, and the pin base 901a is located between the protrusion 901b and the emitter 3b and is electrically connected to the emitter 3b.

[0044] Please continue to refer to Figure 3 The elastic conductive component 9 further includes: a conductive guide 902, the conductive guide 902 includes a first guide 902a and a second guide 902b connected to the first guide 902a, the second guide 902b is connected to the second electrode layer 2, and a part of the side wall of the first guide 902a is slidably connected to the side wall of the protrusion 901b. In this embodiment, the conductive guide 902 is made of beryllium bronze.

[0045] Please continue to refer to Figure 3 The elastic conductive component 9 also includes: an elastic member 903, which is sleeved on the outer wall of the first guide member 902a, one end of the elastic member 903 is against the second guide member 902b, and the other end of the elastic member 903 is against the pin base 901a.

[0046] In this embodiment, the elastic member 903 is a butterfly spring. In other embodiments, the elastic member 903 may also be other elastic structures.

[0047] In order to take into account both the good conductivity and low cost of the elastic conductive component 9, the material used for the pin base 901a is usually copper. In order to achieve a good elastic crimping effect, the area of ​​the pin base 901a is relatively large. In order to prevent the pin base 901a from conducting the gate 3a and the emitter 3b and wearing the power chip 3, the elastic conductive component 9 is electrically connected to the emitter 3b through the third conductive layer 11. Specifically, the side of the third conductive layer 11 facing the elastic conductive component 9 is bonded to the pin base 901a through welding or sintering technology, and the side of the third conductive layer 11 facing the emitter 3b is bonded to the emitter 3b through welding or sintering technology. The thermal expansion coefficient of the third conductive layer 11 is greater than the thermal expansion coefficient of the power chip 3 and less than the thermal expansion coefficient of the elastic conductive component 9. The thermal expansion coefficient of the third conductive layer 11 is 4.8×10^ -6 / ℃~5.8×10^ -6 / ℃, for example, 4.8×10^ -6 / ℃、5.0×10^ -6 / ℃、5.2×10^ -6 / ℃、5.4×10^ -6 / ℃、5.6×10^ -6 / ℃ or 5.8×10^ -6 / °C, in this embodiment, the material of the elastic conductive component 9 is molybdenum.

[0048] Even if the power chip 3 generates a lot of heat during operation, causing the volume of the power chip 3 to expand thermally, the thermal expansion coefficient of the third conductive layer 11 is close to that of the power chip 3, thereby avoiding the mismatch in thermal expansion coefficients between the power chip 3 and the elastic conductive component 9, thereby avoiding the wear of the power chip 3 caused by a large shear force, and avoiding the failure of the power chip 3 after multiple thermal expansion and contraction.

[0049] Please continue to refer to Figure 3 The first conductive layer 402 is located between the first insulating plate 401 and the first electrode layer 1 , and the second conductive layer 403 is located between the first insulating plate 401 and the second electrode layer 2 .

[0050] The composite connecting plate 4 further includes a second insulating plate 404 and a third insulating plate 405; the second insulating plate 404 is located between the first conductive layer 402 and the first electrode layer 1, and plays a role in supporting the first conductive layer 402 and the first electrode layer 1, so that the first conductive layer 402 and the first electrode layer 1 are insulated, and the first conductive layer 402 is also in contact with the surface of the second insulating plate 404 on the side facing away from the first electrode layer 1; the third insulating plate 405 is located between the second conductive layer 403 and the second electrode layer 2, and plays a role in supporting the second conductive layer 403 and the second electrode layer 2, so that the second conductive layer 403 and the second electrode layer 2 are insulated. The second conductive layer 403 is also in contact with the surface of the third insulating plate 405 on the side facing away from the second electrode layer 2.

[0051] The surface area of ​​the second insulating plate 404 facing away from the first electrode layer 1 is larger than the surface area of ​​the first insulating plate 401 facing the first electrode layer 1, the portion of the first conductive layer 402 in contact with the second insulating plate 404 is located outside the first insulating plate 401, and the first bonding wire 5 is in contact with the first conductive layer 402 located outside the first insulating plate 401 and on the surface of the second insulating plate 404.

[0052] The surface area of ​​the first insulating plate 401 facing the second electrode layer 2 is larger than the surface area of ​​the third insulating plate 405 facing away from the second conductive layer 403. The portion of the second conductive layer 403 in contact with the first insulating plate 401 is located outside the third insulating plate 405. The second bonding wire 6 is in contact with the second conductive layer 403 located outside the third insulating plate 405 and on the surface of the first insulating plate 401.

[0053] Please continue to refer to Figure 3 The press-fit power chip packaging structure further includes: a tube shell 10, the tube shell 10 is located between the first electrode layer 1 and the second electrode layer 2, one end of the tube shell 10 is fixedly connected to the first electrode layer 1, and the other end of the tube shell 10 is detachably arranged from the second electrode layer 2. In this embodiment, the tube shell 10 is a SMC composite material (Sheet molding compound), and in other embodiments, the tube shell 10 is a ceramic tube shell.

[0054] One end of the gate terminal 7 away from the first conductive layer 402 is led out from the tube shell 10 .

[0055] One end of the auxiliary emitter terminal 8 away from the second conductive layer 403 is led out from the tube shell 10 .

[0056] Please continue to refer to Figure 3The compression-type power chip packaging structure further includes: an insulating silicone gel 12 , wherein the insulating silicone gel 12 covers the power chip 3 , the first bonding wire 5 , the second bonding wire 6 , part of the gate terminal 7 and part of the auxiliary emitter terminal 8 .

[0057] The insulating silicone gel 12 insulates and protects the power chip 3 and space the first bonding wire 5 , the second bonding wire 6 , the gate terminal 7 and the auxiliary emitter terminal 8 from each other to avoid short circuit abnormality caused by mutual contact.

[0058] Please continue to refer to Figure 3 The second insulating plate 404 is fixedly connected to the first electrode layer 1 through a first welding layer 406 ; the third insulating plate 405 is fixedly connected to the second electrode layer 2 through a second welding layer 407 .

[0059] The first solder layer 406 includes a copper solder layer, and the second solder layer 407 includes a copper solder layer.

[0060] The first insulating plate 401 includes a ceramic insulating plate, the second insulating plate 404 includes a ceramic insulating plate, the third insulating plate 405 includes a ceramic insulating plate, the first conductive layer 402 includes a copper conductive layer, the second conductive layer 403 includes a copper conductive layer, and the composite connecting plate 4 uses a copper-clad ceramic substrate, which has the characteristics of high thermal conductivity, high electrical insulation, high mechanical strength, and low expansion of ceramics, and also has the high conductivity and excellent welding performance of copper.

[0061] The first electrode layer 1 includes a molybdenum electrode layer, and the thermal expansion coefficient of molybdenum is similar to that of the power chip 3, thereby avoiding the mismatch in thermal expansion coefficients between the power chip 3 and the first electrode layer 1, which may cause a large shear force to wear the power chip 3, and avoiding failure of the power chip 3 after multiple thermal expansion and contraction.

[0062] In the compression-type power chip packaging structure provided in this embodiment, the gate 3a is electrically connected to the first conductive layer 402 through the first bonding wire 5, the emitter 3b is electrically connected to the second conductive layer 403 through the second bonding wire 6, the first conductive layer 402 is spaced apart from the first electrode layer 1 and the second electrode layer 2, and the second conductive layer 403 is spaced apart from the first electrode layer 1 and the second electrode layer 2. The gate drive circuit formed by the first conductive layer 402, the first bonding wire 5, the gate 3a, the emitter 3b, the second bonding wire 6 and the second conductive layer 403 and the collector-emitter power circuit formed by the first electrode layer 1, the collector, the emitter 3b and the second electrode layer 403 form a parallel structure. The gate drive circuit, as an auxiliary circuit connecting the emitter 3b and the gate 3a, realizes a Kelvin connection, decouples the gate drive circuit and the collector-emitter power circuit, eliminates the influence of the common-emitter stray inductance on the power chip, thereby improving the switching speed of the power chip, reducing the switching loss of the power chip, and further improving the thermal performance and system efficiency of the compression-type power chip packaging structure.

[0063] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A compression-type power chip packaging structure, characterized in that: include: A first electrode layer and a second electrode layer arranged opposite to each other; A power chip located between the first electrode layer and the second electrode layer, wherein a collector is disposed on a surface of the power chip facing the first electrode layer, and a gate and an emitter are disposed on a surface of the power chip facing the second electrode layer, and the emitter is electrically connected to the second electrode layer; a composite connecting plate located between the first electrode layer and the second electrode layer and located on the side of the power chip, the composite connecting plate comprising: a first insulating plate, a first conductive layer located on one side of the first insulating plate, and a second conductive layer located on a surface of the first insulating plate facing away from the first conductive layer, wherein the first conductive layer and the second conductive layer are spaced apart from the first electrode layer and the second electrode layer respectively; The gate is electrically connected to the first conductive layer through a first bonding wire; the emitter is electrically connected to the second conductive layer through a second bonding wire; An elastic conductive component is located between the power chip and the second electrode layer, the power chip and the second electrode layer are in elastic contact, the elastic conductive component adjusts the pressure difference between the power chip and the composite connecting plate, so that the surface of the power chip is subjected to uniform force, the elastic conductive component electrically connects the emitter and the second electrode layer, and the elastic conductive component is separate from the gate; The elastic conductive component includes a conductive pin, a conductive guide and an elastic member, the conductive pin includes a pin base and a protrusion protruding from the surface of the pin base, the pin base is located between the protrusion and the emitter and is electrically connected to the emitter; the conductive guide includes a first guide and a second guide connected to the first guide, the second guide is connected to the second electrode layer, and part of the side wall of the first guide is slidably connected to the side wall of the protrusion; the elastic member is sleeved on the outer wall of the first guide, one end of the elastic member is abutted against the second guide, and the other end of the elastic member is abutted against the pin base.

2. The compression-type power chip packaging structure according to claim 1, characterized in that: Also includes: a gate terminal, one end of which is connected to the first conductive layer; An auxiliary emitter terminal, one end of which is connected to the second conductive layer.

3. The compression-type power chip packaging structure according to claim 1, characterized in that: The elastic conductive component is electrically connected to the emitter through a third conductive layer, and the thermal expansion coefficient of the third conductive layer is greater than the thermal expansion coefficient of the power chip and less than the thermal expansion coefficient of the elastic conductive component.

4. The compression-type power chip packaging structure according to claim 1, characterized in that: The first conductive layer is located between the first insulating plate and the first electrode layer, and the second conductive layer is located between the first insulating plate and the second electrode layer; The composite connecting plate further comprises a second insulating plate and a third insulating plate; the second insulating plate is located between the first conductive layer and the first electrode layer, and the first conductive layer is also in contact with a surface of the second insulating plate on a side facing away from the first electrode layer; The third insulating plate is located between the second conductive layer and the second electrode layer, and the second conductive layer is also in contact with a surface of the third insulating plate facing away from the second electrode layer.

5. The compression-type power chip packaging structure according to claim 4, characterized in that: The surface area of ​​the second insulating plate facing away from the first electrode layer is larger than the surface area of ​​the first insulating plate facing the first electrode layer, the portion of the first conductive layer in contact with the second insulating plate is located outside the first insulating plate, and the first bonding wire is in contact with the first conductive layer located outside the first insulating plate and on the surface of the second insulating plate; The surface area of ​​the first insulating plate facing the second electrode layer is larger than the surface area of ​​the third insulating plate facing away from the second conductive layer. The portion of the second conductive layer in contact with the first insulating plate is located outside the third insulating plate. The second bonding wire is in contact with the second conductive layer located outside the third insulating plate and on the surface of the first insulating plate.

6. The compression-type power chip packaging structure according to claim 4, characterized in that: The second insulating plate is fixedly connected to the first electrode layer via a first welding layer; and the third insulating plate is fixedly connected to the second electrode layer via a second welding layer.

7. The compression-type power chip packaging structure according to claim 2, characterized in that: Also includes: a tube shell, wherein the tube shell is located between the first electrode layer and the second electrode layer, one end of the tube shell is fixedly connected to the first electrode layer, and the other end of the tube shell is detachably arranged from the second electrode layer; One end of the gate terminal away from the first conductive layer is led out from the tube shell; One end of the auxiliary emitter terminal away from the second conductive layer is led out from the tube shell.

8. The compression-type power chip packaging structure according to claim 1, characterized in that: The first insulating plate includes a ceramic insulating plate, the first conductive layer includes a copper conductive layer, the second conductive layer includes a copper conductive layer, and the first electrode layer includes a molybdenum electrode layer.

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