A method for optimizing the structure of reference sources based on multi-population hierarchical assisted evolution

Abstract

The present invention provides a reference source structure optimization method based on multi-population hierarchical assisted evolution, including S1, dividing the module to be evolved and the fixed function module in the circuit structure, and generating the topological structure of the module to be evolved by using the improved tracking coding method; S2, optimizing the topological structure of the circuit of the module to be evolved by using multi-population hierarchical assisted evolution to obtain the optimal topological structure of the module to be evolved; S3, taking the optimal topological structure of the module to be evolved as the optimal individual, transmitting its parameter information to the fixed function module, and using multi-population hierarchical assistance from local optimization to global optimization to obtain the optimal circuit topological structure. The circuit performance parameters generated by the present invention can reach the level of artificially designed analog integrated circuits. The present invention has the advantages of high time efficiency, strong integrated integrity, automatic design of circuit structure, screening and optimization of circuits, and excellent final circuit performance indicators.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuits, and in particular to a reference source structure optimization method based on multi-population hierarchical assisted evolution. Background Art

[0002] Analog integrated circuits play an indispensable role in circuit system design. Most electronic devices require analog circuits. In the process of analog integrated circuit design, it is necessary to weigh many performance indicators and find a balance between multiple potentially conflicting goals. Circuit simulation is required to continuously simulate, tune and improve. Even for experienced designers, designing analog circuits is still a time-consuming and arduous task. The contradiction between the large demand for analog integrated circuit design and the long cycle of manual design has led to the emergence of automated design of analog integrated circuits.

[0003] However, the current traditional analog integrated circuit automated design software, such as the analog design environment (ADE) GXL provided by Cadence and WiCkeD provided by MunEDA, has the following problems: the performance constraints of analog circuits are complex and difficult to solve; ignoring constraints during circuit parameter optimization will lead to slow optimization speed, overfitting or underfitting, and optimization failure. Summary of the invention

[0004] In view of the above problems, the object of the present invention is to provide a reference source structure optimization method based on multi-population hierarchical assisted evolution, comprising:

[0005] S1, dividing the module to be evolved and the fixed function module in the circuit structure, and using the improved tracking coding method to generate the topological structure of the module to be evolved;

[0006] S2, using multi-population hierarchical assisted evolution to optimize the topological structure of the circuit of the module to be evolved, and obtain the optimal topological structure of the module to be evolved;

[0007] S3, taking the optimal topology of the module to be evolved as the optimal individual, transferring its parameter information to the fixed function module, and using multi-population hierarchical assistance from local optimization to global optimization to obtain the optimal circuit topology.

[0008] Preferably, the method of generating the topological structure of the module to be evolved by adopting an improved tracking coding method includes:

[0009] S11, starting from the starting node, the circuit components are initialized in sequence according to a preset instruction set, and the initial state generates a valid circuit topology structure code according to the instruction set;

[0010] S12, initializing the circuit topology structure model, fixing the circuit structure module, and generating the circuit module to be evolved.

[0011] Preferably, the method of optimizing the topological structure of the circuit of the module to be evolved by using multi-population hierarchical assisted evolution to obtain the optimal topological structure of the module to be evolved includes:

[0012] S21, initialize each topological structure into multiple populations. Multiple populations are specific topological structures of each part. Populations are divided into multiple layers, and sub-populations are connected in the form of trees. The schematic diagram of layered multiple populations is shown in the figure. Figure 4 shown.

[0013] S22, divides the multi-level structure of sub-populations into three levels, namely the top level, the middle level and the bottom level; the specific hierarchical structure of sub-populations and the information transmission method are as follows Figure 5 shown.

[0014] S23, initializing the bottom population, creating the population number in a random manner, and the bottom sub-population transmits information and shares excellent individuals; that is, the bottom population migration; the excellent individuals represent the wlm parameter information of the MOS tube under the excellent structure;

[0015] S24, after the bottom sub-population evolves for a specified number of generations, the fitness is calculated, which is the weighted weight of the performance index, and the sub-population transmits the optimal parameter information with the maximum fitness to the sub-population of the parent node;

[0016] S25, after the evolution of every two bottom-level sub-populations is completed, the chromosomes of the last generation of individuals are merged into the middle-level sub-population;

[0017] S26, the sub-population in the middle layer uses the merged chromosome set as the initial population and starts the evolution of the sub-population in this layer;

[0018] S27, the sub-populations in the middle layer migrate individuals from the sub-populations in the same layer and merge with the sub-populations in the next layer above;

[0019] S28, and so on, the evolution ends at the only sub-population in the top layer, and the optimal topological structure of the circuit model to be evolved is obtained.

[0020] The present invention provides a reference source structure optimization method based on multi-population hierarchical assisted evolution. By dividing the specific structure and the structure to be evolved, taking the inherent circuit logic as the constraint condition, expanding the command set, and using multi-population hierarchical assisted evolution to automatically design a circuit topology structure that meets the performance requirements, and then using the algorithm ideas of proximal strategy optimization and OOR function, multi-objective optimization is achieved according to the circuit constraint conditions. The final automatically designed analog integrated circuit topology structure enables the circuit performance parameters generated by it to reach the analog integrated circuit of the manual design level. The present invention has the advantages of high time efficiency, strong integrated integrity, automatic design of circuit structure, screening and optimization of circuits, and superior final circuit performance indicators. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention is further described using the accompanying drawings, but the embodiments in the accompanying drawings do not constitute any limitation to the present invention. A person skilled in the art can obtain other drawings based on the following drawings without creative work.

[0022] Figure 1 , which is a diagram of an exemplary embodiment of a reference source structure optimization method based on multi-population hierarchical assisted evolution of the present invention.

[0023] Figure 2 , which is a diagram of an exemplary embodiment of the full MOS voltage reference source circuit model of the present invention.

[0024] Figure 3 , which is an exemplary embodiment diagram of the tracking coding of the full MOS reference source circuit of the present invention.

[0025] Figure 4 , which is a schematic diagram of the stratified multi-population of the present invention.

[0026] Figure 5 , which is a diagram of an exemplary embodiment of information transmission between sub-populations of the present invention.

[0027] Figure 6 , which is a diagram of an exemplary embodiment of the cache memory model of the present invention. DETAILED DESCRIPTION

[0028] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0029] like Figure 1 In one embodiment shown, the present invention provides a reference source structure optimization method based on multi-population hierarchical assisted evolution, comprising:

[0030] S1, dividing the module to be evolved and the fixed function module in the circuit structure, and using the improved tracking coding method to generate the topological structure of the module to be evolved;

[0031] S2, using multi-population hierarchical assisted evolution to optimize the topological structure of the circuit of the module to be evolved, and obtain the optimal topological structure of the module to be evolved;

[0032] S3, taking the optimal topology of the module to be evolved as the optimal individual, transferring its parameter information to the fixed function module, and using multi-population hierarchical assistance from local optimization to global optimization to obtain the optimal circuit topology.

[0033] In the reference source circuit, the local refers to the current source module, which is the module to be evolved here, and the fixed function module refers to the current mirror circuit module, startup circuit module, load circuit module and amplifier circuit module of the reference source. The global refers to the local and fixed components that constitute the entire reference source circuit.

[0034] After optimizing the topological structure of the optimal module to be evolved, the local optimization is completed. The topological structure of the optimal module to be evolved is used as the optimal individual, and the parameter information is passed to the topological structures of other modules, and finally the global optimization is completed, that is, global optimization. This optimization method is similar to the transmission and merging of information of individuals in a population.

[0035] In S3, the circuit sampling parameters input into the multi-population hierarchical assistance are expanded from the sampling parameters of the local circuit to the sampling parameters of the global circuit.

[0036] Preferably, the method of generating the topological structure of the module to be evolved by adopting an improved tracking coding method includes:

[0037] S11, starting from the starting node, the circuit components are initialized in sequence according to a preset instruction set, and the initial state generates a valid circuit topology structure code according to the instruction set;

[0038] S12, initializing the circuit topology structure model, fixing the circuit structure module, and generating the circuit module to be evolved.

[0039] Specifically, the main method is to expand the encoding method and add connection rules. The process is detailed as follows:

[0040] This paper decomposes the optimization model of the full MOS voltage reference source circuit into several circuit sub-modules, such as Figure 2 As shown, the internal circuit topology of the current mirror circuit module, the startup circuit module, the load circuit module and the amplifier circuit module is fixed, and the internal device parameters of the circuit are also fixed in the preliminary screening stage, while the module to be evolved needs to continuously generate new structures and be continuously optimized by improving the tracking coding and optimization algorithm.

[0041] The circuit topology structure generation method of the circuit module to be evolved is improved tracking coding. The generation of the circuit topology structure starts from the starting node and generates the required circuit by continuously randomly selecting command sets and continuously randomly selecting circuit components.

[0042] For the reference source circuit optimization model, it is necessary to expand the instruction set of the tracking code and connect it to the external fixed module. The instruction set that needs to be expanded is: CAST-TO-AMPLIFIER (CTA), CAST-TO-MIRROR (CTM), CAST-TO-STARTUP (CTSU) and CAST-TO-ACTIVELOAD (CTAL).

[0043] The specific meaning of each instruction is as follows: The CAST-TO-AMPLIFIER (CTA) instruction means to connect the current circuit to the amplifier circuit module. That is, in the existing circuit structure, a new device is added at the global moving point, the input end is the point where the global moving point is located, and the output end is connected to a node of the amplifier circuit module. Because the amplifier circuit module has multiple nodes exposed to the outside, it is necessary to randomly select an exposed node and save the selected exposed node information in the encoding information.

[0044] The three instructions CTM, CTSU and CTAL are the same as the CTA instruction, which respectively indicate connecting the newly added device to the current mirror circuit module, the startup circuit module and the load circuit module, and all require additional information bits to indicate the specific nodes of the connection.

[0045] At the same time, we added additional information segments to the automatically generated topology to determine the connection method of the starting node and the ending node. In the original model of tracking coding, because the circuit module to be evolved only needs to be connected to the input circuit module and the output circuit module, and no other modules are involved, it is only necessary to connect the starting node of the circuit module to be evolved to the input circuit module, and the ending node to the output circuit module. However, in the reference source circuit topology structure optimization model, there are four modules connected to the outside. Therefore, the starting node and the ending node of the circuit part to be evolved need to randomly select two of the four external circuit modules for connection. The selection method is random selection, and the relevant information is encoded as follows: Figure 3 As shown in the figure, if the operation instruction is one of CTA, CTM, CTSU and CTAL, it is necessary to add an information bit at the last bit of the chromosome segment to indicate the node information of the connected external circuit module. After all MOS tubes are encoded, it is necessary to add chromosome segments to indicate the global input and output node information of the entire circuit module to be evolved. The StartEndNode bit of the last chromosome segment only serves as an identifier, indicating that this chromosome segment contains the information of the input and output nodes.

[0046] Preferably, the method of optimizing the topological structure of the circuit of the module to be evolved by using multi-population hierarchical assisted evolution to obtain the optimal topological structure of the module to be evolved includes:

[0047] S21, initialize each topological structure into multiple populations. Multiple populations are specific topological structures of each part. Populations are divided into multiple layers, and sub-populations are connected in the form of trees. The schematic diagram of layered multiple populations is shown in the figure. Figure 4 shown.

[0048] S22, divides the multi-level structure of sub-populations into three levels, namely the top level, the middle level and the bottom level; the specific hierarchical structure of sub-populations and the information transmission method are as follows Figure 5 shown.

[0049] S23, initializing the bottom population, creating the population number in a random manner, and the bottom sub-population transmits information and shares excellent individuals; that is, the bottom population migration; the excellent individuals represent the wlm parameter information of the MOS tube under the excellent structure;

[0050] S24, after the bottom sub-population evolves for a specified number of generations, the fitness is calculated, which is the weighted weight of the performance index, and the sub-population transmits the optimal parameter information with the maximum fitness to the sub-population of the parent node;

[0051] S25, after the evolution of every two bottom-level sub-populations is completed, the chromosomes of the last generation of individuals are merged into the middle-level sub-population;

[0052] S26, the sub-population in the middle layer uses the merged chromosome set as the initial population and starts the evolution of the sub-population in this layer;

[0053] S27, the sub-populations in the middle layer migrate individuals from the sub-populations in the same layer and merge with the sub-populations in the next layer above;

[0054] S28, and so on, the evolution ends at the only sub-population in the top layer, and the optimal topological structure of the circuit model to be evolved is obtained.

[0055] Using multi-population hierarchical assisted evolution to generate the optimal topology structure can avoid the two problems of being too sensitive to the initial population and being prone to premature maturity in the optimization process. Preferably, the multi-population hierarchical assisted evolution is used to optimize the topology structure of the module to be evolved and the fixed function module to obtain the optimal circuit topology structure, specifically, the topology structure of the module to be evolved and the fixed function module are input into the multi-population hierarchical assisted evolution algorithm together to obtain the final optimal circuit topology structure.

[0056] In the optimization process of S24, we used the OOR function to guide our optimization process. The OOR function can better guide the directional improvement of infeasible solutions from the infeasible domain to the feasible domain, rather than simply ignoring the reorganization solution set. The OOR function returns 0 or a positive value and is defined as follows:

[0057]

[0058] Among them, u i (x) represents the OOR function, x refers to a solution. If it satisfies the constraints of the problem, it is called a feasible solution, otherwise it is called an infeasible solution. i (x) represents the objective function;

[0059] N punish The OOR function first compresses the degree of constraint violation to between 0 and 1, and then multiplies it by the penalty factor to calculate the actual degree of constraint violation. When the solution satisfies the constraint, the OOR function is zero. When the solution does not meet the constraint, the OOR function is greater than zero. The greater the degree of constraint violation, the greater its value, and it rises to N. punish until.

[0060] In the optimization process, in order to reduce the time of calling hspice to calculate the fitness, the cache mechanism is used to query and add the topology structure. The specific steps are as follows:

[0061] Step 5.1, use the hash table data structure to perform query operations and access data based on a pair of key-value pairs;

[0062] Step 5.2, adopt the cache mechanism array and linked list combined storage topology structure, the storage process is to calculate the array index through the hash algorithm;

[0063] Step 5.3: If there is a hash conflict, store it in the array in the form of a linked list;

[0064] Step 5.4: Each element in the final hash table is a key-value pair. The key-value pair is the circuit structure information, and the value is the fitness value of the circuit structure. The final cached memory model is as follows: Figure 6 shown.

[0065] Each time hspice is called to test the circuit performance after optimization, the above cache mechanism will be used. The cache mechanism can also be used in S12 to add extended instructions.

[0066] The present invention provides a reference source structure optimization method based on multi-population hierarchical assisted evolution. By dividing the specific structure and the structure to be evolved, taking the inherent circuit logic as the constraint condition, expanding the command set, and using multi-population hierarchical assisted evolution to automatically design a circuit topology structure that meets the performance requirements, and then using the algorithm ideas of proximal strategy optimization and OOR function, multi-objective optimization is achieved according to the circuit constraint conditions. The final automatically designed analog integrated circuit topology structure enables the circuit performance parameters generated by it to reach the analog integrated circuit of the manual design level. The present invention has the advantages of high time efficiency, strong integrated integrity, automatic design of circuit structure, screening and optimization of circuits, and superior final circuit performance indicators.

[0067] Although embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0068] It should be noted that the functional units / modules in various embodiments of the present invention may be integrated into one processing unit / module.

[0069] In the block, each unit / module may exist physically separately, or two or more units / modules may be integrated into one unit / module. The above integrated unit / module may be implemented in the form of hardware or in the form of software functional unit / module.

[0070] Through the description of the above implementation modes, it should be understood that the embodiments described herein can be implemented by hardware, software, firmware, middleware, code or any appropriate combination thereof. For hardware implementation, the processor can be implemented in one or more of the following units: an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a processor, a controller, a microcontroller, a microprocessor, other electronic units designed to implement the functions described herein or a combination thereof. For software implementation, part or all of the processes of the embodiments can be completed by instructing the relevant hardware through a computer program.

[0071] When implemented, the above program can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication medium includes any medium that is convenient for transmitting a computer program from one place to another. The storage medium can be any available medium that can be accessed by a computer. Computer-readable media can include, but are not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer.

Claims

1. A reference source structure optimization method based on multi-population hierarchical assisted evolution, characterized in that: include: S1, dividing the module to be evolved and the fixed function module in the circuit structure, and using the improved tracking coding method to generate the topological structure of the module to be evolved; S2, using multi-population hierarchical assisted evolution to optimize the topological structure of the module circuit to be evolved, and obtain the optimal topological structure of the module to be evolved; S3, taking the optimal topology of the module to be evolved as the optimal individual, transferring its parameter information to the fixed function module, and using multi-population hierarchical assistance to search from local optimization to global optimization to obtain the optimal circuit topology; The module to be evolved is a current source module; the fixed function module refers to a current mirror circuit module, a startup circuit module, a load circuit module and an amplifier circuit module of a reference source; After optimizing the topological structure of the optimal module to be evolved, the local optimization is completed. The topological structure of the optimal module to be evolved is used as the optimal individual, and the parameter information is passed to the topological structures of other modules to complete the global optimization. The method of using improved tracking coding to generate the topological structure of the module to be evolved includes: S11, starting from the starting node, the circuit components are initialized in sequence according to a preset instruction set, and the initial state generates a valid circuit topology structure code according to the instruction set; S12, initializing the circuit topology structure model, fixing the circuit structure module, and generating the circuit module to be evolved; The method of optimizing the topological structure of the circuit of the module to be evolved by using multiple populations and hierarchical assisted evolution to obtain the optimal topological structure of the module to be evolved includes: S21, initialize each topological structure into multiple populations, where multiple populations are specific topological structures of each part, and the populations are divided into multiple layers, and the sub-populations are connected in the form of a tree; S22, divides the multi-level structure of subpopulations into three levels, namely top level, middle level and bottom level; S23, initializing the bottom population, creating the population number in a random manner, and the bottom sub-population transmits information and shares excellent individuals; that is, the bottom population migration; the excellent individuals represent the wlm parameter information of the MOS tube under the excellent structure; S24, after the bottom sub-population evolves for a specified number of generations, the fitness is calculated, which is the weighted weight of the performance index, and the sub-population transmits the optimal parameter information with the maximum fitness to the sub-population of the parent node; S25, after the evolution of every two bottom-level sub-populations is completed, the chromosomes of the last generation of individuals are merged into the middle-level sub-population; S26, the sub-population in the middle layer uses the merged chromosome set as the initial population and starts the evolution of the sub-population in this layer; S27, the sub-populations in the middle layer migrate individuals from the sub-populations in the same layer and merge with the sub-populations in the next layer above; S28, and so on, the evolution ends at the only sub-population in the top layer, and the optimal topological structure of the circuit model to be evolved is obtained.

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