A single photon detector chip

Abstract

The present invention relates to a single-photon detector chip, which is used to cooperate with a multi-pulse laser to realize the detection of a single photon. The single-photon detector chip includes a single-photon detection unit array composed of a plurality of single-photon detection units and a bias module. The single-photon detection unit array and the bias module are integrated in a single chip. The bias module is connected to the single-photon detection unit array. The single-photon detection unit is provided with a primary screening circuit and a secondary screening circuit. The input end of the secondary screening circuit is connected to the output end of the primary screening circuit. The multi-pulse laser emits a multi-pulse laser pulse train. The primary screening circuit performs a primary comparison screening on the pulses received by multiple devices. The secondary screening circuit uses a delay circuit to perform multi-channel delay on the pulses output by the primary screening circuit, and performs a secondary comparison screening on the multi-channel delayed pulses to extract effective pulses. Compared with the prior art, the present invention has the advantages of high-performance detection capability, low output power consumption, and high working frame rate.

Description

Technical Field

[0001] The present invention relates to the field of light detection technology, and in particular to a single-photon detector chip. Background Art

[0002] A single-photon detector can detect a single photon. By measuring the time difference between the laser emission pulse and the detector receiving pulse, the distance of the target can be obtained. Single-photon detector chips usually contain single-photon pixel arrays, etc., which can directly obtain a three-dimensional image of the target. The single-photon pixel mainly consists of a single-photon detection device, a quenching circuit, and a time-to-digital conversion module. After the laser emits a laser pulse, the single-photon device works in Geiger mode. When the photon reflected by the target is received, the device is triggered to enter Geiger avalanche. After the quenching circuit senses the transient avalanche current output by the device, it quickly adjusts the bias voltage of the single-photon device to allow the single-photon device to exit the avalanche state. At the same time, the quenching circuit outputs a pulse, indicating that an avalanche has occurred in the single-photon device. At the same time as the laser emits the laser, the time-to-digital conversion module starts working. When the pulse of the quenching circuit enters the time-to-digital conversion module, the time-to-digital conversion module stops timing, and the recorded data is the round-trip time information of the photon. The single-photon detector chip outputs the time data stored in each pixel in the pixel array serially to the outside of the chip through the row selection circuit and the column selection circuit.

[0003] In actual scenarios, the single-photon detector chip receives not only the signal pulse emitted by the laser, but also a large number of background light interference pulses or noise pulses. In harsh environments, it may take 100 or even more detections to receive one signal pulse. Under such an extremely low signal-to-noise ratio, the direct imaging quality of the data is extremely poor. Usually, the data of the single-photon detector chip is repeatedly sampled hundreds, thousands or even more times, and the data of each pixel is statistically distributed. Background light interference pulses or noise pulses are generated randomly and irregularly, while signal pulses are generated at fixed times. Therefore, after the trigger pulses are counted along the time dimension, the signal pulses will gather at a certain moment to form a signal peak, while the interference pulses will be randomly distributed throughout the detection time interval, based on which the signal pulses can be extracted.

[0004] The collection and statistical analysis of a large number of samples will bring great challenges to the hardware design of LiDAR. Taking a 320×256 single-photon detector array as an example, if a frame rate of 30 frames / second is to be achieved, the time data accuracy is 12 bits, and a valid sample is extracted after 1000 samplings, then the data rate is as high as 320×256×30×12×1000=29.5Gb / s, which will require extremely high transmission rates and the number of transmission interfaces, and consume a lot of transmission power. In order to reduce the pressure of data transmission, one solution is to design a memory in the chip, temporarily store the collected sample data in the chip, directly perform statistical analysis on the data of each pixel in the chip, and output it after finding the time data of the signal. This can reduce the output data rate by 1000 times to 29.5Mb / s. Although this solution reduces the pressure of data transmission, it greatly increases the on-chip storage space. Even if it is stored according to 100 samplings, 368MB of space is required, which cannot be achieved in chip design. Therefore, this solution is still only suitable for small arrays and low-speed occasions. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a single-photon detector chip with high-performance detection capability, low output power consumption and high working frame rate.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A single-photon detector chip is used to cooperate with a multi-pulse laser to realize the detection of a single photon. The single-photon detector chip includes a single-photon detection unit array composed of a plurality of single-photon detection units and a bias module; the single-photon detection unit array and the bias module are integrated in a single chip; the bias module is connected to the single-photon detection unit array; the single-photon detection unit is provided with a primary screening circuit and a secondary screening circuit; the input end of the secondary screening circuit is connected to the output end of the primary screening circuit; the multi-pulse laser emits a multi-pulse laser pulse train, the primary screening circuit performs a primary comparison screening on the pulses received by multiple devices, the secondary screening circuit uses a delay circuit to perform multi-channel delay on the pulses output by the primary screening circuit, and performs a secondary comparison screening on the multi-channel delayed pulses to extract valid pulses.

[0008] Preferably, the single-photon detection unit also includes a single-photon detection device, a quenching circuit, a time-to-digital conversion module and a three-state gate; one end of the single-photon detection device is connected to the bias module, and the other end is connected to the input end of the quenching circuit; the output end of the quenching circuit is connected to the primary screening circuit; the output end of the secondary screening circuit is connected to the input end of the time-to-digital conversion module; the output end of the time-to-digital conversion module is connected to the three-state gate.

[0009] More preferably, the number of the single-photon detection devices and quenching circuits is several, each single-photon detection device is connected to a quenching circuit, and each quenching circuit is connected to a screening circuit to form a multi-device pulse.

[0010] More preferably, the single photon detection device is a single photon avalanche diode SPAD.

[0011] More preferably, the primary screening circuit includes a first comparator and a first time window circuit; the output end of the quenching circuit is respectively connected to the positive input end of the first comparator and the input end of the first time window circuit; the output end of the first time window circuit is connected to the enable switch control end of the first comparator; the negative input end of the first comparator inputs a preset primary screening threshold; and the output end of the first comparator is connected to the secondary screening circuit.

[0012] More preferably, the secondary screening circuit includes a pulse delay module, a second comparator and a second time window circuit; the output end of the primary screening circuit is respectively connected to the input end of the second time window circuit, the positive input end of the second comparator and the input end of the pulse delay module; the output end of the pulse delay module is respectively connected to the positive input end of the second comparator and the input end of the pulse delay module; the output end of the second time window circuit is connected to the enable switch control end of the second comparator; the negative input end of the second comparator inputs a preset secondary screening threshold; the output end of the second comparator is connected to the input end of the time digital conversion module.

[0013] More preferably, the number of the pulse delay modules is several, the output end of the primary screening circuit is respectively connected to the input ends of several pulse delay modules, the output ends of several pulse delay modules are respectively connected to the input end of the second time window circuit and the positive input end of the second comparator, to form multi-channel delayed pulses.

[0014] More preferably, the delays between the subsequent pulses and the first pulse in the multi-pulse pulse train emitted by the multi-pulse laser are T1, T2, T3, ..., T n , where n is the number of pulse trains; the delay times of the pulse delay modules are T1, T2, T3, ..., T m , where m is the number of pulse delay modules.

[0015] More preferably, the single-photon detector chip is provided with a data output module, which is integrated in the single chip; the data output module is connected to the single-photon detection unit array.

[0016] More preferably, the data output module includes a row selection module, a parallel input serial output module PISO and a column selection module; the enable end of the three-state gate of each single-photon detection unit in the single-photon detection unit array is respectively connected to the output end of the row selection module, and the output end of the three-state gate is respectively connected to the input end of the parallel input serial output module PISO; one end of the column selection module is connected to the parallel input serial output module PISO, and the other end is connected to the data output bus.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The single-photon detector chip in the present invention uses the spatial correlation of the signal laser to analyze and compare the output pulses of multiple single-photon detection devices in the unit, eliminate irrelevant interference pulses, and then use the time correlation between the multiple pulses emitted by the laser to generate multi-path delays for the aforementioned pulses using a delay circuit, analyze and compare the multi-path delay circuits, and further suppress irrelevant interference pulses. Therefore, compared with the traditional full-output solution, the storage, transmission and processing of a large amount of invalid data are reduced, thereby greatly improving the working frame rate, reducing output power consumption, and avoiding massive on-chip storage space. Functions such as photoelectric detection, trigger pulse generation, spatial consistency detection, and delay consistency detection are realized in the single-photon detection unit, and interference pulses and noise pulses are directly suppressed in the unit. The chip has high-performance detection capabilities in harsh environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the overall structure of the single-photon detector chip in the present invention;

[0020] Figure 2 Schematic diagram of the structure of the single photon detection unit in the present invention;

[0021] Figure 3 It is a structural schematic diagram of a primary screening circuit in the present invention;

[0022] Figure 4 It is a structural schematic diagram of the secondary screening circuit in the present invention;

[0023] Figure 5 It is a structural diagram of the data output module in the present invention;

[0024] Figure 6 This is a comparison diagram of output pulses of a primary screening circuit in an embodiment of the present invention;

[0025] Figure 7 1 is a comparison diagram of output pulses of the secondary screening circuit in an embodiment of the present invention.

[0026] The numbers in the figure show:

[0027] 1. Single photon detection unit, 2. Bias module, 3. Multi-pulse laser, 4. Data output module, 101. Single photon detection device, 102. Quenching circuit, 103. Time digital conversion module, 104. Tri-state gate, 105. First comparator, 106. First time window circuit, 107. Pulse delay module, 108. Second comparator, 109. Second time window circuit, 401. Row selection module, 402. Parallel input serial output module PISO, 403. Column selection module. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] The purpose of the present invention is to provide a single-photon detector chip for extracting effective signal pulses within a unit. First, single-photon devices and quenching circuits are used to continuously detect and receive signal photon pulses and interference pulses, and a time window circuit is designed. The number of trigger pulses of multiple single-photon devices in the unit is counted within a narrow time window, and the pulse is output after the comparator determines that it is greater than a certain threshold. The chip cooperates with the laser emission scheme of multiple pulse trains. The above-mentioned output pulses pass through a multi-channel delay module, and the delay time is equal to the time between multiple pulse trains. Then, the number of pulses generated by the delay module is counted and recorded in a narrow time window. After the comparator determines that it is greater than a certain threshold, the pulse is output. The time of the pulse is recorded by the time-to-digital conversion module and temporarily stored in the pixel, and then output to the outside of the chip through the row selection and column selection circuits. The present invention makes full use of the spatial correlation of signal pulses and the temporal correlation between pulses in a pulse train. The signal pulse can be successfully extracted within the unit through multi-device pulse comparison and multi-channel delayed pulse comparison.

[0030] Specific plans such as Figure 1As shown, a single-photon detector chip cooperates with a multi-pulse laser 3 to realize the detection of a single photon, wherein the single-photon detector chip includes a single-photon detection unit array composed of a plurality of single-photon detection units 1 and a bias module 2, the single-photon detection unit array and the bias module 2 are integrated in a single chip, the bias module 2 is connected to the single-photon detection unit array, the single-photon detection unit 1 is provided with a primary screening circuit and a secondary screening circuit, the input end of the secondary screening circuit is connected to the output end of the primary screening circuit, the multi-pulse laser 3 emits a pulse train of multiple pulses, the primary screening circuit performs a primary comparison screening on the pulses received by multiple devices, the secondary screening circuit uses a delay circuit to perform multi-channel delay on the pulses output by the primary screening circuit, and performs secondary comparison screening on the multi-channel delayed pulses to extract valid pulses.

[0031] The structure of the single photon detection unit 1 is as follows: Figure 2 As shown, it also includes a single-photon detection device 101, a quenching circuit 102, a time-to-digital conversion module 103 and a three-state gate 104. One end of the single-photon detection device 101 is connected to the bias module 2, and the other end is connected to the input end of the quenching circuit 102. The output end of the quenching circuit 102 is connected to the primary screening circuit, the output end of the secondary screening circuit is connected to the input end of the time-to-digital conversion module 103, and the output end of the time-to-digital conversion module 103 is connected to the three-state gate 104.

[0032] There are several single-photon detection devices 101 and quenching circuits 102 . Each single-photon detection device 101 is connected to a quenching circuit 102 . Each quenching circuit 102 is connected to a screening circuit to form a multi-device pulse.

[0033] The single photon detection device 101 in this embodiment is a single photon avalanche diode SPAD.

[0034] The structure of a screening circuit is as follows: Figure 3 As shown, it includes a first comparator 105 and a first time window circuit 106, the output end of the quenching circuit 102 is respectively connected to the positive input end of the first comparator 105 and the input end of the first time window circuit 106, the output end of the first time window circuit 106 is connected to the enable switch control end of the first comparator 105, the negative input end of the first comparator 105 inputs a preset primary screening threshold, and the output end of the first comparator 105 is connected to the secondary screening circuit.

[0035] The structure of the secondary screening circuit is as follows Figure 4As shown, it includes a pulse delay module 107, a second comparator 108 and a second time window circuit 109. The output end of the primary screening circuit is respectively connected to the input end of the second time window circuit 109, the positive input end of the second comparator 108 and the input end of the pulse delay module 107. The output end of the pulse delay module 107 is respectively connected to the positive input end of the second comparator 108 and the input end of the pulse delay module 107. The output end of the second time window circuit 109 is connected to the enable switch control end of the second comparator 108. The negative input end of the second comparator 108 inputs a preset secondary screening threshold value. The output end of the second comparator 108 is connected to the input end of the time digital conversion module 103.

[0036] There are several pulse delay modules 107, and the output end of the primary screening circuit is connected to the input end of several pulse delay modules 107 respectively. The output ends of several pulse delay modules 107 are connected to the input end of the second time window circuit 109 and the positive input end of the second comparator 108 respectively, forming a multi-channel delayed pulse.

[0037] The delays between the subsequent pulses and the first pulse in the multi-pulse pulse train emitted by the multi-pulse laser 3 are T1, T2, T3, ..., T n , where n is the number of pulse trains, and the delay times of the pulse delay module 107 are T1, T2, T3, ..., T m , where m is the number of pulse delay modules 107 .

[0038] The single photon detector chip is provided with a data output module 4, such as Figure 5 As shown, the module is integrated in a single chip, and the data output module 4 is connected to the single photon detection unit array. The data output module 4 includes a row selection module 401, a parallel input serial output module PISO402 and a column selection module 403. The enable end of the tri-state gate 104 of each single photon detection unit in the single photon detection unit array is respectively connected to the output end of the row selection module 401, and the output end of the tri-state gate 104 is respectively connected to the input end of the parallel input serial output module PISO402. One end of the column selection module 403 is connected to the parallel input serial output module PISO402, and the other end is connected to the data output bus.

[0039] The working principle of each module is described in detail below:

[0040] 1. Primary screening circuit

[0041] In this embodiment, the number of single-photon detection devices and quenching circuits is four. One end of the four single-photon detection devices is connected to the bias high voltage, and the other end is connected to the input end of the four quenching circuits. The output ends of the four quenching circuits are all connected to the positive input end of the first comparator, and are also connected to the input end of the first time window circuit. The output end of the first time window circuit is connected to the control end of the first comparator enable switch, and the negative input end of the first comparator inputs a preset primary screening threshold, which is provided by the overall chip.

[0042] like Figure 6 As shown in FIG. 1 , the working principle of the primary screening circuit is as follows: each single-photon detector device will continuously receive signal photons or background interference. After the single-photon detector device avalanches, it will quickly output pulses after passing through the quenching circuit. The outputs of the four quenching circuits are input to the first time window circuit together. Whenever a pulse is sensed, the first time window circuit generates a fixed time length (T win1 ) pulse, and turn on the first comparator. During this fixed time length, the comparator will quench the total number of pulses output by the circuit and the reference number N of the comparator. x (e.g., equal to 3) for comparison, if it is greater than 3 pulses, then the comparator outputs a pulse, otherwise no output. This solution can shield most interference, but it is inevitable that some strong interference may still be output.

[0043] Second, the secondary screening circuit

[0044] The number of pulse delay modules is set to three. The output segment of the first comparator is connected to the input ends of the three pulse delay modules respectively, and is connected to the positive input end of the second comparator together with the output ends of the three pulse delay modules, and is also connected to the input end of the second time window circuit. The output end of the first time window circuit is connected to the control end of the second enable switch, and the negative input end of the second comparator inputs a preset secondary screening threshold, which is provided by the overall chip. The output end of the second comparator is connected to the input end of the time digital conversion module, the output end of the time digital conversion module is connected to the input end of the tri-state gate, and the output end of the tri-state gate is connected to the column bus (COL j ), the enable end of the tri-state gate is connected to the row selection signal SelRow i .

[0045] like Figure 7 As shown in the figure, the working principle of the secondary screening circuit is as follows: this part of the circuit needs to cooperate with the laser, the laser emits a multi-pulse pulse train, and the delay between the subsequent pulses and the first pulse is T1, T2, T3, etc. The output of the first comparator is delayed by T1, T2, T3 respectively through three pulse delay modules, and is input to the second time window circuit together. Whenever a pulse is sensed, the second time window circuit generates a fixed time length (T win2) pulse, and turn on the second comparator. During this fixed time length, the comparator will quench the total number of pulses output by the circuit and the reference number N of the comparator. y (e.g., equal to 3) for comparison, if it is greater than 3 pulses, then the comparator outputs a pulse, otherwise no output. This solution can further shield most interference.

[0046] 3. Data Output Module

[0047] The working principle is: the single-photon detector chip has a total of M×N units, namely P 1,1 , ... P 1,N , ... P M,1 , ... P M,N The row selection module generates row selection pulses SelRow1, SelRow2, ..., SelRow M This pulse turns on the tri-state gates in all cells in the same row, transferring the data from the time-to-digital conversion module to the column bus (Col1, Col2, ..., Col N ), the bus data enters the parallel input serial output module (PISO), and the column selection module generates column selection pulses SelCol1, SelCol2, ..., SelCol N , and sequentially transmit the data in PISO to the output bus (Output Bus). After transmitting one row, the row selection module outputs the row selection pulse of the next row, selects the unit data of the next row, and transmits it to PISO. Then the column selection module continues to generate column selection pulses SelCol1, SelCol2, ..., SelCol N , the data in PISO is transferred to the output bus in sequence, and so on, until the data in all units are output.

[0048] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A single-photon detector chip, used for cooperating with a multi-pulse laser (3) to detect a single photon, characterized in that: The single-photon detector chip comprises a single-photon detection unit array composed of a plurality of single-photon detection units (1) and a bias module (2); the single-photon detection unit array and the bias module (2) are integrated in a single chip; the bias module (2) is connected to the single-photon detection unit array; the single-photon detection unit (1) is provided with a primary screening circuit and a secondary screening circuit; the input end of the secondary screening circuit is connected to the output end of the primary screening circuit; the multi-pulse laser (3) emits a multi-pulse laser pulse train, the primary screening circuit performs a primary comparison screening on the pulses received by multiple devices, the secondary screening circuit uses a delay circuit to perform multi-channel delay on the pulses output by the primary screening circuit, and performs a secondary comparison screening on the multi-channel delayed pulses to extract valid pulses; The single-photon detection unit (1) further comprises a single-photon detection device (101), a quenching circuit (102), a time-to-digital conversion module (103) and a tri-state gate (104); one end of the single-photon detection device (101) is connected to the bias module (2), and the other end is connected to the input end of the quenching circuit (102); the output end of the quenching circuit (102) is connected to the primary screening circuit; the output end of the secondary screening circuit is connected to the input end of the time-to-digital conversion module (103); the output end of the time-to-digital conversion module (103) is connected to the tri-state gate (104); The primary screening circuit comprises a first comparator (105) and a first time window circuit (106); the output end of the quenching circuit (102) is respectively connected to the positive input end of the first comparator (105) and the input end of the first time window circuit (106); the output end of the first time window circuit (106) is connected to the enable switch control end of the first comparator (105); the negative input end of the first comparator (105) inputs a preset primary screening threshold; the output end of the first comparator (105) is connected to the secondary screening circuit; The secondary screening circuit comprises a pulse delay module (107), a second comparator (108) and a second time window circuit (109); the output end of the primary screening circuit is respectively connected to the input end of the second time window circuit (109), the positive input end of the second comparator (108) and the input end of the pulse delay module (107); the output end of the pulse delay module (107) is respectively connected to the positive input end of the second comparator (108) and the input end of the pulse delay module (107); the output end of the second time window circuit (109) is connected to the enable switch control end of the second comparator (108); the negative input end of the second comparator (108) inputs a preset secondary screening threshold; the output end of the second comparator (108) is connected to the input end of the time-to-digital conversion module (103); The number of the pulse delay modules (107) is several, the output end of the primary screening circuit is respectively connected to the input ends of several pulse delay modules (107), and the output ends of several pulse delay modules (107) are respectively connected to the input end of the second time window circuit (109) and the positive input end of the second comparator (108), so as to form a multi-path delayed pulse; The delays between the subsequent pulses and the first pulse in the multi-pulse pulse train emitted by the multi-pulse laser (3) are T1, T2, T3, ..., T n , wherein n is the number of pulse trains; the delay times of the pulse delay module (107) are T1, T2, T3, ..., T m , where m is the number of pulse delay modules (107).

2. A single photon detector chip according to claim 1, characterized in that: The number of the single-photon detection devices (101) and quenching circuits (102) is multiple, each single-photon detection device (101) is connected to a quenching circuit (102), and each quenching circuit (102) is connected to a screening circuit to form a multi-device pulse.

3. The single-photon detector chip according to claim 1, characterized in that: The single photon detection device (101) is a single photon avalanche diode SPAD.

4. The single-photon detector chip according to claim 1, characterized in that: The single-photon detector chip is provided with a data output module (4), which is integrated in the single chip; the data output module (4) is connected to the single-photon detection unit array.

5. The single-photon detector chip according to claim 4, characterized in that: The data output module (4) comprises a row selection module (401), a parallel input serial output module PISO (402) and a column selection module (403); the enable end of the tri-state gate (104) of each single-photon detection unit in the single-photon detection unit array is respectively connected to the output end of the row selection module (401), and the output end of the tri-state gate (104) is respectively connected to the input end of the parallel input serial output module PISO (402); one end of the column selection module (403) is connected to the parallel input serial output module PISO (402), and the other end is connected to the data output bus.

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