Mram structure with t-shaped bottom electrode to overcome galvanic effect

Abstract

A memory structure is provided that avoids high resistance due to galvanic effects. High resistance is reduced and / or eliminated by providing a T-shaped bottom electrode configuration (i.e., a single piece) of uniform structure. The T-shaped bottom electrode structure includes a narrow base portion and a wider leg portion. The leg portion of the T-shaped bottom electrode structure has a planar topmost surface with which the MTJ pillar forms an interface.

Description

Technical Field

[0001] The present application relates to a memory structure and a method for forming the same, and more particularly to a magnetoresistive random access memory (MRAM) structure including a T-shaped bottom electrode structure that avoids high resistance due to galvanic effect. Background Art

[0002] MRAM is a viable memory option for standalone and embedded applications such as the Internet of Things (IoT), automotive, or artificial intelligence (AI). MRAM is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These elements are typically formed of two ferromagnetic plates, each of which can maintain a magnetization, separated by a thin dielectric layer, the tunnel barrier layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of the external field storing the memory. The permanent magnet can be called a magnetic pinned layer or reference layer, and the magnet that changes the magnetization to match the magnetization of the external field can be called a magnetic free layer. The magnetic pinned layer, tunnel barrier layer, and magnetic free layer together provide a multi-layer magnetic tunnel junction (MTJ) pillar.

[0003] The MTJ pillar is formed on the bottom electrode. The size of the bottom electrode plays an important role in the array yield loss caused by partial metal short circuits, especially when the MTJ size is reduced to improve switching efficiency. Generally, a small bottom electrode size is desired.

[0004] Furthermore, conventional bottom electrodes in MRAM structures are composed of metals such as TiN or Cu, which are susceptible to a so-called galvanic effect during the chemical mechanical planarization process used to form the bottom electrode. Note that a galvanic effect is observed when the bottom electrode is formed on a conductive structure connected to a complementary metal oxide semiconductor (CMOS) device; it is not observed for a bottom electrode formed on a conductive structure isolated from the CMOS device. The galvanic effect leads to undesirable oxidation and / or corrosion of the bottom electrode, which can result in high resistance and array yield loss. Therefore, there is a need to provide a memory structure (i.e., an MRAM structure) in which the galvanic effect is reduced or even eliminated.

[0005] Therefore, there is a need in the art to solve the above problems. Summary of the Invention

[0006] From a first aspect, the present invention provides a memory structure comprising: a T-shaped bottom electrode structure having a uniform configuration, the T-shaped bottom electrode structure being located on a surface of a complementary metal-oxide-semiconductor (CMOS) device-connected conductive structure, the CMOS device-connected conductive structure being embedded in a first interconnect dielectric material layer; a multi-layer magnetic tunnel junction (MTJ) pillar located on the T-shaped bottom electrode structure, and a top electrode structure located on the MTJ pillar.

[0007] From another aspect, the present invention provides a structure comprising: a first memory cell comprising a first T-shaped bottom electrode structure having a uniform configuration, a first multi-layer magnetic tunnel junction (MTJ) pillar located on the first T-shaped bottom electrode structure, and a first top electrode structure located on the first MTJ pillar, the first T-shaped bottom electrode structure being located on a surface of a complementary metal-oxide-semiconductor (CMOS) device-connected conductive structure, the CMOS device-connected conductive structure being embedded in a first interconnect dielectric material layer; and a second memory cell located laterally adjacent to the first memory cell and comprising a second T-shaped bottom electrode structure having a uniform configuration, a second MTJ pillar, and a second top electrode structure, the second T-shaped bottom electrode structure being located on a surface of an isolated conductive structure embedded in the first interconnect dielectric material layer, the second MTJ pillar being located on the second T-shaped bottom electrode structure, and the second top electrode structure being located on the second MTJ pillar.

[0008] From another aspect, the present invention provides a method of forming a memory structure, the method comprising: forming a second interconnect dielectric material layer on an interconnect level, the interconnect level comprising at least one CMOS device-connected conductive structure embedded in a first interconnect dielectric material layer; forming at least one opening in the second interconnect dielectric material layer, wherein the at least one opening physically exposes a surface of the at least one CMOS device-connected conductive structure; forming a bottom electrode metal-containing layer on the second interconnect dielectric material layer and within the at least one opening; first and second planarizing the bottom electrode metal-containing layer to provide a twice-planarized bottom electrode metal-containing layer; forming a multi-layer magnetic tunnel junction (MTJ) material stack on the twice-planarized bottom electrode metal-containing layer, and forming a top electrode metal-containing layer on the MTJ material stack; and patterning the top electrode metal-containing layer, the MTJ material stack, and the twice-planarized bottom electrode metal-containing layer to provide a top electrode structure, an MTJ pillar, and a T-shaped bottom electrode structure, respectively.

[0009] A memory structure is provided that avoids high resistance due to galvanic effects. The high resistance is reduced and / or eliminated by providing a uniformly constructed T-shaped bottom electrode structure (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider scaffold portion. The scaffold portion of the T-shaped bottom electrode structure has a planar topmost surface with which the MTJ pillar forms an interface.

[0010] In one aspect of the present application, a memory structure is provided. In one embodiment, the memory structure includes a T-shaped bottom electrode structure having a uniform configuration, which is located on a surface of a conductive structure connected to a complementary metal oxide semiconductor (CMOS) device embedded in a first interconnect dielectric material layer. A multilayer magnetic tunnel junction (MTJ) pillar is located on the T-shaped bottom electrode structure, and a top electrode structure is located on the MTJ pillar.

[0011] The MTJ pillar that can be used in the present application can be a bottom pinned MTJ material structure or a top pinned MTJ material structure. The T-shaped bottom electrode structure of the present invention includes a base portion and a bracket portion, and the width of the bracket portion is greater than the width of the base portion. In some embodiments, the second interconnect dielectric material layer can laterally surround the base portion of the T-shaped bottom electrode structure and be located above the first interconnect dielectric material layer. In some embodiments, the diffusion barrier liner can be directly located under the bracket portion of the T-shaped bottom electrode structure and line the sidewalls and bottom wall of the base portion of the T-shaped bottom electrode structure.

[0012] In some embodiments, an encapsulation liner and a third interconnect dielectric material layer may be positioned laterally adjacent to the standoff portion of the T-shaped bottom electrode structure, the MTJ pillar, and the top electrode structure. In further embodiments, a bitline contact may be located on the third interconnect dielectric material layer and contact a surface of the top electrode structure.

[0013] In another aspect of the present application, a structure is provided. In one embodiment, the structure includes a first memory cell, the first memory cell including a first T-shaped bottom electrode structure having a uniform structure, a first multi-layer magnetic tunnel junction (MTJ) pillar located on the first T-shaped bottom electrode structure, and a first top electrode structure located on the first MTJ pillar, the first T-shaped bottom electrode structure being located on the surface of a conductive structure connected to a complementary metal oxide semiconductor (CMOS) device embedded in a first interconnect dielectric material layer. The structure also includes a second memory cell laterally adjacent to the first memory cell. The second memory cell includes a second T-shaped bottom electrode structure having a uniform structure located on the surface of an isolated conductive structure embedded in the first interconnect dielectric material layer; a second MTJ pillar located on the second T-shaped bottom electrode structure; and a second top electrode structure located on the second MTJ pillar.

[0014] The first MTJ pillar and the second MTJ pillar can be a bottom pinned MTJ material structure or a top pinned MTJ material structure. In some embodiments, the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure include a base portion and a scaffold portion, and the width of the scaffold portion is greater than the width of the base portion. In some embodiments, the second interconnect dielectric material layer can laterally surround the base portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure and be located above the first interconnect dielectric material layer. In further embodiments, a diffusion barrier liner can be directly located under the scaffold portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure and line the sidewalls and bottom wall of the base portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure.

[0015] In some embodiments, the encapsulation liner and the third interconnect dielectric material layer may be positioned laterally adjacent to the scaffold portion of each of the first and second T-shaped bottom electrode structures, each of the first and second MTJ pillars, and each of the first and second top electrode structures. In further embodiments, a bit line contact may be located on the third interconnect dielectric material layer and contact a surface of the first and second top electrode structures.

[0016] In another aspect of the present application, a method for forming a memory structure is provided. In one embodiment, the method includes forming a second interconnect dielectric material layer on an interconnect level, the interconnect level including a conductive structure connected to at least one CMOS device embedded in the first interconnect dielectric material layer. At least one opening is then formed in the second interconnect dielectric material layer, wherein the at least one opening physically exposes the surface of the conductive structure connected to at least one CMOS device. Next, a bottom electrode metal-containing layer is formed on the second interconnect dielectric material layer and within the at least one opening. First and second planarization steps are then performed on the bottom electrode metal-containing layer to provide a twice-planarized bottom electrode metal-containing layer. A multilayer magnetic tunnel junction (MTJ) material stack is formed on the twice-planarized bottom electrode metal-containing layer, and then a top electrode metal-containing layer is formed on the MTJ material stack. Next, the top electrode metal-containing layer, the MTJ material stack, and the twice-planarized bottom electrode metal-containing layer are patterned to provide a top electrode structure, an MTJ column, and a T-shaped bottom electrode structure, respectively.

[0017] In some embodiments, the MTJ material stack comprises a bottom pinned MTJ material stack or a top pinned MTJ material stack. In some embodiments, the T-shaped bottom electrode structure is a unitary structure and includes a base portion and a support portion, wherein the width of the support portion is greater than the width of the base portion. In some embodiments, after the patterning step, an encapsulation liner, a third interconnect dielectric material layer, and a bit line contact can be formed. In some embodiments, the patterning can also remove an upper portion of the first interconnect dielectric material layer to provide a concave surface to the first dielectric material layer.

[0018] In some embodiments, before forming the bottom electrode metal-containing layer, a diffusion barrier material layer is formed on the second interconnect dielectric material layer and lines at least one opening. In some embodiments, the patterning further provides a diffusion barrier liner located below the T-shaped bottom electrode structure. In some embodiments, after the patterning step, an encapsulation liner, a third interconnect dielectric material layer, and a bitline contact are formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will now be described, by way of example only, with reference to preferred embodiments, as shown in the accompanying drawings:

[0020] Figure 1 is a cross-sectional view of an exemplary structure that may be employed in one embodiment of the present application, the exemplary structure including a second interconnect dielectric material layer on an interconnect level including a conductive structure for at least one CMOS device connection embedded in the first interconnect dielectric material layer.

[0021] Figure 2 yes Figure 1 A cross-sectional view of the exemplary structure after forming at least one opening in the second interconnect dielectric material layer, wherein the at least one opening physically exposes a surface of a conductive structure connected to at least one CMOS device.

[0022] Figure 3 yes Figure 2 A cross-sectional view of the exemplary structure after forming a bottom electrode metal-containing layer on the second interconnect dielectric material layer and within the at least one opening.

[0023] Figure 4 yes Figure 3 A cross-sectional view of an exemplary structure after a first planarization of the bottom electrode metal-containing layer.

[0024] Figure 5 yes Figure 4 A cross-sectional view of an exemplary structure after a second planarization of the bottom electrode metal-containing layer.

[0025] Figure 6 yes Figure 5A cross-sectional view of an exemplary structure after forming a multi-layer magnetic tunnel junction (MTJ) material stack on the twice-planarized bottom electrode metal-containing layer and forming a top electrode metal-containing layer on the MTJ material stack.

[0026] Figure 7 yes Figure 6 1 is a cross-sectional view of an exemplary structure after patterning the top electrode metal-containing layer, the MTJ material stack, and the twice-planarized bottom electrode metal-containing layer to provide a top electrode structure, an MTJ pillar, and a T-shaped bottom electrode structure, respectively.

[0027] Figure 8 yes Figure 7 A cross-sectional view of the exemplary structure of FIG. 1 after forming an encapsulation liner, a third interconnect dielectric material layer, and a bit line contact.

[0028] Figure 9 yes Figure 2 A cross-sectional view of the exemplary structure after forming a diffusion barrier material layer on the second interconnect dielectric material layer and lining at least one opening.

[0029] Figure 10 yes Figure 9 A cross-sectional view of an exemplary structure after forming a bottom electrode metal-containing layer on a diffusion barrier material layer, planarizing the bottom electrode metal-containing layer for a first time, and planarizing the bottom electrode metal-containing layer for a second time.

[0030] Figure 11 yes Figure 10 A cross-sectional view of an exemplary structure after forming a multi-layer magnetic tunnel junction (MTJ) material stack on a twice-planarized bottom electrode metal-containing layer, forming a top electrode metal-containing layer on the MTJ material stack, and patterning the top electrode metal-containing layer, the MTJ material stack, the twice-planarized bottom electrode metal-containing layer, and the diffusion barrier material layer to provide a top electrode structure, an MTJ pillar, a T-shaped bottom electrode structure, and a diffusion barrier liner, respectively.

[0031] Figure 12 yes Figure 11 A cross-sectional view of the exemplary structure of FIG. 1 after forming an encapsulation liner, a third interconnect dielectric material layer, and a bit line contact.

[0032] FIG. 13 is a cross-sectional view of a prior art memory structure. DETAILED DESCRIPTION

[0033] The present application will now be described in more detail with reference to the following discussion and the accompanying drawings. Note that the drawings in this application are for illustrative purposes only and are not drawn to scale. It should also be noted that identical and corresponding elements are represented by identical reference numerals.

[0034] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth in order to provide an understanding of the various embodiments of the present application. However, it will be understood by those skilled in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0035] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element or there may be intervening elements present. In contrast, when an element is referred to as being "directly below" or "directly below" another element, there are no intervening elements present.

[0036] Note that the figures of the present application illustrate memory device regions where devices such as MRAM devices will be formed. Non-memory device regions may be located laterally adjacent to the memory device regions illustrated in the figures of the present application.

[0037] First reference Figure 1 , showing an exemplary structure that can be adopted in one embodiment of the present application. Figure 1 An exemplary structure includes an interconnect level L n The second interconnect dielectric material layer 18 on the interconnect level L is an integer starting from 1. n The conductive structures 16L, 16R comprising at least one CMOS device connection embedded in the first interconnect dielectric material layer 14. Interconnect level L n At least one isolated conductive structure 16 embedded in the first interconnect dielectric material layer 14 may also be included.

[0038] like Figure 1 As further shown in FIG, the metal level L n-1 Located below the interconnect level Ln. In some embodiments, when n is 1, the metal level L n-1 In other embodiments, when n is 2, 3, 4, etc., the metal level L n-1 is located at the interconnect level L n In any embodiment, the metal level L n-1A dielectric material layer 10 is included, which contains at least one metal-level conductive structure 12 embedded therein, which is directly or indirectly connected to an underlying CMOS device (not shown) that exists in a front-end-of-line (FEOL) level (also not shown).

[0039] When n is 1, the metal level L n-1 The dielectric material layer 10 can be composed of a MOL dielectric material, such as silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than 4.0 (all dielectric constants expressed herein are measured in a vacuum). Moreover, in such an embodiment (i.e., when n is 1), at least one metal level conductive structure 12 is a contact structure including a contact metal or a contact metal alloy, such as tungsten (W), cobalt (Co), platinum (Pt), nickel (Ni), or an alloy thereof.

[0040] When n is greater than 1, the metal level L n-1 The dielectric material layer 10 can be composed of an interconnecting dielectric material, such as silicon dioxide, silsesquioxane, a C-doped oxide including Si, C, O and H atoms (i.e., an organosilicate), a thermosetting polyarylene ether or a multilayer thereof. The term "polyarylene" is used in this application to refer to aromatic groups or inert substituted aromatic groups connected together by bonds, fused rings or inert linking groups, such as oxygen, sulfur, sulfone, sulfoxide, carbonyl, etc. In addition, in such an embodiment (i.e., when n is greater than 1), at least one metal level conductive structure 12 is composed of a conductive metal or a conductive metal alloy. Examples of conductive materials that can be used in this application include copper (Cu), aluminum (Al) or tungsten (W), while an example of a conductive metal alloy is a Cu-Al alloy.

[0041] Interconnection level L n The first interconnect dielectric material layer 14 may be composed of one of the interconnect dielectric materials mentioned above for the dielectric material layer 10. The conductive structures 16L, 16R connected to the at least one CMOS device embedded in the first interconnect dielectric material layer 14 and (if present) the at least one isolated conductive structure 16 may be composed of one of the conductive metals or metal alloys mentioned above for the at least one metal-level conductive structure 12.

[0042] In some embodiments, a diffusion barrier liner (not shown) is formed along the sidewalls and bottom wall of at least one metal level conductive structure 12 and / or at least one CMOS device connected conductive structure 16L, 16R and / or at least one isolated conductive structure 16. Figure 1 In the illustrated embodiment, there is no diffusion barrier liner. The diffusion barrier liner is composed of a diffusion barrier material (i.e., a material that acts as a barrier to prevent conductive materials such as copper from diffusing therethrough). Examples of diffusion barrier materials that can be used to provide a diffusion barrier liner include, but are not limited to, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, the diffusion barrier material can include a material stack of diffusion barrier materials. In one example, the diffusion barrier material can be composed of a stack of Ta / TaN.

[0043] Metal Level L n-1 and interconnection level L n It can be formed using conventional processes known to those skilled in the art. In order not to obscure the method of this application, the method for forming the metal layer L is not provided here. n-1 and interconnection level L n In one embodiment, a damascene process may be used to form the metal level L n-1 and interconnection level L n The damascene process may include forming an opening in a dielectric material, filling the opening with a contact metal-containing material or a conductive metal-containing material, and, if necessary, performing a planarization process such as chemical mechanical polishing (CMP) and / or grinding.

[0044] In some embodiments, at least one metal level conductive structure 12 has a topmost surface that is coplanar with the topmost surface of the dielectric material layer 10, and at least one CMOS device connected conductive structure 16L, 16R and (if present) at least one isolation conductive structure 16 have a topmost surface that is coplanar with the topmost surface of the first interconnect dielectric material layer 14.

[0045] In forming the interconnection level L n Afterwards, at the interconnect level L nA second interconnect dielectric material layer 18 is formed on the physically exposed topmost surface of the dielectric material layer 10. The second interconnect dielectric material layer 18 can be composed of one of the interconnect dielectric materials described above for the dielectric material layer 10. In some embodiments, the second interconnect dielectric material layer 18 is composed of an interconnect material that is compositionally the same as the interconnect dielectric material that provides the first interconnect dielectric material layer 14. In other embodiments, the second interconnect dielectric material layer 18 is composed of an interconnect material that is compositionally different from the interconnect dielectric material that provides the first interconnect dielectric material layer 14. The second interconnect dielectric material layer 18 is a continuous layer that can be formed using conventional deposition processes, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition, evaporation, or atomic layer deposition (ALD). In one embodiment, the second interconnect dielectric material layer 18 can have a thickness (i.e., vertical height) from 50 nm to 200 nm. The thickness of the interconnect dielectric material layer 18 will determine the height of the base portion of the subsequently formed T-shaped bottom electrode structure.

[0046] Now refer to Figure 2 , showing the second interconnect dielectric material layer 18 after forming at least one opening 20 Figure 1 , wherein at least one opening 20 physically exposes the surface of at least one conductive structure 16L, 16R connected to the CMOS device. In some embodiments where isolated conductive structures 16 are present, another opening 20 may be formed in the first interconnect dielectric material layer 14 to physically expose the surface of at least one isolated conductive structure 16.

[0047] Each opening 20 can be formed into the second interconnect dielectric material layer 18 by photolithography and etching. Photolithography includes forming a photoresist material on the material or material stack that needs to be patterned, exposing the photoresist material to a predetermined irradiation pattern, and developing the exposed photoresist to provide a patterned photoresist. Etching can include an anisotropic etching process, such as reactive ion etching (RIE). Each opening 20 can have a width of 5nm to 100nm. The width of each opening 20 will determine the width of the base portion of the T-shaped bottom electrode structure that will be formed subsequently.

[0048] Now refer to Figure 3 , showing the bottom electrode metal-containing layer 22 formed on the second interconnect dielectric material layer 18 and in the at least one opening 20 Figure 2 In the exemplary structure shown, in the embodiment shown, the bottom electrode metal-containing layer 22 completely fills each opening 20, so that the bottom electrode metal-containing layer 22 within each opening 20 forms an interface with the physically exposed surfaces of the conductive structures 16L, 16R connected to at least one CMOS device and (if present) at least one isolated conductive structure 16.

[0049] The bottom electrode metal-containing layer 22 can be made of a conductive material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, or WN. The thickness (i.e., vertical height) of the bottom electrode metal-containing layer 22 is much greater (typically ≥1.5x) than the thickness of the second interconnect dielectric material layer 18. In one embodiment, the thickness of the bottom electrode metal-containing layer 22 is 200 nm to 300 nm. The bottom electrode metal-containing layer 22 can be formed by a conformal deposition process, such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0050] Now refer to Figure 4 , showing the bottom electrode metal-containing layer 22 after the first planarization Figure 3 In the exemplary structure, the first planarization may include chemical mechanical polishing (CMP) and / or grinding to remove the upper portion of the bottom electrode metal-containing layer 22 while retaining the lower portion of the bottom electrode metal-containing layer 22. The retained lower portion of the bottom electrode metal-containing layer 22 may be referred to as a once-planarized bottom electrode metal-containing layer 22P1.

[0051] The once-planarized bottom electrode metal-containing layer 22P1 has a completely flat top surface that is completely above the top surface of the second interconnect dielectric material layer 18. The once-planarized bottom electrode metal-containing layer 22P1 has a thickness less than that of the bottom electrode metal-containing layer 22.

[0052] Now refer to Figure 5 , which shows the bottom electrode metal-containing layer 22 after the second planarization Figure 4 . The second planarization, which may include CMP and / or grinding, removes the upper portion of the once-planarized bottom electrode metal-containing layer 22 while retaining the lower portion of the once-planarized bottom electrode metal-containing layer 22P1. The remaining lower portion of the once-planarized bottom electrode metal-containing layer 22P1 may be referred to as a second-planarized bottom electrode metal-containing layer 22P2.

[0053] The twice-planarized bottom electrode metal-containing layer 22P2 has a completely flat topmost surface that is completely located above the topmost surface of the second interconnect dielectric material layer 18. The twice-planarized bottom electrode metal-containing layer 22P2 has a thickness that is less than that of the once-planarized bottom electrode metal-containing layer 22P1. In the present application, the twice-planarized bottom electrode metal-containing layer 22P2 has an upper portion that extends above the topmost surface of the second interconnect dielectric material layer 18. The upper portion of the twice-planarized bottom electrode metal-containing layer 22P2 extending above the topmost surface of the second interconnect dielectric material layer 18 has a thickness T of from 5 nm to 40 nm. The thickness T of the upper portion of the twice-planarized bottom electrode metal-containing layer 22P2 extending above the topmost surface of the second interconnect dielectric material layer 18 determines the thickness of the scaffold portion of the T-shaped bottom electrode structure to be formed subsequently.

[0054] See now Figure 6 , illustrating the formation of a multi-layer magnetic tunnel junction (MTJ) material stack 24 on the twice-planarized bottom, electrode metal-containing layer 22P2 and a top electrode metal-containing layer 32 on the MTJ material stack 24. Figure 5 An exemplary structure.

[0055] The MTJ material stack 24 includes at least a magnetic pinning layer, a tunnel barrier layer, and a magnetic free layer. Figure 6 As shown, the MTJ material stack 24 is a bottom pinned MTJ material stack, which includes, from bottom to top, a magnetic pinned layer 26, a tunnel barrier layer 28, and a magnetic free layer 30. An optional metal seed layer (not shown) may also be present in the bottom pinned MTJ material stack. In the bottom pinned MTJ material stack, the optional metal seed layer is formed below the magnetic pinned layer 26. The bottom pinned MTJ material stack may also include a non-magnetic spacer layer (not shown) located on the magnetic free layer 30, a second magnetic free layer (not shown) located on the non-magnetic spacer layer, and / or an MTJ cap layer (not shown) located on the magnetic free layer 30 or the second magnetic free layer.

[0056] In other embodiments (not shown), the MTJ material stack 24 is a top pinned MTJ material stack, which includes a magnetic free layer, a tunnel barrier layer, and a magnetic pinned layer from bottom to top; in this embodiment, the order of elements 26 and 30 is the same as Figure 6 In such an embodiment, the top-pinned MTJ material stack may also include an optional metal seed layer below the magnetic free layer, a nonmagnetic spacer layer on the magnetic free layer, a second magnetic free layer on the nonmagnetic spacer layer, and / or an MTJ cap layer on the magnetic pinned layer.

[0057] The various material layers of the MTJ material stack 24 may be formed by utilizing one or more deposition processes, such as sputtering, plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0058] The optional metal seed layer can be composed of platinum (Pt), palladium (Pd), nickel (Ni), rhodium (Rh), iridium (Ir), rhenium (Re), or alloys and multilayers thereof. In one example, the optional metal seed layer is composed of platinum (Pt).

[0059] The magnetic pinned layer 26 has a fixed magnetization. The magnetic pinned layer 26 may be composed of a metal or metal alloy (or stack thereof) including one or more metals exhibiting high spin polarization. In alternative embodiments, exemplary metals for forming the magnetic pinned layer 26 include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys may include the metals exemplified above.

[0060] In another embodiment, the magnetic pinning layer 26 can be a multilayer arrangement having (1) a high spin polarization region formed from a metal and / or metal alloy using the above-mentioned metals, and (2) a region composed of one or more materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and can be arranged as alternating layers. The strong PMA region can also include alloys exhibiting strong PMA, exemplary alloys including cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys can be arranged as alternating layers. In one embodiment, a combination of these materials and regions can also be used as the magnetic pinning layer 26.

[0061] Tunnel barrier layer 28 is composed of an insulator material and is formed to a thickness that provides appropriate tunneling resistance. Exemplary materials for tunnel barrier layer 28 include magnesium oxide, aluminum oxide, and titanium oxide, or a material with higher electrical tunnel conductance, such as a semiconductor or a low-bandgap insulator.

[0062] The magnetic free layer 30 may be composed of a magnetic material (or a stack of magnetic materials) having a magnetization that can change orientation relative to the magnetization orientation of the magnetic pinned layer 26. Exemplary magnetic materials for the magnetic free layer 30 include nickel, cobalt-iron alloys, nickel-iron alloys, cobalt-iron-boron alloys, alloys of cobalt, iron, and / or multilayers.

[0063] If present, the non-magnetic metallic spacer layer is composed of a non-magnetic metal or metal alloy that allows magnetic information to be transferred therethrough and also allows the two magnetically free layers to be magnetically coupled together such that the first and second magnetically free layers are always parallel in an equilibrium state. The non-magnetic metallic spacer layer allows for spin torque switching between the first and second magnetically free layers.

[0064] If present, the second magnetically free layer may include one of the magnetic materials described above for the magnetically free layer 30. In one embodiment, the second magnetically free layer is composed of the same magnetic material as the magnetically free layer 30. In another embodiment, the second magnetically free layer is composed of a magnetic material having a different composition than the magnetically free layer 30.

[0065] If present, the MTJ cap layer may be composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al, or other high melting point metals or conductive metal nitrides. The MTJ cap layer may have a thickness from 2 nm to 25 nm; other thicknesses are also possible and may be used as the thickness of the MTJ cap layer in this application.

[0066] The top electrode metal-containing layer 32 can be composed of a conductive material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. In one embodiment of the present invention, the top electrode metal-containing layer 32 is composed of Ti / TiN. The conductive material providing the top electrode metal-containing layer 32 can be the same as or different in composition from the conductive material providing the bottom electrode metal-containing layer 22.

[0067] In the present application, the top electrode metal-containing layer 32 may have a thickness from 100 nm to 500 nm; although other thicknesses are possible and may be used as the thickness of the top electrode metal-containing layer 32, the top electrode metal-containing layer 32 may be formed by a deposition process such as sputtering, plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0068] Now refer to Figure 7 , which illustrates that after patterning the top electrode metal-containing layer 32, the MTJ material stack 24, and the twice-planarized bottom electrode metal-containing layer 22P2 to provide the top electrode structure 32S, the MTJ pillar 24P, and the T-shaped bottom electrode structure 22S, respectively Figure 6 An exemplary structure.

[0069] The patterning of the top electrode metal-containing layer 32, the MTJ material stack 24, and the twice planarized bottom electrode metal-containing layer 22P2may include first forming a patterned mask (not shown) on the physically exposed surface of the top electrode metal-containing layer 32. In some embodiments, the patterned mask can be composed of a photoresist stack. In one embodiment, the photoresist stack providing the patterned mask can include a bottom organic layer, an intermediate inorganic layer, and a top resist layer. The bottom organic layer of the photoresist stack can include an organic planarization layer (OPL). The bottom organic layer of the photoresist stack can include a spin-on organic layer, such as, for example, near frictionless carbon (NFC), diamond-like carbon, thermoset polyarylene ether, or polyimide. The intermediate inorganic layer of the photoresist stack can include any oxide layer, such as, for example, a low temperature (e.g., less than or equal to 250 °C) CVD oxide, an oxide derived from TEOS (tetraethyl orthosilicate), silicon oxide, siloxane, or a Si-containing anti-reflective coating material (SiARC). The top resist layer of the photoresist stack can be composed of a resist material that provides high resolution photopatterning. The photoresist stack can be first formed by utilizing a series of deposition processes including a first spin-on of the bottom organic layer, a second spin-on of the intermediate inorganic layer, and a third spin-on of the top resist layer. After providing the photoresist stack, the top resist layer is patterned by photolithography (i.e., exposing the top resist layer to a pattern of radiation, and then developing the exposed top resist layer), and thereafter the pattern provided to the top resist layer is transferred into the underlying layers of the photoresist stack providing the patterned mask. The transfer can include one or more etching processes.

[0070] In some embodiments, the patterning can include first patterning the top electrode metal-containing layer 32 utilizing a first etching process, such as, for example, a reactive ion etch, utilizing the patterned mask as an etch mask. The remaining portion of the top electrode metal-containing layer 32, i.e., the unpatterned portion, provides a top electrode structure 32S. The top electrode structure 32S can be cylindrical; although other asymmetric shapes are possible and can be used in this application as a shape for the top electrode structure 32S. The critical dimension (CD) of the top electrode structure 32S can vary, and is not critical in this application.

[0071] After patterning the top electrode metal-containing layer 32, the patterned mask is removed from the top of the top electrode structure 32S formed utilizing conventional processes known to those skilled in the art. The patterning of the MTJ material stack 24 and the twice planarized bottom electrode metal-containing layer 22P2is then performed utilizing ion beam etching (IBE), with the top electrode structure 32S serving as a patterned mask. The remaining (i.e., unpatterned) portion of the MTJ material stack 24 provides an MTJ pillar 24P. In one example and as shown in FIG. 3, the MTJ pillar 24P is cylindrical; although other asymmetric shapes are possible and can be used in this application as a shape for the MTJ pillar 24P. The critical dimension (CD) of the MTJ pillar 24P can vary, and is not critical in this application. Figure 7As shown in FIG, the MTJ pillar 24P, from bottom to top, includes a magnetic pinned material layer portion 26P (i.e., the remaining unetched portion of the magnetic pinned material layer 26), a tunnel barrier layer portion 28P (i.e., the remaining unetched portion of the tunnel barrier layer 28), and a magnetic free layer portion 30P (i.e., the remaining unetched portion of the magnetic free layer 30). In another example (not shown), the MTJ pillar 24P, from bottom to top, includes a magnetic free layer portion 30P, a tunnel barrier layer portion 28P, and a magnetic pinned material layer portion 26P. The MTJ pillar 24P may include the remaining portions of any other layers present in the MTJ material stack 24. The shape of the MTJ pillar 24P may be cylindrical; although other asymmetric shapes are possible and may be used as the shape of the MTJ pillar 24P in the present application; the MTJ pillar 24P and the top electrode structure 32S have the same shape. The critical dimension (CD) of the MTJ pillar 24P may vary and is not critical in the present application. The CD of the MTJ pillar 24P is generally the same as the CD of the top electrode structure 32S.

[0072] The IBE etch continues to pattern the lower twice planarized bottom electrode metal layer 22P2 to provide a T-shaped bottom electrode structure 22S. Figure 7 As shown, the physically exposed upper portion of the second interconnect dielectric material 18 may also be removed. After IBE, the remaining second interconnect dielectric material may have a concave surface, S1, as shown in FIG. Figure 7 shown.

[0073] Each T-shaped bottom electrode structure 22S includes the remaining portion of the twice-planarized bottom electrode metal layer 22P2. Each T-shaped bottom electrode structure 22S includes a base (ie, vertically extending) portion (at Figure 7 The base) and the support (i.e., horizontal) portion (in Figure 7 The T-shaped bottom electrode structure 22S has a uniform structure (i.e., a single piece) without any material interface between the support portion and the base portion. The support portion has an outermost edge that extends beyond the outermost edge of the base portion. In some embodiments (e.g., Figure 7 As shown in FIG. 2 , the outermost edge of the scaffold portion of the T-shaped bottom electrode structure 22S tapers outward from the topmost surface of the scaffold portion to the bottommost surface of the scaffold portion. The base portion of each T-shaped bottom electrode structure 22S has a width smaller than the scaffold portion. The base portion and the scaffold portion of each T-shaped bottom electrode structure 22S are an integral structure (i.e., a single piece) made of the same bottom electrode material. The scaffold portion of each T-shaped bottom electrode structure 22S provides a flat surface with which the MTJ pillar 24P forms an interface. Thus, variations in the height uniformity of the MTJ pillar are avoided.

[0074] Together, the T-shaped bottom electrode structure 22S, the MTJ pillar 24P, and the upper electrode structure 32S provide a memory structure according to the present application. The presence of the T-shaped bottom electrode structure 22S in the memory structure shorts the conductive structures 16L and 16R connected to the CMOS device and the isolated conductive structure 16. Therefore, due to the presence of the T-shaped bottom electrode structure 22S, high resistance is reduced and / or even eliminated due to the aforementioned galvanic effect. Furthermore, no array yield loss is observed due to the presence of the T-shaped bottom electrode structure 22S.

[0075] Now refer to Figure 8 , which illustrates the process after forming the encapsulation liner 34, the third interconnect dielectric material layer 36 and the bit line contact 38 Figure 7 In the exemplary structure of FIG. 1 , an encapsulation liner 34 laterally surrounds the top electrode structure 32S, the MTJ pillar 24P, and the bracket portion of the T-shaped bottom electrode 22S. A third interconnect dielectric material layer 36 is located on the encapsulation liner 34 and fills the gaps between adjacent memory structures. A bitline contact 38 is located above each memory structure and the third interconnect dielectric material layer 36. In this embodiment, the bitline contact 38 has a surface that contacts a surface of each top electrode structure 32S.

[0076] An encapsulation liner 34 may be present on the concave surface S1 of the second interconnect dielectric material layer 18, the encapsulation liner 34 being composed of a dielectric material having a composition different from that of the second interconnect dielectric material layer 18. The dielectric material providing the encapsulation liner 34 may provide passivation for the top electrode structure 32S, the MTJ pillar 24P, and the scaffold portion of the T-shaped bottom electrode 22S. In one embodiment, the encapsulation liner 34 is composed of silicon nitride. In another embodiment, the encapsulation liner 34 may be composed of a dielectric material containing silicon, carbon, and hydrogen atoms. In some embodiments, the dielectric material providing the encapsulation liner 34 may include at least one of nitrogen and oxygen atoms in addition to carbon and hydrogen atoms. In other embodiments, the dielectric material providing the encapsulation liner 34 may include boron atoms in addition to silicon, nitrogen, carbon, and hydrogen atoms. In one example, the encapsulation liner 34 may be composed of an nBLOK dielectric material containing silicon, carbon, hydrogen, nitrogen, and oxygen atoms. In an alternative example, the encapsulation liner 34 may be composed of a SiBCN dielectric material containing silicon, boron, carbon, hydrogen, and nitrogen atoms.

[0077] The encapsulation liner 34 can be formed by first depositing a continuous layer of dielectric material that provides the encapsulation liner 34. During a subsequently performed planarization process for forming the third interconnect dielectric material layer 36, the dielectric material that provides the encapsulation liner 34 is removed from the topmost surface of each top electrode structure 32S. The encapsulation liner 34 can have a thickness of from 10 nm to 200 nm. Other thicknesses are also possible and can be used as the thickness of the encapsulation liner 34. The encapsulation liner 34 generally has a topmost surface that is coplanar with the topmost surface of the top electrode structure 32S.

[0078] The third interconnect dielectric material layer 36 may include one of the interconnect dielectric materials described above. The interconnect dielectric material providing the third interconnect dielectric material layer 36 may be compositionally the same as or different from the interconnect dielectric material providing the first interconnect dielectric material layer 14 and / or the second interconnect dielectric material layer 18. The third interconnect dielectric material layer 36 may be formed using conventional deposition processes, including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or spin coating. After depositing the interconnect dielectric material providing the third interconnect dielectric material layer 36, a planarization process, such as chemical mechanical polishing (CMP), may be performed; as described above, this planarization step also removes the dielectric material providing the encapsulation liner 34 from the topmost surface of the top electrode structure 32S.

[0079] The bit line contact 38 may include one of the above-mentioned conductive metals or metal alloys. The bit line contact 36 may be formed by depositing a conductive metal or metal alloy layer and then patterning the conductive metal or metal alloy layer. As described above, the patterning may be performed by photolithography and etching.

[0080] Now refer to Figure 9 , showing the state after forming a diffusion barrier material layer 19 on the second interconnect dielectric material layer 18 and lining at least one opening 20 Figure 2 The diffusion barrier material layer 19 is a continuous layer of a diffusion barrier material (i.e., a material that acts as a barrier to prevent the diffusion of conductive materials such as copper). Examples of diffusion barrier materials that can be used to provide the diffusion barrier material layer 19 include, but are not limited to, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, the diffusion barrier material layer 19 can include a stack of diffusion barrier materials. In one example, the diffusion barrier material layer 19 can be composed of a stack of Ta / TaN.

[0081] The diffusion barrier material layer 19 can be formed using a deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The diffusion barrier material layer 19 can have a thickness of from 1 nm to 20 nm. Other thicknesses of the diffusion barrier material layer 19 are contemplated and can be used, as long as the thickness of the diffusion barrier material layer 19 does not completely fill the at least one opening 20.

[0082] Now refer to Figure 10 , showing a bottom electrode metal layer (not shown, but as above) formed on the diffusion barrier material layer 19 Figure 3 As described above), first planarizing the bottom electrode metal layer (as described above) Figure 4 as described above) and the second flattening (as described above) Figure 5 The bottom electrode metal layer is provided with a double planarized bottom electrode metal layer 22P2. Figure 9 The first and second planarization steps may include sequential CMP and / or grinding steps. The twice-planarized bottom electrode metal-containing layer 22P2 has a completely flat topmost surface located above the topmost surface of the second interconnect dielectric material layer 18. The twice-planarized bottom electrode metal-containing layer 22P2 has a completely flat topmost surface located above the topmost surface of the second interconnect dielectric material layer 18. Figure 5 The thickness T described in .

[0083] Now refer to Figure 11 , showing the structure after forming a multi-layer magnetic tunnel junction (MTJ) material stack on the twice-planarized bottom electrode metal-containing layer 22P2, forming a top electrode metal-containing layer on the MTJ material stack, and patterning the top electrode metal-containing layer, the MTJ material stack, the twice-planarized bottom electrode metal-containing layer, and the diffusion barrier material layer to provide a top electrode structure 32A, an MTJ pillar 24P, a T-shaped bottom electrode structure 22S, and a diffusion barrier liner 19L, respectively Figure 10 An exemplary structure of .

[0084] Figure 11 The exemplary structure shown can be formed using the above Figure 6 and 7 The basic processing steps and materials in the exemplary structure shown are formed. In this embodiment, as Figure 11 As shown, the diffusion barrier liner 19L is located below the scaffold portion of the T-shaped bottom electrode structure 22S and lines the entirety of the at least one opening 20. Thus, the diffusion barrier liner 19L is located between the T-shaped bottom electrode structure 22S and the second interconnect dielectric material layer 18, and between the bottommost surface of the T-shaped bottom electrode structure 22S and one of the conductive structures 16L, 16R, 16 embedded in the first interconnect dielectric material layer 14.

[0085] Now refer to Figure 12, showing the encapsulation liner 34, the third interconnect dielectric material layer 36 and the bit line contact 38 after forming Figure 11 The encapsulation liner 34, the third interconnect dielectric material layer 36 and the bit line contact 38 used in this embodiment of the present application are similar to those provided in the embodiment of the present invention. Figure 8 The encapsulation liner 34, third interconnect dielectric material layer 36, and bit line contacts 38 used in the exemplary structure shown in are the same.

[0086] Reference is now made to Figure 13, which shows a memory structure of the prior art. The memory structure of the prior art differs from the memory structure of the present application in that the diffusion barrier liner 53L is located between the bottom electrode column 52S and the planar bonding pad structure 54P. Both the bottom electrode column 52S and the planar bonding pad structure 54P are composed of a metal or metal alloy that is easily oxidized and / or corroded. Therefore, the prior art structure can exhibit high resistance and low array yield. It should be noted that in the prior art structure, there is no solid T-shaped bottom electrode structure 22S of uniform construction (i.e., a single piece).

[0087] Although the present application has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the scope of the present application. Therefore, the present application should not be limited to the exact forms and details described and shown, but should fall within the scope of the appended claims.

Claims

1. A memory structure comprising: A T-shaped bottom electrode structure having a uniform structure, the T-shaped bottom electrode structure being located on a surface of a conductive structure connected to a complementary metal oxide semiconductor (CMOS) device embedded in a first interconnect dielectric material layer, the T-shaped bottom electrode structure comprising a base portion and a support portion, the support portion having a width greater than a width of the base portion; a second interconnect dielectric material layer, the second interconnect dielectric material layer being located above the first interconnect dielectric material layer and laterally surrounding the base portion of the T-shaped bottom electrode structure, and wherein the second interconnect dielectric material layer has a concave surface; a multilayer magnetic tunnel junction (MTJ) column located on the T-shaped bottom electrode structure, a top electrode structure located on the MTJ pillar; and An encapsulation liner and a third interconnect dielectric material layer on the concave surface of the second interconnect dielectric material layer, the encapsulation liner and the third interconnect dielectric material layer are positioned laterally adjacent to the standoff portion of the T-shaped bottom electrode structure, the MTJ pillar, and the top electrode structure. 2 . The memory structure of claim 1 , wherein the MTJ pillar comprises a bottom pinned MTJ material structure. 3 . The memory structure of claim 1 , wherein the MTJ pillar comprises a top-pinned MTJ material structure.

4. The memory structure of claim 1 further comprising a diffusion barrier liner directly beneath the standoff portion of the T-shaped bottom electrode structure and lining the sidewalls and bottom walls of the base portion of the T-shaped bottom electrode structure. 5 . The memory structure of claim 4 , further comprising a bitline contact on the third interconnect dielectric material layer and contacting a surface of the top electrode structure.

6. A memory structure comprising: a first memory cell including a first T-shaped bottom electrode structure having a uniform configuration, a first multi-layer magnetic tunnel junction (MTJ) pillar located on the first T-shaped bottom electrode structure, and a first top electrode structure located on the first MTJ pillar, the first T-shaped bottom electrode structure being located on a surface of a conductive structure connected to a complementary metal oxide semiconductor (CMOS) device embedded in a first interconnect dielectric material layer; a second memory cell positioned laterally adjacent to the first memory cell and comprising a second T-shaped bottom electrode structure having a uniform configuration, a second MTJ pillar located on the second T-shaped bottom electrode structure, and a second top electrode structure located on the second MTJ pillar, wherein the second T-shaped bottom electrode structure is located on a surface of an isolated conductive structure embedded in the first interconnect dielectric material layer, wherein the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure include a base portion and a scaffold portion, the scaffold portion having a width greater than a width of the base portion; a second interconnect dielectric material layer overlying the first interconnect dielectric material layer and laterally surrounding the base portion of each of the first and second T-shaped bottom electrode structures, and wherein the second interconnect dielectric material layer has a concave surface; and An encapsulation liner and a third interconnect dielectric material layer are on the concave surface of the second interconnect dielectric material layer, and the encapsulation liner and the third interconnect dielectric material layer are positioned laterally adjacent to the support portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure, each of the first MTJ column and the second MTJ column, and each of the first top electrode structure and the second top electrode structure. 7 . The structure of claim 6 , wherein the first MTJ pillar and the second MTJ pillar comprise a bottom pinned MTJ material structure. 8 . The structure of claim 6 , wherein the first MTJ pillar and the second MTJ pillar comprise a top-pinned MTJ material structure.

9. The structure according to claim 6 further includes a diffusion barrier liner, which is directly located below the support portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure, and lines the side walls and bottom walls of the base portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure.

10. The structure of claim 6, further comprising a bitline contact on the third interconnect dielectric material layer and contacting surfaces of the first and second top electrode structures.

11. A method of forming a memory structure, the method comprising: forming a second interconnect dielectric material layer on an interconnect level including a conductive structure of at least one CMOS device connection embedded in the first interconnect dielectric material layer; forming at least one opening in the second interconnect dielectric material layer, wherein the at least one opening physically exposes a surface of a conductive structure to which the at least one CMOS device is connected; forming a bottom electrode metal-containing layer on the second interconnect dielectric material layer and within the at least one opening; planarizing the bottom electrode metal-containing layer a first time and a second time to provide a twice-planarized bottom electrode metal-containing layer; forming a multi-layer magnetic tunnel junction (MTJ) material stack on the twice-planarized bottom electrode metal-containing layer, and forming a top electrode metal-containing layer on the MTJ material stack; patterning the top electrode metal-containing layer, the MTJ material stack, and the twice-planarized bottom electrode metal-containing layer to provide a top electrode structure, an MTJ pillar, and a T-shaped bottom electrode structure, respectively, wherein the patterning removes an upper portion of the second interconnect dielectric material layer to provide a concave surface for the second interconnect dielectric material layer; as well as After the patterning, an encapsulation liner, a third interconnect dielectric material layer, and a bit line contact are formed on the concave surface of the second interconnect dielectric material layer. The method of claim 11 , wherein the MTJ material stack comprises a bottom pinned MTJ material stack. The method of claim 11 , wherein the MTJ material stack comprises a top-pinned MTJ material stack. 14 . The method according to claim 11 , wherein the T-shaped bottom electrode structure comprises a base portion and a support portion, the support portion having a width greater than a width of the base portion.

15. The method according to any one of claims 11 to 14, further comprising forming a diffusion barrier material layer on the second interconnect dielectric material layer and lining the at least one opening before forming the bottom electrode metal-containing layer.

16. The method of claim 15, wherein patterning further provides a diffusion barrier liner beneath the T-shaped bottom electrode structure.

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