Apparatus and method for tunable filtering

Abstract

The present application provides apparatuses and methods for tunable filtering. In certain embodiments, tunable filters are implemented using one or more controllable capacitors formed on a semiconductor die and using one or more shielded integrated inductors formed on a secondary circuit board that is attached to a carrier circuit board. Additionally, the shielded integrated inductors are formed from patterned metallization layers of the secondary circuit board and shielding is provided on the secondary circuit board and / or carrier circuit board to shield the inductors from the semiconductor die and / or other components.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic systems, and more particularly, to tunable filters for radio frequency electronic devices. Background Art

[0002] Electronic systems can use tunable filters to adjust the frequencies filtered within a signal chain. Tunable filters can be used in many different applications, including, but not limited to, base stations, mobile devices, measurement instruments, industrial electronics, military electronics, laptops, tablets, professional broadband digital radios, and compact and / or portable instruments. In contrast to fixed filters, tunable filters allow for additional flexibility for a given application by providing control over the specific frequencies filtered. Summary of the Invention

[0003] The present application provides apparatus and methods for tunable filtering. In certain embodiments, a tunable filter is implemented using one or more controllable capacitors formed on a semiconductor chip and one or more shielded integrated inductors formed on a secondary circuit board, which is attached to a carrier circuit board. In addition, the shielded integrated inductor is formed by a patterned metallization layer of the secondary circuit board, and shielding is provided on the secondary circuit board and / or the carrier circuit board to shield the inductor from the semiconductor chip and / or other components. By implementing the tunable filter in this manner, a number of advantages are achieved, including a high quality factor (Q-factor), ultra-wideband performance, and / or the ability to quickly tune.

[0004] In one aspect, a radio frequency (RF) system with tunable filtering is provided. The RF system includes a semiconductor chip having a first controllable capacitor formed thereon. The RF system further includes a first circuit board configured to be attached to a second circuit board. The first circuit board includes a first inductor structure formed therein by metallization of the first circuit board, and the first inductor structure is configured to resonate with the first controllable capacitor to provide a tunable filter. The first inductor structure is shielded from the semiconductor chip by an inductor shielding structure formed at least in part by the metallization of the first circuit board.

[0005] In another aspect, a method of tunable filtering is provided. The method includes the steps of controlling the capacitance of a controllable capacitor formed on a semiconductor chip, tuning the controllable capacitor with an inductor structure formed by metallization of the first circuit board in a first circuit board, wherein the first circuit board is attached to a second circuit board, and shielding the inductor structure from the semiconductor chip using an inductor shielding structure formed at least in part by the metallization of the first circuit board.

[0006] In another aspect, a tunable filter is provided. The tunable filter includes a controllable capacitor formed on a semiconductor chip, and an inductor structure formed in a first circuit board by metallization of the first circuit board. The first circuit board is attached to a second circuit board, and the inductor structure resonates with the controllable capacitor. The tunable filter further includes an inductor shielding structure formed at least partially by the metallization of the first circuit board and surrounding the inductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A Schematic diagram of a tunable filter according to one embodiment.

[0008] Figure 1B A schematic diagram of a tunable filter according to another embodiment is provided.

[0009] Figure 2A A schematic diagram of a cross section of a radio frequency (RF) system according to one embodiment.

[0010] Figure 2B A schematic diagram of a cross-section of an RF system according to another embodiment is provided.

[0011] Figure 3A A perspective view of a multi-turn inductor according to one embodiment.

[0012] Figure 3B A perspective view of a multi-turn inductor according to another embodiment is provided.

[0013] Figure 4A A perspective view of a pair of multi-turn inductors according to one embodiment.

[0014] Figure 4B A perspective view of a pair of multi-turn inductors according to another embodiment is provided.

[0015] Figure 5 A perspective view of a pair of multi-turn inductors according to another embodiment is provided.

[0016] Figure 6 A perspective view of a comb-type inductor structure according to one embodiment.

[0017] Figure 7A FIG2 is a perspective view of another embodiment of a pair of comb-type inductors with the top ground plate omitted.

[0018] Figure 7B for Figure 7A A perspective view of the pair of comb-type inductors, including the top ground plate.

[0019] Figure 8A A perspective view of a cross-coupled inductor structure according to one embodiment.

[0020] Figure 8B To include Figure 8A Schematic diagram of one embodiment of a cross-coupled filter of cross-coupled inductors.

[0021] Figure 8C for Figure 8B An example of a gain versus frequency plot for a cross-coupled filter.

[0022] Figure 9A A perspective view of an embodiment of a dual mode filter according to an embodiment.

[0023] Figure 9B for Figure 9A An example of a gain versus frequency plot for a dual-mode filter.

[0024] Figure 10A Schematic diagram of a tunable filter according to one embodiment.

[0025] Figure 10B A schematic diagram of a tunable filter according to another embodiment is provided.

[0026] Figure 11 Schematic diagram of one example of an RF communication system that may include one or more tunable filters in accordance with the teachings herein.

[0027] Figure 12 Schematic diagram of a controllable capacitor according to one embodiment.

[0028] Figure 13 A schematic diagram of a semiconductor chip according to one embodiment is shown. DETAILED DESCRIPTION

[0029] The detailed description of the following embodiments presents various descriptions of specific embodiments of the present invention. In this description, reference is made to the accompanying drawings, in which the same reference numerals may indicate identical or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. In addition, it should be understood that certain embodiments may include more elements and / or a subset of the elements shown in the drawings. In addition, some embodiments may include any appropriate combination of features from two or more of the accompanying drawings.

[0030] Radio frequency (RF) filters are used in a variety of applications to filter the frequency content of RF signals. For example, in wireless communication systems, RF filters may be implemented with a bandpass frequency response to limit the frequency content of RF signals to a specific frequency range or band. Such RF filters may be used in the transmit and / or receive paths of wireless communication systems. To provide additional flexibility, it is desirable to implement tunable RF filters.

[0031] Apparatus and methods for tunable filtering are provided herein. In certain embodiments, the tunable filter is implemented using one or more controllable capacitors formed on a semiconductor chip and one or more shielded integrated inductors formed on a secondary circuit board, which is attached to a carrier circuit board. Furthermore, the shielded integrated inductor is formed from a patterned metallization layer of the secondary circuit board and provides shielding on the secondary circuit board and / or the carrier circuit board to shield the inductor from the semiconductor chip and / or other components.

[0032] By implementing a tunable filter in this manner, many advantages are achieved, including a high quality factor (Q-factor), ultra-wideband performance, and / or the ability to quickly tune. In contrast, tunable filters implemented using lumped inductors are bulky, costly, and / or require component changes for adjustment and calibration.

[0033] In some embodiments, the semiconductor chip is mounted to a first side of a carrier circuit board, while the secondary circuit board is mounted to a second side of the carrier circuit board, opposite the first side. Thus, the controllable capacitor on the semiconductor chip can be connected to the inductor on the secondary circuit board via the carrier circuit board. In other embodiments, the semiconductor chip is mounted to the secondary circuit board, which is in turn mounted to the carrier circuit board.

[0034] Shielded integrated inductors can be implemented in various ways, including but not limited to using a multi-wound inductor structure and / or a comb-type inductor structure. When multiple inductors are formed in a secondary circuit board, shielding can be provided between the inductors or can be omitted, for example, to form a cross-coupled filter structure and / or a dual-mode filter.

[0035] The tunable filter herein can provide filtering for RF signals of various signal frequencies, including but not limited to signals in the very high frequency (VHF) range (30 megahertz (MHz) to 300 MHz) or the ultra high frequency (UHF) range (300 MHz to 3 gigahertz (GHz)).

[0036] Figure 1A FIG. 1 is a schematic diagram of a tunable filter 10 according to an embodiment. In this embodiment, the tunable filter 10 is implemented using a semiconductor chip 1 , a carrier circuit board 2 , and a secondary circuit board 3 .

[0037] like Figure 1A As shown, the semiconductor chip 1 includes controllable capacitors 5a, 5b, ... 5n. Although three controllable capacitors are depicted, the semiconductor chip 1 may include more or fewer controllable capacitors. The semiconductor chip 1 is attached to a first side 4a of a carrier circuit board 2. Figure 1A The semiconductor chip 1 of the semiconductor chip is also referred to herein as an integrated circuit (IC).

[0038] In some embodiments, the carrier circuit board 2 is a multi-layer circuit board, such as a printed circuit board (PCB). Figure 1A Not depicted, other components may be attached to the carrier circuit board 2, such as one or more other semiconductor chips, integrated passive devices (IPDs), or surface mount devices (SMDs). Such components may be attached to either or both sides of the carrier circuit board 2.

[0039] Continue to refer Figure 1A Secondary circuit board 3 is attached to second side 4b of carrier circuit board 2, such that secondary circuit board 3 and semiconductor chip 1 are located on opposite sides of carrier circuit board 2. Secondary circuit board 3 includes multiple conductive layers (e.g., copper metal layers separated from each other by a dielectric), and an inductor structure is formed from these conductive layers. In particular, secondary circuit board 3 includes shielded integrated inductors 6a, 6b, ..., 6n formed from the conductive layers of a patterned board. Although three shielded integrated inductors are depicted, more or fewer shielded integrated inductors may be included.

[0040] Shielded integrated inductors 6a, 6b, ..., 6n are shielded from semiconductor chip 1. Thus, electromagnetic interference from inductors 6a, 6b, ..., 6n is prevented from reaching semiconductor chip 2. In some embodiments, a metal layer of a circuit board is used to form a ground plane interposed between shielded integrated inductors 6a, 6b, ..., 6n and semiconductor chip 1, thereby allowing the semiconductor chip to be positioned directly above one or more inductors. Such a ground plane can be formed on a layer of carrier circuit board 2 or on a layer (e.g., the top or outermost layer) of secondary circuit board 3, between inductors 6a, 6b, ..., 6n and semiconductor chip 1.

[0041] In some embodiments, the conductive layer of the secondary circuit board 3 is patterned to form a cage surrounding the shielded integrated inductors 6a, 6b, ..., 6n. The cage can be grounded. Thus, in some embodiments, grounded metal can surround the shielded integrated inductors 6a, 6b, ..., 6n on all sides.

[0042] Controllable capacitors 5a, 5b, ..., 5n are connected to shielded integrated inductors 6a, 6b, ..., 6n to form inductor-capacitor (LC) resonators. Such LC resonators can be connected together to provide one or more tunable filters for filtering the signal content of RF signals. LC resonators can be connected together to form a variety of filtering circuits. Although shown with a one-to-one correspondence between controllable capacitors and inductors, other embodiments are possible. Therefore, the number of controllable capacitors and inductors does not need to be the same.

[0043] The tunable filter can be at least partially controlled by varying the capacitance of the LC resonator. In one example, the controllable capacitors 5a, 5b, ..., 5n each comprise a set of selectable capacitor cells, and data received from the interface of the semiconductor chip 1 can be used to select the capacitance value of this set, thereby providing tuning. In a second example, the controllable capacitors 5a, 5b, ..., 5n each comprise a varactor with analog tuning. Although two tuning examples are provided, the teachings herein are applicable to a variety of tuning implementations. In certain embodiments, the inductance of the LC resonator can also be tuned, for example, by using switches to change the length of the inductor and / or control the number of inductors connected in series or in parallel.

[0044] Figure 1B FIG. 2 is a schematic diagram of a tunable filter 20 according to another embodiment. Figure 1B The tunable filter 20 is similar to Figure 1A The tunable filter 10 is different in that in the tunable filter 20, the secondary circuit board 3 is inserted between the semiconductor chip 1 and the carrier circuit board 2. In particular, the semiconductor chip 1 is attached to the first side of the secondary circuit board 3, while the second side of the secondary circuit board 3 is attached to the first side 4a of the carrier circuit board 2.

[0045] To provide shielding between the shielded inductor structures 6a, 6b, ..., 6n and the semiconductor chip 1, the secondary circuit board 3 may include a ground plane on the metal layer between the inductors 6a, 6b, ..., 6n and the semiconductor chip 1. For example, the top or outermost conductive layer of the secondary circuit board 3 may be used to form such a ground plane. The secondary circuit board 3 may also include walls that form part of a grounding cage to shield the inductors 6a, 6b, ..., 6n from the semiconductor chip 1. A bottom ground plane may also be included on the secondary circuit board 3 or the carrier circuit board 2.

[0046] Figure 2A A schematic diagram of a cross-section of an RF system 50 according to one embodiment is shown. The RF system 50 includes a semiconductor chip 21 (including at least one controllable capacitor formed thereon), a secondary circuit board 22, a carrier circuit board 23, a first multi-wound inductor 24a, a second multi-wound inductor 24b, a first metal connector 25a, a second metal connector 25b, an inductor shielding structure 26, a front-side component 27, a back-side component 28, solder balls 30, copper pillars 31, and an RF shield 32.

[0047] In the illustrated embodiment, the secondary circuit board 22 includes two shielded inductor structures, corresponding to a first multi-wrap inductor 24a and a second multi-wrap inductor 24b. These shielded inductor structures are formed from a conductive layer (e.g., a patterned metallization layer separated by a dielectric) of the secondary circuit board 22. Although two shielded inductor structures are depicted, the secondary circuit board 22 can be adapted to include more or fewer shielded inductor structures. Furthermore, although an example with multi-wrap inductors is depicted, the secondary circuit board 22 can be implemented to include other types of inductors. Multi-wrap inductors are also referred to herein as multi-turn inductors.

[0048] Secondary circuit board 22 can correspond to various types of multilayer circuit boards, such as PCBs. In some embodiments, secondary circuit board 22 corresponds to a PCB with a single lamination step. Thus, secondary circuit board 22 can be implemented using a low-cost process, helping to achieve a low-cost and scalable overall RF system.

[0049] In some embodiments, the PCB comprises at least three conductive layers. In some embodiments, the conductive layers are copper, such as low-resistance thick copper.

[0050] Using PCB technology to form inductors 24a and 24b also offers the advantages of tight tolerances and controlled repeatability relative to lumped technology.

[0051] like Figure 2A As shown, semiconductor chip 21 is attached to first side 48a of carrier circuit board 23. In this example, semiconductor chip 21 is connected using copper pillars 31 in a flip-chip configuration. Using a flip-chip configuration with copper pillars 31 provides low inductance and low resistance to help achieve a high quality factor (Q-factor), broadband operation, and / or high frequency operation. In addition, a flip-chip configuration can be associated with low radiation and parasitics. However, other embodiments are also possible, such as a configuration using wire bonding.

[0052] In the illustrated embodiment, the secondary circuit board 22 is attached to the second side 48b of the carrier circuit board 23. In this example, solder balls 30 are used to provide connectivity between the secondary circuit board 22 and the carrier circuit board 23, for example, using a ball grid array (BGA). However, other embodiments are possible, such as using a land grid array (LGA).

[0053] Although for the sake of clarity in the diagram Figure 2A Although not depicted, the semiconductor chip 21 includes at least one controllable capacitor. In addition, metal connections are provided through the carrier circuit board 23 to provide the desired electrical connection between the controllable capacitor on the semiconductor chip 21 and the shielded integrated inductor formed in the secondary circuit board 22.

[0054] For example, in the illustrated embodiment, a first metal connector 25a is provided for connecting the first end of the first multi-turn inductor 24a to a first pin of the semiconductor chip 21 (or in parallel to a first group of pins to reduce inductance), and a second metal connector 25b is provided for connecting the first end of the second multi-turn inductor 24b to a second pin of the semiconductor chip 21 (or to a second group of pins).

[0055] In the illustrated embodiment, the second end of the first multi-turn inductor 24a and the second end of the second multi-turn inductor 24b are connected to the inductor shielding structure 26, which is grounded. However, other embodiments are possible, such as a configuration that also includes metal connections through the carrier circuit board 23 for connecting the second ends of the inductors 24a and 24b to corresponding pins (or pin groups) on the semiconductor chip 21.

[0056] The carrier circuit board 23 may also include input / output connections for the semiconductor chip 21 and / or the secondary circuit board 22. In some embodiments, the carrier circuit board 23 is a custom circuit board that can be modified for a specific application. Thus, the semiconductor chip 21 and the secondary circuit board 22 can be deployed in a wide variety of applications, and minor modifications can be made to the form and fit of the custom circuit board to accommodate specific RF frequency ranges and / or maintain confidentiality regarding the RF operating frequency.

[0057] like Figure 2A As shown in FIG, the inductor shielding structure 26 provides shielding between the inductor integrated in the secondary circuit board 22 and other components, including the semiconductor chip 21. The inductor shielding structure 26 acts as a grounded metal surrounding the inductors 24a and 24b on all sides.

[0058] In the illustrated embodiment, the inductor shielding structure 26 includes a bottom ground plate 41, a grounding wall 42, and a top ground plate 43, which are interposed between the semiconductor chip 21 and the inductors 24a and 24b. An opening is provided in the top ground plate 43 to allow passage of electrical connection between the semiconductor chip 21 and the inductors 24a and 24b formed in the secondary circuit board 22.

[0059] However, other embodiments of the inductor shielding structure are possible. In one example, a grounding wall is included between inductors 24a and 24b, which run from bottom ground plane 41 to ground plane 43 through the BGA. Implementing the inductor shielding structure in this manner provides electrical isolation between the inductors. However, such a grounding wall can be omitted or included in a modified form to provide magnetic coupling between the inductors within secondary circuit board 22.

[0060] The top ground plane 43 is also used to limit electromagnetic radiation from the semiconductor chip 21 to other components.

[0061] In the illustrated embodiment, a portion of the top ground plane 43 and the wall 42 are formed in the carrier circuit board 23, while another portion of the bottom ground plane 41 and the wall 42 are formed in the secondary circuit board 22. Thus, the resonant cavity in which the inductor resides is implemented on both the carrier circuit board 23 and the secondary circuit board 22. By implementing the inductor shielding structure 26 on both the secondary circuit board 22 and the carrier circuit board 23, a smaller height H1 of the resonant component is achieved relative to implementing the shielding entirely on the secondary circuit board 22.

[0062] In certain embodiments, the inductor shielding structure 26 provides shielding for both electromagnetic interference (EMI) and electromagnetic compatibility (EMC).

[0063] In the illustrated embodiment, the inductor shielding structure 26 shields multiple inductors. Thus, a more compact area is achieved using a separate EMI / EMC shield for each inductor coil relative to a large conventional coil.

[0064] like Figure 2A As shown, semiconductor chip 21 and front-side components 27 are attached to first side 48a of carrier circuit board 23. Additionally, RF shield 32 is attached to first side 48a of carrier circuit board 23 to enclose semiconductor chip 21 and front-side components 27 within the cavity. Due to the low profile or height of semiconductor chip 21, the front side of carrier circuit board 23 also has a low profile. In some embodiments, front-side components 27 include RF components that can be connected to semiconductor chip 21 via connectors via carrier circuit board 23. Examples of front-side components 27 include other semiconductor chips, IPDs, and / or SMDs.

[0065] Continue to refer Figure 2A , backside assembly 28 is connected to the second side of carrier circuit board 23. In some embodiments, backside assembly 28 includes low-frequency or DC components, which may include, for example, other semiconductor chips, connectors, and / or other components. Because backside assembly 28 can be tall, including secondary circuit board 22 on second side 48b of carrier circuit board 23 has little impact on the overall height of the system. Inductor shielding structure 26 helps prevent the electromagnetic field generated by inductors 24a and 24b from reaching backside assembly 28.

[0066] Figure 2B According to another embodiment, a schematic diagram is shown of a cross section of an RF system 60. The RF system 60 includes a semiconductor chip 21 (including at least one controllable capacitor thereon), a secondary circuit board 22', a carrier circuit board 23', a first multi-turn inductor 24a, a second multi-turn inductor 24b, a first metal connector 25a, a second metal connector 25b, an inductor shielding structure 26', a front-side component 27, a back-side component 28, solder balls 30, copper pillars 31, and an RF shield 32'.

[0067] Compared to Figure 2A RF system 50, Figure 2B RF system 60 includes a different arrangement of semiconductor chip 21, secondary circuit board 22', and carrier circuit board 23'. Specifically, semiconductor chip 21 is attached to a first side of secondary circuit board 22', and a second side of secondary circuit board 22' is attached to first side 48a of carrier circuit board 23'. Additionally, RF shield 32' is attached to first side 48a of carrier circuit board 23' and surrounds semiconductor chip 21, secondary circuit board 22', and front-side component 27 within the cavity.

[0068] In the illustrated embodiment, the secondary circuit board 22′ includes a first multi-turn inductor 24a and a second multi-turn inductor 24b, which are formed in the secondary circuit board by a patterned conductive layer of the secondary circuit board 22′. Although an example with two multi-turn inductors is depicted, the secondary circuit board 22′ may be implemented with more or fewer inductors and / or different types of inductors.

[0069] Inductors 24a and 24b are shielded by inductor shielding structure 26'. Figure 2A The inductor shielding structure 26, Figure 2B The inductor shielding structure 26' is entirely formed on the secondary circuit board 22'. Figure 2B The height H2 of the resonant component is greater than Figure 2A The height H1 of the resonant component.

[0070] like Figure 2B As shown, inductor shielding structure 26' includes a bottom ground plane 41', walls 42', and a top ground plane 43. Top ground plane 43 includes openings for electrical connections 25a and 25b between the pins of semiconductor chip 21 and the first ends of inductors 25a and 25b. Furthermore, in this example, the second ends of inductors 25a and 25b are grounded to bottom ground plane 41' via connectors.

[0071] Although an example is shown with no shielding between inductors 24a and 24b, other embodiments include a grounded wall between the inductors.

[0072] Figure 3A A perspective view of a multi-turn inductor 120 according to one embodiment includes a first turn 101 , a second turn 102 , a third turn 103 , a fourth turn 104 , a first leg 111 , a second leg 112 , a third leg 113 , a fourth leg 114 , and a fifth leg 115 .

[0073] The multi-turn inductor 120 illustrates one embodiment of an inductor structure that may be formed in a secondary circuit board. However, the teachings herein are applicable to inductor structures implemented in other ways.

[0074] In the illustrated embodiment, the first turn 101 is formed in a first patterned metallization layer of the secondary circuit board, the second turn 102 is formed in a second patterned metallization layer of the secondary circuit board, the third turn 103 is formed in a third patterned metallization layer of the secondary circuit board, and the fourth turn 104 is formed in a fourth patterned metallization layer of the secondary circuit board. Figure 3A The dielectric between the metallization layers is not depicted.

[0075] The first leg 111 is connected to one end of the first turn 101 and serves as a first terminal of the multi-turn inductor 120. The second leg 112 is connected to one end of the fourth turn 104 and serves as a second terminal of the multi-turn inductor 120.

[0076] Third leg 113 connects first turn 101 to second turn 102. Additionally, fourth leg 114 connects second turn 102 to third turn 103, while fifth leg 115 connects third turn 103 to fourth turn 104. In certain embodiments, one or more of legs 113, 114, or 115 serve as terminals for tapping multi-turn inductor 120. For example, leg 114 may serve as a center tap of multi-turn inductor 120. Such a tap may be connected to a pin of a semiconductor chip to facilitate implementation of a tunable filter topology utilizing the tapped inductor.

[0077] Figure 3B According to another embodiment, a perspective view of a multi-turn inductor 130 is shown. The multi-turn inductor 130 includes a first turn 101', a second turn 102', a third turn 103', a fourth turn 104', a first leg 111', a second leg 112', a third leg 113', a fourth leg 114', and a fifth leg 115'.

[0078] The multi-turn inductor 130 illustrates another embodiment of an inductor structure that may be formed in a secondary circuit board. However, the teachings herein are applicable to inductor structures implemented in other ways.

[0079] Figure 3B The multi-turn inductor 130 is similar to Figure 3A The multi-turn inductor 120 is different in that Figure 3B The multi-turn inductor 130 is implemented with a tighter number of turns.

[0080] By adjusting the number of turns and / or length, the desired total inductance of the multi-turn inductor can be achieved.

[0081] Figure 4A FIG. 1 is a perspective view of a pair of multi-turn inductors 170 according to one embodiment. The pair of multi-turn inductors 170 includes a first multi-turn inductor 120a, a second multi-turn inductor 120b, and a plurality of pillars 151.

[0082] This pair of multi-turn inductors 170 illustrates another embodiment of an inductor structure that may be formed in a secondary circuit board. However, the teachings herein are applicable to inductor structures implemented in other ways.

[0083] In the embodiment shown, according to Figure 3A The multi-turn inductors 120 are respectively implemented as a first multi-turn inductor 120a and a second multi-turn inductor 120b.

[0084] like Figure 4A As shown, the posts 151 form walls around the sides of the pair of multi-turn inductors 170. In some embodiments, the posts 151 are grounded.

[0085] Figure 4B According to another embodiment, a perspective view of a pair of multi-turn inductors 180 is shown. The pair of multi-turn inductors 180 includes a first multi-turn inductor 120a, a second multi-turn inductor 120b, a first plurality of pillars 151, and a second plurality of pillars 152. The number of the plurality of pillars 152 can be increased or decreased to control the amount of magnetic coupling between the inductors 120a and 120b.

[0086] This pair of multi-turn inductors 180 illustrates another embodiment of an inductor structure that may be formed in a secondary circuit board. However, the teachings herein are applicable to inductor structures implemented in other ways.

[0087] Figure 4B This pair of multi-turn inductors 180 is similar to Figure 4A The pair of multi-turn inductors 170 is different in that the pair of multi-turn inductors 180 further includes a post 152 providing shielding between the first multi-turn inductor 120a and the second multi-turn inductor 120b. In some embodiments, both the post 151 and the post 152 are grounded.

[0088] Figure 5 According to another embodiment, a perspective view of a pair of multi-turn inductors 190 is shown. The pair of multi-turn inductors 190 includes a first multi-turn inductor 181a, a second multi-turn inductor 181b, a plurality of pillars 182, and a ring 183. Although the ring 183 is depicted as solid, it need not be continuous. For example, the ring 183 may be formed from the same metal layer used for inductors 181a and 181b.

[0089] This pair of multi-turn inductors 190 illustrates another embodiment of an inductor structure that may be formed in a secondary circuit board. However, the teachings herein are applicable to inductor structures implemented in other ways.

[0090] like Figure 5As shown, the first multi-turn inductor 181a and the second multi-turn inductor 181b are surrounded by pillars 182, which act as walls that shield the sides of the inductors along the outer perimeter. In addition, rings 183 are integrated into these walls to further enhance the shielding effect. In some embodiments, the pillars 182 and the rings 183 are grounded.

[0091] Figure 6 A perspective view of a comb-type inductor structure 220 according to one embodiment. The comb-type inductor structure 220 includes a first comb-type inductor 201a, a second comb-type inductor 201b, a third comb-type inductor 202a, a fourth comb-type inductor 202b, and a ground plane 204. Figure 6 Only the bottom portion of the ground plate 204 is shown in FIG, but the ground plate 204 may surround the inductor on all four side walls and / or be located above the inductor.

[0092] Comb-type inductor structure 220 illustrates another embodiment of an inductor structure that may be formed in a secondary circuit board. However, the teachings herein are applicable to inductor structures implemented in other ways.

[0093] like Figure 6 , depicts a first terminal 211, a second terminal 212, a third terminal 213, a fourth terminal 214, a fifth terminal 215, and a sixth terminal 216. In some embodiments, each of the first terminal 211, the second terminal 212, the third terminal 213, and the fourth terminal 214 is connected to a controllable capacitor formed on the semiconductor chip, thereby forming a resonant structure. In some embodiments, the fifth terminal 215 and the sixth terminal 216 serve as input / output terminals.

[0094] Figure 7A FIG. 2 is a perspective view of another embodiment of a pair of comb-type inductors 240 , in which the top ground plate 233 is omitted. Figure 7B for Figure 7A FIG. 2 is a perspective view of a pair of comb-type inductors 240 including a top ground plate 233 .

[0095] This pair of comb inductors 240 includes a first comb inductor 231a, a second comb inductor 231b, and a post 232 surrounding each comb inductor, thereby surrounding both combs 231a and 231b and acting as a wall therebetween.

[0096] Figure 8A A perspective view of a cross-coupled inductor structure 250 according to one embodiment is shown. The cross-coupled inductor structure 250 includes a first comb-type inductor 241a, a second comb-type inductor 241b, a third comb-type inductor 241c, a fourth comb-type inductor 241d, and a pillar 244. For clarity, the ground planes above and below the structure have been omitted from the drawing.

[0097] Cross-coupled inductor structure 250 illustrates another embodiment of an inductor structure that may be formed in a secondary circuit board. However, the teachings herein are applicable to inductor structures implemented in other ways.

[0098] like Figure 8A As shown, the first comb-type inductor 241a is cross-coupled to the second comb-type inductor 241b due to the omission of posts 244 between these inductors. Posts 244 act as walls that otherwise shield the inductors from each other and from external components. By controlling the number and position of posts 244 between the comb-type inductors, the desired cross-coupling can be achieved.

[0099] By providing cross-coupling, a band-stop feature can be provided. For example, such a band-stop feature can be magnetically connected from the first resonator to the last resonator by adjusting the ground vias or posts. Although cross-coupling with a comb-type inductor is depicted, other types of inductors can also be cross-coupled.

[0100] Figure 8B To include Figure 8A Schematic diagram of an embodiment of a cross-coupled filter 260 of a cross-coupled inductor structure 250. The cross-coupled filter 260 includes a first inductor 251a, a second inductor 251b, a third inductor 251c and a fourth inductor 251d, which can be used Figure 8A The cross-coupled filter 260 further includes a first capacitor 252a, a second capacitor 252b, a third capacitor 252c, a fourth capacitor 252d, a fifth capacitor 252e, a sixth capacitor 252f, a seventh capacitor 252g, an eighth capacitor 252h, and a ninth capacitor 252i, any or all of which may be controllable.

[0101] Figure 8C for Figure 8B FIG. 2 is an example of a gain versus frequency graph of the cross-coupling filter 260. This graph depicts example performance of a constant 3 dB bandwidth and cross-coupling providing a band-limited response.

[0102] Figure 9A A perspective view of one embodiment of a dual mode filter 280 according to one embodiment. Figure 9A The dual-mode filter 280 is similar to Figure 6 The comb-type inductor structure 220 is different in that the dual-mode filter 280 further includes a first controllable capacitor 271, a second controllable capacitor 272, a third controllable capacitor 273, and a fourth controllable capacitor 274 connected as shown. The controllable capacitors depicted are formed on a semiconductor chip (now Figure 9A shown in ).

[0103] Figure 9B for Figure 9A An example of a gain versus frequency graph for the dual-mode filter 280 is shown in FIG.

[0104] refer to Figure 9A and Figure 9B The examples shown utilize complex resonators with more than one resonant mode. The added resonant modes allow for an adjustable band-stop response (e.g., a notch). Such adjustable notches also allow for a sharper band-stop response without significantly impacting the passband insertion loss. In certain embodiments, the resonant modes include at least one differential or odd-mode resonance and at least one common or even-mode resonance.

[0105] Figure 10A A schematic diagram of a tunable filter 910 according to one embodiment is shown. The tunable filter 910 includes series inductors 901A, 901B, ..., 901N and parallel capacitors 902A, 902B, ..., 902N electrically connected between an input terminal (IN) and an output terminal (OUT), as shown. Any number of inductors and / or capacitors may be included, and any combination of components may be controlled.

[0106] Control circuit (in Figure 10A (not shown) the component values ​​of the controllable components can be adjusted to achieve tuning.

[0107] Figure 10B According to another embodiment, a schematic diagram of a tunable filter 920 is shown. Tunable filter 920 includes series capacitors 911A, 911B, ..., 911N and parallel inductors 912A, 912B, ..., 912N electrically connected between an input (IN) and an output (OUT), as shown. Any number of inductors and / or capacitors may be included, and any combination of components may be controlled.

[0108] Control circuit (in Figure 10B (not shown) the component values ​​of the controllable components can be adjusted to achieve tuning.

[0109] In one embodiment, Figure 10B The tunable filter 920 is Figure 10A The tunable filters 910 are arranged in cascade (in any order or sequence) to provide a tunable bandpass filter.

[0110] In some embodiments, a tunable filter such as Figure 10A Tunable filter 910 or Figure 10B The tunable filter 920 is implemented with low impedance to increase linear performance in the presence of AC voltage swings.

[0111] Figure 11Schematic diagram of one example of an RF communication system 1010 that may include one or more tunable filters in accordance with the teachings herein.

[0112] Although RF communication system 1010 illustrates one example of an electronic system that may include one or more tunable filters described herein, tunable filters may also be used in other configurations of electronic systems.

[0113] In addition, despite Figure 11 Although a specific configuration of components is shown in FIG, RF communication system 1010 can be adapted and modified in various ways. For example, RF communication system 1010 can include more or fewer receive paths and / or transmit paths. Additionally, RF communication system 1010 can be modified to include more or fewer components and / or different arrangements of components, including, for example, different arrangements of RF switching circuits, amplifiers, and / or filters.

[0114] In the illustrated configuration, the RF communication system 1010 includes a baseband processor 1001, an I / Q modulator 1002, an I / Q demodulator 1003, a first tunable filter 1005A, a power amplifier 1006, a transmit / receive (T / R) switch 1007, a low noise amplifier (LNA) 1008, an antenna 1009, a second tunable filter 1005B, and a third tunable filter 1005C. While the first through third tunable filters 1005A-1005C are exemplary uses of tunable filters, other placements of tunable filters in the transmit and / or receive paths of the RF communication system 1010 are possible.

[0115] like Figure 11 As shown, baseband processor 1001 generates an in-phase (I) transmission signal and a quadrature-phase (Q) transmission signal, which are provided to I / Q modulator 1002. Additionally, baseband processor 1001 receives an I receive signal and a Q receive signal from I / Q demodulator 1003. The I and Q transmission signals correspond to signal components of the transmission signal having a specific amplitude, frequency, or phase. For example, the I transmission signal and the Q transmission signal represent an in-phase sinusoidal component and a quadrature-phase sinusoidal component, respectively, and may be equivalent representations of the transmission signal. Furthermore, the I and Q receive signals correspond to signal components of the receive signal having a specific amplitude, frequency, and phase.

[0116] In some embodiments, the I transmission signal, the Q transmission signal, the I reception signal, and the Q reception signal are digital signals. Alternatively, the baseband processor 1001 may include a digital signal processor, a microprocessor, or a combination thereof for processing digital signals.

[0117] The I / Q modulator 1002 receives and processes the I and Q transmit signals from the baseband processor 1001 to generate a modulated RF signal. In some configurations, the I / Q modulator 1002 may include a DAC configured to convert the I and Q transmit signals into an analog format, a mixer for up-converting the I and Q transmit signals to a radio frequency, and a signal combiner for combining the up-converted I and Q signals into a modulated RF signal.

[0118] The first tunable filter 1005A receives the modulated RF signal from the I / Q modulator 1002 and provides the filtered RF signal to the input of the power amplifier 1006. In certain configurations, the first tunable filter 1005A can be configured to provide a bandpass filter, wherein the lower and upper cutoff frequencies of the bandpass are tunable based on an input control signal received by the first tunable filter 1005A. In some embodiments, the first tunable filter 1005A can also be configured to implement a low-pass filter, a bandpass filter, a notch filter, a high-pass filter, or a combination thereof based on the input control signal. Thus, the specific set of frequencies filtered by the first tunable filter 1005A can be adjusted using the input control signal applied to the first tunable filter 1005A.

[0119] The power amplifier 1006 can amplify the filtered RF signal to generate an amplified RF signal, which is provided to the transmit / receive switch 1007. The transmit / receive switch 1007 is further electrically connected to the second tunable filter 1005B and the input of the low-noise amplifier 1008. The second tunable filter 1005B is connected to the antenna 1009. Thus, in this example, the power amplifier 1006 provides the amplified RF signal to the antenna 1009 via the transmit / receive switch 1007 and the second tunable filter 1005B. However, other embodiments are possible, such as a configuration in which the second tunable filter 1005B is omitted.

[0120] In certain configurations, the second tunable filter 1005B can be configured to operate similarly to the first tunable filter 1005A, for example, by selectively implementing a bandpass filter, a lowpass filter, a notch filter, a highpass filter, or a combination thereof based on a control input signal received at the second tunable filter 1005B. Thus, the specific set of frequencies filtered by the second tunable filter 1005B can be adjusted using the input control signal applied to the second tunable filter 1005B.

[0121] The transmit / receive switch 1007 can be used to selectively connect the antenna 1009 (via the second tunable filter 1005B) to the output of the power amplifier 1006 or the input of the low noise amplifier 1008. In some embodiments, the transmit / receive switch 1007 can provide many other functions, including but not limited to frequency band switching and / or switching between different power modes.

[0122] The LNA 1008 receives the antenna receive signal from the transmit / receive switch 1007 and generates an amplified antenna receive signal that is provided to the fourth tunable filter 1005C, which is configured to filter the receive signal and provide the filtered receive signal to the I / Q demodulator 1003 .

[0123] In certain configurations, the third tunable filter 1005C can be configured to operate similarly to the first tunable filter 1005A, for example, by selectively implementing a bandpass filter, a lowpass filter, a notch filter, a highpass filter, or a combination thereof based on an input signal received at the third tunable filter 1005C.

[0124] This I / Q demodulator 1003 can be used to generate an I receive signal and a Q receive signal, as described above. In some configurations, the I / Q demodulator 1003 can include a pair of mixers for attenuating the mixing of the receive signal with a pair of clock signals that are approximately 90 degrees out of phase. Alternatively, the mixers can generate down-converted signals that can be provided to an ADC for generating the I and Q receive signals.

[0125] Figure 12 Schematic diagram of a controllable capacitor 1140 according to one embodiment. Controllable capacitor 1140 includes a first set of field effect transistors (FETs) 1101a, 1101b, ..., 1101n, a second set of FETs 1102a, 1102b, ..., 1102n, a first set of capacitors 1103a, 1103b, ..., 1103n, a second set of capacitors 1104a, 1104b, ..., 1104n, a control circuit 1105, a first set of gate resistors 1111a, 1111b, ..., 1111n, and a second set of gate resistors 1112a, 1112b, ..., 1112n.

[0126] Controllable capacitor 1140 illustrates one embodiment of a controllable capacitor that can be included on a semiconductor chip and used in a tunable filter. However, the teachings herein are applicable to other embodiments of controllable capacitors. Furthermore, although a single controllable capacitor is depicted, multiple controllable capacitors can be included on a semiconductor chip.

[0127] Implementing controllable capacitors on semiconductor chips may offer numerous advantages, such as low equivalent series resistance (ESR), small size, low cost, and / or low reactance.

[0128] In the embodiment shown, the controllable circuit 1140 is implemented using a plurality of circuit branches connected in parallel between a first RF terminal RF1 and a second RF terminal RF2, which in some embodiments are connected to pins of a semiconductor chip. Additionally, in this embodiment, each circuit branch comprises a series combination of a pair of FETs and a pair of capacitors. For example, Figure 12 The leftmost branch of comprises a series combination of FET 1101a, capacitor 1103a, capacitor 1104a and FET 1102a.

[0129] In certain embodiments, the controllable capacitor is implemented with a multi-finger array feed (eg, feeds to terminals RF1 and / or RF2 and / or feeds to separate branches) to help provide a low reactance capacitor with low ESR.

[0130] like Figure 12 As shown, control circuit 1105 selectively enables any desired number of branches based on data received from interface 1108. This interface corresponds to any interface of the semiconductor chip, including but not limited to a serial interface or bus. By enabling the desired number of branches, the capacitance between the first RF terminal RF1 and the second RF terminal RF2 is controlled.

[0131] The control circuit 1105 selects a specific branch by turning on or off the FET in that branch. Figure 12 As shown, the control circuit provides control signals to each branch through a gate resistor that provides isolation. Although an example with two FETs per branch is shown, more or fewer FETs may be included to achieve the desired power handling capability. The FETs may be implemented in various ways, including but not limited to metal oxide semiconductor FETs (MOSFETs), such as those manufactured using a silicon-on-insulator (SOI) process.

[0132] In certain embodiments, a shared control circuit is used when multiple controllable capacitors are present. Additionally, the control circuit can control multiple controllable capacitors using a single control or using joint (common) tuning.

[0133] In the illustrated embodiment, each branch includes a pair of capacitors. By including multiple capacitors in series, enhanced linearity and / or smaller capacitance step sizes can be achieved relative to implementations with a single capacitor in each branch. While an example with two capacitors per branch is shown, more or fewer capacitors may be included. The capacitors can be implemented in various ways, including but not limited to metal-insulator-metal (MIM) capacitors.

[0134] The FETs and capacitors in each branch can have any desired size. In some embodiments, the capacitors in each branch are weighted according to a desired weighting scheme. By weighting the capacitors, a wider capacitance tuning range can be achieved compared to embodiments where each branch has a fixed weight. The capacitor sizes can be weighted or unweighted depending on the implementation.

[0135] In the illustrated embodiment, the control circuit 1105 includes a memory 1106 that stores a lookup table (LUT) 1107. The memory 1106 can be used to store capacitance settings for the controllable capacitor 1140, thereby allowing for rapid switching between filter states. For example, the LUT 1107 can be used to map capacitance settings (e.g., which branch combination is selected) to a desired input frequency. In certain embodiments, an interface 1108 is used to write to the memory 1105 and / or for a user to indicate a desired center frequency range and / or bandwidth for the tunable filter.

[0136] Figure 13 Schematic diagram of a semiconductor chip 1150 according to one embodiment. The semiconductor chip 1150 includes various controllable capacitors, including FETs and a capacitor bank 1141 (which may be used, for example, Figure 12 ), a PIN diode and capacitor group 1142, a diode varactor 1143, a microelectromechanical system (MEMS) capacitor 1144 and a barium strontium titanate (BST) capacitor 1145.

[0137] Although five examples of controllable capacitors are shown, the teachings herein are applicable to a wide range of controllable capacitors. In particular, any suitable controllable capacitor may be used in accordance with the tunable filters herein.

[0138] application

[0139] Devices employing the above-described schemes can be implemented as various electronic devices. Examples of electronic devices include, but are not limited to, RF communication systems, consumer electronics, electronic test equipment, communication infrastructure, and the like. For example, tunable filters can be used in a wide range of RF communication systems, including, but not limited to, base stations, mobile devices, measurement instruments, industrial electronics, military electronics, laptops, tablets, professional broadband digital radios, and compact and / or portable instruments. The teachings herein are applicable to RF communication systems operating over a wide range of frequencies and frequency bands, including those using time division duplexing (TDD) and / or frequency division duplexing (FDD).

[0140] in conclusion

[0141] The foregoing description may refer to elements or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, and is not necessarily mechanically connected. Similarly, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, and is not necessarily mechanically coupled. Thus, although the various schematics shown in the drawings depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in actual embodiments (assuming the functionality of the depicted circuitry is not adversely affected).

[0142] Although the present invention has been described with respect to certain embodiments, other embodiments readily apparent to those skilled in the art, including embodiments that provide some of the features and advantages described herein, also fall within the scope of the present invention. Furthermore, the various embodiments described above may be combined to provide further embodiments. Furthermore, certain features described in the context of one embodiment may also be incorporated into other embodiments. Accordingly, the scope of the present invention is defined solely by reference to the appended claims.

Claims

1. A radio frequency (RF) system with tunable filtering, the RF system comprising: a semiconductor chip including a first controllable capacitor formed thereon; as well as a first circuit board comprising a first inductor structure formed therein by metallization of the first circuit board, the first inductor structure being configured to resonate with the first controllable capacitor to provide a tunable filter, wherein the first inductor structure is shielded from the semiconductor chip by an inductor shielding structure formed at least in part by the metallization of the first circuit board. 2 . The RF system of claim 1 , wherein each side of the first inductor structure is shielded by the inductor shielding structure. 3 . The RF system of claim 1 , further comprising a second circuit board, the first circuit board being configured to be attached to the second circuit board. 4 . The RF system of claim 3 , wherein a first portion of the inductor shielding structure is formed on the first circuit board, and a second portion of the inductor shielding structure is formed on the second circuit board. 5 . The RF system of claim 3 , wherein the semiconductor chip is attached to a first side of the second circuit board, and the first circuit board is attached to a second side of the second circuit board opposite to the first side. 6 . The RF system of claim 5 , further comprising an RF shield located on the first side of the second circuit board and enclosing the semiconductor chip in a cavity. 7 . The RF system of claim 3 , wherein the semiconductor chip is attached to a first side of the first circuit board, and the second circuit board is attached to a second side of the first circuit board opposite the first side.

8. The RF system of claim 1 , wherein the semiconductor chip further comprises a second controllable capacitor, and the first circuit board further comprises a second inductor structure formed therein by the metallization of the first circuit board, wherein the second controllable capacitor and the second inductor structure operate in the tunable filter.

9. The RF system of claim 8, wherein the inductor shielding structure includes a portion interposed between the first inductor structure and the second inductor structure.

10. The RF system of claim 8, wherein the first inductor structure and the second inductor structure are electromagnetically coupled within the inductor shielding structure, and wherein the tunable filter corresponds to a dual-mode filter or a coupled filter. The RF system of claim 1 , wherein the first inductor structure corresponds to a multi-turn inductor or a comb-type inductor.

12. The RF system of claim 1 , wherein the first controllable capacitor comprises a plurality of selectable circuit branches connected in parallel with each other between the first RF terminal and the second RF terminal, wherein each of the plurality of selectable circuit branches comprises a series combination of at least one field effect transistor (FET) and at least one capacitor.

13. The RF system of claim 1, wherein the semiconductor chip further comprises a control circuit comprising a memory coupled to a serial interface and configured to store a table of settings for the first controllable capacitor.

14. The RF system of claim 1, wherein the first inductor structure comprises at least one terminal connected to a pin of the semiconductor chip and at least one terminal connected to the inductor shielding structure.

15. The RF system of claim 1, wherein the first circuit board corresponds to a multi-layer printed circuit board (PCB) formed using a single lamination step.

16. A method for tunable filtering, the method comprising: controlling the capacitance of a controllable capacitor formed on a semiconductor chip; causing the controllable capacitor to resonate with an inductor structure formed in a first circuit board by metallization of the first circuit board, wherein the first circuit board is attached to a second circuit board; as well as The inductor structure is shielded from the semiconductor chip using an inductor shielding structure formed at least in part from the metallization of the first circuit board.

17. The method of claim 16, wherein shielding the inductor structure comprises shielding each side of the inductor structure with the inductor shielding structure.

18. The method of claim 16, wherein shielding the inductor structure comprises shielding the inductor structure using a first portion of the inductor shielding structure formed on the first circuit board and using a second portion of the inductor shielding structure formed on the second circuit board.

19. A tunable filter comprising: A controllable capacitor formed on a semiconductor chip; an inductor structure formed in a first circuit board by metallization of the first circuit board, the first circuit board being configured to be attached to a second circuit board, wherein the inductor structure resonates with the controllable capacitor; as well as An inductor shielding structure is at least partially formed by the metallization of the first circuit board and surrounds the inductor structure.

20. The tunable filter of claim 19, further comprising a second circuit board, wherein a first portion of the inductor shielding structure is formed on the first circuit board, and a second portion of the inductor shielding structure is formed on the second circuit board.

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