System and method for multi-core memory reference instruction validation

Abstract

The present application relates to the technical field of processor, and particularly relates to a multi-core memory access instruction verification system and method, which comprises a DUT monitor, an access instruction queue, a storage instruction queue, a memory access instruction controller, a storage buffer, a memory model, an access data comparator, a storage data comparator, an atomic instruction comparator and a secondary cache comparator. The present application supports multi-core multi-cluster memory access instruction verification, and the number of cores and clusters can be configured, which is parameterized and scalable. The present application supports real-time comparison of the correctness of memory access instruction execution of each core in a multi-core system, including comparison of the correctness of access data when the access instruction is submitted, and comparison of the correctness of write data when the storage instruction updates the cache. The present application supports verification of atomic operation instructions in a multi-core system, and supports verification of secondary cache key interfaces in a multi-cluster system, which has a strong market application prospect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, in particular to a multi-core memory access instruction verification system and method. BACKGROUND

[0002] The execution order of instructions in a processor can be divided into program order and global memory order, the program order refers to the order of instructions in a program, and the global memory order refers to the order in which memory access instructions are performed, for a load (access instruction), the time point of performance is the time point at which the load data can be determined, and for a store (storage instruction), the time point of performance is the time point at which the store data can be seen by other cores.

[0003] Different memory consistency models have different requirements for the execution order of memory access instructions, the sequential consistency model is the most stringent, and requires that the global memory order and the program order be consistent, but such a multi-core system often has poor performance, and in actual multi-core systems, designs such as load forward store data and store buffer are added to improve performance, the addition of such designs makes the memory consistency model have relaxed requirements for the execution order of memory access instructions, and the global memory order does not necessarily conform to the program order, which brings great difficulty to multi-core verification, and the verification system must accurately know the global memory order of the memory access instruction to perform data comparison.

[0004] At present, there is no perfect tool on the market that can perform memory access instruction verification of a multi-core system. Therefore, the present application provides a multi-core memory access instruction verification system and method. SUMMARY

[0005] In view of the deficiencies of the prior art, the present application discloses a multi-core memory access instruction verification system and method, which is used to solve the problem that the multi-core system verification and design in the prior art are tightly coupled, and there is no tool that can perfectly support the verification of multi-core memory access instructions.

[0006] The present application is implemented by the following technical solutions:

[0007] In a first aspect, the present application provides a multi-core memory access instruction verification method, comprising the following steps:

[0008] The S1 instruction generator generates instructions and judges the instruction type through the verification system, and stores the access instruction in the access instruction queue if the instruction is an access instruction, and stores the storage instruction in the storage instruction queue if the instruction is a storage instruction;

[0009] The S2 instruction is stored in the access instruction queue, the access instruction information in the monitored DUT is updated, and the corresponding instruction in the access instruction queue is synchronously updated;

[0010] The S3 determines whether it is a cacheable address according to the address attribute, and executes the access instruction or writes the memory model according to the result;

[0011] The S4 monitors the access instruction submission in the DUT when the access instruction is executed, compares the access data saved in the verification system with the access data obtained in the DUT, and outputs the comparison result;

[0012] The S5 monitors the cache update information in the DUT when the memory model is written, writes the corresponding data in the storage buffer into the memory model, compares the write data with the DUT write data, and outputs the comparison result.

[0013] Further, in the method, after the instruction is stored in the access instruction queue, it is determined whether it is a cacheable address according to the address attribute, if it is a non-cacheable address, the perform time point is the time point when the read request in the DUT is sent to the peripheral interface, and if it is a cacheable address, the perform time point is the time point when the access instruction obtains data from the first-level cache.

[0014] Further, in the method, if it is a non-cacheable address, when the corresponding access request on the DUT peripheral interface is monitored, it is determined from which core the request comes, the access instruction of the core in the verification system is executed, data is obtained from the memory model, and the data is reserved for subsequent comparison.

[0015] Further, in the method, if it is a cacheable address, when the instruction obtains data in the DUT, the access instruction of the core in the verification system is executed.

[0016] Further, in the method, after the instruction is stored in the storage instruction queue, it is determined whether it is a cacheable address according to the address attribute, if it is a non-cacheable address, the perform time point is the time point when the write request in the DUT is sent to the peripheral interface, and if it is a cacheable address, the perform time point is the time point when the storage instruction is written from the storage buffer to the cache.

[0017] Further, in the method, if it is a non-cacheable address, when the corresponding write request on the DUT peripheral interface is monitored, it is determined from which core the request comes, the storage instruction of the core in the verification system is executed, data is written into the memory model, and the write data and the DUT write data are compared, and the comparison result is printed.

[0018] Further, in the method, if the address is cacheable, the DUT is monitored to determine whether the stored instruction is submitted, and if the stored instruction is submitted, the information of the stored instruction, including the address and data, is stored in a storage buffer.

[0019] In a second aspect, the application provides a multi-core memory access instruction verification system, which is used for the multi-core memory access instruction verification method in the first aspect, and comprises

[0020] A DUT monitor is configured to monitor the key signals of the DUT, so that the verification system performs corresponding operations according to the monitored DUT signals;

[0021] An access instruction queue is configured to store the information of the access instruction, and after the instruction generator sends the instruction to the DUT and the verification system, the access instruction is stored in the access instruction queue according to the type of the instruction;

[0022] A storage instruction queue is configured to store the information of the storage instruction, and after the instruction generator sends the instruction to the DUT and the verification system, the storage instruction is stored in the access instruction queue according to the type of the instruction;

[0023] A memory access instruction controller is configured to control when the memory access instruction information in the verification system is updated, to perform the operations of accessing the memory model and updating the memory model or to compare the data, and to flush the queue in the verification system for the behavior of the DUT with the flush pipeline;

[0024] A storage buffer is configured to store the corresponding instruction in the storage instruction queue in the verification system, and the corresponding data in the storage buffer is written into the memory model, and the corresponding instruction information in the storage buffer is deleted;

[0025] A memory model is configured to be the memory model in the verification system, and the time point of accessing and updating the memory model by the memory access instruction is the time point of performing the memory access instruction;

[0026] An access data comparator is configured to compare the data obtained by the instruction in the verification system and the data obtained by the DUT when the access instruction is submitted, and to print the comparison result;

[0027] A storage data comparator is configured to compare the write data of the instruction in the verification system and the write data in the DUT when the DUT storage instruction updates the cache, and to print the comparison result;

[0028] An atomic instruction comparator is configured to verify the correctness of the instruction with atomic operation in the multi-core system;

[0029] The secondary cache comparator is used for comparing key interfaces of the secondary cache in the DUT, and comparing whether the address and data in the related interfaces are consistent with the data corresponding to the address in the memory template.

[0030] Further, the DUT monitor monitors key signals of the DUT, including memory access instruction address data update information, instruction submission information, store buffer update information and level-1 cache update information, and secondary cache key interface signals.

[0031] The atomic instruction comparator verifies the correctness of instructions with atomic operations in a multi-core system, including LRSC and AMO instructions in the RISCV instruction set, and the comparator is used for comparing whether the LR instruction retrieval data is correct, whether the SC instruction execution result is successful or failed, and whether the AMO instruction obtained data is correct.

[0032] The secondary cache comparator compares key interfaces of the secondary cache in the DUT, including a read request interface of a core and the secondary cache, a read request interface of the secondary cache and a next-level memory, and a secondary cache monitoring interface.

[0033] Further, in the access instruction queue, when the address, attribute and other information of the access instruction in the DUT are updated, the corresponding instruction information in the queue is synchronously updated; when the access instruction in the DUT is submitted, the corresponding instruction in the queue is deleted.

[0034] In the storage instruction queue, when the address, attribute, data and other information of the storage instruction in the DUT are updated, the corresponding instruction information in the queue is synchronously updated; when the access instruction in the DUT is submitted, the corresponding instruction in the queue is deleted, and the instruction information is stored in the storage buffer.

[0035] The present application has the following beneficial effects:

[0036] The present application supports memory access instruction verification of a multi-core multi-cluster system, and the number of cores and clusters can be configured, so that parameterization is achieved, and scalability is achieved.

[0037] The present application supports real-time comparison of the correctness of memory access instruction execution of each core in a multi-core system, including comparison of the correctness of the data obtained by the access instruction when the access instruction is submitted, and comparison of the correctness of the write data when the storage instruction updates the cache.

[0038] The present application supports verification of atomic operation instructions in a multi-core system, supports verification of key interfaces of secondary caches in a multi-cluster system, and has a strong market application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0040] Figure 1 is a structure diagram of a multi-core memory access instruction verification system in the embodiment of the present application;

[0041] Figure 2 is a flowchart of execution of a memory access instruction in the verification system in the embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the protection scope of the present application.

[0043] Embodiment 1

[0044] Referring to Figure 1 , the embodiment discloses a multi-core memory access instruction verification system package DUT monitor, an access instruction queue, a storage instruction queue, a memory access instruction controller, a storage buffer, a memory model, an access data comparator, a storage data comparator, an atomic instruction comparator, and a second-level cache comparator. The following will describe these modules.

[0045] The DUT monitor in the embodiment is used to monitor key signals of the DUT, including memory access instruction address data update information, instruction submission information, store buffer update information, first-level cache update information, and second-level cache key interface signals. The verification system performs corresponding operations according to the monitored DUT signals.

[0046] The access instruction queue in the embodiment is used to store information of access instructions. The instruction generator simultaneously sends instructions to the DUT and the verification system, and stores the access instructions in the access instruction queue according to the instruction types.

[0047] When the access instruction address and attribute information in the DUT are updated, the corresponding instruction information in the queue is synchronously updated in the further implementation of the embodiment.

[0048] When the access instruction in the DUT is submitted, the corresponding instruction in the queue is deleted in the further implementation of the embodiment.

[0049] The embodiment stores the store instruction queue for storing the information of the store instruction. The instruction generator sends the instruction to the DUT and the verification system simultaneously, and stores the store instruction into the access instruction queue according to the type of the instruction.

[0050] When the information of the store instruction address, attribute, data and the like in the DUT is updated, the corresponding instruction information in the queue is updated synchronously in the further embodiment.

[0051] When the access instruction in the DUT is submitted, the corresponding instruction in the queue is deleted, and the instruction information is stored into the store buffer in the further embodiment.

[0052] The embodiment of the access instruction controller is used for controlling when the access instruction information in the verification system is updated, when the operation of accessing and updating the memory model is performed, and when the data is compared.

[0053] The controller needs to flush the queue in the verification system for the behavior of the DUT with the flush pipeline in the further embodiment.

[0054] The embodiment of the store buffer is used for storing the corresponding instruction in the store instruction queue in the verification system into the store buffer when the store instruction in the DUT is submitted.

[0055] When the data in the DUT is written from the store buffer to the cache, the corresponding data in the store buffer is also written into the memory model, and the corresponding instruction information in the store buffer is deleted in the further embodiment.

[0056] The embodiment of the memory model is used for the memory model in the verification system. Each core has the read and write permission. The time point of accessing and updating the memory model by the access instruction is the time point of performing the access instruction. There is only the memory model without the cache model in the verification system.

[0057] The embodiment of the access data comparator is used for comparing the data obtained by the instruction in the verification system and the data obtained by the DUT when the access instruction is submitted, and printing the comparison result.

[0058] The embodiment of the store data comparator is used for comparing the write data of the instruction in the verification system and the write data in the DUT when the store instruction in the DUT updates the cache, and printing the comparison result.

[0059] The embodiment of the atomic instruction comparator is used for verifying the correctness of the instruction with the atomic operation in the multi-core system.

[0060] The embodiment is further implemented, such as LRSC (Load-Reserved, Store-Conditional) in the RISCV instruction set, AMO instruction, the comparator is used for comparing whether the LR instruction retrieval data is correct, whether the SC instruction execution result is successful or failed, and whether the AMO instruction obtained data is correct.

[0061] The secondary cache comparator of the embodiment is used for comparing the key interfaces of the secondary cache in the DUT, including the read request interface of the core and the secondary cache, the read request interface of the secondary cache and the next level memory, and the secondary cache monitoring interface, and mainly comparing whether the address and data in the interfaces are consistent with the data corresponding to the address in the memory template.

[0062] The comparator can find the inconsistency between the verification system and the DUT data early, without waiting for the access instruction comparator to report an error, thereby greatly reducing the debug difficulty and shortening the debug time.

[0063] Embodiment 2

[0064] In the specific implementation level, the embodiment provides an execution flow of an access instruction in the verification system, and the execution flow is specifically as follows:

[0065] The instruction generator sends the instruction to the verification system, and if it is judged that the instruction type is an access instruction, the instruction is stored in the access instruction queue;

[0066] The DUT is monitored to update information of the access instruction, including the address, the attribute, the access size and the like, and the information is synchronously updated to the corresponding instruction in the access instruction queue;

[0067] According to the address attribute, it is judged whether it is a cacheable address, which affects the determination of the perform time point of the access instruction, if it is a non-cacheable address, the perform time point is the time point when the read request in the DUT is sent to the peripheral interface, if it is a cacheable address, the perform time point is the time point when the access instruction obtains data from the first cache;

[0068] In the embodiment, if it is a non-cacheable address, when the corresponding access request on the DUT peripheral interface is monitored, it is judged from which core the request comes, the access instruction of the core in the verification system is executed, the data is obtained from the memory model, and the data is reserved for subsequent comparison;

[0069] In the embodiment, if it is a cacheable address, when the DUT obtains data of the instruction, the access instruction of the core in the verification system is executed;

[0070] In the embodiment, for the cacheable address, since the access instruction is executed speculatively, the data can be obtained from the store instruction queue, the store buffer and the memory model, and the access instruction controller needs to select the data from the correct source, save the data after obtaining the data, and use the data for subsequent comparison;

[0071] When the submission of the access instruction in the DUT is monitored, the access data saved in the verification system and the access data obtained in the DUT are compared and verified, and the comparison result is printed.

[0072] Embodiment 3

[0073] At the specific implementation level, the embodiment provides a storage instruction execution process in the verification system, and the process is as follows:

[0074] The instruction generator sends the instruction to the verification system, and if it is judged that the instruction type is a storage instruction, the instruction is stored in the storage instruction queue;

[0075] The update information of the storage instruction in the DUT, including the address, the attribute, the write data and the size, is monitored and synchronously updated to the corresponding instruction in the storage instruction queue;

[0076] According to the address attribute, it is judged whether it is a cacheable address, which affects the determination of the perform time point of the storage instruction. If it is a non-cacheable address, the perform time point is the time point when the write request in the DUT is sent to the peripheral interface. If it is a cacheable address, the perform time point is the time point when the storage instruction is written into the cache from the storage buffer;

[0077] In the embodiment, if it is a non-cacheable address, when the corresponding write request on the DUT peripheral interface is monitored, it is judged from which core the request comes, the storage instruction of the core in the verification system is executed, the data is written into the memory model, the write data and the DUT write data are compared, and the comparison result is printed;

[0078] In the embodiment, if it is a cacheable address, it is monitored whether the storage instruction in the DUT is submitted. If it is submitted, the storage instruction information, including the address and the data, is stored in the storage buffer;

[0079] The update information of the cache in the DUT is monitored. If the cache is updated, the corresponding data in the storage buffer is written into the memory model, the write data and the DUT write data are compared, and the comparison result is printed.

[0080] Embodiment 4

[0081] The embodiment provides a multi-core access instruction verification method, as shown in Figure 2 The method comprises the following steps:

[0082] The S1 instruction generator generates instructions and judges the instruction type through the verification system, and stores the access instruction in the access instruction queue if the instruction is an access instruction, and stores the storage instruction in the storage instruction queue if the instruction is a storage instruction;

[0083] The S2 instruction is stored in the access instruction queue, and the access instruction information in the monitored DUT is updated, and the corresponding instruction in the access instruction queue is synchronously updated;

[0084] The S3 judges whether it is a cacheable address according to the address attribute, and executes the access instruction or writes the memory model according to the result;

[0085] The S4 monitors the access instruction submission in the DUT when the access instruction is executed, compares the access data saved in the verification system with the access data obtained in the DUT, and outputs the comparison result;

[0086] The S5 monitors the cache update information in the DUT when the memory model is written, writes the corresponding data in the storage buffer into the memory model, compares the write data with the DUT write data, and outputs the comparison result.

[0087] In this embodiment, after the instruction is stored in the access instruction queue, it is judged whether it is a cacheable address according to the address attribute, if it is a non-cacheable address, the perform time point is the time point when the DUT sends the access request to the peripheral interface, if it is a cacheable address, the perform time point is the time point when the access instruction obtains data from the first cache.

[0088] In this embodiment, if it is a non-cacheable address, when the corresponding access request on the DUT peripheral interface is monitored, it is judged from which core the request comes, the access instruction of the core in the verification system is executed, the data is obtained from the memory model, and the data is reserved for subsequent comparison.

[0089] In this embodiment, if it is a cacheable address, when the DUT obtains data of the instruction, the access instruction of the core in the verification system is executed.

[0090] In this embodiment, after the instruction is stored in the storage instruction queue, it is judged whether it is a cacheable address according to the address attribute, if it is a non-cacheable address, the perform time point is the time point when the DUT sends the write request to the peripheral interface, if it is a cacheable address, the perform time point is the time point when the storage instruction writes the data from the storage buffer to the cache.

[0091] In this embodiment, if it is a non-cacheable address, when the corresponding write request on the DUT peripheral interface is monitored, it is judged from which core the request comes, the storage instruction of the core in the verification system is executed, the data is written into the memory model, and the write data is compared with the DUT write data, and the comparison result is printed.

[0092] In the embodiment, if the address is cacheable, it is monitored whether the storage instruction in the DUT is submitted, and if the storage instruction is submitted, the storage instruction information, including the address, data and the like, is stored into the storage buffer.

[0093] The key of supporting the verification of the storage instruction of the multi-core in the embodiment is to accurately grasp the perform time point of the storage instruction, and the perform means that the operation of the instruction can be seen by other cores.

[0094] The perform time point of the storage instruction is also affected by the access address attribute, and if the access address is non-cacheable, the perform time point is the time point at which the write request is sent to the peripheral interface in the DUT, and if the access address is cacheable, the perform time point is the time point at which the storage instruction writes the data into the cache from the storage buffer.

[0095] The embodiment supports the verification of the atomic operation correctness of the instruction, supports the verification of the secondary cache key interface, and early reports the data error through the monitoring of the secondary cache interface before the storage instruction error, thereby improving the debug efficiency.

[0096] The embodiment supports the number of processors and the number of clusters to be configured, and has strong expansibility.

[0097] In summary, the embodiment supports the verification of the memory access instruction of the multi-core and multi-cluster, and the number of cores and clusters can be configured, thereby achieving parameterization and having scalability.

[0098] The embodiment supports real-time comparison of the correctness of the memory access instruction executed by each core in the multi-core system, including comparison of the correctness of the data obtained by the access instruction when the access instruction is submitted, and comparison of the correctness of the write data when the storage instruction updates the cache.

[0099] The embodiment supports the verification of the atomic operation instruction in the multi-core system and the verification of the secondary cache key interface in the multi-cluster system, and has strong market application prospect.

[0100] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for verifying a multi-core memory access instruction, the method comprising: The method comprises the following steps: S1 An instruction generator generates instructions and judges the instruction type through a verification system, and stores the access instruction in an access instruction queue if it is an access instruction, and stores the storage instruction in a storage instruction queue if it is a storage instruction; S2 The access instruction is stored in the access instruction queue, the access instruction information in the DUT is updated, and the corresponding instruction in the access instruction queue is synchronously updated; S3 Whether the address is a cacheable address is judged according to the address attribute, and the access instruction or the write memory model of the corresponding process is executed according to the result; after the instruction is stored in the access instruction queue, whether the address is a cacheable address is judged according to the address attribute, if the address is not a cacheable address, the perform time point is the time point when the read request in the DUT is sent to the peripheral interface, if the address is a cacheable address, the perform time point is the time point when the access instruction obtains data from the first-level cache; After the instruction is stored in the storage instruction queue, whether the address is a cacheable address is judged according to the address attribute, if the address is not a cacheable address, the perform time point is the time point when the write request in the DUT is sent to the peripheral interface, if the address is a cacheable address, the perform time point is the time point when the storage instruction writes data from the storage buffer to the cache; S4 If the instruction is an access instruction, if the address is not a cacheable address, when the corresponding access request on the DUT peripheral interface is monitored, it is judged from which core the request comes, the access instruction of the core in the verification system is executed, data is obtained from the memory model, and the data is reserved for subsequent comparison; if the address is a cacheable address, when the data obtained by the instruction in the DUT is monitored, the access instruction of the core in the verification system is executed; the access data saved in the verification system and the access data obtained in the DUT are compared, and the comparison result is outputted; S5 If the instruction is a storage instruction, if the address is not a cacheable address, when the corresponding write request on the DUT peripheral interface is monitored, it is judged from which core the request comes, the storage instruction of the core in the verification system is executed, data is written into the memory model, and the write data and the DUT write data are compared, and the comparison result is printed; if the address is a cacheable address, whether the storage instruction in the DUT is submitted is monitored, if the storage instruction has been submitted, the storage instruction information, including the address, the data and the like, is stored in the storage buffer; the cache update information in the DUT is monitored, then the corresponding data in the storage buffer is written into the memory model, and the write data and the DUT write data are compared, and the comparison result is outputted.

2. A multi-core memory access instruction verification system, the system is used to be executed by the multi-core memory access instruction verification method as claimed in claim 1, characterized in that, The DUT monitor is used to monitor the key signals of the DUT, so that the verification system performs corresponding operations according to the monitored DUT signals; the access instruction queue is used to store the information of access instructions, and the access instructions are stored in the access instruction queue according to the instruction types after the instruction generator sends the instructions to the DUT and the verification system; the storage instruction queue is used to store the information of storage instructions, and the storage instructions are stored in the access instruction queue according to the instruction types after the instruction generator sends the instructions to the DUT and the verification system at the same time; the memory access instruction controller is used to control when the memory access instruction information in the verification system is updated, to perform the operations of accessing the memory model and updating the memory model or to compare the data, and to flush the pipeline for the DUT, and to flush the queue in the verification system; The storage buffer is used to verify the storage of the corresponding instructions in the storage instruction queue in the verification system, and the corresponding data in the storage buffer is written into the memory model, and the corresponding instruction information in the storage buffer is deleted; the memory model is used to verify the memory model in the verification system, and the time point of accessing and updating the memory model by the memory access instruction is the time point of performing the memory access instruction, if it is an access instruction, the instruction is stored in the access instruction queue, and whether the address is cacheable is judged according to the address attribute, if the address is not cacheable, the time point of performing is the time point when the read request in the DUT is sent to the peripheral interface, if the address is cacheable, the time point of performing is the time point when the access instruction obtains the data from the first-level cache; if it is a storage instruction, the instruction is stored in the storage instruction queue, and whether the address is cacheable is judged according to the address attribute, if the address is not cacheable, the time point of performing is the time point when the write request in the DUT is sent to the peripheral interface, if the address is cacheable, the time point of performing is the time point when the storage instruction writes the data into the cache from the storage buffer; the access data comparator is used to compare the data obtained by the instruction in the verification system and the data obtained by the DUT when the access instruction is submitted, and print the comparison result; the storage data comparator is used to compare the write data of the instruction in the verification system and the write data in the DUT when the DUT storage instruction updates the cache, and print the comparison result; the atomic instruction comparator is used to verify the correctness of the instructions with atomic operations in the multi-core system; the second-level cache comparator is used to compare the key interfaces of the second-level cache in the DUT, and compare whether the addresses and data in the related interfaces are consistent with the data corresponding to the addresses in the memory template.

3. The multi-core load instruction verification system of claim 2, wherein, The DUT monitor monitors key signals of the DUT, including memory access instruction address data update information, instruction submission information, store buffer update information, and level one cache update information, and level two cache key interface signals; the atomic instruction comparator verifies the correctness of instructions with atomic operations in the multi-core system, including LRSC and AMO instructions in the RISCV instruction set; the comparator is used to compare whether the LR instruction retrieval data is correct, whether the SC instruction execution result is successful or failed, and whether the AMO instruction obtained data is correct; and the level two cache comparator compares key interfaces of the level two cache in the DUT, including a read request interface of the core and the level two cache, a read request interface of the level two cache and the next level memory, and a level two cache monitoring interface.

4. The multi-core load instruction verification system of claim 2, wherein, In the access instruction queue, when the access instruction address, attribute and other information in the DUT are updated, the corresponding instruction information in the queue is synchronously updated; when the access instruction in the DUT is submitted, the corresponding instruction in the queue is deleted; in the storage instruction queue, when the storage instruction address, attribute, data and other information in the DUT are updated, the corresponding instruction information in the queue is synchronously updated; when the access instruction in the DUT is submitted, the corresponding instruction in the queue is deleted, and the instruction information is stored into the storage buffer.

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