Memory with test function and method of testing the same

Abstract

The present application provides a memory with test function and a test method thereof. The memory includes a memory array having memory cells, input buffers divided into even groups and odd groups, and output buffers divided into even groups and odd groups; at least two data input pads providing test data to the memory cells via the even input buffers and the odd input buffers, respectively; first and second logic gates performing first logical operations on outputs of the even output buffers and the odd output buffers, respectively; a third logic gate performing a second logical operation on outputs of the first and second logic gates; and at least one data output pad coupled to an output of the third logic gate for providing test results of the memory cells.

Description

Technical Field

[0001] The present invention relates to a memory, and in particular to a memory with a testing function and a testing method thereof. Background Art

[0002] With the advancement of semiconductor memory, the number of I / O ports has increased significantly. So-called hypermulti-I / O (e.g., 512 I / O, 1024 I / O) memories, such as DRAM, can have a large number of I / O ports (e.g., 512, 1024, or even more). This type of memory is a very effective solution for achieving extremely high bandwidth between on-chip logic and memory.

[0003] On the other hand, testing high-I / O DRAMs is extremely difficult because automatic test equipment (ATE) typically has limited I / O driver-comparator resources, and probe cards also have limited probe resources. In the DRAM and logic areas on the same die, there are usually no additional I / O pads, making it impractical to place too many pads for testing.

[0004] Therefore, testing a large number of I / O DRAMs and repairing defective memory cells is very important for improving yield. It is necessary to develop a memory structure and a testing method that can reduce the number of input pads and output pads used for testing. Summary of the Invention

[0005] According to one embodiment of the present invention, a memory with a test function is provided. The memory includes a memory array, at least two data input pads, a first logic gate, a second logic gate, a third logic gate, and at least one data output pad. The memory array includes memory cells, a plurality of input buffers, and a plurality of output buffers, wherein the plurality of input buffers are divided into even input buffers and odd input buffers, and the plurality of output buffers are divided into even output buffers and odd output buffers. In a test write mode, the at least two data input pads provide test data to the memory cells via the even input buffers and the odd input buffers, respectively. In a test read mode, the first logic gate performs a first logic operation on the output of the even output buffer. The second logic gate performs the first logic operation on the output of the odd output buffer in the test read mode. The third logic gate performs a second logic operation on the outputs of the first and second logic gates. The at least one data output pad is coupled to the output of the third logic gate for providing a test result of the memory cell.

[0006] According to one embodiment, the first logic gate and the second logic gate may be exclusive OR (XOR) gates, and the third logic gate may be a NOR (NOR) gate.

[0007] According to one embodiment, the memory array may further include a plurality of sub-arrays arranged in a matrix. Each of the plurality of sub-arrays may include a plurality of bit lines divided into a plurality of even bit lines and a plurality of odd bit lines. The even bit lines and the odd bit lines may be interleaved with each other. The test data from the even input buffer is written into the memory cell via the even bit lines, and the test data from the odd input buffer is written into the memory cell via the odd bit lines.

[0008] According to one embodiment, each of the plurality of sub-arrays may further include a first set of local I / O lines connected to the even bit lines via corresponding sense amplifiers; a second set of local I / O lines connected to the odd bit lines via corresponding sense amplifiers; and a set of main I / O lines intersecting the first set of local I / O lines and the second set of local I / O lines.

[0009] According to one embodiment, the number of the set of main I / O lines may be equal to the number of the first set of local I / O lines and the second set of local I / O lines.

[0010] According to one embodiment, each of the plurality of sub-arrays may further include a predetermined number of spare bit lines for replacing defective bit lines in the sub-array. In one embodiment, once the defective bit line in the sub-array is detected, all of the predetermined number of spare bit lines may be replaced with the bit line.

[0011] According to one embodiment, the memory may be a high-I / O semiconductor memory. In one embodiment, the high-I / O semiconductor memory is a high-I / O DRAM.

[0012] According to another embodiment of the present invention, a method for testing a memory is provided, wherein the memory has a memory array having a plurality of even input buffers and odd input buffers and a plurality of even output buffers and odd output buffers. The method includes: writing test data into memory cells of the memory under test via the plurality of even input buffers and odd input buffers via at least two data input pads; reading the test data from the memory cells via the plurality of even output buffers and odd output buffers; performing a first logic operation on outputs of the plurality of even output buffers to obtain a first logic value and performing a first logic operation on outputs of the plurality of odd output buffers to obtain a second logic value; performing a second logic operation on the first and second logic values ​​to output a third logic value on at least one data output pad; and determining whether the memory cell is defective or non-defective based on the third logic value.

[0013] According to one embodiment, in the above method, the test data from one of the at least two data input pads can be continuously burst-written into the even input buffer, and the test data from the other of the at least two data input pads can be continuously burst-written into the odd input buffer.

[0014] According to one embodiment, in the above method, the first logical operation may be an exclusive OR, and the second logical operation may be a negative OR.

[0015] According to one embodiment, in the above method, the memory array may further include a plurality of sub-arrays arranged in a matrix, and each of the plurality of sub-arrays includes a plurality of bit lines divided into a plurality of even bit lines and a plurality of odd bit lines. The method may further include: writing the test data from the even input buffer to the memory cell via the even bit lines, and writing the test data from the odd input buffer to the memory cell via the odd bit lines.

[0016] According to one embodiment, in the above method, each of the plurality of sub-arrays may further include a predetermined number of spare bit lines, and the method includes replacing defective bit lines in the sub-array with the predetermined number of spare bit lines.

[0017] According to one embodiment, in the above method, once the defective bit line in the sub-array is detected, all of the predetermined number of spare bit lines may be replaced with the bit line.

[0018] According to one embodiment, in the above method, the memory may be a high-I / O semiconductor memory. According to one embodiment, the high-I / O semiconductor memory may be a high-I / O DRAM.

[0019] As described, the I / O buffers of a memory array are divided into even and odd groups, and at least two data input pads and at least one data output pad are provided for testing. In this way, testing of a memory with a large number of I / Os can be easily implemented, potentially with fewer test I / O pads. Furthermore, testing can be accomplished by providing logic gates without increasing the complexity of the memory configuration. Without placing an excessive number of pads for testing the memory, the method and circuit can be easily applied to memory configurations with a very large number of I / Os. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 An example of a very high I / O DRAM is shown for brief description according to an embodiment of the present invention.

[0021] Figure 2A and Figure 2B A schematic timing diagram illustrating continuous burst write and burst read operations for a memory is shown.

[0022] Figure 3A Draw Figure 1 portion of the memory array.

[0023] Figure 3B Draw Figure 3A A sub-array of the memory array shown in .

[0024] Figure 3C Draw Figure 3B The portion of the subarray shown in .

[0025] Figure 3D Draw Figure 3C Examples of changes.

[0026] Figure 4 FIG. 1 illustrates an I / O buffer structure according to an embodiment of the present invention.

[0027] Figures 5A to 5C FIG. 1 is a conceptual diagram illustrating a method for performing test mode writing according to an embodiment of the present invention.

[0028] Figures 6A to 6C A conceptual diagram illustrating a method for performing a test mode read according to an embodiment of the present invention is shown.

[0029] Figure 7 A flow chart for testing memory cells of a very high IO memory according to an embodiment of the present invention is shown.

[0030] Figure 8 An exemplary redundancy method for an embodiment of the present invention is shown.

[0031]

Explanation of symbols

[0032] 100: Memory array

[0033] 120:X decoder

[0034] 122:Y decoder

[0035] 124: Main Amplifier

[0036] 126:FIFO

[0037] 128:I / O buffer

[0038] 200: Subarray

[0039] 210, 212, 214: Logic gates

[0040] AD:Address

[0041] ADD: address line

[0042] BA: Memory Bank Line

[0043] BA0: ​​memory bank number

[0044] BL, BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL1022, BL1023: bit lines

[0045] C: Memory unit

[0046] CA0: column address

[0047] CMD: Command line

[0048] CK_t, CK: clock signal

[0049] D0, D1: data input pads

[0050] D00, D01, D02...D43, Q00, Q01, Q02...Q33: data

[0051] D: Input buffer

[0052] DRAM: Memory

[0053] De: Even input buffer

[0054] Do: Odd input buffer

[0055] DQ, DQ0, DQ31: data ports

[0056] LIO: Local I / O

[0057] MIO: Master I / O

[0058] Q: Output buffer

[0059] Q0, Q1, Q2, Q3: data output pads

[0060] Qe: Even output buffer

[0061] Qo: odd output buffer

[0062] RL: Read latency

[0063] S100, S102, S104, S106, S108: Steps

[0064] SA: Sense Amplifier

[0065] T1, T2, T3, T5: Timing

[0066] WL, WLO, WL511: Write wait time / word line

[0067] WR, RD: Command

[0068] YSL:Select Line DETAILED DESCRIPTION

[0069] The test circuit and method of the present invention can be applied to various memory devices, such as semiconductor memories, having a large number of I / O ports. In the following description, DRAM is used as an example to facilitate understanding of the present invention and does not limit the scope of the present invention. Other possible memory types can also be tested based on the concepts of the present invention and can be modified appropriately as necessary.

[0070] Figure 1 An example of a multi-I / O DRAM is briefly described according to an embodiment of the present invention. Figure 1 The memory includes a memory array 100, an X decoder 120, a Y decoder 122, a main amplifier 124, a FIFO 126, and an I / O buffer 128. Data can be written to or read from the I / O buffer 128 via data ports DQ<127:0>. The functions and operations of the basic circuit blocks are substantially the same or similar to those of conventional architectures, and their actual architecture does not affect the implementation of this embodiment, so a detailed description is omitted.

[0071] In addition, if Figure 1 As shown, in order to operate the memory in the test mode according to an embodiment of the present invention, it includes at least two data input pads D0 and D1 of the I / O buffer 128 for providing test data to the memory array 100 in the test write mode, and includes at least one data output pad Q0 (or data output pad Q1...) for outputting the test result from the I / O buffer 128 in the test read mode.

[0072] exist Figure 1 As an example, the memory array 100 has 128 I / O buffers, two data input pads D0 and D1, and four data output pads Q0 (Q<31:0>), Q1 (Q<63:32>), Q2 (Q<95:64>), and Q3 (Q<127:96>). Test data is written into the memory array 100 via the data input pads D0 and D1, and the test results are output from the data output pads Q0-Q3.

[0073] Figure 2A and Figure 2B A schematic timing diagram illustrating continuous burst write and burst read operations for a memory is shown. Figure 2A As shown, at timing T1 of the clock signal CK_t, a WR (write) command is issued on the command line CMD, and the column address CA0 and the bank number BA0 are selected and issued on the address line ADD and the bank line BA, respectively, so that data will be written to the memory cell at the selected bank BA0 and the column address CA0. When the write latency WL = 1, data writing to the selected memory cell begins at timing T2. Then, at timing T3, timing T5, ..., the write command WR, address ADD, and bank BA are successively issued. As a result, data D00, D01, D02, ..., D43 are successively burst-written to the selected memory cells via ports D[511:0].

[0074] exist Figure 2B , briefly depicts the timing diagram for continuous burst read operations. Figure 2B As shown, Figure 2A As shown, at timing T1 of clock signal CK_t, command RD (read) is issued on command line CMD, and column address CA0 and bank number BA0 are selected and issued on address line ADD and bank line BA, respectively. This causes data to be read from the memory cell at selected bank BA0 and column address CA0. With read latency RL = 4, for example, data reading from the selected memory cell begins at timing T5. Subsequently, read commands RD, address ADD, and bank BA are successively issued at timings T3, T5, ... . Consequently, data Q00, Q01, Q02, ..., Q33 are sequentially burst-read from the selected memory cells via ports Q[511:0].

[0075] Therefore, generally speaking, when there is test data to be written to or read from a large number of I / O memories (such as DRAM), the number of I / O pads for data input and output needs to be the same using burst writing and reading. According to the present invention, the data input pads are reduced to at least two ( Figure 1 The data input pads D0, D1) and the data output pads will be reduced to at least one ( Figure 1 Data output pads Q0, Q2).

[0076] Figure 3A Draw Figure 1 portion of the memory array. Figure 3A , which shows the left portion of memory array 100 having 64MB and further includes 8 x 16 sub-arrays. That is, the array is divided into 16 sections (sections 0 through 15) in the column direction (bit line direction) and 8 sections in the row direction (word line direction), i.e., in a matrix format. Furthermore, sub-arrays in the same column are further connected by select lines YSL. For example, select lines YSL can be used to connect eight BL pairs to eight local I / O pairs (LIO pairs).

[0077] Figure 3B Draw Figure 3A A subarray of the memory array shown. Figure 3B As shown, Figure 3B The sub-array 200 further includes a plurality of word lines WL, a plurality of bit lines BL intersecting the plurality of word lines, and a plurality of memory cells C, wherein each memory cell C is disposed at each intersection of a word line and a bit line. In addition, a plurality of sense amplifiers (SA) are further included to be connected to corresponding bit lines. Figure 3B In the example shown, there are 512 word lines (word lines WL0-WL511), 1024 bit lines BL (bit lines BL0-BL1023), and 1024 sense amplifiers (512 SAs are arranged in the upper portion of the sub-array 200 and another 512 SAs are arranged in the lower portion of the sub-array 200).

[0078] Figure 3C Draw Figure 3B The portion of the subarray shown. Figure 3C, which depicts bit lines BL0 to BL7, 8 pairs of LIOs, and 8 pairs of main I / Os (MIOs). For example, the even bit lines BL0, BL2, BL4, and BL6 are respectively connected to the 4 pairs of LIOs (the first group) in the upper portion of the sub-array 200, and the odd bit lines BL1, BL3, BL5, and BL7 are respectively connected to the other 4 pairs of LIOs (the second group) in the lower portion of the sub-array 200. In addition, the 8 pairs of MIOs and the two groups of 4 pairs of LIOs in the upper and lower portions of the sub-array 200. In this case, the bit lines BL<0, 2, 4, 6> are respectively connected to MIO<0, 2, 4, 6>, and the bit lines BL<1, 3, 5, 7> are respectively connected to MIO<1, 3, 5, 7>. Therefore, data can be transmitted via the even data port DQ <even>Data is burst read from or written to bit lines BL<0, 2, 4, 6>, which are connected to MIO<0, 2, 4, 6> respectively and can be accessed through odd data ports DQ <odd>Data is burst-read from or burst-written to the bit lines BL<1, 3, 5, 7>, which are connected to MIO<1, 3, 5, 7>, respectively.

[0079] exist Figure 3C In the configuration shown in FIG, subarray 200 further includes a plurality of bit lines, such as bit lines BL0-BL1023. The plurality of bit lines BL0-BL1023 are further divided into even bit lines BL0, BL2, BL4, ..., BL1022 and odd bit lines BL1, BL3, BL5, ..., BL1023. The even bit lines BL0, BL2, BL4, ..., BL1022 are interleaved with the odd bit lines BL1, BL3, BL5 ..., BL1023. Furthermore, test data from even input buffer De (from data input pad D0) is written to even bit lines (e.g., BL0, BL2 ... BL6), and test data from odd input buffer Do (from data input pad D1) is written to odd bit lines (e.g., BL1, BL3 ... BL7).

[0080] Figure 3D Draw Figure 3C As shown in 3D, in this case, the bit lines BL<0, 1, 2, 3> are connected to MIO<0, 2, 4, 6> respectively, and the bit lines BL<4, 5, 6, 7> are connected to MIO<1, 3, 5, 7> respectively. Therefore, the even data port DQ <even>Data is burst read from or written to bit lines BL<0, 1, 2, 3>, which are connected to MIO<0, 2, 4, 6> respectively and can be accessed through odd data ports DQ <odd>Data is burst-read from or written to bit lines BL<4, 5, 6, 7>, which are connected to MIO<1, 3, 5, 7>, respectively. The mapping between bit lines BL and MIO can be modified based on design requirements. Furthermore, eight adjacent bit lines BL can be selected from bit lines BL0 through BL1023 based on a received address via select line YSL.

[0081] Figure 4 FIG. 1 shows an I / O buffer structure according to an embodiment of the present invention. Figure 4 As shown, Figure 1 The I / O buffer 128 may include an input buffer D and an output buffer Q. The input buffer D may be further divided into an even input buffer De and an odd input buffer Do, and the output buffer Q may be further divided into an even output buffer Qe and an odd output buffer Qo.

[0082] According to an embodiment of the present invention, test data can be burst written to the memory cells of the memory array 100 via at least two data input pads D0 and D1. For example, the test data is burst written to the even input buffers De<0, 2, 4, 6, 8 ...> of the memory via the data input pad D0, and the test data is burst written to the odd input buffers Do<1, 3, 5, 7, 9 ...> of the memory via the data input pad D1. After the test data is written to the input buffer 128, the test data is sequentially transferred to the FIFO 126 corresponding to each sub-array. Then, the test data is transmitted via MIO<0, 2, 4, 6> and MIO<1, 3, 5, 7> and further transmitted via the following steps: Figures 3A to 3D The eight LIO pairs shown write test data to the memory cells. In this way, test data is continuously written to the memory cells under test. In test read mode, the test data previously written to the memory cells is read. The test data is transmitted via MIO<7:0> and then sequentially transmitted to FIFO 126 and output buffer 128.

[0083] Next, refer to Figures 5A to 5C 、 Figures 6A to 6C as well as Figure 7 The memory test circuit and method of this embodiment are further described in detail.

[0084] Figures 5A to 5C A conceptual diagram for performing test mode writing according to an embodiment of the present invention is shown. Figure 5A As shown, a memory array 100 (refer to Figure 1 ) has a left portion (e.g., a size of 64MB) and has a 64-port DQ<63:0> as an I / O port. Figure 5A , which depicts an example of writing test data into input buffer D<7:0>, i.e., the data length is 8, but the present invention is not limited to this example. The data length can be modified based on design requirements, such as D<31:0> or D<63:0>.

[0085] Figure 5B FIG. 1 is a schematic diagram showing how test data for testing is written into the input buffer 128 (burst write). Figure 5B As shown, the I / O buffer 128 further includes input buffers D<0, 1, 2, 3, 4...> and output buffers Q<0, 1, 2, 3, 4...>. According to an embodiment of the present invention, the input buffers D<0, 1, 2, 3, 4> are further divided into even input buffers De<0, 2, 4, 6...> and odd input buffers Do<1, 3, 5, 7...>, and the output buffers Q<0, 1, 2, 3, 4...> are further divided into even input buffers Qe<0, 2, 4, 6...> and odd input buffers Qo<1, 3, 5, 7...>.

[0086] In test mode writing, externally provided test data is sequentially written into the memory cells under test via input buffers D<0, 1, 2, 3, 4, ...> using two paths D0 and D1. That is, test data is written into even input buffers De<0, 2, 4, 6, ...> using data input pad D0 and into odd input buffers Do<1, 3, 5, 7, ...> using data input pad D1. In this way, test data from data input pad D0 and test data from data input pad D1 can be written in parallel to even input buffers De<0, 2, 4, 6, ...> and odd input buffers Do<1, 3, 5, 7, ...>. In other embodiments, there may be four data input pads (data input pads D0-D3) or more, depending on design requirements.

[0087] like Figure 5C As shown in FIG, at timing T2 of the clock signal CK, a write WR command CMD is issued, address AD<8:0> of CA0 is issued, and memory bank 0 (BA) is selected for write. Next, at timing T3 of the clock signal CK, test data to be written is continuously written via data input pads D0 and D1. The test data written to the memory cells of memory array 100 via data input pad D0 is written to even-numbered input buffers De<0, 2, 4, 6, 8 ...>, and the test data written to the memory cells of memory array 100 via data input pad D1 is written to odd-numbered input buffers Do<1, 3, 5, 7, 9 ...>.

[0088] Therefore, because a memory chip can share two common data input pads D0 and D1, and the input buffers are divided into even input buffers and odd input buffers, the number of input pads receiving test data can be greatly reduced. In addition, any test data pattern can be written to adjacent memory cells to detect defective memory cells by using data input pads D0 and D1.

[0089] After the test data is written to the memory, a test pattern read is performed to complete the test operation. The test pattern read is further described in detail below.

[0090] Figures 6A to 6C A conceptual diagram for performing test mode reading according to an embodiment of the present invention is shown. Figure 6A , which illustrates a memory array 100 (refer to Figure 1 ) has a left portion (e.g., a size of 64MB) and has a 64-port DQ<63:0> as an I / O port. Figure 6A In this example, test data is read from output buffer Q<31:0>, where the data length is 32. However, the present invention is not limited to this example. The data length can be modified as needed, such as Q<64:0> or longer. Furthermore, in this embodiment, two data output pads, Q0 and Q1, are provided to provide test results. Data output pad Q0 is provided to output test results from the output of output buffer Q<31:0>, and output pad Q1 is provided to output test results from the output of output buffer Q<63:32>.

[0091] Next, refer to Figure 6B and Figure 6C To further illustrate the test mode read. Figure 6B The following describes test mode reads (burst reads) from output buffers Q<31:0> corresponding to ports DQ0 to DQ31. Output buffers Q<31:0> are also divided into even-numbered output buffers Qe<0, 2, 4, 6, ... 30> and odd-numbered output buffers Qo<1, 3, 5, 7, ... 31>.

[0092] like Figure 6C As shown in FIG, at timing T2 of the clock signal CK, a command CMD to read RD is issued, address AD<8:0> of CA0 is issued, and memory bank 0 (BA) is selected for reading. Then, at timing T5 of the clock signal CK, test results (i.e., "pass" or "fail") are continuously provided via data output pads Q0, Q1, ..., Q15.

[0093] The test data previously written to the memory cell is read in a burst fashion through the output buffer Q<31:0>. That is, the test data is read from the memory cell and then transmitted through the FIFO 126 to the output buffer Q<31:0>.

[0094] Furthermore, the test circuit can also include a first logic gate 210, a second logic gate 212, and a third logic gate 214. According to one embodiment of the present application, the first logic gate 210 and the second logic gate 212 can be XOR gates and the third logic gate 214 can be a NOR gate. The XOR gates 210, 212 and the NOR gate 214 will be used to illustrate the test operation, but are not intended to limit the practice of the present application. As shown in FIG. 2, the output of the even output buffer Qe<0,2,4...30> is input to the XOR gate 210 and the output of the odd output buffer Qo<1,3,5...31> is input to the XOR gate 212. The outputs of the XOR gates 210, 212 (the first logic value and the second logic value) are then input to the NOR gate 214 and the test result is generated which is then output through the data output pad Q0. The value Q0 on the data output pad Q0 will indicate the test result showing whether the memory cell under test is defective or not. Figure 6B

[0095] Furthermore, the first logic gate 210, the second logic gate 212, and the third logic gate 214 are provided corresponding to each data output pad. If two data output pads Q0, Q1 are provided, then two sets of the first logic gate 210, the second logic gate 212, and the third logic gate 214 are also provided for performing the logic operation for each data output pad.

[0096] When each even output buffer Qe<0,2,4,30> has the same data and each odd output buffer Qo<1,3,5...31> has the same data, the output of the XOR gate 210 should be "0", i.e., "pass" (not defective), and the output of the XOR gate 212 (odd DQ) should be 0, i.e., "pass", otherwise the output of the XOR gate 210 or the XOR gate 212 will be 1, i.e., "fail" (defective). When both outputs of the XOR gate 210, 212 are 0, the output of the NOR gate 214 will be "1", i.e., "pass", which means that the memory cell is not defective. Conversely, when both outputs of the XOR gate 210, 212 are not 0, the output of the NOR gate 214 will be "0", i.e., "fail", which means that the memory cell is defective.

[0097] ​In summary, the present invention provides a memory device with test functionality. The memory device may include a memory array, at least two data input pads D0 and D1, a first logic gate 210, a second logic gate 212, a third logic gate 214, and at least one data output pad Q0. The memory array includes memory cells, a plurality of input buffers (such as D<511:0>), and a plurality of output buffers (such as Q<511:0>). The plurality of input buffers D<511:0> are divided into even input buffers De<0, 2, 4 ... 510> and odd input buffers Do<1, 3, 5 ... 511>, and the plurality of output buffers Q<511:0> are divided into even output buffers Qe<0, 2, 4 ... 510> and odd output buffers Qo<1, 3, 5 ... 511>. At least two data input pads D0 and D1 provide test data to the memory cell in a test write mode via the even input buffers De<0, 2, 4, ... 510> and the odd input buffers Do<1, 3, 5, ... 511>, respectively. A first logic gate 210 performs a first logic operation (e.g., exclusive OR) on the outputs of the even output buffers Qe<0, 2, 4, ... 510> in a test read mode. A second logic gate performs a first logic operation (e.g., exclusive OR) on the outputs of the odd output buffers Qo<1, 3, 5, ... 511> in a test read mode. A third logic gate 214 performs a second logic operation (e.g., negated OR) on the outputs of the first logic gate 210 and the second logic gate 212. At least one data output pad Q0 is coupled to the output of the third logic gate 214 for providing a test result (e.g., "pass" or "fail") for the memory cell.

[0098] In the above arrangement, by dividing the I / O buffers into even and odd groups and providing at least two data input pads and at least one data output pad, testing for a large number of I / O memories can be easily implemented with potentially fewer test I / O pads.

[0099] Figure 7 A flow chart for testing a memory cell of a multi-IO memory according to an embodiment of the present invention is shown. Figure 7 and Figures 5A to 5B As shown in FIG, in step S100, test data is written into memory cells of a memory under test via a plurality of even input buffers and odd input buffers via at least two data input pads. For example, test data from data input pad D0 is sequentially written into even input buffers De<0, 2, 4, 6 ... 62>, and test data from data input pad D1 is sequentially written into odd input buffers Do<1, 3, 5, 7 ... 63>. In one embodiment, two data input pads (or lines) are used to input test data, making testing of high-I / O memories (such as DRAM) easy and feasible.

[0100] Next, in step S102, test data is read from the memory cells via a plurality of even output buffers and odd output buffers. Figure 6B As shown in FIG, test data are read from the even output buffers Qe<0, 2, 4, 6, . . . 30> and the odd output buffers Qo<1, 3, 5, 7, . . . 31>.

[0101] In step S104 and Figure 6B As shown in FIG, a first logic operation is performed on the outputs of a plurality of even output buffers to obtain a first logic value, and a first logic operation is performed on the outputs of a plurality of odd output buffers to obtain a second logic value. The first logic operation may be an exclusive OR. In this example, the outputs of the plurality of even output buffers Qe<0, 2, 4, 6 . . . 30> are provided to an exclusive OR gate 210 and generate a first logic value (i.e., the output of the exclusive OR gate 210), and the outputs of the plurality of odd output buffers Qo<1, 3, 5, 7 . . . 31> are provided to an exclusive OR gate 212 and generate a second logic value (i.e., the output of the exclusive OR gate 212).

[0102] In step S106, a second logic operation is further performed on the first and second logic values ​​to output a third logic value on at least one data output pad. The second logic operation can be NOR. In this example, the outputs of XOR gates 210 and 212 (i.e., the first and second logic values) are provided to NOR gate 214, and the third logic value (i.e., the output of NOR gate 214) is output via data output pad Q0. The test operation on output buffers Q<63:32> is identical, and data output pad Q1 will output a test result based on the test read of output buffers Q<63:32>.

[0103] In step S108, the memory cell may be determined to be defective or non-defective based on the third logic value. Thus, depending on Q0, Q1 (the third logic value), it may indicate whether the tested memory cell passed (logic "1") or failed (logic "0").

[0104] According to the testing method of the present invention, at least two data input pads (data input pad D0, data input pad D1) and at least one data output pad (Q0) are used to test a memory with a large number of I / Os, and without the need to set up too many pads for testing the memory, the test of the memory with a large number of I / Os is easy and executable.

[0105] Figure 8 Schematic redundancy method for an embodiment of the present invention is shown. Figure 8 As shown in , in an embodiment, for example, four spare YSL lines (bit lines) are further provided for each sub-array. After the test is performed, if any defective memory cell is found in the sub-array, all YSL lines are replaced with spare YSL lines, regardless of where the defective memory cell is. Basically, each sub-array can be read or written using a number of 8 (port DQ). Therefore, the redundancy method can replace a number of 4×8 in parallel. In this method, when 1 of Q<31:0> has a defective memory cell, Q0 displays a failed result (such as Figure 6B = "0" in ), and the defective YSL can be replaced by a spare YSL according to the Q0 result.

[0106] In summary, according to the present invention, by dividing the I / O buffer into even and odd groups and providing at least two data input pads and at least one data output pad, testing of a memory with a large number of I / Os can be easily implemented, potentially with fewer test I / O pads. Furthermore, testing can be accomplished by providing logic gates without increasing the complexity of the memory configuration. Without placing an excessive number of pads for testing the memory, the method and circuit can be easily applied to memory configurations with a very large number of I / Os.

[0107] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations as long as they come within the scope of the appended claims and their equivalents.< / odd> < / even> < / odd> < / even>

Claims

1. A memory with a test function, comprising: A memory array having memory cells and a plurality of input buffers and a plurality of output buffers, wherein the plurality of input buffers are divided into even input buffers and odd input buffers, and the plurality of output buffers are divided into even output buffers and odd output buffers; at least two data input pads for providing test data to the memory cell via the even input buffer and the odd input buffer, respectively, in a test write mode; a first logic gate configured to perform a first logic operation on an output of the even output buffer in a test read mode; a second logic gate, configured to perform the first logic operation on the output of the odd output buffer in the test read mode; and a third logic gate, performing a second logic operation on the outputs of the first logic gate and the second logic gate; as well as At least one data output pad is coupled to the output of the third logic gate for providing a test result of the memory cell.

2. The memory with a test function as claimed in claim 1, wherein the first logic gate and the second logic gate are exclusive OR (XOR) gates, and the third logic gate is a NOR (NOR) gate.

3. The memory with test function as claimed in claim 1, wherein the memory array further comprises a plurality of sub-arrays arranged in a matrix form, and Each of the plurality of sub-arrays includes a plurality of bit lines, the plurality of bit lines being divided into a plurality of even bit lines and a plurality of odd bit lines. The even bit lines and the odd bit lines are interleaved with each other, and The test data from the even input buffer is written into the memory cell via the even bit lines, and the test data from the odd input buffer is written into the memory cell via the odd bit lines.

4. The memory with test function according to claim 3 , wherein each of the plurality of sub-arrays further comprises: a first set of local I / O lines connected to the even bit lines via corresponding sense amplifiers; a second set of local I / O lines connected to the odd bit lines via corresponding sense amplifiers; and A set of main I / O lines intersects the first set of local I / O lines and the second set of local I / O lines. 5 . The memory with a test function as claimed in claim 4 , wherein the number of the set of master I / O lines is equal to the number of the first set of local I / O lines and the second set of local I / O lines.

6. The memory with test function as claimed in claim 3, wherein each of the plurality of sub-arrays further comprises a predetermined number of spare bit lines for replacing defective bit lines in the sub-array.

7. The memory with a test function as claimed in claim 6, wherein once the defective bit line in the sub-array is detected, all of the predetermined number of spare bit lines are replaced with the bit line.

8. The memory with a test function according to claim 1, wherein the memory is a high-I / O semiconductor memory.

9. The memory with a test function according to claim 8, wherein the multi-I / O semiconductor memory is a multi-I / O DRAM.

10. A method for testing a memory, wherein the memory has a memory array, the memory array having a plurality of even input buffers and odd input buffers and a plurality of even output buffers and odd output buffers, the method comprising: Writing test data into memory cells of the memory under test via at least two data input pads and via the plurality of even input buffers and odd input buffers, reading the test data from the memory cell via the plurality of even output buffers and odd output buffers; performing a first logic operation on outputs of the plurality of even output buffers to obtain a first logic value, and performing a first logic operation on outputs of the plurality of odd output buffers to obtain a second logic value; performing a second logic operation on the first logic value and the second logic value to output a third logic value on at least one data output pad; as well as Whether the memory cell is defective or non-defective is determined based on the third logic value.

11. The method for testing a memory according to claim 10 , wherein the test data from one of the at least two data input pads is continuously burst-written into the even input buffer, and the test data from the other of the at least two data input pads is continuously burst-written into the odd input buffer. 12 . The method for testing a memory according to claim 10 , wherein the first logical operation is an exclusive-OR, and the second logical operation is a negative-OR.

13. The method for testing a memory according to claim 10 , wherein the memory array further comprises a plurality of sub-arrays arranged in a matrix form, and each of the plurality of sub-arrays comprises a plurality of bit lines divided into a plurality of even bit lines and a plurality of odd bit lines, and the method further comprises: writing the test data from the even input buffer to the memory cell via the even bit line, and The test data is written from the odd input buffer to the memory cell via the odd bit lines.

14. The method for testing a memory according to claim 13 , wherein each of the plurality of sub-arrays further comprises a predetermined number of spare bit lines, and the method for testing a memory comprises: Defective bit lines in the sub-array are replaced with the predetermined number of spare bit lines.

15. The method for testing a memory as claimed in claim 14, wherein upon detecting the defective bit line in the sub-array, all of the predetermined number of spare bit lines are replaced with the bit line.

16. The method for testing a memory according to claim 10, wherein the memory is a high I / O semiconductor memory.

17. The method for testing a memory according to claim 16, wherein the high-I / O semiconductor memory is a high-I / O DRAM.

Images