Wafer matching methods and apparatus, fabrication methods, electronic devices and storage media

Abstract

This invention provides a wafer matching method and apparatus, a fabrication method, an electronic device, and a storage medium. The wafer matching method includes: obtaining a set of influence factors for multiple first wafers and multiple second wafers; obtaining a set of principal component factors by dimensionality reduction based on the set of influence factors; determining the degree of matching between each first wafer and each second wafer based on the set of principal component factors; and selecting a second wafer that matches the first wafer from the multiple second wafers based on the degree of matching. This invention not only reduces the workload in determining the degree of matching between wafers by using the set of principal component factors to represent all influence factors, thus improving the production efficiency of 3D memory, but also ensures optimal and stable matching between the first and second wafers by matching the degree of matching, thereby improving the reliability of 3D memory devices fabricated by bonding processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a wafer matching method and apparatus, a method for fabricating a three-dimensional memory, an electronic device, and a storage medium. Background Technology

[0002] With the development of the electronics industry, the functions of chips are becoming increasingly complex, and new semiconductor technologies are constantly emerging. The fabrication of three-dimensional memory typically employs hybrid bonding technology, which involves bonding two wafers together to form the corresponding functional product.

[0003] However, during the bonding process, the characteristics of the wafer itself can affect the bonding result between wafers. Therefore, to ensure effective bonding between two wafers, strict control of wafer quality parameters is required. However, high quality requirements mean low production efficiency. In addition, when bonding between two wafers, suboptimal bonding combinations may occur, leading to increased uncertainty in the bonding process and reduced reliability of the fabricated 3D memory.

[0004] Therefore, existing technologies have shortcomings and need to be improved and developed. Summary of the Invention

[0005] This invention provides a wafer matching method and apparatus, a method for fabricating a three-dimensional memory, an electronic device, and a storage medium, aiming to improve the production efficiency and reliability of three-dimensional memory.

[0006] In a first aspect, the present invention provides a wafer matching method, comprising: obtaining a set of influence factors for a plurality of first wafers and a plurality of second wafers; obtaining a set of principal component factors by dimensionality reduction based on the set of influence factors; determining the degree of matching of each first wafer with respect to each second wafer based on the set of principal component factors; and selecting a second wafer that matches the first wafer from the plurality of second wafers based on the degree of matching.

[0007] The step of determining the matching degree of each first wafer relative to each second wafer based on the principal component factor set includes: obtaining a first parameter set corresponding to each first wafer and a second parameter set for each second wafer based on the principal component factor set; and determining the matching degree based on the first parameter set and the second parameter set.

[0008] The step of analyzing the first parameter set and the second parameter set to determine the degree of matching includes:

[0009] Calculate the similarity distance between the first parameter set and the second parameter set; determine the matching degree based on the similarity distance.

[0010] The step of selecting a second wafer that matches the first wafer from a plurality of second wafers according to the matching degree includes: for each first wafer, sorting a plurality of second wafers according to the matching degree to establish a first lookup table; for each second wafer, sorting a plurality of first wafers according to the matching degree to establish a second lookup table; and determining a first wafer that matches each second wafer according to the first lookup table and the second lookup table.

[0011] The method further includes, after obtaining the influence factor sets of multiple first wafers and multiple second wafers, obtaining a first feature parameter set corresponding to each first wafer and a second feature parameter set corresponding to each second wafer based on the influence factor sets; and performing dimensionless processing on the first feature parameter set and the second feature parameter set.

[0012] The step of obtaining the principal component factor set by dimensionality reduction of the influence factor set includes: establishing analysis conditions; and obtaining the principal component factor set by dimensionality reduction of the influence factor set based on the analysis conditions.

[0013] Secondly, the present invention also provides a method for fabricating a three-dimensional memory, comprising: determining a second wafer that matches a first wafer using the wafer matching method described above; and bonding the first wafer and the second wafer.

[0014] Thirdly, the present invention also provides a wafer matching device, comprising: an acquisition module for acquiring a set of influence factors for a plurality of first wafers and a plurality of second wafers; an analysis module for analyzing and acquiring a set of principal component factors based on the set of influence factors; a determination module for determining the degree of matching of each first wafer relative to each second wafer based on the set of principal component factors; and a matching module for selecting a second wafer that matches the first wafer from the plurality of second wafers based on the degree of matching.

[0015] The determining module includes: an acquisition unit, configured to acquire a first parameter set corresponding to each first wafer and a second parameter set corresponding to each second wafer based on the principal component factor set; and a determining unit, configured to determine the matching degree based on the first parameter set and the second parameter set.

[0016] The determining module includes: a calculation subunit for calculating the similarity distance between the first parameter set and the second parameter set; and a determining subunit for determining the matching degree based on the similarity distance.

[0017] The matching module includes: a first establishing unit, configured to sort multiple second wafers according to the matching degree for each first wafer to establish a first lookup table; a second establishing unit, configured to sort multiple first wafers according to the matching degree for each second wafer to establish a second lookup table; and a matching unit, configured to determine a first wafer that matches each second wafer according to the first lookup table and the second lookup table.

[0018] Fourthly, the present invention also provides a storage medium storing a computer-executable program, which, when invoked, executes the wafer matching method as described above.

[0019] Fifthly, the present invention also provides an electronic device, the electronic device comprising an input device, one or more memories, and one or more processors, the input device being configured to receive an influence factor set for each first wafer and also being configured to receive an influence factor set for each second wafer, the one or more memories storing a computer-executable program, the computer-executable program being invoked by the one or more processors to execute the wafer matching method as described above.

[0020] This invention provides a wafer matching method and apparatus, a method for fabricating a three-dimensional memory, an electronic device, and a storage medium. The wafer matching method includes: obtaining a set of influence factors for multiple first wafers and multiple second wafers; obtaining a set of principal component factors by dimensionality reduction based on the set of influence factors; determining the degree of matching between each first wafer and each second wafer based on the set of principal component factors; and selecting a second wafer that matches the first wafer from the multiple second wafers based on the degree of matching. In this invention, by reducing the dimensionality of the set of influence factors of the wafers to obtain the set of principal component factors, the correlation between the sets of influence factors can be eliminated, and a smaller set of principal component factors can represent the entire set of influence factors, reducing the workload in determining the degree of matching between wafers and improving matching efficiency, thereby improving the production efficiency of three-dimensional memory. This invention also matches the first wafers and second wafers based on the degree of matching, which can ensure that the matching between the wafers is optimal, which helps to reduce the uncertainty in the bonding process, thereby improving the reliability of the three-dimensional memory device fabricated by the bonding process. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of the wafer matching method provided in an embodiment of the present invention;

[0023] Figure 2 This is an application scenario diagram of the three-dimensional memory fabrication method provided in the embodiments of the present invention;

[0024] Figure 3 This is another schematic flowchart of the wafer matching method provided in an embodiment of the present invention;

[0025] Figure 4 This is the first comparison table provided in the embodiments of the present invention;

[0026] Figure 5 This is the second comparison table provided in the embodiments of the present invention;

[0027] Figure 6 This is the matching result table provided in the embodiments of the present invention;

[0028] Figure 7 This is a schematic diagram of the wafer matching device provided in an embodiment of the present invention;

[0029] Figure 8 This is a schematic diagram of the structure of the determining unit provided in an embodiment of the present invention;

[0030] Figure 9 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0032] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0033] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0034] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0035] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0036] This invention provides a wafer matching method, a wafer matching device, a method for fabricating a three-dimensional memory, and a storage medium.

[0037] Please see Figure 1 , Figure 1 This is a schematic flowchart of the wafer matching method provided in an embodiment of the present invention. Figure 2 As shown, this wafer matching method can specifically be used to match array wafers and CMOS wafers. The matched array wafers and CMOS wafers are bonded to form a three-dimensional memory. However, this matching method is not limited to matching array wafers and CMOS wafers. For example, in other embodiments, it can also be used to match carrier wafers and device wafers.

[0038] like Figure 1 As shown, the matching method may include the following steps:

[0039] Step S101: Obtain the influence factor sets of multiple first wafers and multiple second wafers.

[0040] In this embodiment, the first wafer can be an array wafer, and the second wafer can be a CMOS wafer, or the first wafer can be a CMOS wafer and the second wafer can be an array wafer, meaning the first wafer and the second wafer are one of two different types of wafers. There can be multiple first wafers and multiple second wafers, and the number of first wafers and second wafers can be the same or different. It should be noted that in this embodiment, it is preferable to use first wafers and second wafers of the same model for matching to avoid subsequent bonding processes being impossible due to matching with wafers of different models. For multiple first wafers or second wafers, it is preferable to use wafers produced in the same batch to reduce structural errors between multiple first wafers or multiple second wafers. For the first wafer and the second wafer, the set of influencing factors may include wafer curvature S1, wafer expansion rate S2, wafer bonding X-direction position error S3, wafer bonding Y-direction position error S4, bonding oxide layer thickness S5, and wafer thickness S6. For different types of influencing factors, taking the first wafer as an example, the first wafer has corresponding characteristic parameter values. The set of these characteristic parameter values ​​is defined as the characteristic parameter set of the first wafer, which is a physical characteristic inherent in the wafer itself. Therefore, after step S101, the process further includes:

[0041] Based on different influence factors, obtain the first characteristic parameter set for each first wafer and the second characteristic parameter set for each second wafer.

[0042] The first feature parameter set and the second feature parameter set are dimensionless.

[0043] Since different parameter values ​​have different units and magnitudes depending on the type of influencing factor, for example, the difference in magnitude between the units of bonding oxide layer thickness S5 and wafer thickness S6 is exponential. Therefore, in order to eliminate the influence of the units and magnitudes of different influencing factors on the subsequent matching process, it is necessary to perform dimensionless processing on the influencing factors.

[0044] Specifically, the corresponding dimensionless processing is achieved by applying the z-score (zero-mean normalization) formula to the parameter values:

[0045] Taking the first wafer as an example, in the above formula, S is the characteristic parameter value of each first wafer, the sample mean corresponding to multiple characteristic parameter values ​​of the first wafer, and σ is the sample standard deviation corresponding to multiple characteristic parameter values ​​of the first wafer. After dimensionless transformation, the average value of each characteristic parameter value is 0, and the standard deviation is 1, thereby eliminating the influence of dimensions and orders of magnitude.

[0046] Step S102: Obtain the principal component factor set by dimensionality reduction based on the influencing factor set;

[0047] Please see Figure 3 Specifically, step S102 may include:

[0048] Step S1021: Establish analysis conditions.

[0049] Step S1022: Dimensionally reduce the set of influencing factors according to the analysis conditions to obtain the set of principal component factors.

[0050] Specifically, these analytical conditions can be obtained using Principal Component Analysis (PCA). PCA recombines the original numerous influencing factors into a new set of uncorrelated principal component factors, effectively differentiating the evaluated objects and highlighting their differences. These principal component factors can be obtained by linearly matching the original influencing factors. For example, principal component factor X1 = 0.8*S′1 + 0.6*S′2 + 0.3*S′3 + 0.1*S′4 + 0.2*S′5 + 0.3*S′6, and principal component factor X2 = 0.2*S′1 + 0.1*S′2 + 0.7*S′3 + 0.8*S′4 + 0.2*S′5 + 0.3*S′6. Since different influencing factors have different weights, principal component factor X1 primarily measures the impact of wafer deformation on the matching process, while principal component factor X2 primarily measures the impact of bonding alignment on the matching process. In this embodiment, when dimensionality reduction is performed by weighting the impact factors, principal component factors with a cumulative percentage of 80% are used to represent all impact factors. The principal component factor set is defined as (X1, X2, ..., X...). k The value of k depends on the results of principal component analysis. Since there are 6 types of influencing factors in this embodiment, it is preferable that k is less than 6.

[0051] S103: Determine the degree of matching of each of the first wafers relative to each of the second wafers based on the principal component factor set.

[0052] Please see Figure 3 Specifically, step S103 may include:

[0053] Step S1031: Obtain the first parameter set corresponding to each first wafer and the second parameter set corresponding to each second wafer based on the principal component factor.

[0054] The first parameter set and the second parameter set are obtained by processing the dimensionless first and second characteristic parameter sets according to the analysis conditions. In this embodiment, when the first wafer is selected as an array wafer, the first parameter set is defined as {X}. a1 ,X a2,…,X ak When the second wafer is selected as a CMOS wafer, the second parameter set is defined as {X}. c1 ,X c2 ,…,X ck}

[0055] Step S1032: Determine the degree of matching based on the first parameter set and the second parameter set.

[0056] Specifically, step S1032 may include: calculating the similarity distance between the first parameter set and the second parameter set; and determining the matching degree based on the similarity distance.

[0057] When the first parameter set is defined as {X a1 ,X a2 ,…,X ak}, define the second parameter set as {X c1 ,X c2 ,…,X ck When}, the degree of matching between each of the first wafers and each of the second wafers can be determined by the cosine similarity or Euclidean distance when the first parameter set and the second parameter set are used as vectors.

[0058] Among them, Euclidean distance:

[0059]

[0060] in,

[0061] Angle θ (cosine similarity): For a given first wafer, the degree of matching can be determined by ranking the Euclidean distances or angles between the first wafer's first parameter set and the second parameter sets of multiple second wafers and the first parameter set. A smaller Euclidean distance or angle indicates a better match between the second wafer and the first wafer. It should be noted that when the Euclidean distance alone is insufficient for ranking, the angle can be used as an auxiliary ranking method. In this embodiment, a comprehensive evaluation can be performed using the values ​​of Euclidean distance and cosine similarity until a ranking level is determined. Specifically, multiple second wafers can be ranked from highest to lowest matching degree, from level 1 to level n, where n is a natural number greater than 1, and the value of n depends on the number of second wafers requiring matching.

[0062] For a given second wafer, the degree of matching can be determined by sorting the calculated Euclidean distances or angles between the second set of parameters of the second wafer and the first set of parameters of multiple first wafers. A smaller Euclidean distance or angle indicates a better match between the first and second wafers. In this embodiment, multiple first wafers can be sorted in descending order of matching degree from level 1 to level n, where n is a natural number greater than 1, and the value of n depends on the number of first wafers.

[0063] S104: Select a second wafer that matches the first wafer from among the multiple second wafers according to the matching degree.

[0064] When multiple second wafers are sorted in descending order of matching degree from highest to lowest, the second wafer with a ranking of 1 is the optimal match for the first wafer. However, when each first wafer needs a stable matching second wafer, the second wafer with a ranking of 1 is not necessarily a stable match for the first wafer, because it can choose another first wafer with a higher matching degree. Therefore, to ensure stable matching between multiple first wafers and multiple second wafers, as follows... Figure 5 As shown, step S104 may further include:

[0065] Step S1041: For each of the first wafers, sort the multiple second wafers according to the degree of matching to establish a first lookup table.

[0066] Please see Figure 4 and Figure 5 In this embodiment, the first wafer is selected as an array wafer Ai, and the second wafer is a CMOS wafer Cj, with both the first and second wafers numbered 25. Figure 4 As shown, multiple second wafers Cj can be sorted in descending order of matching degree from high to low by using the order from level 1 to level 25.

[0067] Step S1042: For each of the second wafers, sort the multiple first wafers according to the degree of matching to establish a second lookup table.

[0068] like Figure 5 As shown, multiple first wafers Ai can be sorted in descending order of matching degree from high to low by using the order from level 1 to level 25.

[0069] Step S1043: Determine the first wafer that matches each of the second wafers according to the first lookup table and the second lookup table.

[0070] Step S1043 can be implemented using the Gale-Shapley algorithm (GS algorithm). When multiple first wafers are matched with multiple second wafers, the first and second wafers are respectively the requester and receiver of the matching request. The requesting object Ai (representing the first wafer), i = 1, 2…25, sends a matching request to the other object Cj (representing the second wafer), j = 1, 2…n. Each Cj compares the received matching requests according to a second lookup table, retaining the higher-ranking Ai and rejecting the others. The rejected Ai continues to send new matching requests to other Cjs until no more Ais wish to send matching requests. At this point, each Cj finally accepts its retained matching requests. A key aspect of this algorithm is that higher-ranking matching requests are not immediately accepted but are only temporarily retained without rejection, i.e., "delayed acceptance." The Gale-Shapley algorithm is used to establish a stable match between each second wafer and a first wafer. This effectively utilizes all wafers when matching multiple wafers, resulting in stable matching of first and second wafers. Therefore, this method not only saves costs but also improves the tolerance of the bonding process. It should be further noted that since the first and second wafers are of two different wafer types, and the matching result obtained by the GS algorithm is favorable to the party issuing the matching request, the type of first wafer can be selected based on the degree of impact of different wafer types on the performance of the 3D memory.

[0071] The specific implementation of step S1043 can be as follows:

[0072] Step 1: Create two arrays, M_A and M_C, to store the pairing status of the first and second wafers, respectively. Initialize both arrays to -1, where -1 indicates no pairing.

[0073] Step 2: Retrieve the first unpaired Array Wafer A from M_A and record its index as i. If no Array Wafer can be retrieved (i.e., i = -1), it means all have been paired, so skip to step 8.

[0074] Step 3: Take out the C(j)th CMOS Wafer from the list in the first reference table (j is initialized to 0);

[0075] Step 4: If the extracted CMOSWaferC(j) has not been paired yet, then they can be paired.

[0076] Step 5: If the CMOSWaferC(j) has already been paired, then retrieve the Array Wafer a that is paired with this CMOSWafer C(j) from M_C[j], record its index as i2, and compare it with the Array Wafer A to be matched using the second reference table. If A is before a, meaning that for Array Wafer A, the CMOSWaferC(j) is closer to Array Wafer A, then change the CMOS pairing result M_c[j] to pair with A, i.e., set M_c[j] = i. At the same time, Array Wafer A is paired with this CMOSWafer C(j), i.e., set M_A[i] = j. Array Wafer A is temporarily left out, and the Ai corresponding to i2 in the first reference table is set to -1, indicating that there is no match.

[0077] Step 6: If CMOSWafer C(j) rejects ArrayWaferA because it is closer to ArrayWaferA, then ArrayWaferA can no longer match CMOSWafer C(j). It can only find the C(j+1)th CMOS Wafer in its closest first reference table, set j = j+1, and then jump to step 3 above.

[0078] Step 7: After the operations in steps 3-6 above, this Array Wafer A is now paired. After it is successfully paired, other Array Wafers that have already been paired may be kicked out. We just need to continue looping step 2 to find the first Array Wafer that has not been paired and pair it. Therefore, we need to skip to step 2.

[0079] Step 8: Reaching this step indicates that all Array Wafers have been paired, meaning all Arrays and CMOS Wafers have been successfully paired, and the matching results can be output. After the above steps, stable matching is complete. In this embodiment, when the first lookup table and the second lookup table are as follows... Figure 4 and Figure 5 As shown, the final matching result image is as follows. Figure 6 As shown. The above operations can be implemented through code.

[0080] In the wafer matching method provided by this invention, the principal component factor set is obtained by dimensionality reduction of the wafer's influence factor set, which can eliminate the correlation between influence factors. Furthermore, a smaller number of principal component factors can represent all influence factors, reducing the workload in determining the matching degree between wafers and improving matching efficiency, thereby improving the production efficiency of three-dimensional memory. This invention also matches the first wafer and the second wafer based on the matching degree, which can ensure that the matching between wafers is optimal, which helps to reduce the uncertainty in the bonding process and thus improve the reliability of three-dimensional memory devices prepared by the bonding process.

[0081] This invention also provides a method for fabricating a three-dimensional memory, comprising: determining a second wafer that matches a first wafer using any of the wafer matching methods described above; and bonding the first wafer and the second wafer. Please refer to [link to previous document]. Figure 2 , Figure 2 This is an application scenario diagram of the preparation method, such as... Figure 2 As shown, by using the wafer matching method provided above, the first wafer (CMOS wafer: C15) and the second wafer (array wafer: A15) can be determined to be the optimal stable match. Then, A15 and C15 are bonded to obtain the final product (three-dimensional memory).

[0082] Based on the methods described in the above embodiments, this embodiment will be further described from the perspective of a wafer matching device. Please refer to [link / reference needed]. Figure 7 , Figure 7 This is a schematic diagram of the wafer matching device provided in an embodiment of the present invention. The wafer matching device includes an acquisition module 10, an analysis module 20, a determination module 30, and a matching module 40, wherein:

[0083] (1) Obtain module 10

[0084] The acquisition module 10 is used to acquire the influence factor sets of multiple first wafers and multiple second wafers.

[0085] The first wafer can be an array wafer, and the second wafer can be a CMOS wafer. The types of the first and second wafers can be interchangeable. There can be multiple first and second wafers, and the number of first and second wafers can be the same or different. It should be noted that in this embodiment, it is preferable to use first and second wafers of the same model for matching to avoid subsequent bonding processes being impossible due to the use of different models of wafers. For multiple first or second wafers, it is preferable to use wafers produced in the same batch to reduce structural errors between multiple first or second wafers. For the first and second wafers, the set of influencing factors may include wafer curvature S1, wafer expansion rate S2, wafer bonding X-direction position error S3, wafer bonding Y-direction position error S4, bonding oxide layer thickness S5, and wafer thickness S6. For different types of influencing factors, taking the first wafer as an example, the first wafer has corresponding characteristic parameter values. The set of these characteristic parameter values ​​is defined as the characteristic parameter set of the first wafer, which is a physical characteristic inherent to the wafer itself. The acquisition module 10 is also used to: acquire the first characteristic parameter set corresponding to each first wafer and the second characteristic parameter set corresponding to each second wafer according to different influencing factors; and perform dimensionless processing on the first characteristic parameter set and the second characteristic parameter set.

[0086] Since different parameter values ​​have different units and magnitudes depending on the type of influencing factor, for example, the difference in magnitude between the units of bonding oxide layer thickness S5 and wafer thickness S6 is exponential. Therefore, in order to eliminate the influence of the units and magnitudes of different influencing factors on the subsequent matching process, it is necessary to perform dimensionless processing on the influencing factors.

[0087] Specifically, the corresponding dimensionless processing is achieved by applying the z-score (zero-mean normalization) formula to the parameter values:

[0088] Taking the first wafer as an example, in the above formula, S is the characteristic parameter value of each first wafer, the sample mean corresponding to multiple characteristic parameter values ​​of the first wafer, and σ is the sample standard deviation corresponding to multiple characteristic parameter values ​​of the first wafer. After dimensionless transformation, the average value of each characteristic parameter value is 0, and the standard deviation is 1, thereby eliminating the influence of dimensions and orders of magnitude.

[0089] (2) Analysis Module 20

[0090] Analysis module 20 is used to analyze and obtain the principal component factor set based on the set of influencing factors.

[0091] Specifically, the analysis module 20 is used to: establish analysis conditions; and reduce the dimensionality of the influencing factor set based on the analysis conditions to obtain the principal component factor set.

[0092] Specifically, these analytical conditions can be obtained using Principal Component Analysis (PCA). In PCA, the weights of different influencing factors come from the characteristic parameter set itself, and the principal component factors constructed based on these weights can distinguish the evaluation objects as much as possible, highlighting their differences. These principal component factors can be obtained by linearly matching the influencing factors. For example, principal component factor X1 = 0.8*S′1 + 0.6*S′2 + 0.3*S′3 + 0.1*S′4 + 0.2*S′5 + 0.3*S′6, and principal component factor X2 = 0.2*S′1 + 0.1*S′2 + 0.7*S′3 + 0.8*S′4 + 0.2*S′5 + 0.3*S′6. Since the weights of different influencing factors are different, principal component factor X1 mainly measures the impact of wafer deformation degree on the matching process, while principal component factor X2 mainly measures the impact of bonding alignment degree on the matching process. In this embodiment, when dimensionality reduction is performed by weighting the impact factors, principal component factors with a cumulative percentage of 80% are used to represent all impact factors. The principal component factor set is defined as (X1, X2, ..., X...). k The value of k depends on the results of principal component analysis. Since there are 6 types of influencing factors in this embodiment, it is preferable that k is less than 6.

[0093] (3) Determine module 30

[0094] The determination module 30 is used to determine the degree of matching of each of the first wafers relative to each of the second wafers based on the principal component factor.

[0095] The determining module 30 includes an acquisition unit 31 and a determining unit 32.

[0096] The acquisition unit 31 is used to acquire the first parameter set corresponding to each of the first wafers and the second parameter set corresponding to each of the second wafers based on the principal component factor;

[0097] The first parameter set and the second parameter set are obtained by processing the dimensionless first and second characteristic parameter sets according to the analysis conditions. In this embodiment, when the first wafer is selected as an array wafer, the first parameter set is defined as {X}. a1 ,X a2 ,…,X ak When the second wafer is selected as a CMOS wafer, the second parameter set is defined as {X}. c1 ,X c2 ,…,X ck}

[0098] Determining unit 32 is used to determine the degree of matching based on the first parameter set and the second parameter set. For example... Figure 8 As shown, the determining unit 32 includes: a calculation subunit 321, used to calculate the similarity distance between the first parameter set and the second parameter set; and a determining subunit 322, used to determine the matching degree based on the similarity distance.

[0099] When the first parameter set is defined as {X a1 ,X a2 ,…,X ak}, define the second parameter set as {X c1 ,X c2 ,…,X ck When}, the degree of matching between each of the first wafers and each of the second wafers can be determined by the cosine similarity or Euclidean distance when the first parameter set and the second parameter set are used as vectors.

[0100] Among them, Euclidean distance:

[0101]

[0102] in,

[0103] Angle θ (cosine similarity): For a given first wafer, the degree of matching can be determined by ranking the Euclidean distances or angles between the first wafer's first parameter set and the second parameter sets of multiple second wafers and the first parameter set. A smaller Euclidean distance or angle indicates a better match between the second wafer and the first wafer. It should be noted that when the Euclidean distance alone is insufficient for ranking, the angle can be used as an auxiliary ranking method. In this embodiment, a comprehensive evaluation can be performed using the values ​​of Euclidean distance and cosine similarity until a ranking level is determined. Specifically, multiple second wafers can be ranked in descending order of matching degree from level 1 to level n, where n is a natural number greater than 1, and the value of n depends on the number of second wafers requiring matching.

[0104] For a given second wafer, the degree of matching can be determined by sorting the calculated Euclidean distances or angles between the second set of parameters of the second wafer and the first set of parameters of multiple first wafers. A smaller Euclidean distance or angle indicates a better match between the first and second wafers. In this embodiment, multiple first wafers can be sorted in descending order of matching degree from level 1 to level n, where n is a natural number greater than 1, and the value of n depends on the number of first wafers.

[0105] (4) Matching module 40

[0106] The matching module 40 is used to select a second wafer from multiple second wafers that matches the first wafer based on the matching degree. When the multiple second wafers are sorted in descending order of matching degree from highest to lowest, the second wafer with a ranking level of 1 is the optimal match for the first wafer. However, when each first wafer needs to have a stable matching second wafer, the second wafer with a ranking level of 1 is not necessarily a stable match for the first wafer, because the second wafer can choose another first wafer with a higher matching degree. Therefore, in order to achieve a stable match between multiple first wafers and multiple second wafers, such as... Figure 7 As shown, the matching module 40 includes a first establishment unit 41, a second establishment unit 42, and a matching unit 43.

[0107] The first establishing unit 41 is used to sort multiple second wafers according to the matching degree for each first wafer to establish a first lookup table.

[0108] Please see Figure 4 and Figure 5 In this embodiment, the first wafer is selected as an array wafer Ai, and the second wafer is a CMOS wafer Cj, with both the first and second wafers numbered 25. Figure 4 As shown, multiple second wafers Cj can be sorted in descending order of matching degree from high to low using a ranking from level 1 to level 25. The second establishment unit 42 is used to, for each second wafer, sort multiple first wafers according to the matching degree to establish a second lookup table.

[0109] like Figure 5 As shown, multiple first wafers Ai can be sorted in descending order of matching degree from high to low by using the order from level 1 to level 25.

[0110] Matching unit 43 is used to determine a first wafer that matches each of the second wafers according to the first lookup table and the second lookup table.

[0111] Step S1043 can be implemented using the Gale-Shapley algorithm (GS algorithm). When multiple first wafers are matched with multiple second wafers, the first and second wafers are respectively the requester and receiver. The requesting object Ai, i = 1, 2…25, sends a matching request to the receiving object Cj, j = 1, 2…n. Each Cj compares the received matching requests according to a second lookup table, retaining the higher-ranking Ai and rejecting the others. The rejected Ai continues to send new matching requests to other Cjs until no more Ais wish to send matching requests. At this point, each Cj finally accepts its retained matching requests. A key aspect of this algorithm is that higher-ranking matching requests are not immediately accepted but are only temporarily retained without rejection, i.e., "delayed acceptance." The Gale-Shapley algorithm is used to establish a stable match between each second wafer and a first wafer. This effectively utilizes all wafers when matching multiple wafers, resulting in stable matching of first and second wafers. Therefore, this method not only saves costs but also improves the tolerance of the bonding process. It should be further noted that since the first and second wafers are of two different wafer types, and the matching result obtained by the GS algorithm is favorable to the party issuing the matching request, the type of first wafer can be selected based on the degree of impact of different wafer types on the performance of the 3D memory.

[0112] The specific implementation method can be as follows:

[0113] Step 1: Create two arrays, M_A and M_C, to store the pairing status of the first and second wafers, respectively. Initialize both arrays to -1, where -1 indicates no pairing.

[0114] Step 2: Retrieve the first unpaired Array Wafer A from M_A and record its index as i. If no Array Wafer can be retrieved (i.e., i = -1), it means all have been paired, so skip to step 8.

[0115] Step 3: Take out the C(j)th CMOS Wafer from the list in the first reference table (j is initialized to 0);

[0116] Step 4: If the extracted CMOSWaferC(j) has not been paired yet, then they can be paired.

[0117] Step 5: If the CMOSWaferC(j) has already been paired, then retrieve the Array Wafer a that is paired with this CMOSWafer C(j) from M_C[j], record its index as i2, and compare it with the Array Wafer A to be matched using the second reference table. If A is before a, meaning that for Array Wafer a, the CMOSWaferC(j) is closer to Array Wafer A, then change the CMOS pairing result M_c[j] to pair with A, i.e., set M_c[j] = i. At the same time, Array Wafer A is paired with this CMOSWafer C(j), i.e., set M_A[i] = j. Array Wafera is temporarily left out, and Ai corresponding to i2 in the first reference table is set to -1, indicating that there is no match.

[0118] Step 6: If CMOSWafer C(j) rejects ArrayWaferA because it is closer to ArrayWaferA, then ArrayWaferA can no longer match CMOSWafer C(j). It can only find the C(j+1)th CMOS Wafer in its closest first reference table, set j = j+1, and then jump to step 3 above.

[0119] Step 7: After the operations in steps 3-6 above, this Array Wafer A is now paired. After it is successfully paired, other Array Wafers that have already been paired may be kicked out. We just need to continue looping step 2 to find the first Array Wafer that has not been paired and pair it. Therefore, we need to skip to step 2.

[0120] Step 8: Reaching this step indicates that all Array Wafers have been paired, meaning all Arrays and CMOS Wafers have been successfully paired, and the matching results can be output. After the above steps, stable matching is complete. In this embodiment, when the first lookup table and the second lookup table are as follows... Figure 4 and Figure 5 As shown, the final matching result image is as follows. Figure 6 As shown. The above operations can be implemented through code.

[0121] As described above, the wafer matching device provided by this invention acquires multiple first wafers and multiple second wafers through an acquisition module, obtains principal component factors based on the acquisition factors through an analysis module, determines the matching degree of each first wafer relative to each second wafer based on the principal component factors through a determination module, and selects a second wafer that matches the first wafer from the multiple second wafers based on the matching degree through a matching module. In this invention, by reducing the dimensionality of the wafer's acquisition factor set to obtain the principal component factor set, the correlation between acquisition factors can be eliminated, and fewer principal component factors can represent all acquisition factors, reducing the workload in determining the matching degree between wafers and improving matching efficiency, thereby improving the production efficiency of three-dimensional memory. Furthermore, this invention matches the first and second wafers based on the matching degree, ensuring optimal matching between wafers, which helps reduce uncertainties in the bonding process and improves the reliability of three-dimensional memory devices fabricated by the bonding process.

[0122] Figure 9 This is a schematic diagram of an electronic device provided by the present invention. (See diagram below.) Figure 9 As shown, the electronic device 90 includes an input device 91, one or more memories 93, and one or more processors 92. The input device 91 is used to receive the influence factor set of each first wafer and also to receive the influence factor set of each second wafer. The one or more memories 93 store a computer-executable program, which can be invoked by the one or more processors 92 to execute the wafer matching method described above. Thus, the electronic device 90 can quickly obtain a second wafer that matches the first wafer, ensuring the bonding effect of the subsequent first and second wafers.

[0123] The present invention also provides a storage medium storing a computer-executable program, which, when invoked, can execute the wafer matching method as described above.

[0124] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.

[0125] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A wafer matching method characterized by comprising: The method comprises the following steps: obtaining a set of influence factors of a plurality of first wafers and a plurality of second wafers; dimensionally reducing the set of influence factors to obtain a set of principal component factors; determining a matching degree of each of the first wafers with respect to each of the second wafers according to the set of principal component factors; for each of the first wafers, ranking the plurality of second wafers according to the matching degree to establish a first reference table, the first reference table ranking the plurality of second wafers in descending order of matching degree from high to low in the order of rank 1 to rank n, where n is a natural number greater than 1, and the value of n depends on the number of second wafers to be matched; for each of the second wafers, ranking the plurality of first wafers according to the matching degree to establish a second reference table, the second reference table ranking the plurality of first wafers in descending order of matching degree from high to low in the order of rank 1 to rank n, where n is a natural number greater than 1, and the value of n depends on the number of first wafers; determining a first wafer matched with each of the second wafers according to the first reference table and the second reference table.

2. The wafer matching method according to claim 1, wherein The step of determining a matching degree of each of the first wafers with respect to each of the second wafers according to the set of principal component factors comprises: obtaining a first parameter set corresponding to each of the first wafers and a second parameter set corresponding to each of the second wafers according to the set of principal component factors; determining the matching degree according to the first parameter set and the second parameter set.

3. The wafer matching method according to claim 2, wherein The step of determining the matching degree according to the first parameter set and the second parameter set comprises: calculating a similarity distance between the first parameter set and the second parameter set; determining the matching degree according to the similarity distance.

4. The wafer matching method according to claim 1, wherein After the step of obtaining a set of influence factors of a plurality of first wafers and a plurality of second wafers, the method further comprises: obtaining a first characteristic parameter set corresponding to each of the first wafers and a second characteristic parameter set corresponding to each of the second wafers according to different influence factors; dimensionless processing the first characteristic parameter set and the second characteristic parameter set.

5. The wafer matching method of claim 1, wherein The step of dimensionally reducing the set of influence factors to obtain a set of principal component factors comprises: establishing an analysis condition; dimensionally reducing the set of influence factors to obtain the set of principal component factors according to the analysis condition.

6. A method of fabricating a three-dimensional memory, comprising: The method comprises the following steps: determining a second wafer matched with a first wafer by the wafer matching method according to any one of claims 1 to 5; bonding the first wafer and the second wafer.

7. A wafer matching apparatus characterized by comprising: The method comprises the following steps: an obtaining module, configured to obtain a set of influence factors of a plurality of first wafers and a plurality of second wafers; an analysis module, configured to dimensionally reduce the set of influence factors to obtain a set of principal component factors; a determination module, configured to determine a matching degree of each of the first wafers with respect to each of the second wafers according to the set of principal component factors; a first establishing unit, configured to, for each of the first wafers, rank the plurality of second wafers according to the matching degree to establish a first reference table, the first reference table ranking the plurality of second wafers in descending order of matching degree from high to low in the order of rank 1 to rank n, where n is a natural number greater than 1, and the value of n depends on the number of second wafers to be matched; a second establishing unit, configured to rank the first wafers according to the matching degree for each of the second wafers to establish a second correspondence table, the second correspondence table ranking the first wafers in descending order of the matching degree from high to low in the order of level 1 to level n, where n is a natural number greater than 1, and the value of n depends on the number of the first wafers; a matching unit, configured to determine the first wafer matched with each of the second wafers according to the first correspondence table and the second correspondence table.

8. The wafer matching apparatus according to claim 7, wherein The determining module comprises: an obtaining unit, configured to obtain a first parameter set corresponding to each of the first wafers and a second parameter set corresponding to each of the second wafers according to the principal component factor set; a determining unit, configured to determine the matching degree according to the first parameter set and the second parameter set.

9. The wafer matching apparatus according to claim 8, wherein The determining unit comprises: a calculating unit, configured to calculate a similarity distance between the first parameter set and the second parameter set; a determining sub-unit, configured to determine the matching degree according to the similarity distance.

10. A storage medium, characterized by The storage medium has stored therein a computer executable program, when the computer executable program is invoked, the wafer matching method in any one of claims 1-5 is executed.

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