A peak voltage detection circuit and a peak voltage detection method

Abstract

The present invention discloses a peak voltage detection circuit and a peak voltage detection method. The circuit includes: NMOS transistor M1, NMOS transistor M2, NMOS transistor M6, PMOS transistor M3, PMOS transistor M4, PMOS transistor M7, and PMOS transistor M8, a tail current source I1, a pull-down current source I2, and a sample-and-hold capacitor Ch. Among them, the NMOS transistors M1 and M2 form a differential input transistor pair. The gate of the PMOS transistor M3 is connected to the gate of the PMOS transistor M4, and the gate of the PMOS transistor M7 is connected to the gate of the PMOS transistor M8. A switch S5 is also connected between the drain of the PMOS transistor M3 and the source of the PMOS transistor M4. The circuit in the present invention can collect and hold the peak voltage of the echo pulse with linear amplification for a certain period of time for gray-scale measurement, thereby reducing the requirement for the speed of the ADC. Moreover, it can reduce the measurement error caused by circuit offset and achieve accurate measurement.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and particularly to a peak voltage detection circuit and a peak voltage detection method. Background Art

[0002] In laser ranging technology, the method of obtaining target distance information by measuring the round-trip flight time (TOF) of a laser is widely used. Among them, the direct measurement scheme of modulating the laser intensity into a narrow pulse has the characteristics of low device cost and simple data processing. The laser TOF ranging principle mainly includes a laser emitting a laser pulse, and the echo signal after being reflected by the target is received by a photodetector. The echo time is obtained by processing the photocurrent signal and the target distance information is calculated. The measurement of the laser echo time is generally judged by detecting that the intensity of the time-domain echo signal reaches a certain threshold. However, the amplitude of the echo signal will affect the time when the echo crosses the threshold, resulting in an error, which is called the wandering error. Generally, this wandering error can be compensated in the ranging result by means of a gray scale look-up table. In order to obtain the gray scale information of the echo, it is necessary to measure the peak voltage of the echo signal. Therefore, the existing TOF ranging systems generally include an echo time measurement circuit and an echo voltage peak detection circuit, and the peak amplitude information of the echo is detected while measuring the laser pulse flight time. At present, the pulse modulation width in the TOF ranging system with centimeter-level accuracy is generally in the order of nanoseconds. To further improve the ranging accuracy, the pulse width needs to be modulated smaller, and a high-speed peak detection circuit is required.

[0003] Limited by the switching speed of discrete devices, a high-speed pulse peak voltage detection circuit cannot be designed and built on an electronic board with an operational amplifier, a switch and passive devices. The existing peak detection schemes applied to the field of narrow pulse TOF laser ranging with nanosecond-level modulation are mainly realized by a high-speed ADC cooperating with high-precision delay passive devices. In order to accurately capture the peak of the laser echo and consider the issues of power consumption and data throughput, this scheme requires the ADC sampling rate to reach more than dozens of megahertz. Since the sampling of the peak time in this scheme is fixed relative to the time of the echo threshold determination, and in the laser ranging of complex target scenes, the pulse width of the target echo will change significantly, so the error of peak detection is large. At the same time, the hardware scale of this scheme is large. In addition to the basic high-speed ADC device and passive delay device, it also requires peripheral circuits such as a high-speed ADC reference source, a clock source, and decoupling capacitors. Summary of the Invention

[0004] The present invention provides a peak voltage detection circuit and a peak voltage detection method to solve the problems that the existing peak voltage detection circuit has a high requirement for the sampling rate of the ADC, a large hardware scale and a large detection error.

[0005] To this end, according to the first aspect, the present invention provides a peak voltage detection circuit, including:

[0006] NMOS transistors M1, NMOS transistor M2, NMOS transistor M6, PMOS transistors M3, PMOS transistors M4, PMOS transistors M7 and PMOS transistor M8, a tail current source I1, a pull-down current source I2, and a sample-and-hold capacitor Ch, where

[0007] NMOS transistors M1 and M2 form a differential input pair. The gates of PMOS transistors M3 and M4 are connected to each other. The gates of PMOS transistors M7 and M8 are connected to each other. There is also a switch S5 connected between the drain of PMOS transistor M3 and the source of PMOS transistor M4.

[0008] The drain of NMOS transistor M1 is connected to the drain of PMOS transistor M3 and the gate of NMOS transistor M6 through switch S1. The drain of NMOS transistor M2 is connected to the drain and gate of PMOS transistor M4 through switch S2. The drain of NMOS transistor M1 is also connected to the drain of PMOS transistor M7 through switch S3. The drain of NMOS transistor M2 is also connected to the drain and gate of PMOS transistor M8 through switch S4. The sources of PMOS transistors M3, M4, M7, and M8, and the drain of NMOS transistor M6 are all connected to the power supply.

[0009] The source of NMOS transistor M6 is connected to one end of the sample-and-hold capacitor Ch. The other end of the sample-and-hold capacitor Ch is grounded. The pull-down current source I2 is also connected in series with switch S6 and then connected in parallel across the two ends of the sample-and-hold capacitor Ch. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 are connected to the tail current source I1 and then grounded.

[0010] The drain of PMOS transistor M7 is the output terminal of the peak voltage detection circuit. The gate of NMOS transistor M1 can be switched between the input terminal and the output terminal of the peak voltage detection circuit through switches S8 and S9.

[0011] Furthermore, the peak voltage detection circuit further includes: a reset voltage source V1. The reset voltage source V1 is connected in series with switch S7 and then connected in parallel across the two ends of the sample-and-hold capacitor Ch.

[0012] Furthermore, the peak voltage detection circuit further includes: a buffer Buffer, which is connected to the input terminal of the drain of PMOS transistor M7. The output terminal of the buffer Buffer is the output terminal of the peak voltage detection circuit.

[0013] According to a second aspect, the present invention also provides a peak voltage detection method for the peak voltage detection circuit in the above first aspect, including the following steps:

[0014] Control the closing of switch S1, switch S2, switch S6, and switch S8 to put the peak voltage detection circuit into the write state; at this time, the sampling and holding capacitor Ch detects the peak value of the pulse voltage and holds it at the peak level;

[0015] When the pulse of the pulse voltage ends, control the opening of switch S6;

[0016] Control the opening of switch S1, switch S2, switch S6, and switch S8, and control the closing of switch S3, switch S4, switch S5, and switch S9 to put the peak voltage detection circuit into the read state; at this time, the output terminal of the peak voltage detection circuit can be triggered by the rising edge of the read clock to output and hold the peak level on the sampling and holding capacitor Ch.

[0017] Furthermore, the peak voltage detection circuit further includes: a reset voltage source V1, and the reset voltage source V1 is connected in series with switch S7 and then connected in parallel across both ends of the sampling and holding capacitor Ch; before the step of controlling the closing of switch S1, switch S2, switch S6, and switch S8 to put the peak voltage detection circuit into the write state, the following steps are further included:

[0018] Control the closing of switch S3, switch S4, switch S6, and switch S7 to put the peak voltage detection circuit into the reset state; at this time, the level of the sampling and holding capacitor Ch is reset to the reset level V1.

[0019] The technical solution provided by the present invention has the following advantages:

[0020] 1. The peak voltage detection circuit provided by the present invention can collect and hold the peak voltage of the echo pulse with linear amplification for a certain period of time for gray-scale measurement, thereby reducing the requirement for the speed of the ADC; and by setting the common input differential pair transistors in the read and write states of the circuit, the measurement error caused by circuit offset is reduced, and accurate measurement is achieved; in addition, the turn-off pull-down bias current source in the circuit enables the voltage detection circuit to have a high loop gain bandwidth product during the sampling stage, thereby ensuring high-speed following of the input pulse and further ensuring accurate measurement. Description of the Drawings

[0021] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a circuit structure schematic diagram of a peak voltage detection circuit provided by an embodiment of the present invention;

[0023] Figure 2 The flowchart of steps of a peak voltage detection method provided by an embodiment of the present invention;

[0024] Figure 3 is Figure 1 the working timing diagram of the peak voltage detection circuit in

[0025] Figure 4 is Figure 1 the simplified schematic diagram of the peak voltage detection circuit in the write state in

[0026] Figure 5 is Figure 1 the simplified schematic diagram of the peak voltage detection circuit in the read state in Specific embodiments

[0027] Next, the technical solution of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0028] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0029] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] Embodiment 1

[0031] This embodiment provides a peak voltage detection circuit. As shown in Figure 1 , the peak voltage detection circuit includes: NMOS transistor M1, NMOS transistor M2, NMOS transistor M6, PMOS transistor M3, PMOS transistor M4, PMOS transistor M7, and PMOS transistor M8, tail current source I1, pull-down current source I2, and sample and hold capacitor Ch. Among them,

[0032] The NMOS transistor M1 and the NMOS transistor M2 form a differential input transistor pair. The gates of the PMOS transistor M3 and the PMOS transistor M4 are connected to each other. The gates of the PMOS transistor M7 and the PMOS transistor M8 are connected to each other. A switch S5 is also connected between the drain of the PMOS transistor M3 and the source of the PMOS transistor M4.

[0033] The drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor M3 and the gate of the NMOS transistor M6 through the switch S1. The drain of the NMOS transistor M2 is connected to the drain and the gate of the PMOS transistor M4 through the switch S2. The drain of the NMOS transistor M1 is also connected to the drain of the PMOS transistor M7 through the switch S3. The drain of the NMOS transistor M2 is also connected to the drain and the gate of the PMOS transistor M8 through the switch S4. The sources of the PMOS transistor M3, the PMOS transistor M4, the PMOS transistor M7, the PMOS transistor M8, and the drain of the NMOS transistor M6 are all connected to the power supply.

[0034] The source of the NMOS transistor M6 is connected to one end of the sampling and holding capacitor Ch. The other end of the sampling and holding capacitor Ch is grounded. The pull-down current source I2 is also connected in series with the switch S6 and is connected in parallel across both ends of the sampling and holding capacitor Ch. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 are connected to the tail current source I1 and then grounded.

[0035] The drain of the PMOS transistor M7 is the output terminal of the peak voltage detection circuit. The gate of the NMOS transistor M1 can be switched between the input terminal and the output terminal of the peak voltage detection circuit through the switches S8 and S9.

[0036] In this embodiment, the switching between the closing and opening of each switch can correspondingly switch the working state of the peak voltage detection circuit. Specifically, when switches S1, S2, S6, and S8 are closed (other switches are open), the peak voltage detection circuit enters the read state. At this time, the core circuit is configured by the gating of the switches as a two-stage amplifier with unity-gain negative feedback as the error amplifier. The first stage is a classic five-transistor amplifier, and the second stage is a simple inverting amplifier including a pull-up current source and a peak-holding capacitor. The error amplifier can unidirectionally charge the sample-and-hold capacitor Ch to achieve the functions of peak detection and holding. At this time, NMOS transistors M1 and M2 in the circuit are the differential input pair transistors of the first stage; PMOS transistors M3 and M4 serve as a current mirror and are the active load of the first-stage amplifier; NMOS transistor M6 is the input transistor of the second-stage amplifier and is used to charge the sample-and-hold capacitor Ch. And a tiny pull-down current source I2 in the circuit provides a bias current for the second-stage amplifier circuit, so that the error amplifier also has a large gain-bandwidth product at the start of the pulse (the pulse of the pulse voltage to be detected). When the pulse ends, the current bias is turned off in time to prevent leakage error during peak level holding. The magnitude of the bias current can be set according to actual applications, and a trade-off is made between the pulse peak level following speed and the holding leakage error.

[0037] In this embodiment, when switches S3, S4, S5, and S9 are closed (other switches are open), the peak voltage detection circuit enters the write state. At this time, the pulse input signal is disconnected, and the core circuit is configured by the gating of the switches as a two-stage amplifier with unity negative feedback and a peak sampling capacitor as the input as the readout buffer. The differential input pair transistors of the first stage are shared with the error amplifier, and the second-stage amplifier is used to provide a greater load driving ability and a greater output swing. At this time, NMOS field-effect transistor M1 is turned off through switch S5 to ensure that the voltage in the peak-holding capacitor Ch is not affected.

[0038] As an optional implementation manner of this embodiment, as Figure 1 shown, the peak voltage detection circuit may further include a reset voltage source V1. The reset voltage source V1 is connected in series with switch S7 and then connected in parallel across both ends of the sample-and-hold capacitor Ch.

[0039] At this time, the peak voltage detection circuit is configured to enter the reset state through the gating of the switches. Specifically, switches S3, S4, S6, and S7 are closed (other switches are open). At this time, the level of the sample-and-hold capacitor Ch is reset to the initial (reset) level V1.

[0040] As an optional implementation manner of this embodiment, as Figure 1As shown, the peak voltage detection circuit may further include a buffer Buffer. At this time, the input end of the drain of the PMOS transistor M7 is connected, and the output end of the buffer Buffer is the output end of the peak voltage detection circuit.

[0041] The peak voltage detection circuit in this embodiment can collect and hold the peak voltage of the echo pulse with linear amplification for a certain time for gray-scale measurement, thereby reducing the requirement for the speed of the ADC; and by setting the input differential pair transistors shared in the read and write states of the circuit, the measurement error caused by circuit offset is reduced to achieve accurate measurement; in addition, the switchable pull-down bias current source in the circuit enables the voltage detection circuit to have a high loop gain bandwidth product in the sampling stage, thereby ensuring high-speed following of the input pulse and further ensuring accurate measurement.

[0042] Embodiment 2

[0043] This embodiment provides a peak voltage detection method, which is essentially the usage method of the peak voltage detection circuit in the above Embodiment 1. As Figure 2 shown, the peak voltage detection method includes the following steps:

[0044] S10: Control the closing of switches S1, S2, S6, and S8 to make the peak voltage detection circuit enter the write state. At this time, the sampling and holding capacitor Ch detects the peak value of the pulse voltage and holds it at the peak level.

[0045] S20: When the pulse of the pulse voltage ends, control the opening of switch S6.

[0046] S30: Control the opening of switches S1, S2, S6, and S8, and control the closing of switches S3, S4, S5, and S9 to make the peak voltage detection circuit enter the read state. At this time, the output end of the peak voltage detection circuit can be triggered by the rising edge of the read clock to output and hold the peak level on the sampling and holding capacitor Ch.

[0047] As an optional implementation manner of this embodiment, when the peak voltage detection circuit further includes: a reset voltage source V1, and the reset voltage source V1 is connected in series with the switch S7 and then connected in parallel across both ends of the sampling and holding capacitor Ch, as Figure 2 shown, before step S10 in the above peak voltage detection method, there is further a step S40:

[0048] S40: Control the closing of switches S3, S4, S6, and S7 to make the peak voltage detection circuit enter the reset state. At this time, the level of the sampling and holding capacitor Ch is reset to the reset level V1.

[0049] The following is a detailed description of the above steps S10 - S40:

[0050] Figure 3 It is the working timing diagram of the peak voltage detection circuit in Embodiment 1. As Figure 3 shown, the working timing of the peak voltage detection circuit is divided into three states (phases), namely the reset state "RST", the write state "Write", and the read state "Read".

[0051] Among them, the reset state is controlled by RST, and the high level is valid. When resetting, the read-write control signal (RpWn) must be in the write state with a low level. In the reset state, the voltage on the peak holding capacitor is fully reset to the initial level. To ensure complete discharge and reset of the capacitor, the duration of the reset state needs to be greater than 50 ns.

[0052] In the reset state, Figure 1 switches S3, S4, S6, and S7 are closed (other switches are open). At this time, the level of the sample and hold capacitor Ch is reset to the initial (reset) level V1.

[0053] Keep "RpWn" at 0. When "RST" jumps from 1 to 0, it switches to the write state. At this time, WTRIG starts to be valid. The first rising edge of WTRIG turns on the first echo, and the falling edge turns off the first echo. At this time, the peak voltage detection circuit has been gated and can receive and store the peak value of the echo. In the write state, the main function of the circuit is to detect and hold the peak value of the pulsed input voltage. At this time, Figure 1 switches S1, S2, S6, and S8 are closed (other switches are open). And through the gating of the switches, the core circuit is configured as a two-stage amplifier with unity-gain negative feedback as an error amplifier. The first stage is a classic five-transistor amplifier, and the second stage is a simple inverting amplifier including a pull-up current source and a peak holding capacitor. This error amplifier can unidirectionally charge the holding capacitor to achieve the functions of peak detection and holding. Among them, NMOS transistors M1 and M2 are the differential input pair transistors of the first stage; PMOS transistors M3 and M4 act as a current mirror and are the active load of the first-stage amplifier; NMOS transistor M6 is the input transistor of the second-stage amplifier, which is used to charge the peak holding capacitor Ch. A small pull-down current source I2 provides a bias current for the second-stage amplifier circuit, so that the error amplifier also has a large gain-bandwidth product at the start of the pulse. When the pulse ends, turn off this current bias in time to prevent leakage error when the peak level is held. The magnitude of this bias current can be set according to actual applications, and a trade-off can be made between the peak level following speed of the pulse and the holding leakage error.

[0054] Keep "RST" at 0. After "RpWn" jumps from 0 to 1, it enters the read state. At this time, Figure 1The switches S3, S4, S5, and S9 are closed (other switches are open). Through the gating switch, the pulse input signal is disconnected. The core circuit is configured with a unity negative feedback two-stage amplifier with a peak sampling capacitor as the input as the readout buffer. The differential input pair transistors of the first stage are shared with the error amplifier, and the second-stage amplifier is used to provide a greater load driving ability and a greater output swing. At this time, the NMOS transistor M1 is turned off through the switch S5 to ensure that the voltage in the sampling and holding capacitor Ch is not affected. In the read state, the rising edge of the read clock RCLK triggers the VOUT output to hold the echo peak level on the capacitor, and this level can be sampled and digitized by a low-speed ADC.

[0055] To further illustrate how the peak voltage detection circuit eliminates the offset voltage, the Figure 1 shown peak voltage detection circuit can be transformed into the Figure 4 and Figure 5 shown form. Since the offset voltage of the peak voltage detection circuit mainly comes from the input differential pair transistors, Figure 3 shown is the influence of the offset voltage on the peak voltage VH on the sampling and holding capacitor Ch in the write state. At this time, VH is as shown in Equation (1-1).

[0056] V H =V IN -V off (1-1)

[0057] Figure 4 shown is the influence of the offset voltage on the output peak result in the read state. At this time, Vout is as shown in Equation (1-2).

[0058] V out =V H +V off =V IN (1-2)

[0059] It can be found from Equations (1-1) and (1-2) that the method of sharing the input differential pair transistors for reading and writing can cancel the influence of the circuit offset.

[0060] Obviously, the above embodiments are only examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A peak voltage detection circuit, characterized in that, Comprising: NMOS transistor M1, NMOS transistor M2, NMOS transistor M6, PMOS transistor M3, PMOS transistor M4, PMOS transistor M7 and PMOS transistor M8, tail current source I1, pull-down current source I2, sample-and-hold capacitor Ch and reset voltage source V1, wherein, The NMOS transistors M1 and M2 form a differential input pair. The gates of the PMOS transistor M3 and the PMOS transistor M4 are connected to each other. The gates of the PMOS transistor M7 and the PMOS transistor M8 are connected to each other. A switch S5 is also connected between the drain of the PMOS transistor M3 and the source of the PMOS transistor M4; The drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor M3 and the gate of the NMOS transistor M6 through a switch S1. The drain of the NMOS transistor M2 is connected to the drain and gate of the PMOS transistor M4 through a switch S2. The drain of the NMOS transistor M1 is also connected to the drain of the PMOS transistor M7 through a switch S3. The drain of the NMOS transistor M2 is also connected to the drain and gate of the PMOS transistor M8 through a switch S4. The sources of the PMOS transistor M3, the PMOS transistor M4, the PMOS transistor M7, the PMOS transistor M8 and the drain of the NMOS transistor M6 are all connected to the power supply; The source of the NMOS transistor M6 is connected to one end of the sample-and-hold capacitor Ch. The other end of the sample-and-hold capacitor Ch is grounded. The pull-down current source I2 is also connected in series with a switch S6 and then connected in parallel across both ends of the sample-and-hold capacitor Ch. The sources of the NMOS transistor M1 and the NMOS transistor M2 are connected to the tail current source I1 and then grounded; The drain of the PMOS transistor M7 is the output terminal of the peak voltage detection circuit. The gate of the NMOS transistor M1 can be switched between the input terminal and the output terminal of the peak voltage detection circuit through a switch S8 and a switch S9; The reset voltage source V1 is connected in series with a switch S7 and then connected in parallel across both ends of the sample-and-hold capacitor Ch; The peak voltage detection method of the peak voltage detection circuit includes the following steps: Control to close the switch S3, the switch S4, the switch S6 and the switch S7 to make the peak voltage detection circuit enter the reset state. At this time, the level of the sample-and-hold capacitor Ch is reset to the reset level V1; Control to close the switch S1, the switch S2, the switch S6 and the switch S8 to make the peak voltage detection circuit enter the write state. At this time, the sample-and-hold capacitor Ch detects the peak value of the pulse voltage and holds it at the peak level; When the pulse of the pulse voltage ends, control to open the switch S6; Control to disconnect the switch S1, the switch S2, the switch S6, and the switch S8, and control to close the switch S3, the switch S4, the switch S5, and the switch S9, so that the peak voltage detection circuit enters the read state; at this time, the output terminal of the peak voltage detection circuit can be triggered by the rising edge of the read clock to output and hold the peak level on the sample and hold capacitor Ch.

2. The peak voltage detection circuit according to claim 1, characterized in that It further includes: A buffer Buffer, which is connected to the input terminal of the drain of the PMOS transistor M7, and the output terminal of the buffer Buffer is the output terminal of the peak voltage detection circuit.

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