A silicon carbide power diode with a triple junction terminal extension structure and a preparation method thereof

Abstract

The present invention discloses a silicon carbide power diode with a triple junction terminal extension structure and a preparation method thereof. The main structure of this device is a cylindrical structure, which is composed of an N+ type SiC substrate layer, an N-type SiC drift layer, and a P+ type SiC layer from bottom to top; the three JTE structures of this device extend from the inside to the outside in a concentric circle around the P+ type SiC layer, and are all doped with P-type impurities, but the doping size and uniformity are different; the upper and lower electrodes are respectively drawn from the P+ type SiC layer and the N+ type SiC substrate layer. The gradual impurity doping of the G-JTE2 layer is achieved by introducing graphene as an ion implantation technology for a mask layer and a vertical displacement control technology for the mask layer. The present invention creatively improves the SiC gradual impurity doping process and the device JTE structure, which can reduce the difficulty of designing impurity concentration in the JTE technology and increase the breakdown voltage of the device and the JTE layer doping dose window.

Description

Technical Background

[0001] The invention relates to a power diode, and in particular to a silicon carbide power diode with a triple-junction terminal extension structure and a preparation method thereof.

[0002] Background Field

[0003] Silicon (Si)-based devices play a very important role in almost all power electronic systems, whether they are smart home appliances, daily rail transportation, or AC / DC power transmission and transformation systems. However, today, Si-based power devices are rapidly approaching the theoretical limit determined by the characteristics of their own materials. Simply relying on optimizing the design, process, and integration of Si-based devices and their corresponding modules to further tap their performance potential can no longer meet the requirements of today's power electronic technology in terms of high efficiency and low energy consumption. Compared with Si materials, SiC materials have wider bandgap width, higher critical breakdown electric field, higher thermal conductivity and other characteristics. These characteristics enable power devices made of this material to meet high voltage, high temperature, radiation resistance and other conditions.

[0004] At present, SiC power diodes are gradually replacing Si-based power diodes in the fields of high-speed rail transportation, power grid transmission, aerospace, etc. It should be noted that there are many types of SiC power diodes on the market, among which SiC PIN power diodes are the most widely used SiC power diodes due to their advantages such as higher on-state current density and smaller reverse leakage. However, in the SiC PIN power diodes actually prepared, the breakdown voltage value obtained by the device is much smaller than the theoretical voltage value when people designed it. This is mainly because there is a certain curvature at the edge of the PN junction, which causes the strong electric field to be too concentrated. As the external bias increases, the edge electric field will quickly increase to the critical electric field of the material. This phenomenon is called the electric field edge effect. This phenomenon will cause the device to avalanche breakdown prematurely before reaching the theoretical breakdown voltage, causing the device to fail. Therefore, edge terminal technology is needed to alleviate the edge electric field concentration to increase the actual breakdown voltage of the power diode. So far, edge termination technologies include field plates (FP), field limiting rings (FLR) and junction termination extensions (JTE). Among them, JTE technology has the characteristics of simple preparation process, high breakdown efficiency and small termination area. Therefore, it has become a more common edge termination technology used in SiC PIN power diodes.

[0005] Nowadays, although the double-junction JTE structure SiC PIN power diode has improved the problem that the breakdown voltage is too sensitive to the JTE layer doping dose in the traditional single-junction JTE structure SiC PIN power diode, it also increases the difficulty of designing the impurity concentration in the JTE technology, because the ratio of the ion implantation dose between the JTE1 layer and the JTE2 layer in the traditional double-junction JTE structure SiC PIN power diode needs to be strictly controlled to have a larger breakdown voltage value, and the optimal ratio is difficult to determine. In terms of process, the appropriate doping dose window of the JTE layer and the JTE2 layer is also relatively narrow. It is worth noting that the doping dose window of the JTE layer is an important indicator for measuring the SiC PIN power diode of the JTE structure. It means that the device can maintain 85% of the theoretical breakdown voltage value within a certain JTE layer doping dose range. The wider the doping dose window of the JTE layer, the higher the reliability of the diode. Here, if you want to increase the breakdown voltage value of the SiC PIN power diode with a double-junction JTE structure and the doping dose window of the JTE layer in the process, you can introduce a uniformly doped JTE3 layer and a uniformly doped JTE4 layer at the edge of the JTE2 layer. Although this can improve the reliability of the device, the amount of improvement is very limited. In addition, if more JTE layers are introduced, it means introducing more physical variables, such as the length of the JTE3 layer, the depth of the JTE3 layer, the concentration of the JTE3 layer, etc., which will inevitably bring greater difficulties to the optimization of device reliability.

[0006] In order to significantly improve the reliability of SiC PIN power diodes without adding more physical variables, the present invention introduces G-JTE layer technology in power diode devices, hoping to improve device reliability while not causing difficulties in the process preparation of the device. Although researchers had similar ideas a long time ago, they were restricted by the current traditional gradient doping technology and SiC high temperature process requirements, and the optimization of the G-JTE layer preparation process has always been unsatisfactory, and there are still many problems caused by the process. For example, there are currently two mainstream G-JTE preparation processes. One is to use a specific instrument to fix one end of the N+ type SiC substrate layer and the other end of the P+ type SiC layer, and then continuously rotate the SiC PIN power diode, and control the injection energy of the ion implanter to inject Al + Ions are implanted into the N-type SiC drift layer to form a G-JTE layer. Although this method can well prepare SiC PIN power diodes with G-JTE layers, it requires constant adjustment of the device's rotation speed and is not suitable for the actual preparation process. Another method is to control the growth rate of the SiC crystal to achieve this, which is mainly to control the Al content of the ion implanter while growing the SiC crystal. +The energy and angle of ion implantation are used to achieve gradual doping of the JTE layer. This method can theoretically produce a longer G-JTE layer, but it greatly increases the difficulty of the process and has poor reliability.

[0007] Therefore, in order to make the SiC PIN power diode have a wider JTE layer doping dosage window, a simpler JTE layer impurity concentration design, a larger breakdown voltage value, a simpler reliability optimization method and a simpler preparation process, the present invention designs a SiC power diode with a three-junction terminal extension structure, and introduces the G-JTE layer technology, which can not only make the device have a larger breakdown voltage within a wider JTE layer doping dosage range, but also make the device have a simpler reliability optimization method. In addition, the SiC power diode of the three-junction JTE structure of the present invention does not need to strictly control the doping dosage ratio between each JTE layer, and can also have a larger breakdown voltage value, which greatly reduces the difficulty of designing impurity concentration in JTE technology. In preparing the G-JTE layer, the present invention proposes a novel preparation process, which mainly utilizes the vertical displacement control of the graphene mask layer with circular through holes to realize the gradual doping of the JTE layer. Compared with the traditional preparation process of the G-JTE layer, the G-JTE layer preparation process of the present invention has higher reliability and lower difficulty. Finally, the present invention uses graphene material as a mask layer for ion implantation. Graphene has a higher melting point of about 3600°C, while SiO 2 The melting point of SiO is about 1723℃, and the melting point of graphene is about 2 The material is twice as thick as SiO 2 The material is more suitable for high temperature environment because in the preparation process, the ion implantation area needs to be activated and annealed at high temperature. 2 There is a risk of decomposition, but graphene materials are not easily decomposed at high temperatures and will not affect the performance of the diode. Summary of the invention

[0008] The purpose of the present invention is to provide a silicon carbide power diode with a triple junction terminal extension structure and a preparation method thereof, so as to solve the difficulties of complex preparation process and low reliability of the traditional G-JTE layer, and ultimately solve the problems of low breakdown voltage and narrow doping dosage window of the JTE layer in the process in the traditional dual-zone JTE structure SiCPIN power diode.

[0009] The technical solution for achieving the purpose of the present invention is:

[0010] A silicon carbide power diode with a triple-junction terminal extension structure, wherein the main structure of the diode is a cylindrical structure, which comprises an N+ type SiC substrate layer, an N- type SiC drift layer, and a P+ type SiC layer from bottom to top;

[0011] At the edge of the P+ type SiC layer, three ring-shaped JTE layer structures are extended from the inside to the outside in a concentric circle shape, which are a uniformly highly doped JTE1 layer, a gradually medium-doped G-JTE2 layer, and a uniformly low-doped JTE3 layer; a Ti / Ni metal top electrode is led out from the top of the P+ type SiC layer; and a Ti / Ni metal bottom electrode is led out from the bottom of the N+ type SiC substrate layer.

[0012] Furthermore, the thickness of the cylindrical N+ type SiC substrate layer is 5 to 10 μm, and the cross-sectional radius is 170 to 300 μm; the thickness of the cylindrical N-type SiC drift layer is 10 to 15 μm, and the cross-sectional radius is 170 to 300 μm; the thickness of the cylindrical P+ type SiC layer is 0.65 to 1 μm, and the cross-sectional radius is 10 to 15 μm; the thickness of the annular JTE1 layer is 1 to 1.5 μm, and the ring width is 20 to 30 μm; the thickness of the annular G-JTE2 layer is 1.25 to 1.5 μm, and the ring width is 30 to 40 μm; the thickness of the annular JTE3 layer is 1.5 to 2 μm, and the ring width is 25 to 35 μm.

[0013] The method for preparing the SiC power diode with a triple-junction terminal extension structure comprises the following steps:

[0014] S1: First, an N-type SiC drift layer is grown on an N+ type SiC substrate layer;

[0015] S2: Covering the surface of the N-type SiC drift layer with graphene to make it a mask layer during ion implantation; graphene has the characteristic of high temperature resistance. Selecting graphene as the mask layer during ion implantation can prevent the mask layer from being decomposed in the high temperature environment during ion implantation;

[0016] S3: Use ion implantation machine to implant Al + Ions are implanted into the N-type SiC drift layer to form a P+ type SiC layer with a cylindrical structure;

[0017] S4: Use ion implantation machine to implant Al + Ions are implanted into the N-type SiC drift layer at the edge of the P+ type SiC layer to form a JTE1 layer with a ring structure;

[0018] S5: Use ion implantation machine to implant Al + Ions are implanted into the N-type SiC drift layer at the edge of the JTE1 layer to form a G-JTE2 layer with a ring structure;

[0019] S6: Use ion implantation machine to implant Al + Ions are implanted into the N-type SiC drift layer at the edge of the G-JTE2 layer to form a JTE3 layer with a ring structure;

[0020] S7: Finally, a top electrode is led out above the P+ type SiC layer, and a bottom electrode is led out below the N+ type SiC substrate layer.

[0021] Furthermore, in S5, an ion implanter is used to implant Al + Ions are implanted into the N-type SiC drift layer at the edge of the JTE1 layer to form a G-JTE2 layer with a ring structure. The specific steps are as follows:

[0022] S51: firstly preparing a graphene mask layer;

[0023] S52: etching a circular through hole on the graphene mask layer;

[0024] S53: placing a graphene mask layer with a circular through hole on top of the SiC PIN power diode on which the P+ layer doping and the JTE1 layer doping have been completed and aligning the layer;

[0025] S54: The vertical displacement control technology of the graphene mask layer is used to realize the gradual doping of the JTE2 layer, which is specifically manifested as: making the Al injected by the ion implanter + The ions penetrate through the circular through hole of the graphene mask layer and enter the N-type SiC drift layer. During the implantation process, the graphene layer with the circular through hole is slowly moved vertically upward, and the implantation energy of the ion implanter is adjusted to ensure that the G-JTE2 layer can be formed.

[0026] Furthermore, the concentration of the P+ type SiC layer is 2.4×10 19 cm -3 The concentration of the JTE1 layer is 7×10 18 cm -3 The initial doping concentration of the G-JTE2 layer is 6×10 18 cm -3 ~8×10 16 cm -3 The final doping concentration is 2×10 16 cm -3 The concentration of the JTE3 layer is 1×10 16 cm -3

[0027] Furthermore, a negative voltage is applied to the top electrode in S6, and a positive voltage is applied to the bottom electrode, so as to provide a reverse bias to the SiC PIN power diode.

[0028] The working principle of the above-mentioned silicon carbide power diode with a triple-junction terminal extension structure is:

[0029] The SiC PIN power diode is based on the PIN junction structure, which is composed of a P+ type SiC layer, an N-type SiC drift layer, and an N+ type SiC substrate layer. When the SiC PIN power diode is in the reverse breakdown state, as the reverse bias voltage at both ends of the diode increases, the space charge region of the diode will gradually expand to the lightly doped N-type SiC drift layer, causing the electric field to be too concentrated at the P+ / N-junction between the N-type SiC drift layer and the P+ type SiC layer, causing the electric field at this location to quickly increase to the critical electric field of the material, causing the device to break down prematurely and fail.

[0030] The reverse breakdown mechanism of SiC PIN power diodes is avalanche breakdown. When the reverse bias applied to both ends of the diode increases, the electric field in the space charge region gradually increases. At this time, the electrons and holes passing through the space charge region will accelerate their drift under the action of the electric field and increase their kinetic energy. The electrons and holes with large kinetic energy will constantly collide with the atoms in the lattice, so that the valence electrons bound in the covalent bonds are excited to form free electron-hole pairs, that is, collision ionization. Under the action of the electric field, the electron-hole pairs ionized by collision continue to collide with other valence electrons in the lattice, and new free electron-hole pairs are generated, causing the number of electrons and holes to rise in an avalanche-like manner. At this time, the current flowing through the PN junction of the diode increases sharply, that is, avalanche breakdown occurs.

[0031] In order to alleviate the electric field edge effect of SiC PIN power diodes, a JTE terminal structure can be introduced into the SiC PIN power diode. Taking the double-junction JTE as an example, the charge distribution in the depletion region of a conventional double-junction JTE SiC PIN power diode during reverse breakdown is as follows: Figure 3 The working principle of the JTE structure is as follows: when a reverse bias is applied to both ends of the diode, the JTE1 layer and the JTE2 layer are in a completely depleted state under the action of the reverse bias. At this time, only the immovable ionized acceptor impurity charges are left in the two JTE layers. The ionized acceptor impurities will generate a Coulomb electric field, and the width of the depletion layer that actually withstands the applied voltage will increase, which can weaken the electric field edge gathering phenomenon at the edge of the device's main junction and increase the device's breakdown voltage value.

[0032] Moreover, when designing a SiC PIN power diode with a JTE layer structure, the concentration of the JTE layer needs to be gradually reduced to ensure that the charge in the JTE layer is completely exhausted when the device breaks down. This can make the electric field distribution as uniform as possible while alleviating the main junction electric field, so that the device obtains the highest breakdown voltage and higher terminal efficiency. The present invention also follows this rule when designing the G-JTE layer. In the present invention, a gradually doped G-JTE layer is introduced into the SiC PIN power diode with a double-junction JTE structure to form a SiC power diode with a triple-junction JTE structure. In this device, the G-JTE layer can be regarded as a plurality of JTE layers with gradually decreasing concentrations connected together. Such a design can reduce the physical variables that need to be considered. When the concentrations of the uniformly doped JTE1 layer and the uniformly doped JTE3 layer have been determined, it is only necessary to ensure that the initial doping concentration of the G-JTE layer is lower than the concentration of the JTE1 layer, and the tail doping concentration of the G-JTE layer is higher than the concentration of the JTE3 layer. In this way, without adding additional physical quantities, the device can have a larger breakdown voltage value within a wider range of doping doses of the JTE layer.

[0033] By adopting the above technical solution, the present invention has the following beneficial effects:

[0034] (1) The present invention introduces the G-JTE technology, which not only enables the device to have a larger breakdown voltage within a wider JTE layer doping dosage range, but also allows the device to have a simpler reliability optimization method.

[0035] (2) The SiC power diode with a triple-junction JTE structure of the present invention does not need to strictly control the ratio of doping doses between the JTE layers and can also have a larger breakdown voltage value, which greatly reduces the difficulty of designing impurity concentration in JTE technology.

[0036] (3) The present invention proposes a novel G-JTE layer preparation process, which mainly utilizes the vertical displacement control of the graphene layer with circular through holes to achieve the gradual doping of the JTE layer. Compared with the traditional G-JTE layer preparation process, the G-JTE layer preparation process of the present invention is novel, less difficult and more reliable.

[0037] (4) The present invention uses graphene materials to replace the traditional SiO 2 As a mask layer during ion implantation, graphene is resistant to high temperatures and is not easily decomposed at high temperatures during ion implantation, which will not affect the performance of the diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of a SiC power diode with a triple-junction JTE structure according to the present invention

[0039] Figure 2 Process flow chart for preparing G-JTE2 layer

[0040] Figure 3 The charge distribution in the depletion region of a traditional double-junction JTE structure SiC PIN power diode during reverse breakdown

[0041] Figure 4 A schematic cross-sectional view of a SiC power diode with a triple-junction JTE structure according to the present invention

[0042] Figure 5 The breakdown voltage curve of the traditional double-junction JTE structure SiC power diode

[0043] Figure 6 The breakdown voltage variation curve of a SiC power diode with a triple-junction JTE structure according to the present invention is shown in FIG.

[0044] The numbers in the figure are: N+ type SiC substrate layer 1, N- type SiC drift layer 2, P+ type SiC layer 3, JTE1 layer 4, G-JTE2 layer 5, JTE3 layer 6, top electrode 31, bottom electrode 11 DETAILED DESCRIPTION

[0045] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments in conjunction with the accompanying drawings.

[0046] See Figure 1 , a SiC power diode with a triple-junction JTE structure in this embodiment, the main structure of the diode is a cylindrical structure, which includes, from bottom to top, an N+ type SiC substrate layer 1, an N- type SiC drift layer 2, and a P+ type SiC layer 3; the three JTE layer structures of the diode extend from the inside to the outside in a concentric circle around the edge of the P+ type SiC layer 1, and include, in turn, a JTE1 layer 4 with a ring structure, a G-JTE2 layer 5 with a ring structure, and a JTE3 layer 6 with a ring structure; a Ti / Ni metal top electrode 31 is led out from the top of the P+ type SiC layer 3; and a Ti / Ni metal bottom electrode 11 is led out from the bottom of the N+ type SiC substrate layer 1.

[0047] The thickness of the cylindrical N+ type SiC substrate layer 1 is 5μm and the cross-sectional radius is 170μm; the thickness of the cylindrical N-type SiC drift layer 2 is 10μm and the cross-sectional radius is 170μm; the thickness of the cylindrical P+ type SiC layer 3 is 0.65μm and the cross-sectional radius is 10μm; the thickness of the annular JTE1 layer 4 is 1μm and the ring width is 20μm; the thickness of the annular G-JTE2 layer 5 is 1.25μm and the ring width is 30μm; the thickness of the annular JTE3 layer 6 is 1.5μm and the ring width is 25μm.

[0048] A SiC power diode with a triple-junction JTE structure in this embodiment includes the following steps:

[0049] S1: First, an N-type SiC drift layer 2 is grown on an N+ type SiC substrate layer 1. The cross-sectional radius of the N+ type SiC substrate layer 1 and the N-type SiC drift layer 2 is 170 μm, and the doping material is N. The doping concentration of the N+ type SiC substrate layer 1 is 1×10 19 cm -3 , with a thickness of 5 μm and a doping concentration of 9×10 15 cm -3 , thickness is 10 μm;

[0050] S2: multi-layer graphene (with a total thickness of about 6 nm) is prepared by mechanical stripping, and is covered on the surface of the N-type SiC drift layer 2; then the graphene layer is dry-etched using a 2 μm photoresist as a mask to form an ion implantation mask;

[0051] S3: Etch a circular window on the graphene with a radius of 10 μm, and use an ion implanter to implant 400°C Al + Ions are implanted into the N-type SiC drift layer 2 through the graphene window, and the total implantation dose is about 6×10 14 cm -2 The injection energy is 160keV and the number of injections is 5. The purpose is to form a concentration of 2.4×10 19 cm -3 , a P+ type SiC layer 3 with a depth of 0.65 μm, after completion, the graphene mask layer is removed;

[0052] S4: Re-cover with a 6nm graphene mask layer, etch a ring window on the graphene at the top edge of the P+ SiC layer 3, the inner diameter of the window opening is 10μm, the ring width is 20μm, and the 350℃ Al + Ions are injected into the N-type SiC drift layer 2 at the edge of the P+ type SiC layer 3 through the graphene window, and the total injection dose is about 1×10 14 cm -2 The injection energy is 350keV and the number of injections is 7. The purpose is to form a concentration of 7×10 18 cm -3 , JTE1 layer 4 with a depth of 1 μm, after completion, the graphene mask layer is removed;

[0053] S5: Re-cover with a 6nm graphene mask layer, and etch a ring window on the top graphene of the edge of JTE1 layer 4. The inner diameter of the window opening is 30μm and the ring width is 30μm. Similarly, use the ion implanter to implant 300℃ Al+ Ions are injected into the N-type SiC drift layer 2 at the edge of the JTE1 layer 4 through the graphene window with an injection energy of 800 keV to form (with a starting concentration of 2×10 17 cm -3 For example, the endpoint concentration is 2×10 16 cm -3 ) G-JTE2 layer 5 with a depth of 1.25 μm; the specific steps are as follows:

[0054] S51: firstly, a graphene mask layer with a thickness of 6 nm is prepared by mechanical stripping;

[0055] S52: etching a circular through hole on the graphene mask layer, wherein the inner diameter of the through hole is 30 μm;

[0056] S53: placing a graphene mask layer with circular through holes on top of the SiC PIN power diode;

[0057] S54: Figure 2 As shown, a continuous ion implantation process is performed on the edge of the JTE1 layer 4. The graphene mask layer with a circular through hole is aligned above the diode. At this time, the ion implanter is turned on. During the implantation process, the total implantation dose is about 1×10 12 cm -2 The implantation energy is 800 keV, and the concentration is about 2×10 16 cm -3 Then, the graphene mask layer with circular through holes is slowly and vertically raised, and within about 5 minutes, the graphene mask layer is raised to a distance of about 25 μm from the SiC PIN power diode. In the process of slowly and vertically raising the graphene mask layer, the ineffective injection area of ​​the ion implanter and the area where the graphene mask layer blocks the SiC PIN power diode will be reduced, that is, the ion implanter injects Al + The effective area of ​​ions will increase with the distance between the graphene mask layer and the SiC PIN power diode. Due to the different ion implantation times in different areas, the actual Al + The dose of ion implantation will also be different, thus forming a G-JTE2 layer 5;

[0058] S55: After completing the above steps, a ring with a width of 30 μm and a starting concentration of 2×10 17 cm -3 The end point concentration is 2×10 16 cm -3 After the G-JTE2 layer 5 is completed, the graphene mask layer is removed;

[0059] S6: Re-cover with a 6nm graphene mask layer, and etch a ring window on the top graphene of the edge of G-JTE2 layer 5. The inner diameter of the window opening is 60μm and the ring width is 25μm. Similarly, use the ion implanter to implant 300℃ Al + Ions are implanted into the N-type SiC drift layer 2 at the edge of the G-JTE2 layer 5 through the graphene layer, and the total implantation dose is about 2×10 12 cm -2 The injection energy is 1000 keV and the number of injections is 7. The purpose is to form a concentration of 1×10 16 cm -3 , a JTE3 layer 6 with a depth of 1.5 μm, after completion, the graphene mask layer is removed;

[0060] S7: After completing the above processes, an activation annealing process is performed on the P+ type SiC layer 3, the JTE1 layer 4, the G-JTE2 layer 5, and the JTE3 layer 6. The activation annealing is mainly performed on the four regions simultaneously in an argon (Ar) environment at 1800-2000°C. No cover layer is added during the process. The duration is about 30 minutes.

[0061] S8: Deposit metal nickel (Ni) and titanium (Ti) on the top of the diode P+ SiC layer 3 and the bottom of the N+ SiC substrate layer 1 to facilitate the formation of ohmic contacts, forming metal top electrodes 31 and bottom metal electrodes 11 respectively; the specific method is to re-cover the 6nm graphene mask layer, etch the graphene layer on the top of the P+ SiC layer 3 to form an opening, deposit the Ni layer by sputtering, and form an electrode pattern by wet etching, and then deposit the Ti layer on the bottom of the N+ substrate layer 1 by the same process. The thickness of the Ti and Ni layers are in the range of 25-35nm and 90-110nm respectively;

[0062] S9: After completing the above process, remove the excess graphene mask layer on the surface of the N-type SiC drift layer 2, and finally cover the N-type SiC drift layer 2 with a layer of 0.5 μm SiO 2 layer.

[0063] Figure 4This is a cross-sectional schematic diagram of a SiC power diode with a triple-junction JTE structure of the present invention. The introduction of G-JTE technology in a power diode device can not only enable the device to have a larger breakdown voltage within a wider JTE layer doping dose range, but also allow the device to have a simpler reliability optimization method. In addition, the SiC power diode with a triple-junction JTE structure of the present invention does not need to strictly control the doping dose ratio between each JTE layer, and can also have a larger breakdown voltage value, which greatly reduces the difficulty of designing impurity concentration in JTE technology. In the process of preparing the G-JTE layer, the present invention mainly utilizes the vertical displacement control of the graphene mask layer with circular through holes to achieve the gradual doping of the JTE layer. This method has higher reliability and lower difficulty. Finally, the present invention utilizes the high temperature resistance of the graphene material, so that it is used as a mask layer during ion implantation, avoiding the decomposition of the mask layer under the high temperature environment during ion implantation.

[0064] Figure 5 This is the breakdown characteristic curve of the traditional double-junction JTE structure SiC power diode. Figure 6 The breakdown characteristic curve of the SiC power diode with triple-junction JTE structure of the present invention is shown in the figure. From the comparison between the two figures, it can be found that when the traditional SiC power diode with double-junction JTE structure maintains 85% of the theoretical breakdown voltage value, the doping dose range of the JTE1 layer is 3.3×10 17 cm -3 ~1.2×10 18 cm -3 (12×10 17 cm -3 ), the window width is about 8.7, and this doping dosage window is relatively narrow. When the SiC power diode of the triple-junction JTE structure of the present invention maintains 85% of the theoretical breakdown voltage value, the starting doping dosage range of the G-JTE2 layer is 2.2×10 17 cm -3 ~5×10 18 cm -3 (50×10 17 cm -3 ), the width of the window is about 47.8, which is nearly 5 times wider than the doping dose window of the traditional double-junction JTE structure SiC power diode, successfully improving the problem of narrow doping dose window of the JTE layer.

[0065] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A silicon carbide power diode with a triple junction terminal extension structure, characterized in that: The main structure of the diode is a cylindrical structure, which comprises, from bottom to top, an N+ type SiC substrate layer (1), an N- type SiC drift layer (2), and a P+ type SiC layer (3); Three JTE layer structures with annular structures are extended from the inside to the outside in a concentric circle shape at the edge of the P+ type SiC layer (3), which are a uniformly highly doped JTE1 layer (4), a gradually medium-doped G-JTE2 layer (5), and a uniformly low-doped JTE3 layer (6) in sequence; a Ti / Ni metal top electrode (31) is led out from the top of the P+ type SiC layer (3); and a Ti / Ni metal bottom electrode (11) is led out from the bottom of the N+ type SiC substrate layer (1); The steps of forming the G-JTE2 layer (5) are: S51: firstly preparing a graphene mask layer; S52: etching a circular through hole on the graphene mask layer; S53: placing a graphene mask layer with a circular through hole on top of the SiC PIN power diode on which the P+ layer doping and the JTE1 layer doping have been completed and aligning the layer; S54: The vertical displacement control technology of the graphene mask layer is used to realize the gradual doping of the JTE2 layer, which is specifically manifested as: making the Al injected by the ion implanter + The ions are transmitted through the circular through holes in the graphene mask layer and enter the N-type SiC drift layer (2). During the implantation process, the graphene layer with the circular through holes is slowly moved vertically upward, and the implantation energy of the ion implanter is adjusted to ensure that the G-JTE2 layer (5) can be formed.

2. The silicon carbide power diode with a triple junction terminal extension structure according to claim 1, characterized in that: The cylindrical N+ type SiC substrate layer (1) has a thickness of 5-10 μm and a cross-sectional radius of 170-300 μm; The cylindrical N-type SiC drift layer (2) has a thickness of 10-15 μm and a cross-sectional radius of 170-300 μm; The cylindrical P+ type SiC layer (3) has a thickness of 0.65-1 μm and a cross-sectional radius of 10-15 μm; The annular JTE1 layer (4) has a thickness of 1-1.5 μm and an annular width of 20-30 μm; The annular G-JTE2 layer (5) has a thickness of 1.25-1.5 μm and an annular width of 30-40 μm; The annular JTE3 layer (6) has a thickness of 1.5-2 μm and an annular width of 25-35 μm.

3. A method for preparing a silicon carbide power diode with a triple junction terminal extension structure as claimed in any one of claims 1 to 2, characterized in that: The following steps are involved: S1: First, an N-type SiC drift layer (2) is grown on an N+ type SiC substrate layer (1); S2: Covering the surface of the N-type SiC drift layer (2) with graphene so that it serves as a mask layer during ion implantation; S3: Use ion implantation machine to implant Al + Injecting into the N-type SiC drift layer (2) to form a P+ type SiC layer (3) with a cylindrical structure; S4: Use ion implantation machine to implant Al + Ions are implanted into the N-type SiC drift layer (2) at the edge of the P+ type SiC layer (3) to form a JTE1 layer (4) of a ring structure; S5: Use ion implantation machine to implant Al + Ions are implanted into the N-type SiC drift layer (2) at the edge of the JTE1 layer (4) to form a G-JTE2 layer (5) of a ring structure; S6: Use ion implantation machine to implant Al + Ions are implanted into the N-type SiC drift layer (2) at the edge of the G-JTE2 layer (5) to form a JTE3 layer (6) of a ring structure; S7: Finally, a top electrode (31) is led out from above the P+ type SiC layer (3), and a bottom electrode (11) is led out from below the N+ type SiC substrate layer (1).

4. A silicon carbide power diode with a triple junction terminal extension structure and a method for preparing the same according to claim 3, characterized in that: In step S1, the doping materials of the N+ type SiC substrate layer and the N- type SiC drift layer are both nitrogen, and the doping concentrations are 1×10 19 cm -3 ,9×10 15 cm -3 .

5. The method for preparing a silicon carbide power diode with a triple-junction terminal extension structure according to claim 3, characterized in that: The concentration of the P+ type SiC layer (3) is 2.4×10 19 cm -3 The concentration of the JTE1 layer (4) is 7×10 18 cm -3 The initial doping concentration of the G-JTE2 layer (5) is 6×10 18 cm -3 ~8×10 16 cm -3 The final doping concentration is 2×10 16 cm -3 The concentration of the JTE3 layer (6) is 1×10 16 cm -3 .

6. The method for preparing a silicon carbide power diode with a triple-junction terminal extension structure according to claim 3, characterized in that: A negative voltage is applied to the top electrode (31) in S6, and a positive voltage is applied to the bottom electrode (11), so as to provide a reverse bias to the SiC PIN power diode.

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