Semiconductor device with an impurity-doped dielectric region

Abstract

A semiconductor device includes a vertical stacked structure on a substrate that includes an interlayer insulating layer and a gate electrode. A barrier dielectric region is provided on sidewalls of an opening in the stacked structure. A lateral impurity region is provided that extends between the barrier dielectric region and the interlayer insulating layer and between the barrier dielectric region and the gate electrode. A lower impurity region is also provided that extends between the barrier dielectric region and the substrate.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2017 - 0155585, filed on November 21, 2017, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The inventive concept relates to semiconductor devices, and more particularly, to semiconductor devices having impurity regions. Background art

[0004] The integration degree of semiconductor devices such as flash memories is an important factor that can determine the price of semiconductor products. Three - dimensional semiconductor devices including three - dimensionally arranged memory cells and large semiconductor wafers have been proposed to increase the integration degree of such semiconductor devices. Since the constituent elements of three - dimensional semiconductor devices have a more compact size to increase the integration degree of three - dimensional semiconductor devices, the defect rate of three - dimensional semiconductor devices increases. Summary of the invention

[0005] One aspect of the inventive concept may provide a semiconductor device that supports an increase in integration density and can improve distribution characteristics.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor device is provided, including a blocking dielectric provided on a lower region and a stacked structure including a gate electrode facing the blocking dielectric and an inter - layer insulating layer. A lateral impurity region is also provided, disposed in a boundary region between the inter - layer insulating layer and the blocking dielectric. A lower impurity region is also provided, disposed in a boundary region between the lower region and the blocking dielectric.

[0007] According to another embodiment of the inventive concept, a semiconductor device is provided, including a memory cell vertical structure on a substrate and a stacked structure provided on the substrate. Each memory cell vertical structure may include a first gate dielectric. The stacked structure includes a gate electrode facing the memory cell vertical structure and an inter - layer insulating layer. A lateral impurity region is provided, disposed in a boundary region between the memory cell vertical structure and the stacked structure.

[0008] According to another embodiment of the inventive concept, a semiconductor device is provided, including a lower region, a blocking dielectric provided on the lower region, and a stacked structure including a gate electrode facing the blocking dielectric and an inter - layer insulating layer. A lower impurity region is also provided, disposed in a boundary region between the lower region and the blocking dielectric.

[0009] According to another embodiment of the inventive concept, an integrated circuit memory device is provided, including a stacked structure on a substrate. The stacked structure includes at least one interlayer insulating layer and at least one gate electrode. A blocking dielectric region is disposed on sidewalls of an opening (e.g., a vertical opening) in the stacked structure. A lateral impurity region is provided and extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided and extends between the blocking dielectric region and the substrate. The lower region may also be disposed on the substrate, and the lower region may be configured as a semiconductor material in contact with the blocking dielectric region.

[0010] According to other aspects of this embodiment of the inventive concept, at least a portion of the lower impurity region extends within the lower region, and the lower region is electrically coupled to the substrate. A data storage layer may be disposed on the blocking dielectric region, and a tunnel dielectric layer may be disposed on the data storage layer. A channel semiconductor layer may be provided and extends on the tunnel dielectric layer and contacts the lower region. The blocking dielectric region, the data storage layer, and the tunnel dielectric layer may extend between the channel semiconductor layer and the gate electrode. In addition, a gate dielectric layer may be provided and extends between the gate electrode and the blocking dielectric region. In some embodiments of these embodiments of the inventive concept, the dielectric constant associated with the gate dielectric layer is greater than the dielectric constant associated with the blocking dielectric region. In addition, the gate dielectric layer may contact the blocking dielectric region, and the lateral impurity region may extend into a boundary region between the gate dielectric layer and the blocking dielectric region. The lateral impurity region may include carbon impurities.

[0011] According to other embodiments of the inventive concept, a non-volatile memory cell is provided, including a semiconductor channel region and a data storage region on the semiconductor channel region. A tunnel dielectric region is provided and extends between the semiconductor channel region and the data storage region. A gate dielectric region is disposed on the data storage region. The gate dielectric region preferably includes a carbon impurity region. A blocking dielectric region is provided and extends between the gate dielectric region and the data storage region. The blocking dielectric region also includes a carbon impurity region. A gate electrode is disposed on the gate dielectric region.

[0012] According to other aspects of the memory cell, the dielectric constant associated with the gate dielectric region may be greater than the dielectric constant associated with the blocking dielectric region. In addition, the gate dielectric region may contact the blocking dielectric region at an interface therebetween. The level of carbon impurities in the gate dielectric region may vary with the distance from the interface, and the level of carbon impurities in the blocking dielectric region may vary with the distance from the interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a schematic block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] Figure 2 is a circuit diagram conceptually showing an example of a memory cell array of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0016] Figure 3 is a plan view of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0017] Figure 4A and Figure 4B is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0018] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B and Figure 8 is a partial enlarged view showing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0019] Figure 7 is a diagram showing the impurity distribution in a part of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0020] Figure 9A is a cross-sectional view of a modified semiconductor device according to an exemplary embodiment of the inventive concept.

[0021] Figure 9B is a cross-sectional view of a modified semiconductor device according to an exemplary embodiment of the inventive concept.

[0022] Figure 10 、 Figure 11 、 Figure 13 、 Figure 14 and Figure 15 is a cross-sectional view showing a method of forming a semiconductor device according to an exemplary embodiment of the inventive concept.

[0023] Figure 12A is a step flowchart showing a method of forming a semiconductor device according to an exemplary embodiment of the inventive concept.

[0024] Figure 12B is a step flowchart showing a method of forming a semiconductor device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] Examples of a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to Figure 1 which is a schematic block diagram of the semiconductor device. Refer to Figure 1 ​Figure 1 , according to an example embodiment, the semiconductor device 10 may include a memory cell array region 20 and a control logic region 30. The memory cell array region 20 may include a plurality of memory blocks, and each memory block may include a plurality of memory cells. The control logic region 30 may include a row decoder 32, a page buffer 34, and a control circuit 36.

[0026] The memory cells of the memory cell array region 20 may be connected to the row decoder 32 via a string selection line SSL, a plurality of word lines WL, and a ground selection line GSL, and may be connected to the page buffer 34 via bit lines BL. In an example embodiment, a plurality of memory cells arranged in the same row may be connected to the same word line WL, and a plurality of memory cells arranged in the same column may be connected to the same bit line BL.

[0027] The row decoder 32 may decode an input address to generate and send a driving signal for the word line WL. In response to the control of the control circuit 36, the row decoder 32 may supply a word line voltage generated by the voltage generation circuit of the control circuit 36 to the selected word line WL and the unselected word line WL in the word line WL.

[0028] The page buffer 34 may be connected to the memory cell array region 20 via the bit line BL to read the information stored in the memory cells. According to the operation mode, the page buffer 34 may temporarily store the data to be stored in the memory cells, or may read out the data stored in the memory cells. The page buffer 34 may include a column decoder and a sense amplifier. The column decoder may selectively activate the bit lines BL of the memory cell array region 20, and the sense amplifier may read the voltage of the bit line BL selected by the column decoder during a read operation to read the data stored in the selected memory cell. The control circuit 36 may control the operations of the row decoder 32 and the page buffer 34. The control circuit 36 may receive an external control signal and an external voltage, and may operate in response to the received control signal. The control circuit 36 may include a voltage generation circuit, which may use the external voltage to generate the voltages required for internal operations, such as a programming voltage, a read voltage, an erase voltage, etc. The control circuit 36 may control a read operation, a write operation, and / or an erase operation in response to a control signal. In addition, the control circuit 36 may include an input / output (I / O) circuit. The I / O circuit may receive data DATA during a programming operation and transfer DATA to the page buffer 34, and may output DATA received from the page buffer 34 externally during a read operation.

[0029] Reference Figure 2 , the above reference will be described Figure 1 described semiconductor device 10 ( Figure 1 ) of the memory cell array region 20 ( Figure 1 ) circuit example.Figure 2 Conceptually shows a circuit diagram of an example of the memory cell array region 20 ( Figure 1 ). Refer to Figure 2 , the memory cell array region 20 ( Figure 1 ) may include: memory cells MC connected in series with each other; and a first selection transistor ST1 and a second selection transistor ST2 respectively connected to opposite ends of the series-connected memory cells MC. The first selection transistor ST1, the second selection transistor ST2, and the memory cells MC between the first selection transistor ST1 and the second selection transistor ST2 may form a corresponding memory string S. The memory cells MC connected in series with each other may be respectively connected to word lines WL for selecting the memory cells MC.

[0030] The gate terminal of the first selection transistor ST1 may be connected to the first selection line SL1, and the source terminal of the first selection transistor ST1 may be connected to the common source line CSL. The gate terminal of the second selection transistor ST2 may be connected to the second selection line SL2, and the source terminal of the second selection transistor ST2 may be connected to the drain terminal of the memory cell MC. In the example, the first selection transistor ST1 may be a ground selection transistor, and the second selection transistor ST2 may be a string selection transistor. In the example, the first selection line SL1 may be a ground selection line, and the second selection line SL2 may be a string selection line.

[0031] Figure 2 Shows a structure in which a single first selection transistor ST1 and a single second selection transistor ST2 can be connected to the memory cells MC connected in series with each other. In different embodiments, there may also be multiple first selection transistors ST1 or multiple second selection transistors ST2 connected to the memory cells MC.

[0032] In the example, a first dummy line DL1 may be provided between the bottommost word line WL in the word lines WL and the first selection line SL1, and a second dummy line DL2 may be provided between the uppermost word line WL in the word lines WL and the second selection line SL2. The first dummy line DL1 may be provided as a single or multiple first dummy lines DL1, and the second dummy line DL2 may be provided as a single or multiple second dummy lines DL2.

[0033] The drain terminal of the second selection transistor ST2 may be connected to the bit line BL. When a signal is applied to the gate terminal of the second selection transistor ST2 through the second selection line SL2, the signal applied through the bit line BL can be sent to the memory cells MC connected in series with each other, whereby a data read operation or a write operation can be performed. In addition, an operation for erasing the data stored in the memory cells MC can be performed by applying a data erase voltage having a certain level to the memory cells MC through the substrate.

[0034] According to an example embodiment, the semiconductor device 10 may include at least one dummy string DS. The at least one dummy string DS may include a string having a dummy channel electrically isolated from the bit line BL.

[0035] Reference will now be made to Figure 3 , Figure 4A and Figure 4B to describe an example of the memory cell array region 20 of the semiconductor device 10 according to an example embodiment (see, for example, Figure 1 ). Figure 3 is a plan view showing an example of the memory cell array region 20 ( Figure 1 ) of the semiconductor device 10 according to an embodiment of the inventive concept; Figure 4A is a cross-sectional view taken along the line I-I' of Figure 3 ; Figure 4B is a cross-sectional view taken along the line II-II' of Figure 3 . Further, Figure 5A is a partial enlarged view of the region "A1" of Figure 4A , Figure 5B is a partial enlarged view of the region "A2" of Figure 4B .

[0036] Referring to Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B , a stacked structure 169 may be disposed on a substrate 103. In some embodiments of the inventive concept, the substrate 103 may be a semiconductor substrate. For example, the substrate 103 may be a semiconductor substrate including a semiconductor region or a silicon region. The stacked structure 169 may include interlayer insulating layers 106 and gate electrodes 166 that are alternately and repeatedly stacked. The gate electrodes 166 may be formed of a conductive material including at least one of doped polysilicon, metal nitride (e.g., TiN), metal silicide (e.g., WSi, TiSi, or TaSi), or metal (e.g., W). The interlayer insulating layers 106 may be formed of silicon oxide. As shown, the gate electrode 166 may include a lower gate electrode 166g, an upper gate electrode 166s disposed on the lower gate electrode 166g, and an intermediate gate electrode disposed between the upper gate electrode 166s and the lower gate electrode 166g. In one example, the lower gate electrode 166g may be the first selection line SL1 described above with reference to Figure 2 . In another example, the upper gate electrode 166s may be the second selection line SL2 described above with reference to Figure 2 . In another example, the intermediate gate electrode may include a first dummy line 166d1, a second dummy line 166d2, and a word line 166w disposed between the first dummy line 166d1 and the second dummy line 166d2. The first dummy line 166d1 may be the one described above with reference to Figure 2The described first dummy line DL1, and the second dummy line 166d2 can be the above reference Figure 2 The described second dummy line DL2, and the word line 166w can be the above reference Figure 2 The described word line WL.

[0037] Regarding the interlayer insulating layer 106, the lowermost interlayer insulating layer 106L can be disposed between the lower gate electrode 166g and the substrate 103, the second lowermost interlayer insulating layer 106a can be disposed between the lower gate electrode 166g and the first dummy line 166d1, and the uppermost interlayer insulating layer 106U can be disposed on the upper gate electrode 166s.

[0038] The first capping insulating layer 151 and the second capping insulating layer 178 can be sequentially disposed on the stacked structure 169. The first capping insulating layer 151 and the second capping insulating layer 178 can be formed of silicon oxide.

[0039] The isolation structure 175 can be disposed on the substrate 103. Each isolation structure 175 can include a conductive pattern 175b and a lateral partition wall 175a disposed on a side surface of the conductive pattern 175b. The conductive pattern 175b can include polysilicon, metal nitride, metal, or metal silicide. The lateral partition wall 175a can be formed of an insulating material such as silicon oxide. The isolation structure 175 can penetrate the stacked structure 169 and the first capping insulating layer 151.

[0040] The source region 172 can be disposed below the isolation structure 175. In an example, the source region 172 can be the above reference Figure 1 or Figure 2 The described common source line CSL. The source region 172 can have n-type conductivity, and a portion of the substrate 103 adjacent to the source region 172 can have p-type conductivity.

[0041] The insulating line pattern 154 can extend along the length direction of the isolation structure 175, can be disposed between the isolation structures 175, and can penetrate the upper gate electrode 166s while traversing the upper gate electrode 166s. The insulating line pattern 154 can be formed of silicon oxide. A vertical structure can be disposed on the substrate 103 to extend in a direction perpendicular to the surface of the substrate 103. The vertical structure can be disposed between the isolation structures 175.

[0042] The vertical structures may include storage cell vertical structures VSc1, VSc2, and VSc3, and dummy vertical structure VSd. Also, the storage cell vertical structures VSc1, VSc2, and VSc3 may include an outer storage cell vertical structure VSc1 relatively close to the isolation structure 175, an inner storage cell vertical structure VSc3 relatively far from the isolation structure 175, and an intermediate storage cell vertical structure VSc2 disposed between the outer storage cell vertical structure VSc1 and the inner storage cell vertical structure VSc3. Thus, the outer storage cell vertical structure VSc1 may be closer to the isolation structure 175 than the inner storage cell vertical structure VSc3.

[0043] The dummy vertical structure VSd may penetrate the stacked structure 169 while penetrating the insulating line pattern 154. The insulating line pattern 154 and the dummy vertical structure VSd may be disposed in the middle between the isolation structures 175. The dummy vertical structure VSd may be farther from the isolation structure 175 than the storage cell vertical structures VSc1, VSc2, and VSc3. Each of the vertical structures VSd, VSc1, VSc2, and VSc3 may include a channel semiconductor layer 142 and a first gate dielectric 133.

[0044] According to one example, each of the vertical structures VSd, VSc1, VSc2, and VSc3 may include an insulating core pattern 145 and a pad layer 144 disposed on the insulating core pattern 145. The channel semiconductor layer 142 may surround the side surface of the insulating core pattern 145 and may cover the bottom surface of the insulating core pattern 145. The first gate dielectric 133 may surround the outer surface of the channel semiconductor layer 142.

[0045] According to another example, each of the vertical structures VSd, VSc1, VSc2, and VSc3 may include a lower region 118 disposed below the channel semiconductor layer 142 and the first gate dielectric 133. The lower region 118 may be connected to the channel semiconductor layer 142. In some embodiments, the lower region 118 may face the lower gate electrode 166g, and the channel semiconductor layer 142 may face the upper gate electrode 166s and the intermediate gate electrodes 166d1, 166w, and 166d2.

[0046] The channel semiconductor layer 142 may be formed of a semiconductor material. For example, the channel semiconductor layer 142 may be formed of a semiconductor material such as polysilicon. The lower region 118 may be formed of epitaxial silicon grown from the substrate 103 by an epitaxial process. The lower region 118 may be used as the channel region of a transistor including the lower gate electrode 166g. Such a transistor may be the first select transistor ST1 described above with reference to Figure 2 described above.

[0047] In an exemplary embodiment, the lower region 118 may also be referred to as a "semiconductor region", a "channel region", or a "silicon region". The pad layer 144 may be formed of doped polysilicon. For example, the pad layer 144 may be formed of polysilicon having n-type conductivity. The insulating core pattern 145 may be formed of an insulating material such as silicon oxide.

[0048] The first gate dielectric 133 may be disposed between the channel semiconductor layer 142 and the stacked structure 169 such that the first gate dielectric 133 faces the stacked structure 169. In addition, the second gate dielectric 163 may be inserted between the interlayer insulating layer 106 and the gate electrode 166 and may extend between the gate electrode 166 and the vertical structures VSd, VSc1, VSc2, and VSc3.

[0049] In some embodiments, the lower gate dielectric 160 may be disposed between the lower region 118 and the lower gate electrode 166g. The lower gate dielectric 160 may be formed as a silicon oxide layer formed by thermal oxidation of the lower region 118. The lower gate dielectric 160 may contact the lower region 118 while contacting the second gate dielectric 163 inserted between the lower gate dielectric 160 and the lower gate electrode 166g.

[0050] The bit line contact plug 181 may penetrate the first capping insulating layer 151 and the second capping insulating layer 178 and may be electrically connected to the pad layer 144 of the memory cell vertical structures VSc1, VSc2, and VSc3. The bit line contact plug 181 may be electrically connected to the bit line BL described above with reference to Figure 1 and Figure 2 description.

[0051] The pad layer 144 of the dummy vertical structure VSd may be spaced apart from the bit line contact plug 181. Thus, the dummy vertical structure VSd may be electrically insulated from the bit line BL described above with reference to Figure 1 or Figure 2 description.

[0052] In the example, the distance between portions of the interlayer insulating layer 106 disposed in a region close to the separation structure 175 may be greater than the distance between the remaining portions of the interlayer insulating layer 106 disposed in a region close to the dummy vertical structure VSd or close to the inner memory cell vertical structure VSc3. In the interlayer insulating layer 106 of the stacked structure 169, the distance between the interlayer insulating layers 106 adjacent to each other in the vertical direction may be greater in a region close to the separation structure 175 than in a region away from the separation structure 175. Since the distance between the interlayer insulating layers 106 may depend on the thickness of the gate electrode 166, the thickness of the portion of the gate electrode 166 disposed in a region close to the separation structure 175 may be greater than the thickness of the remaining portions of the gate electrode 166 disposed in a region close to the dummy vertical structure VSd or close to the inner memory cell vertical structure VSc3.

[0053] At least one of the first gate dielectric 133 and the second gate dielectric 163 may include a layer for storing information. For example, the first gate dielectric 133 may include a layer for storing information. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the second gate dielectric 163 may also include a layer for storing information.

[0054] Hereinafter, reference will be made to Figure 6A and Figure 6B and in conjunction with the above reference to Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B to describe an example of a semiconductor device in which the first gate dielectric 133 included therein has a layer for storing information. Figure 6A is Figure 5A a partial enlarged view of the region “B1” of Figure 5B and Figure 6B is Figure 5A a partial enlarged view of the region “B2” of Figure 5B and

[0055] Referring to Figures 3 to 5B 、 Figure 6A and Figure 6B ,the first gate dielectric 133 may include a blocking dielectric 126, a data storage layer 128, and a tunnel dielectric 130. The data storage layer 128 may be disposed between the tunnel dielectric 130 and the blocking dielectric 126. The tunnel dielectric 130 may contact the channel semiconductor layer 142. The stacked structure 169 may include a gate electrode 166 and an interlayer insulating layer 106 facing the blocking dielectric 126 of the first gate dielectric 133. As described above, the second gate dielectric 163 may include a portion disposed between the blocking dielectric 126 and the gate electrode 166.

[0056] The tunnel dielectric 130 may include silicon oxide and / or silicon oxide doped with impurities. The data storage layer 128 may be inserted between the channel semiconductor layer 142 and the gate electrode 166, and may be a layer for storing information in a non-volatile memory device (e.g., a flash memory device). For example, the data storage layer 128 may be formed of a material such as silicon nitride, which can capture and retain electrons injected from the channel semiconductor layer 142 through the tunnel dielectric 130 according to the operating conditions of the non-volatile memory device (e.g., a flash memory device), or can remove the electrons captured within the data storage layer 128. The second gate dielectric 163 may include a high-k material having a dielectric constant higher than that of the blocking dielectric, such as AlO, etc.

[0057] The data storage layer 128 may store data in a region of the gate electrode 166 facing the portion (e.g., word line 166w) corresponding to the word line WL described above Figure 1 or Figure 2 The region in which information can be stored in the data storage layer 128 of at least one of the vertical structures VSc1, VSc2, and VSc3 of the memory cell vertical structure may be arranged in a direction perpendicular to the surface of the substrate 103, and may form the memory string S described above Figure 2 described.

[0058] The blocking dielectric 126 may be formed of silicon oxide. The blocking dielectric 126 may have a first surface 126a facing a stacked structure 169 including the interlayer insulating layer 106, the second gate dielectric 163, and the gate electrode 166, and a second surface 126b facing the data storage layer 128. The first surface 126a of the blocking dielectric 126 may contact the interlayer insulating layer 106 and the second gate dielectric 163.

[0059] The first surface 126a of the blocking dielectric 126 facing the stacked structure 169 including the interlayer insulating layer 106, the second gate dielectric 163, and the gate electrode 166 may also be referred to as the "boundary 126a" between the blocking dielectric 126 and the stacked structure 169.

[0060] In an exemplary embodiment, a lateral impurity region IR may be provided in a region adjacent to the first surface 126a (e.g., boundary 126a) of the blocking dielectric 126. For example, the lateral impurity region IR may include a first impurity region IR1 ( Figure 6A ) provided in the boundary region between the blocking dielectric 126 and the interlayer insulating layer 106, and a second impurity region IR2 ( Figure 6B)。Therefore, the lateral impurity region IR can be disposed in the boundary region between the barrier dielectric 126 and the interlayer insulating layer 106, and can also extend into the boundary region between the second gate dielectric 163 and the barrier dielectric 126. In some embodiments, the lateral impurity region IR can include carbon as an impurity, and can even include carbon and nitrogen as impurities.

[0061] In an example, a first impurity region IR1 of the lateral impurity region IR ( Figure 6A ) can include a region where impurities can diffuse from the boundary 126a between the barrier dielectric 126 and the interlayer insulating layer 106 into the barrier dielectric 126 and a region where impurities can diffuse from the boundary 126a between the barrier dielectric 126 and the interlayer insulating layer 106 into the interlayer insulating layer 106. When the barrier dielectric 126 and the interlayer insulating layer 106 are formed of silicon oxide, the first impurity region IR1 of the lateral impurity region IR ( Figure 6A ) can be formed of silicon oxide including impurities. The impurities can include carbon, or can include carbon and nitrogen.

[0062] In another example, a second impurity region IR2 of the lateral impurity region IR ( Figure 6B ) can include a region where impurities can diffuse from the boundary 126a between the barrier dielectric 126 and the second gate dielectric 163 into the barrier dielectric 126 and a region where impurities can diffuse from the boundary 126a between the barrier dielectric 126 and the second gate dielectric 163 into the second gate dielectric 163. When the barrier dielectric 126 is silicon oxide and the second gate dielectric 163 is aluminum oxide, the second impurity region IR2 of the lateral impurity region IR ( Figure 6B ) can be formed of silicon oxide containing impurities and aluminum oxide including impurities. The impurities can include carbon, or can include carbon and nitrogen.

[0063] Reference will be made to Figure 7 to describe an example of the concentration distribution of the lateral impurity region IR. Figure 7 is a graph showing an example of the concentration distribution of the lateral impurity region IR disposed in the boundary region between the interlayer insulating layer 106 and the barrier dielectric 126.

[0064] Referring to Figure 7 , the lateral impurity region IR can be formed in the boundary region between the interlayer insulating layer 106 and the barrier dielectric 126. The first impurity region IR1 can have the highest impurity concentration at the boundary 126a between the interlayer insulating layer 106 and the barrier dielectric 126.

[0065] Referring again to Figure 3 , Figure 4A and Figure 4B, the first gate dielectric 133 may extend between the channel semiconductor layer 142 and the stacked structure 169, although other configurations are possible. For example, the channel semiconductor layer 142 may include a bent portion in its lower region.

[0066] Reference will be made to Figure 8 describe an example of a semiconductor device including the channel semiconductor layer 142 modified as described above, Figure 8 is a partial enlarged view showing a modified example of region "D" of Figure 4A . Referring to Figure 8 , the first gate dielectric 133 may include a portion that bends downward facing the stacked structure 169 and faces the lower region 118. As described above, the lower region 118 may be referred to as the "semiconductor region" or "silicon region". The blocking dielectric 126 may contact the lower region 118 while contacting the stacked structure 169, the data storage layer 128 may be disposed between the channel semiconductor layer 142 and the blocking dielectric 126, and may be spaced apart from the lower region 118, and the tunneling dielectric 130 may be disposed between the data storage layer 128 and the channel semiconductor layer 142, and may be spaced apart from the lower region 118.

[0067] The lower impurity region IR' may extend from the lateral impurity region IR formed in the boundary region between the interlayer insulating layer 106 and the blocking dielectric 126 into the boundary region between the blocking dielectric 126 and the lower region 118. The lower impurity region IR' may include the same impurities as the lateral impurity region IR. According to one example, the lateral impurity region IR and the lower impurity region IR' may include carbon as an impurity, or include carbon and / or nitrogen as an impurity.

[0068] In another example, the channel semiconductor layer 142 may extend from the upper surface of the lower region 118 into the lower region 118. The lower portion of the channel semiconductor layer 142 may be disposed at a lower level than the lower level of the first gate dielectric 133. The channel semiconductor layer 142 may also extend from the upper surface of the lower region 118 into the lower region 118 to contact a portion of the lower region 118 that does not include the lower impurity region IR'. In this way, the lower impurity region IR' can suppress an increase in the contact resistance between the channel semiconductor layer 142 and the lower region 118, thereby significantly reducing the resistance level between the channel semiconductor layer 142 and the lower region 118.

[0069] Referring again to Figure 3 , Figure 4A and Figure 4B, each of the vertical structures VSd, VSc1, VSc2, and VSc3 described above may include a channel semiconductor layer 142 that does not face a part of the gate electrode 166 (e.g., the lower gate electrode 166g) of the stacked structure 169 but faces the remaining gate electrodes 166d1, 166w, 166d2, and 166s. However, the exemplary embodiments of the inventive concept are not limited thereto. The vertical structures VSd, VSc1, VSc2, and VSc3 may be modified to include a channel semiconductor layer that faces all the gate electrodes 166 of the stacked structure 169. Reference will be made to Figure 9A to describe examples of the vertical structures VSd, VSc1, VSc2, and VSc3 that can be modified as described above, Figure 9A which is a cross-sectional view conceptually showing a modified example of a semiconductor device according to an exemplary embodiment.

[0070] Reference Figure 9A , the channel semiconductor layer 142 of each of the vertical structures VSd, VSc1, VSc2, and VSc3 may penetrate the stacked structure 169. Accordingly, the channel semiconductor layer 142 may face the upper gate electrode 166s, the middle gate electrodes 166d1, 166w, and 166d2, and the lower gate electrode 166g among the gate electrodes 166. A first gate dielectric 133 may be inserted between the channel semiconductor layer 142 and the gate electrode 166.

[0071] The vertical structures VSd, VSc1, VSc2, and VSc3 may include the same blocking dielectric as described above with reference to Figures 3 to 7 , and a lateral impurity region similar to the lateral impurity region described above with reference to Figures 3 to 7 may be included between the vertical structures VSd, VSc1, VSc2, and VSc3 and the stacked structure 169. In addition, a lower impurity region substantially the same as the lower impurity region described above with reference to Figure 8 may be provided in the boundary region between the blocking dielectric of each of the vertical structures VSd, VSc1, VSc2, and VSc3 and the substrate 103. The lateral impurity region and the lower impurity region as described above have been described with reference to Figures 3 to 8 , and thus will not be described in detail.

[0072] The vertical structures VSd, VSc1, VSc2, and VSc3 may be spaced apart from each other. However, other configurations are also possible. For example, reference will be made to Figure 9B to describe a modified example of the vertical structures VSd, VSc1, VSc2, and VSc3, Figure 9B which is a cross-sectional view conceptually showing another modified example of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0073] Reference Figure 9B, an insulating layer 202 may be disposed on a substrate 201. A first lower region 203a and a second lower region 203b may be sequentially disposed on the insulating layer 202. The first lower region 203a and the second lower region 203b may be formed of a semiconductor material or a doped silicon material and may be referred to as a "semiconductor region" or a "silicon region". The first lower region 203a and the second lower region 203b may be a back gate electrode or a fin gate electrode.

[0074] Stacked structures 208 and 260 may be disposed on the second lower region 203b. The stacked structures 208 and 260 may include interlayer insulating layers 206 and 207 (collectively denoted as interlayer insulating layer 208) and gate electrodes 257s and 257w (collectively denoted as gate electrode 260), and the interlayer insulating layer 208 and the gate electrode 260 may be sequentially stacked. The interlayer insulating layer 208 may include a lower interlayer insulating layer 206 and an upper interlayer insulating layer 207 disposed above the lower interlayer insulating layer 206. The upper interlayer insulating layer 207 may be thicker than each lower interlayer insulating layer 206. The gate electrode 260 may be inserted between the interlayer insulating layers 208. The topmost gate electrode 257s in the gate electrode 260 may be a select gate electrode. The gate electrode 257w in the gate electrode 260 disposed below the topmost gate electrode 257s may be a word line.

[0075] A first capping insulating layer 245 and a second capping insulating layer 281 may be sequentially disposed on the stacked structures 208 and 260. A separation structure 274 may penetrate the first capping insulating layer 245 and the stacked structures 208 and 260. The separation structure 274 may be formed of an insulating material such as silicon oxide.

[0076] A memory cell vertical structure 242 may penetrate the stacked structures 208 and 260. The memory cell vertical structure 242 may include a first vertical structure 242_1 and a second vertical structure 242_2 facing each other with the separation structure 274 therebetween.

[0077] The first vertical structure 242_1 and the second vertical structure 242_2 of the memory cell vertical structure 242 may be connected to each other through a connection portion 243. The connection portion 243 may extend horizontally from the lower portions of the first vertical structure 242_1 and the second vertical structure 242_2. The connection portion 243 may be embedded in the first lower region 203a and the second lower region 203b and may connect the lower portions of the first vertical structure 242_1 and the second vertical structure 242_2.

[0078] Each of the first vertical structure 242_1 and the second vertical structure 242_2 may include an insulating core pattern 237, a channel semiconductor layer 235, a first gate dielectric 233, and a pad layer 239. The insulating core pattern 237, the channel semiconductor layer 235, the first gate dielectric 233, and the pad layer 239 may respectively correspond to the insulating core pattern 145, the channel semiconductor layer 142, the first gate dielectric 133, and the pad layer 144 described above with reference to Figure 3 , Figure 4A and Figure 4B .

[0079] The first gate dielectric 233 may include a blocking dielectric 226, a data storage layer 228, and a tunnel dielectric 230, and the blocking dielectric 226, the data storage layer 228, and the tunnel dielectric 230 may respectively correspond to the blocking dielectric 126, the data storage layer 128, and the tunnel dielectric 130 described above with reference to Figures 3 to 7 .

[0080] In the first vertical structure 242_1, the second vertical structure 242_2, and the connection portion 243, the insulating core pattern 237 portion may penetrate the stacked structures 208 and 260 while being connected to each other below the stacked structures 208 and 260 and the separation structure 274, and the channel semiconductor layer 235 may be inserted between the insulating core pattern 237 and the first gate dielectric 233. The pad layer 239 may be disposed in the upper region of each of the first vertical structure 242_1 and the second vertical structure 242_2 and may be connected to the channel semiconductor layer 235. The pad layer 239 may be formed of polysilicon having n-type conductivity.

[0081] According to some embodiments, the impurity region IR” may be disposed in the boundary region between the blocking dielectric 226 of each of the first vertical structure 242_1 and the second vertical structure 242_2 and the stacked structures 208 and 260, and in the boundary region between the blocking dielectric 226 and the first lower region 203a and the second lower region 203b. The impurity region IR” may include impurities substantially the same as those included in the above-described lateral impurity region IR and lower impurity region IR’. For example, the impurity region IR” may include carbon as an impurity, or may include carbon and / or nitrogen as an impurity.

[0082] The bit line 287 may be disposed on the second capping insulating layer 281. The bit line contact plug 286 may be disposed between the bit line 287 and the first vertical structure 242_1. The source line 278 may be disposed on the first capping insulating layer 245. The source contact plug 277 may be disposed between the source line 278 and the second vertical structure 242_2.

[0083] Reference will be made to Figures 10 to 15An example of a method of forming a semiconductor device according to an exemplary embodiment is described, wherein: (i) Figure 10 , Figure 11 and Figures 13 to 15 are cross-sectional views taken along line I-I' in Figure 3 , (ii) Figure 12A is a flowchart showing an example of a method of forming a semiconductor device, and (iii) Figure 12B is a flowchart showing a modified example of a method of forming a semiconductor device according to an exemplary embodiment.

[0084] Referring to Figure 10 , a substrate 103 such as a semiconductor substrate can be provided, and a molded structure 112 can be formed on the substrate 103. The molded structure 112 can include an interlayer insulating layer 106 and a sacrificial gate layer 109 that are alternately stacked with each other. In the molded structure 112, the uppermost layer and the lowermost layer can be interlayer insulating layers, that is, the uppermost interlayer insulating layer 106U and the lowermost interlayer insulating layer 106L. Among the interlayer insulating layers 106, the second lowermost interlayer insulating layer 106a can be thicker than the lowermost interlayer insulating layer 106L.

[0085] The interlayer insulating layers 106 can be sequentially arranged in a direction perpendicular to the substrate 103 and can be spaced apart from each other. Each sacrificial gate layer 109 can be inserted between the interlayer insulating layers 106. The interlayer insulating layer 106 can be formed of, for example, silicon oxide, and the sacrificial gate layer 109 can be formed of, for example, silicon nitride. Holes 115 can be formed to penetrate the molded structure 112, extend into the substrate 103, and expose the substrate 103. The holes 115 can be formed as a plurality of holes.

[0086] Referring to Figure 11 , a lower region 118 can be formed to fill the lower region of the holes 115. The lower region 118 can be an epitaxial silicon layer formed using a selective epitaxial growth (SEG) process. A conformal first gate dielectric 133 can be formed on the substrate 103 having the lower region 118.

[0087] Reference will be made to Figure 10 , Figure 11 , Figure 12A and Figure 12B to describe an example of a method of forming the first gate dielectric 133.

[0088] Referring to Figure 10 , Figure 11 and Figure 12A , holes 115 penetrating the molded structure 112 can be formed (S10), and the inner walls of the holes 115 can be doped with impurities (S15). The inner walls of the holes 115 can be doped with impurities after the lower region 118 is formed in the lower region of the holes 115. To form the above referenceFigure 9A For the described semiconductor device, the formation of the lower region 118 may also be omitted, and instead, the inner wall of the hole 115 may be doped with an impurity (e.g., carbon). Subsequently, a blocking dielectric (S20) may be formed. The blocking dielectric may be the blocking dielectric 126 described above with reference to Figures 3 to 6B ( Figure 6A or Figure 6B ).

[0089] The formation of the blocking dielectric may include: forming a conformal preliminary layer on the substrate 103 having the hole 115; forming a blocking dielectric of an oxide obtained by oxidizing the preliminary layer, and the preliminary layer may be formed of a material different from that of the interlayer insulating layer 106 or the sacrificial gate layer 109 of the molded structure 112. In some embodiments, the interlayer insulating layer 106 may be formed of silicon oxide, the sacrificial gate layer 109 may be formed of silicon nitride, and the preliminary layer may be formed as a silicon layer. Oxidizing the preliminary layer may include oxidizing the entire preliminary layer while substantially not oxidizing the molded structure 112.

[0090] While oxidizing the preliminary layer, the impurity injected into the inner wall of the hole 115 may diffuse, so that an impurity region may be formed in the boundary region between the molded structure 112 and the blocking dielectric 126 starting from the inner wall of the hole 115( Figure 6A or Figure 6B ). For example, the first impurity region IR1 of the lateral impurity region IR( Figures 3 to 6B ) formed in the boundary region between the interlayer insulating layer 106 and the blocking dielectric 126 described above with reference to Figure 6A ) and the lower impurity region IR’( Figure 8 ) formed in the boundary region between the blocking dielectric 126 and the lower region 118 described above with reference to Figure 8 ) may be formed by the impurity diffused during the oxidation of the preliminary layer. Subsequently, a data storage layer (S25) may be formed. The data storage layer may be the data storage layer 128 described above with reference to Figures 3 to 6B ( Figure 6A or Figure 6B ). Subsequently, a tunnel dielectric (S30) may be formed. The tunnel dielectric may be the tunnel dielectric 130 described above with reference to Figures 3 to 6B ( Figure 6A or Figure 6B ).

[0091] Refer to the modification examples and Figure 10 、 Figure 11 and Figure 12B, a hole 115 of the through-molded structure 112 as described above can be formed (S10). Subsequently, an impurity-containing layer (S115) can be formed. The impurity-containing layer can conformally cover the inner wall of the hole 115. In some embodiments, the impurity-containing layer can be a carbon-containing silicon layer (e.g., a carbon-doped silicon layer). In other embodiments, the impurity-containing layer can be a layer containing carbon, nitrogen, and silicon (e.g., an SiCN or SiOCN layer).

[0092] Subsequently, a blocking dielectric can be formed by an oxidation process (S120). The oxidation process can oxidize the impurity-containing layer to form silicon oxide. At the same time, the impurities contained in the impurity-containing layer can be diffused into the boundary regions between the impurity-containing layer and the molded structure 112 and between the impurity-containing layer and the lower region 118. Therefore, the impurity-containing layer can be formed as a silicon oxide layer, and the impurities contained in the impurity-containing layer can be diffused into the boundary regions between the impurity-containing layer and the molded structure 112 and between the impurity-containing layer and the lower region 118 to form impurity regions. Subsequently, a data storage layer (S25) can be formed, and then a tunnel dielectric (S30) can be formed. Therefore, when the process described above is performed Figure 12A or Figure 12B described, impurities can remain or can be formed on the outer surface of the first gate dielectric 133.

[0093] Subsequently, referring to Figure 13 , a channel semiconductor layer 142 can be conformally formed on a substrate 103 having a first gate dielectric 133. An insulating core pattern 145 can be formed on the channel semiconductor layer 142 to fill a part of the hole 115, and a pad layer 144 can be formed on the insulating core pattern 145 to fill the remaining part of the hole 115. While forming the insulating core pattern 145, the part of the channel semiconductor layer 142 disposed above the insulating core pattern 145 can be removed, and while forming the pad layer 144, the part of the first gate dielectric 133 disposed above the uppermost interlayer insulating layer 106U can be removed. Therefore, a vertical structure can be formed in the hole 115. The vertical structure can include storage unit vertical structures VSc1, VSc2, and VSc3 and dummy vertical structure VSd, as described above with reference to Figures 3 to 6B described.

[0094] Referring to Figure 14 , a trench 157 can be formed to penetrate the first capping insulating layer 151 and the molded structure 112 ( Figure 13 ), and expose the substrate 103. Subsequently, the sacrificial gate layer 109 ( Figure 13 ) exposed through the trench 157 in the molded structure 112 ( Figure 13 ) can be removed to form a void 158.

[0095] In an example, forming the void 158 by removing the sacrificial gate layer 109 ( Figure 13 ) may include: removing a portion of the sacrificial gate layer 109 ( Figure 13 ), etching a portion of the interlayer insulating layer 106 to extend the void 158 near the entrance of the trench 157, and removing the remaining portion of the sacrificial gate layer 109.

[0096] As referred to above Figure 12A and Figure 12B stated, the first gate dielectric 133 may include a blocking dielectric. As described above, the blocking dielectric of the first gate dielectric 133 may include the lateral impurity region IR referred to above Figure 6A or Figure 6B described. As described above, the lateral impurity region IR ( Figure 6A or Figure 6B ) may prevent or significantly reduce etching damage to the blocking dielectric of the first gate dielectric 133 when etching the sacrificial gate layer 109 ( Figure 13 ) to form the void 158. Thus, as described above, the lateral impurity region IR ( Figure 6A or Figure 6B ) may be used to improve the thickness distribution characteristics of the blocking dielectric of the first gate dielectric 133. Thereafter, the lower gate dielectric 160 may be formed on the side surface of the lower region 118 exposed through the void 158. The lower gate dielectric 160 may be formed using a thermal oxidation process.

[0097] Now referring to Figure 15 , the second gate dielectric 163 may be formed to conformally cover the inner wall of the void 158, and the gate electrode 166 may be formed to fill the void 158. As referred to above Figure 12A or Figure 12B stated, a portion of the impurities remaining on the outer surface of the first gate dielectric 133 may diffuse into the second gate dielectric 163 to form a part of the lateral impurity region IR.

[0098] Referring again to Figure 3 , Figure 4A and Figure 4B , a separation structure 175 may be formed to fill the trench 157 ( Figure 15 ). Forming the separation structure 175 may include forming a lateral partition wall 175a on the sidewall of the trench 157, and forming a conductive pattern 175b to fill the trench 157. In an example, before forming the conductive pattern 175b, a source region 172 may be formed in the portion of the substrate 103 exposed through the trench 157. Thus, the source region 172 may be formed below the separation structure 175.

[0099] The second capping insulating layer 178 may be formed to cover the isolation structure 175 and the first capping insulating layer 151. Next, the bit line contact plug 181 may be formed to penetrate the first capping insulating layer 151 and the second capping insulating layer 178, and electrically connected to the pad layer 144 of the memory cell vertical structures VSc1, VSc2, and VSc3.

[0100] According to an exemplary embodiment, a semiconductor device may include: a barrier dielectric 126 disposed on a lower region 118; a stacked structure 169 including a gate electrode 166 and an interlayer insulating layer 106 facing the barrier dielectric 126; a lateral impurity region IR disposed in a boundary region between the interlayer insulating layer 106 and the barrier dielectric 126; and a lower impurity region IR' disposed in a boundary region between the lower region 118 and the barrier dielectric 126.

[0101] According to an exemplary embodiment, a semiconductor device may include: memory cell vertical structures VSc1, VSc2, and VSc3 disposed on a substrate 103; a stacked structure 169 disposed on the substrate 103 and including a gate electrode 166 and an interlayer insulating layer 106 facing the memory cell vertical structures VSc1, VSc2, and VSc3; and a lateral impurity region IR disposed in a boundary region between the memory cell vertical structures VSc1, VSc2, and VSc3 and the stacked structure 169.

[0102] According to an exemplary embodiment, a semiconductor device may include: a lower region 118 ( Figure 4A , Figure 4B or Figure 8 ), or a first lower region 203a and a second lower region 203b ( Figure 9B ); a barrier dielectric 126 ( Figure 4A , Figure 4B or Figure 8 ) disposed on the lower region 118 ( Figure 8 ), or a barrier dielectric 226 ( Figure 9B ) disposed on the first lower region 203a and the second lower region 203b ( Figure 9B ); a stacked structure 169 ( Figure 4A , Figure 4B or Figure 8 ) including a gate electrode 166 ( Figure 4A , Figure 4B or Figure 8 ) and an interlayer insulating layer 106 ( Figure 4A , Figure 4B or Figure 8 ), or a stacked structure 169 ( Figure 4A , Figure 4B or Figure 8 ) including a gate electrode facing the barrier dielectric 226 ( Figure 9B) of the gate electrode 260 ( Figure 9B ) and interlayer insulating layer 208 ( Figure 9B ) including stacked structures 208 and 260 ( Figure 9B ); and disposed in the lower area 118 ( Figure 4A , Figure 4B or Figure 8 ) and the blocking dielectric 126 ( Figure 4A , Figure 4B or Figure 8 ) in the lower impurity region IR'( Figure 8 ), or disposed in the first lower area 203a and the second lower area 203b ( Figure 9B ) and the blocking dielectric 226 ( Figure 9B ) in the lower impurity region IR" ( Figure 9B ).

[0103] According to example embodiments, as described above, the lateral impurity region IR( Figure 6A or Figure 6B ) can be used to improve the thickness distribution characteristics of the blocking dielectric 126 of the first gate dielectric 133. For example, in the lateral impurity region IR formed in the boundary region between the stacked structure 169 and the blocking dielectric 126, the portion of the lateral impurity region IR formed on the outer surface of the blocking dielectric 126 can significantly suppress the thickness distribution characteristics of the first gate dielectric 133. Figure 14 The sacrificial gate layer 109 is removed to form the gate electrode 166 of the stacked structure 169 ( Figure 13 ) in the etching process of the blocking dielectric 126. Therefore, the lateral impurity region 114 can improve the thickness distribution characteristics of the blocking dielectric 126. The improved thickness distribution characteristics of the blocking dielectric 126 can increase the performance of the semiconductor device, or can increase the number of gate electrodes 166 disposed in the stacked structure 169, thereby improving the integration of the semiconductor device.

[0104] As described above, according to an exemplary embodiment of the present invention, a semiconductor device can be provided that can improve the thickness distribution characteristics of a blocking dielectric facing a stacked structure including a gate electrode and an interlayer insulating layer. For example, an impurity region can be formed in a boundary region between the stacked structure and the blocking dielectric, so that the thickness reduction of the blocking dielectric that occurs during the process of forming the gate electrode in the stacked structure can be significantly reduced. Therefore, the thickness distribution characteristics of the blocking dielectric can be improved. The improved thickness distribution characteristics of the blocking dielectric can increase the performance of the semiconductor device, or can increase the number of gate electrodes provided in the stacked structure, thereby improving the integration of the semiconductor device.

[0105] Although the exemplary embodiments have been shown and described above, those skilled in the art should understand that various modifications and changes can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor device, comprising: A blocking dielectric, disposed on the lower region; A stacked structure including a gate electrode facing the blocking dielectric and an interlayer insulating layer; A lateral impurity region is disposed centered on a first boundary between the interlayer insulating layer and the blocking dielectric, adjacent to the first boundary in the interlayer insulating layer and adjacent to the first boundary in the blocking dielectric; And A lower impurity region is disposed centered on a second boundary between the lower region and the blocking dielectric, adjacent to the second boundary in the lower region and adjacent to the second boundary in the blocking dielectric, wherein a region of the interlayer insulating layer in which the lateral impurity region is disposed is a part of the interlayer insulating layer.

2. The semiconductor device according to claim 1, wherein, The lower region includes a semiconductor region, and the blocking dielectric contacts the semiconductor region.

3. The semiconductor device according to claim 1, further comprising: A channel semiconductor layer, contacting the lower region and facing the blocking dielectric; A data storage layer, disposed between the channel semiconductor layer and the blocking dielectric and spaced apart from the lower region; And A tunnel dielectric, disposed between the data storage layer and the channel semiconductor layer and spaced apart from the lower region.

4. The semiconductor device according to claim 3, further comprising: A gate dielectric, disposed between the gate electrode and the interlayer insulating layer and extending between the gate electrode and the blocking dielectric to contact the blocking dielectric, wherein the gate dielectric is formed of a high-k dielectric having a dielectric constant greater than that of the blocking dielectric.

5. The semiconductor device according to claim 4, wherein, The lateral impurity region is further disposed centered on a third boundary between the gate dielectric and the blocking dielectric, adjacent to the third boundary in the gate dielectric and adjacent to the third boundary in the blocking dielectric.

6. The semiconductor device according to claim 1, wherein, The lateral impurity region and the lower impurity region include the same impurity, and the same impurity includes carbon.

7. A semiconductor device, comprising: A storage cell vertical structure, disposed on a substrate, each storage cell vertical structure including a first gate dielectric; A stacked structure, disposed on the substrate and including a gate electrode facing the storage cell vertical structure and an interlayer insulating layer; And A lateral impurity region is disposed centered on a first boundary between the storage cell vertical structure and the stacked structure, adjacent to the first boundary in the storage cell vertical structure and adjacent to the first boundary in the stacked structure, wherein a region of the stacked structure in which the lateral impurity region is disposed is a part of the stacked structure.

8. The semiconductor device according to claim 7, further comprising: A second gate dielectric, disposed between the interlayer insulating layer and the gate electrode and extending between the gate electrode and the first gate dielectric.

9. The semiconductor device according to claim 8, wherein, The first gate dielectric includes a blocking dielectric contacting the interlayer insulating layer and the second gate dielectric, and The lateral impurity region is configured to be centered on a second boundary between the blocking dielectric and the interlayer insulating layer to be adjacent to the second boundary in the blocking dielectric and adjacent to the second boundary in the interlayer insulating layer, and centered on a third boundary between the blocking dielectric and the second gate dielectric to be adjacent to the third boundary in the blocking dielectric and adjacent to the third boundary in the second gate dielectric.

10. The semiconductor device according to claim 9, wherein, The first gate dielectric further includes a data storage layer and a tunnel dielectric. The data storage layer is disposed between the blocking dielectric and the tunnel dielectric. The blocking dielectric has a first surface facing the stack structure and a second surface facing the data storage layer. The lateral impurity region is closer to the first surface of the blocking dielectric than to the second surface of the blocking dielectric.

11. The semiconductor device according to claim 7, wherein, The impurity in the lateral impurity region includes carbon.

12. The semiconductor device according to claim 7, further comprising: A separation structure is disposed on the substrate. The separation structure penetrates the stack structure. The storage cell vertical structure is disposed between the separation structures. The interlayer insulating layer and the gate electrode are respectively configured as a plurality of interlayer insulating layers and a plurality of gate electrodes, and the plurality of interlayer insulating layers and the plurality of gate electrodes are alternately and repeatedly stacked. The stack structure includes the plurality of interlayer insulating layers and the plurality of gate electrodes.

13. The semiconductor device according to claim 12, wherein, The distance between portions of the plurality of interlayer insulating layers of the stack structure that are disposed in a region close to the separation structure and adjacent to each other in the vertical direction is greater than the distance between portions of the plurality of interlayer insulating layers that are disposed in a region far from the separation structure and adjacent to each other in the vertical direction.

14. A semiconductor device, comprising: Lower region; A channel semiconductor layer in contact with the lower region; A blocking dielectric disposed on the lower region; A stack structure including a gate electrode and an interlayer insulating layer facing the blocking dielectric; And A lower impurity region is configured to be centered on a first boundary between the lower region and the blocking dielectric to be adjacent to the first boundary in the lower region and adjacent to the first boundary in the blocking dielectric. The region in the lower region where the lower impurity region is disposed is a part of the lower region.

15. The semiconductor device according to claim 14, wherein, The lower region includes a semiconductor region.

16. The semiconductor device according to claim 14, wherein, The blocking dielectric includes an upper portion in contact with the stack structure and a lower portion in contact with the lower region.

17. The semiconductor device according to claim 16, further comprising: A lateral impurity region is configured to be centered on a second boundary between the stack structure and the blocking dielectric to be adjacent to the second boundary in the stack structure and adjacent to the second boundary in the blocking dielectric.

18. The semiconductor device according to claim 17, wherein, The lateral impurity region and the lower impurity region include carbon as an impurity.

19. The semiconductor device according to claim 14, further comprising: A data storage layer is disposed between the channel semiconductor layer and the blocking dielectric and is spaced apart from the lower region. And A tunnel dielectric is disposed between the data storage layer and the channel semiconductor layer and is spaced apart from the lower region.

20. The semiconductor device according to claim 19, further comprising: A pad layer is disposed on the channel semiconductor layer and is electrically connected to the channel semiconductor layer. A bit line contact plug, electrically connected to the pad layer; and A bit line, electrically connected to the bit line contact plug.

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