Electronic device and manufacturing method thereof, electronic device

Abstract

Embodiments of the present application provide an electronic device, a manufacturing method thereof and an electronic device, and relate to the technical field of semiconductors. The electronic device can be used for growing nanowires in a plane. The electronic device can include a substrate and at least one nanowire. The substrate has at least one groove. The nanowire is embedded in the groove. The groove has at least one groove wall. The nanowire extends along one groove wall of the groove and is in contact with the groove bottom. The groove wall has a guiding effect, so that the nanowire can grow in the plane of the groove bottom along the extension direction of the groove wall, which is conducive to large-scale manufacturing of the electronic device. The plane of the groove bottom can be parallel to the surface of the circuit board for carrying the electronic device. Therefore, when the nanowire grows in the plane of the groove bottom, it is conducive to large-scale integration of the electronic device on the circuit board.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to an electronic device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the rapid development of large-scale integrated circuit technology, the number of transistors integrated on a single chip increases dramatically, and the feature size of the transistors is continuously reduced. However, when the size of a traditional planar metal-oxide-semiconductor (MOS) transistor is reduced to the nanometer scale, the control ability of the MOS transistor on the channel current becomes weak, resulting in serious leakage current. At present, a nanowire field effect transistor can improve the performance of the transistor while improving the chip integration, because it has smaller size, better gate control characteristics, and smaller subthreshold swing. However, the nanowire is grown in a non-planar manner by using the current nanowire growth process, which reduces the large-scale realizability of the chip. SUMMARY

[0003] The present application provides an electronic device, a manufacturing method thereof, and an electronic device, which are used for growing a nanowire in a planar manner.

[0004] To achieve the above object, the present application adopts the following technical solutions:

[0005] In an aspect of the embodiments of the present application, an electronic device is provided. The electronic device can include a substrate and at least one nanowire. The substrate has at least one groove. The nanowire is embedded in the groove. The nanowire extends along one groove wall of the groove and is in contact with the groove bottom. In this way, the groove wall has a guiding effect, so that the nanowire can grow in a planar manner in the plane where the groove bottom is located, which is beneficial to the large-scale manufacturing of the electronic device. In addition, the plane where the groove bottom is located can be parallel to the surface of the circuit board for carrying the electronic device. Therefore, when the nanowire grows in the plane where the groove bottom is located, it is beneficial to the large-scale integration of the electronic device on the circuit board.

[0006] It should be noted that the groove provided on the substrate is not a structure or a film layer independent of the substrate, but a structure feature with an indefinite number in a specific layer of the substrate. The groove is composed of a groove bottom and a groove wall, and the composition and position of the groove bottom and the groove wall depend on the specific position of the groove in the product, for example, depend on the composition and position of the part of the film layer or structure penetrated by the groove in the direction perpendicular to the substrate between the film layers and structures of the substrate.

[0007] Optionally, the nanowire is made of a semiconductor material, and the Raman half-peak width of the nanowire is 1-2 times the Raman half-peak width of a single crystal material having the same material composition as the nanowire. The peak position of the nanowire is within a range of 0 cm -1 -2 cm -1 from the peak position of the single crystal material having the same material composition as the nanowire. In this way, the nanowire has high crystallinity. The Raman half-peak width of the nanowire can be close to the Raman half-peak width of the single crystal material, and thus the nanowire has high crystallinity.

[0008] Optionally, when the nanowire is a silicon nanowire, the Raman half-peak width of the nanowire is 4.5±0.5 cm -1 , and the peak position of the nanowire is 520.7±1 cm -1 . The Raman half-peak width of the single crystal silicon is 3.6 cm -1 , and the peak position of the single crystal silicon is 520.1 cm -1 . Therefore, the Raman half-peak width of the silicon nanowire provided in the embodiments of the present application can be close to the Raman half-peak width of the single crystal silicon.

[0009] Optionally, two nanowires are embedded in each trench. The two nanowires in the same trench extend along two opposite groove walls of the trench, respectively. Each groove wall of the trench can guide the growth of the nanowire.

[0010] Optionally, the substrate includes a substrate body and a first dielectric layer which are stacked, the trench is arranged on the first dielectric layer, and the groove bottom of the trench is the first dielectric layer. The nanowire is in contact with the first dielectric layer on the side close to the substrate body. The first dielectric layer can buffer the heat generated by the laser, so that the heat is not directly transmitted to the substrate body, and the substrate body is not burned under high heat.

[0011] Optionally, the material of the part of the substrate body close to the first dielectric layer includes at least one of polyimide or polydimethylsiloxane. The first dielectric layer includes at least one of a silicon nitride layer, a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide layer. In this way, the substrate composed of the substrate body and the first dielectric layer is a flexible substrate, so that the electronic device prepared can be bent under external force. In addition, the first dielectric layer can buffer the heat of the substrate body made of a flexible material, so as to avoid burning the substrate body due to excessive heat.

[0012] Optionally, the substrate includes a substrate body and a first dielectric layer which are stacked, the trench is arranged on the first dielectric layer, and the trench penetrates the first dielectric layer, that is, the groove bottom of the trench is the substrate body. The nanowire is in contact with the substrate body on the side close to the substrate body. In this case, since the nanowire is in contact with the substrate body, the substrate body can be made of a material with high heat resistance.

[0013] Optionally, the substrate body and the first dielectric layer are made of the same material. In this case, the substrate body and the first dielectric layer can be integrated.

[0014] Optionally, the material of the substrate body comprises at least one of yellow polyimide, silicon nitride or silicon oxide. The substrate body made of the above-mentioned material has a high heat resistance.

[0015] Optionally, the electronic device further comprises a second dielectric layer. The second dielectric layer is located on the side of the nanowire away from the substrate and covers the substrate and the nanowire. The second dielectric layer and the substrate form a containing cavity for containing the nanowire. The material of the second dielectric layer is an insulating and opaque material with optical and electrical isolation properties. The second dielectric layer is used to isolate the nanowire from other conductive components on the upper surface of the second dielectric layer.

[0016] Optionally, in the case where the substrate comprises a substrate body and a first dielectric layer stacked together, the material of the second dielectric layer is the same as that of the first dielectric layer. In this way, the manufacturing process can be simplified.

[0017] Optionally, in the case where the material of the nanowire is a semiconductor material, the Raman half-peak width of the nanowire is 1-2 times the Raman half-peak width of a single crystal material with the same substance composition as the nanowire, and the peak position of the nanowire is within the range of 0 cm -1 ~ 2 cm -1 Optionally, in the case where the material of the nanowire is a semiconductor material, the Raman half-peak width of the nanowire is 1-2 times the Raman half-peak width of a single crystal material with the same substance composition as the nanowire, and the peak position of the nanowire is within the range of 0 cm

[0018] Optionally, two nanowires are embedded in each trench. In the case where the two nanowires in the same trench extend along the two opposite walls of the trench, respectively, the two nanowires in the same trench are a first nanowire and a second nanowire. In addition, the at least one gate electrode comprises a first gate electrode and a second gate electrode arranged at intervals. The vertical projection of the first nanowire on the second dielectric layer is within the range of the vertical projection of the first gate electrode on the second dielectric layer. The vertical projection of the second nanowire on the second dielectric layer is within the range of the vertical projection of the second gate electrode on the second dielectric layer. In this case, the above-mentioned electronic device can comprise two transistors, one of which comprises the above-mentioned first gate electrode and the first nanowire, and the other of which can comprise the second gate electrode and the second nanowire.

[0019] Optionally, the electronic device further comprises an isolation column arranged in the second dielectric layer. The isolation column is located between the first nanowire and the second nanowire, and the dielectric constant of the isolation column is less than the dielectric constant of the second dielectric layer. The parasitic capacitance between the first nanowire and the second nanowire can be reduced by the isolation column.

[0020] Optionally, the gate electrode covers a plurality of nanowires located in different trenches. In this way, the transistor can have multiple channels, which is conducive to increasing the working current of the transistor.

[0021] Optionally, the vertical projection of the groove wall of the trench on the substrate is a curve, and the nanowire extending along the groove wall of the trench is a curve. When the substrate for carrying the nanowire is the flexible substrate described above, in the process of bending deformation of the substrate, the curved nanowire can release stress by deformation when the substrate is bent. Therefore, when the electronic device is prepared by using the curved nanowire described above, the electronic device can obtain better bending characteristics.

[0022] Optionally, the depth d of the trench satisfies 50nm≤d≤1μm. When the depth d of the trench is less than 50nm, the depth d of the trench is too shallow, which is not conducive to embedding the nanowire in the trench. When the depth d of the trench is greater than 1μm, the thickness of the electronic device is too thick due to the large depth of the trench, which is not conducive to the ultra-thin design of the electronic device. In addition, the width w of the trench satisfies 500nm≤w≤100μm. When the width w of the trench is less than 500nm, the precision requirement of the mask exposure process is high, which is not conducive to reducing the production cost. When the width w of the trench is greater than 100μm, the width of the electronic device will be increased, which is not conducive to the miniaturization design of the electronic device.

[0023] Optionally, the material of the nanowire is a metal material. The nanowire composed of the semiconductor material described above can be subjected to a metallization process, so that the material constituting the nanowire is converted into a metal, thereby making the application range of the electronic device wider.

[0024] In another aspect of the embodiments of the present application, an electronic device is provided. The electronic device can include a circuit board and any one of the electronic devices described above. The electronic device is arranged on the circuit board and electrically connected to the circuit board. The electronic device has the same technical effects as the electronic device provided in the foregoing embodiments, and details are not repeated here.

[0025] In another aspect of the embodiments of the present application, a manufacturing method for the electronic device is provided. The manufacturing method comprises the following steps. First, at least one groove is formed on a substrate. Then, a plurality of catalytic metal particles are formed at one end of the groove. An amorphous precursor is formed on the side of the substrate with the groove, and the amorphous precursor is in contact with the catalytic metal particles. Then, the catalytic metal particles are irradiated by a laser, and the catalytic metal particles absorb the material of the amorphous precursor. One of the catalytic metal particles moves along one wall of the groove and grows into a nanowire along the moving direction of the catalytic metal particle. The absorption rate of the catalytic metal particles to the laser is higher than the absorption rate of the substrate to the laser. The manufacturing method for the electronic device has the same technical effects as the electronic device provided by the above embodiments, and thus the details are not described herein.

[0026] Optionally, the step of forming at least one groove on the substrate comprises the following steps. First, a first dielectric layer is formed on the substrate. Then, a plurality of grooves are formed on the first dielectric layer, and the groove bottom is the first dielectric layer. In addition, the step of growing the nanowire comprises the step of growing the nanowire at the groove bottom. The technical effects of the first dielectric layer are the same as described above, and thus the details are not described herein.

[0027] Optionally, the manufacturing method further comprises the step of forming a second dielectric layer on the substrate with the nanowire, the second dielectric layer covers the substrate and the nanowire, and a holding cavity for accommodating the nanowire is formed between the second dielectric layer and the substrate. The technical effects of the second dielectric layer are the same as described above, and thus the details are not described herein.

[0028] Optionally, the step of forming a plurality of catalytic metal particles at one end of the groove comprises the following steps. First, a suspension liquid with metal oxide nanoparticles is coated at one end of the groove. Then, the dispersion medium in the suspension liquid with metal oxide nanoparticles is volatilized to form a plurality of metal oxide nanoparticles dispersed at one end of the groove. Then, the metal oxide nanoparticles are reduced to form a plurality of catalytic metal particles. The catalytic metal particles obtained by using the suspension liquid can increase the dispersion degree of the catalytic metal particles and reduce the number of uncontrollable nanowires compared with the thin film with metal oxide nanoparticles obtained by evaporation. At the same time, the catalytic metal particles are prevented from being too dense and absorbing too much heat in the laser heating process.

[0029] Optionally, the wavelength range of the laser is 700 nm-2000 nm. The absorption rate of the metal material to the laser is high, and the laser with the above wavelength range is used in the process of growing the nanowire, which is beneficial to selectively making the local position of the electronic device to be formed, such as the position of the catalytic metal particles, have a higher temperature to generate a nanowire with higher crystallinity. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0031] Figure 2 A structural schematic diagram of an electronic device provided in an embodiment of the present application; Figure 1 A structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0032] Figure 3A A structural schematic diagram of an electronic device provided in an embodiment of the present application; Figure 1 A structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0033] Figure 3B A sectional view obtained by cutting along the dashed line O-O in the embodiment of the present application; Figure 3A

[0034] Figure 4 A flowchart of a manufacturing method of an electronic device provided in an embodiment of the present application;

[0035] Figure 5A A structural schematic diagram of a structure formed in the process of S101 in the embodiment of the present application; Figure 4

[0036] Figure 5B A structural schematic diagram of a structure formed in the process of S101 in the embodiment of the present application; Figure 4

[0037] Figure 5C A structural schematic diagram of another structure formed in the process of S101 in the embodiment of the present application; Figure 4

[0038] Figure 5D A structural schematic diagram of another structure formed in the process of S101 in the embodiment of the present application; Figure 4

[0039] Figure 6A A structural schematic diagram of a structure formed in the process of S102 in the embodiment of the present application; Figure 4

[0040] Figure 6B A structural schematic diagram of a structure formed in the process of S102 in the embodiment of the present application; Figure 4

[0041] Figure 6C A structural schematic diagram of another structure formed in the process of S102 in the embodiment of the present application; Figure 4

[0042] Figure 7 A structural schematic diagram of another structure formed in the process of S102 in the embodiment of the present application; Figure 4

[0043] Figure 8 A structural schematic diagram of a structure formed in the process of S103 in the embodiment of the present application; Figure 4

[0044] ​​​​​​​​​​Figure 9A To perform Figure 4 A schematic view of one structure formed in S104 in the above embodiment;

[0045] Figure 9B To perform Figure 9A SEM view in top view direction;

[0046] Figure 10 A schematic view of heat transport provided in the above embodiment;

[0047] Figure 11A To perform Figure 4 A schematic view of another structure formed in S104 in the above embodiment;

[0048] Figure 11B To perform Figure 4 A schematic view of another structure formed in S104 in the above embodiment;

[0049] Figure 12 A Raman spectrum view of a nanowire provided in the above embodiment;

[0050] Figure 13 A HRTEM image of a nanowire provided in the above embodiment;

[0051] Figure 14 A TEM electron diffraction image of a nanowire provided in the above embodiment;

[0052] Figure 15 A schematic view of a structure of an electronic device provided in the above embodiment;

[0053] Figure 16 A schematic view of a structure of another electronic device provided in the above embodiment;

[0054] Figure 17 A schematic view of a structure of another electronic device provided in the above embodiment;

[0055] Figure 18 A schematic view of a structure of another electronic device provided in the above embodiment;

[0056] Figure 19A A output characteristic curve view of a nanocrystal transistor provided in the above embodiment;

[0057] Figure 19B A transfer characteristic curve view of a nanocrystal transistor provided in the above embodiment;

[0058] Figure 20 A schematic view of a structure of another electronic device provided in the above embodiment;

[0059] Figure 21Another structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0060] Figure 22 Another structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0061] Figure 23 A schematic diagram of a manufacturing method of another electronic device provided by an embodiment of the present application;

[0062] Figure 24 For Figure 23 SEM image in top view.

[0063] Reference signs:

[0064] 01-electronic device; 10-electronic device; 100-substrate; 20-nanowire; 101-trench; A1-trench wall; A2-trench bottom; 20a-first nanowire; 20b-second nanowire; 120-first dielectric layer; 110-substrate body; 201-mask; 200-photoresist; 30-catalytic metal particles; 301-suspension; 302-metal oxide nanoparticles; 40-amorphous precursor; 50-second dielectric layer; 51-housing cavity; 52-gate; 53-source; 54-drain; 60-isolation column. DETAILED DESCRIPTION

[0065] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0066] Hereinafter, the terms "first", "second", and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more of the features.

[0067] In addition, in the present application, the orientation terms such as "up", "down", and the like can include but are not limited to the orientation defined by the relative position of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the relative position of the components in the drawings.

[0068] In the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood broadly, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate medium. In addition, the term "electrical connection" can be direct electrical connection, or indirect electrical connection through intermediate medium.

[0069] Embodiments of the present application provide an electronic device, which can include a mobile phone, a pad, a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and the like. Embodiments of the present application do not specially limit the specific form of the electronic device.

[0070] The electronic device 01 can include a printed circuit board (PCB) and an electronic device 10 disposed on the PCB, as shown in FIG. 1. Figure 1 In some embodiments of the present application, the electronic device 10 can be a control chip with data processing capability. For example, a system on a chip (SoC), a power management unit (PMU), a graphics processing unit (GPU), or a central processing unit (CPU). Alternatively, the electronic device 10 can be a memory chip. For example, a universal flash storage (UFS) or a double data rate (DDR) memory. Alternatively, in some other embodiments of the present application, the electronic device 10 can be a sensor. For example, an optical sensor, a temperature sensor, a pressure sensor, and the like. Embodiments of the present application do not specially limit the specific form of the electronic device 10.

[0071] The structure and manufacturing method of the electronic device 10 are described below. In some embodiments of the present application, the electronic device 10 can include a substrate 100 and at least one nanowire 20, as shown in FIG. 2. Figure 2 The substrate 100 has at least one groove 101. The groove 101 has at least one groove wall A1. The nanowire 20 can be embedded in the groove 101, and one nanowire 20 can extend along one groove wall A1 of the groove 101. At this time, the nanowire 20 and the groove wall A1 of the groove 101 both extend along the X direction in FIG. 2. In addition, the nanowire 20 is in contact with the groove bottom A2 of the groove 101. Figure 2

[0072] ​It should be noted that one groove wall A1 of the trench 101 is for the growth of one nanowire 20. The parts of one groove wall A1 in the embodiments of the present application are connected together. Thus, one nanowire 20 can grow along the extension direction of one groove wall A1, so as to achieve the purpose of preparing one complete nanowire 20. The above-mentioned one complete nanowire 20 is independent of whether the groove wall A1 guiding it has an angle or a curvature, etc.

[0073] In addition, the at least one groove wall A1 of the trench 101 means that, as shown in Figure 2 One trench 101 has two oppositely arranged groove walls A1, and the different groove walls A1 in the same trench 101 are not connected. Alternatively, in some other embodiments of the present application, when the above-mentioned trench 101 is located at the edge position of the substrate 100, the trench 101 near the outermost part at the edge position can no longer be provided with a groove wall A1. At this time, the shape of the trench 101 is not concave, but is similar to a step, and the trench 101 has one groove wall A1.

[0074] In this case, the groove wall A1 of the trench 101 has a guiding effect, so that the nanowire 20 can grow in the plane of the groove bottom A2 of the trench 101 along the extension direction of the groove wall A1, which is beneficial to the large-scale production of electronic devices. In addition, the plane of the groove bottom A2 of the above-mentioned trench 101 can be parallel to Figure 1 the surface of the PCB for carrying the electronic device 10. Thus, when the nanowire 20 grows in the plane of the groove bottom A2 of the trench 101, it is beneficial to the large-scale integration of the electronic device on the PCB.

[0075] For example, the material of the above-mentioned nanowire 20 can be a semiconductor material, such as a semiconductor material having at least one of silicon (Si) element or germanium (Ge) element. Alternatively, the nanowire 20 composed of the above-mentioned semiconductor material is subjected to a metallization treatment, so that the material of the nanowire 20 is converted into a metal. Hereinafter, for the convenience of description, the material of the nanowire 20 is taken as the above-mentioned semiconductor material for example.

[0076] In addition, Figure 2 The above-mentioned description is taken as an example that one nanowire 20 is arranged in the trench 101. In some other embodiments of the present application, as shown in Figure 3A two nanowires 20 are embedded in each trench 101. In this case, as shown in Figure 3B (see the cross-sectional view obtained by cutting along the dashed line O-O in Figure 3A The two nanowires in the same trench 101, such as the first nanowire 20a and the second nanowire 20b, respectively extend along the two opposite groove walls of the trench 101, such as the groove wall A1a and the groove wall A1b.

[0077] The following describes an example of the method for manufacturing the electronic device 10 by taking an example of embedding two nanowires 20 in each trench 101 as shown in FIG. 1. Figure 3A The method for manufacturing the electronic device 10 can include the steps S101-S104 as shown in FIG. 2 in some embodiments of the present application. Figure 4

[0078] S101, as shown in FIG. 1, at least one trench 101 is formed on the substrate 100. Figure 5A S101, as shown in FIG. 1, at least one trench 101 is formed on the substrate 100.

[0079] For example, as shown in FIG. 1, the substrate 100 can include a substrate body 110 and a first dielectric layer 120 which are stacked. Figure 5B For example, the material of the substrate body 110 close to the first dielectric layer 120 can include at least one of a high polymer such as polyimide (PI), polydimethylsiloxane (PDMS), etc. For example, the substrate body 110 can be composed of a PI layer and a PDMS layer which are stacked. Alternatively, the part of the substrate body 110 close to the first dielectric layer 120 can be composed of at least one of the PI layer and the PDMS layer, and the part of the substrate body 110 away from the first dielectric layer 120 can be composed of a laminated structure of a PI layer, a silicon nitride layer and a PI layer.

[0080] Alternatively, the substrate body 110 can be a hard substrate. For example, the substrate body 110 can be a glass substrate, or a silicon wafer composed of silicon nitride (SiN x ) or silicon oxide (e.g., silicon dioxide).

[0081] For example, the material of the first dielectric layer 120 can include silicon nitride (SiN x ), silicon nitride (SiN x ), silicon oxynitride, silicon oxide (SiO x ), or aluminum oxide (Al2O3). Alternatively, the first dielectric layer 120 can be composed of a multi-layer film layer structure composed of a plurality of different single-layer film layers as described above. For example, the material of the first dielectric layer 120 can be silicon dioxide (SiO2).

[0082] ​Based on this, in the process of performing the above S101, a layer of silicon dioxide (SiO2) film with a thickness of 600nm-500μm can be deposited on the substrate body 110 mainly composed of PI by using a plasma enhanced chemical vapor deposition (PECVD) process, as the first dielectric layer 120 shown in Figure 5B .

[0083] Next, a trench 101 shown in Figure 5A is formed on the first dielectric layer 120, and the bottom A2 of the trench 101 is the first dielectric layer 120. As an example, as shown in Figure 5C , a photoresist 200 shown in Figure 5C can be spin-coated on the side surface of the first dielectric layer 120 away from the substrate body 110 by a spin-coating process, for example, by using a spin coater through a two-step spin-coating method (pre-rotation 500rpm, 9s; post-rotation 4000rpm, 30s).

[0084] As an example, taking the photoresist 200 as a positive photoresist as an example, the places that can be irradiated by light rays (indicated by arrows in Figure 5C ) can be dissolved in the developing solution in the subsequent developing step, while the places that are not irradiated by light rays cannot be dissolved in the developing solution. Conversely, when the photoresist 200 is a negative photoresist, the places that can be irradiated by light rays cannot be dissolved in the developing solution in the subsequent developing step, while the places that are not irradiated by light rays can be dissolved in the developing solution.

[0085] After the developing process is completed, a part of the first dielectric layer 120 at the position not covered by the photoresist 200 can be etched away by using a plasma etching process to form the bottom A2 of the trench 101 shown in Figure 5D , and the part covered by the photoresist 200 forms the sidewall A1 of the trench 101. Next, the remaining photoresist 200 is removed, thereby completing the preparation of the trench 101.

[0086] The depth d of the trench 101 formed by the above process can satisfy 50nm≤d≤1μm, and the width w of the trench 101 can satisfy 500nm≤w≤100μm. The depth d of the trench 101 can be determined by the etching depth when etching the first dielectric layer 120 at the position not covered by the photoresist 200, and the width w of the trench 101 can be determined by the width of the light-transmitting region (or the light-blocking region for a negative photoresist) of the mask 201.

[0087] In this case, when the depth d of the trench 101 is < 50 nm, the depth d of the trench 101 is too shallow to embed the nanowire 20 into the trench 101. When the depth d of the trench 101 is > 1 μm, the depth of the trench 101 is too large to make the electronic device 10 too thick, which is not conducive to the ultra-thin design of the electronic device 10. For example, the depth d of the trench 101 can be 60 nm, 100 nm, 200 nm, 500 nm or 800 nm. In addition, when the width w of the trench 101 is < 500 nm, the precision requirement of the mask exposure process is high, which is not conducive to the reduction of production cost. When the width w of the trench 101 is > 100 μm, the width of the electronic device 10 is increased, which is not conducive to the miniaturization design of the electronic device 10. For example, the width w of the trench 101 can be 600 nm, 800 nm, 1 μm, 50 μm or 80 μm.

[0088] It should be noted that the above is a description of the process of forming the trench 101 on the first dielectric layer 120 by using a photolithography process (including mask, exposure, development and etching processes). In other embodiments of the present application, a deposition process can also be used to form the trench wall A1 and the trench bottom A2 of the trench 101 when the first dielectric layer 120 is made by using a mask to form film layers with different thicknesses at different positions of the substrate body 110. Alternatively, in other embodiments of the present application, a mechanical scribing process can also be used to remove part of the material of the first dielectric layer 120 to form the above-mentioned trench 101 on the first dielectric layer 120. In addition, an inkjet printing process can also be used to form the above-mentioned trench 101.

[0089] S102, at one end of the trench 101, a plurality of catalytic metal particles 30 as shown in Figure 6A are formed.

[0090] In the process of performing S102, first, a suspension 301 as shown in Figure 6B containing metal oxide nanoparticles, such as indium oxide (In2O3) nanoparticles, can be coated at one end of the trench 101. The suspension 301 can be formed by dispersing In2O3 nanoparticles in ethanol as a dispersion medium. Next, the dispersion medium (e.g. ethanol) in the suspension of metal oxide (e.g. In2O3) nanoparticles is volatilized to form a plurality of metal oxide nanoparticles (e.g. In2O3) 302 dispersed at one end of the trench 101 as shown in Figure 6C .

[0091] Then, in a vacuum environment, the Figure 6CThe structure shown is subjected to an annealing process at about 230°C, and the metal oxide nano (for example, In2O3) particles 302 are subjected to a reduction treatment for about 5 minutes using a hydrogen (H) element plasma treatment process, so that the catalytic metal (for example, In) particles 30 shown can be obtained. The diameter of the catalytic metal particles 30 can be about 200 nm, so that in subsequent laser heating, the heated area of the electronic device 10 to be formed that mainly receives laser irradiation can be reduced to a very low level, which is beneficial to reducing the heat received by the substrate 100. Figure 6A The diameter of the catalytic metal particles 30 can be about 200 nm, so that in subsequent laser heating, the heated area of the electronic device 10 to be formed that mainly receives laser irradiation can be reduced to a very low level, which is beneficial to reducing the heat received by the substrate 100.

[0092] It should be noted that the catalytic metal particles 30 described above are described by taking single-component metal indium (In) as an example. In other embodiments of the present application, the catalytic metal particles 30 described above can also be single-component metals such as gallium (Ga), tin (Tin), and bismuth (Bi), or an alloy material composed of two or more of the above-mentioned metals.

[0093] In addition, it should be noted that, as shown in Figure 6B In the process of coating the suspension 301 at one end of the groove 101, the suspension 301 not only coats the groove bottom A2 of the groove 101, but also some of the suspension 301 will be on the upper surface A3 of the groove wall A1. In this way, when the ethanol in the suspension 301 as a dispersion medium volatilizes, and the metal oxide nano (for example, In2O3) particles 302 are reduced to catalytic metal particles 30, as shown in Figure 6A Some of the catalytic metal particles 30 are located on the groove bottom A2 of the groove 101, and some of the catalytic metal particles 30 are located on the upper surface A3 of the groove wall A1. However, of the catalytic metal particles 30 described above, only the two catalytic metal particles 30 located at the groove wall A1 of the groove 101 can generate nanowires with controllable direction in subsequent steps, as shown in Figure 7 The remaining catalytic metal particles 30 generate nanowires with uncontrollable direction and short length, and this part of the uncontrollable nanowires can be removed in subsequent steps using etching process.

[0094] Based on this, the catalytic metal particles 30 obtained by using the suspension 301 described above can increase the dispersion degree of the catalytic metal particles 30 obtained finally, and reduce the number of the above-mentioned uncontrollable nanowires. At the same time, it avoids the catalytic metal particles being too dense, and absorbing heat exceeding the tolerance range of the structure in laser heating. The following is described by taking the catalytic metal particles 30 located at the groove wall A1 of the groove 101 as an example for convenience of description.

[0095] S103, on one side of the substrate 100 having the groove 101, form Figure 8The amorphous precursor 40 shown is in contact with the catalytic metal particles 30.

[0096] This application does not limit the order of S102 and S103 described above. For convenience, the following description uses S103 as an example of S102. In this case, during the execution of S103, for example, an amorphous precursor 40 with a thickness of 10 nm-200 nm can be formed on the side surface of the substrate 100 having the trench 101. This amorphous precursor 40 can cover the catalytic metal particles 30 and the side surface of the first dielectric layer 120 in the substrate 100 away from the substrate body 110.

[0097] When the thickness of the amorphous precursor 40 is less than 10 nm, the nanowires 20 are easily grown due to their thinness. When the thickness of the amorphous precursor 40 is greater than 200 nm, the thickness increases the dissolution of the catalytic metal particles 30 in the amorphous silicon precursor 40, resulting in the nanowires 40 not reaching the required growth length. For example, the thickness of the amorphous precursor 40 can be 15 nm, 20 nm, 50 nm, 100 nm, or 150 nm.

[0098] Furthermore, the material of the amorphous precursor 40 may include at least one of amorphous silicon and amorphous germanium. For example, when the film layer formed by the amorphous precursor 40 is an amorphous silicon film layer, silicon nanowires can be formed under the catalytic action of the catalytic metal particles 30. Similarly, when the film layer formed by the amorphous precursor 40 is an amorphous germanium film layer, germanium nanowires can be formed under the catalytic action of the catalytic metal particles 30.

[0099] S104, using laser ( Figure 9A (As indicated by the arrow in the image) The catalytic metal particles 30 are irradiated, and the catalytic metal particles 30 absorb the material from the amorphous precursor 40. Among the multiple catalytic metal particles 30, one catalytic metal particle 30 moves along one wall A1 of the trench 101 and grows nanowires 20 along the direction of movement of the catalytic metal particle 30.

[0100] For example, the aforementioned laser can be emitted by a laser, and the wavelength range of the laser can be 700nm to 2000nm. For instance, infrared light with a wavelength of 808nm can irradiate the catalytic metal particles 30, causing the temperature of the catalytic metal particles 30 to exceed 400℃, for example, reaching approximately 700℃ and melting. At this time, the catalytic metal particles 30 located at position A1 on the wall of the trench 101 move along the extension direction of the wall A1 under the guidance of the wall A1.

[0101] Meanwhile, the catalytic metal particles 30 that have undergone melting can absorb the material of the amorphous precursor 40, so as to grow the nanowires 20 as shown in the drawing along the groove wall A1 of the groove 101 in the surface where the groove bottom A2 is located. In this way, Figure 9B the nanowires 20 can be grown along the groove wall A1 of the groove 101 in the surface where the groove bottom A2 is located. Figure 9B As shown in the drawing, Figure 9A a scanning electron microscope (SEM) image of the local structure in the top-down direction (the position of the block of the electronic device 10) can be obtained. As shown in the drawing, Figure 9B the shape of the groove 101 can be clearly seen, and it can be seen that the nanowires 20 grow along the extension direction of the groove wall A1 of the groove 101. Figure 9B It should be noted that,

[0102] the line segment marked with “500 nm” in the drawing represents a length scale, and the size represented by the length of the line segment is 500 nm. The meaning of the length scale in the following electron microscope images is the same as described above, and will not be described here. Figure 9B

[0103] As can be seen from the above manufacturing method, in the process of growing the nanowires 20 in the plane where the groove bottom A2 of the groove 101 is located, the solid catalytic metal particles 30 need to be heated to become liquid, and the liquid catalytic metal particles 30 generate solid nanowires 20 after absorbing the material of the amorphous precursor 40. Therefore, the nanowire growth method provided in the embodiments of the present application adopts an in-plane solid-liquid-solid (IPSLS) nanowire growth mode.

[0104] When this growth mode is adopted, the absorption rate of the catalytic metal particles 30 to the laser is higher than the absorption rate of the substrate 100 to the laser. Therefore, in the process of performing S104, when the laser irradiates the catalytic metal particles 30, the heat generated by the catalytic metal particles 30 is high, for example, as shown in the drawing, it can reach more than 400°C, thereby facilitating the formation of nanowires 20 with high crystallinity, and further improving the quality of the electronic device 10. Figure 10

[0105] In addition, the absorption rate of the substrate 100 to the laser is relatively low compared with the catalytic metal particles 30. The above is Figure 11A ​​The groove bottom A2 of the trench 101 is disposed on the first dielectric layer 120, and in this case, the catalytic metal particles 30 are separated from the substrate body 110 by a portion of the first dielectric layer 120, so that the nanowire 20 formed in the trench 101 is in contact with the first dielectric layer 120 on the side close to the substrate body 110. In this way, when the catalytic metal particles 20 are irradiated with laser light in the process of S104, the heat generated by the laser light is partially absorbed by the first dielectric layer 120 before being transmitted to the substrate body 110, so that the first dielectric layer 120 can buffer the heat generated by the laser light, avoiding the heat being directly transmitted to the substrate body 110 and causing the substrate body 110 to be burned under high heat.

[0106] For example, as shown in FIG. 1, the substrate 100 is irradiated with laser light, and the temperature of the first dielectric layer 120 in the substrate 100 is about 350°C, while the highest temperature of the substrate body 110 on the side of the first dielectric layer 120 away from the catalytic metal particles 30 can be about 300°C, and the lowest temperature can be about 50°C. Figure 10

[0107] In summary, in the method for manufacturing the electronic device 10, in the process of growing the nanowire 20 in the plane, the entire substrate 100 does not need to be heated, but only the local position of the electronic device 10 to be formed, such as the position of the catalytic metal particles 20, is selectively heated to a higher temperature to generate a nanowire 20 with higher crystallinity. This is conducive to preparing a transistor with higher gate control characteristics and smaller sub-threshold swing.

[0108] The Raman half-peak width of the nanowire 20 with high crystallinity can be close to the Raman half-peak width of a single crystal material with the same material composition as the nanowire 20, for example, the Raman half-peak width of the nanowire 20 can be 1-2 times the Raman half-peak width of a single crystal material with the same material composition as the nanowire 20. In addition, the peak position of the nanowire 20 with high crystallinity can be close to the peak position of a single crystal material with the same material composition as the nanowire 20, for example, the difference between the peak position of the nanowire 20 and the peak position of a single crystal material with the same material composition as the nanowire 20 is within the range of 0 cm -1 ~ 2 cm -1 .

[0109] It should be noted that the single crystal material with the same material composition as the nanowire 20 refers to, for example, when the nanowire 20 is a silicon nanowire, the single crystal material with the same material composition as the nanowire 20 can be single crystal silicon (c-Si). Alternatively, when the nanowire 20 is a germanium nanowire, the single crystal material with the same material composition as the nanowire 20 can be single crystal germanium. ​

[0110] For example, in the case where the nanowire 20 mentioned above is a silicon nanowire, such as Figure 12 As shown in the Raman spectrum, the full width at half maximum (FW) of the silicon nanowire 20 (SiNW) provided in this embodiment is 4.5 ± 0.5 cm⁻¹. -1 The full width at half maximum (FWHM) of the Raman spectral density for single-crystal silicon is 3.6 cm. -1 The peak position of the silicon nanowire 20 provided in this embodiment is 520.7 ± 1 cm. -1 The peak position of monocrystalline silicon is 520.1 cm⁻¹. -1 .

[0111] In addition, by Figure 13 As shown in the high-resolution transmission electron microscope (HRTEM) image, the highly crystalline nanowires 20 formed in this embodiment have uniformly distributed crystals (particles in the figure), and the spacing S1 between any two adjacent crystal planes is about 3.1 angstroms.

[0112] Based on this, such as Figure 14 As shown in the TEM electron diffraction pattern, each spot (the white dot in the image) represents a crystal plane. It can be seen that the multiple spots exhibit good discreteness (not interconnected to form a ring-like pattern) and are uniformly distributed, indicating that the nanowires 20 formed in this embodiment have highly consistent crystal orientation, a high degree of single-crystal density, and few defects.

[0113] on the other hand, Figure 11A In this process, the substrate 100 used to support the nanowires 20 has a lower laser absorption rate than the catalytic metal particles 30. Therefore, during fabrication, the substrate 100 experiences a lower temperature, preventing it from burning. Furthermore, as described above, the substrate 100 may include a substrate body 110 and a first dielectric layer 120 stacked together. The substrate body 110 can be made of a flexible organic material, such as PI or PDMS. The first dielectric layer 120 is made of an inorganic material, such as SiO2. Under the thermal buffering effect of the first dielectric layer 120, the heat generated by the laser can be absorbed, reducing the temperature of the flexible substrate body 110 to a level that it can withstand (e.g., below 300°C). This avoids direct contact between the temperature-sensitive flexible substrate body 110 and the catalytic metal particles 30 heated to above 400°C, thus protecting the flexible substrate body 110 and achieving the goal of growing nanowires 20 on the flexible substrate. The thickness of the first dielectric layer 120 can be between 600nm and 500μm, thereby providing an effective thermal buffer to the flexible substrate 110 while avoiding the disadvantage of excessive thickness of the electronic device 10 for product miniaturization design.

[0114] In addition, the substrate 100 composed of the flexible substrate body 110 and the first dielectric layer 120 can be a flexible substrate capable of being deformed under the action of an external force, as shown in the figure. Figure 11B In this case, the electronic device 10 shown in the figure can be applied to the field of flexible electronic equipment 01, such as flexible displays, wearable electronic devices, implantable electronic devices, etc. Figure 11B

[0115] The above is an example of a substrate 100 that can include a substrate body 110 and a first dielectric layer 120 arranged in layers, and a groove bottom A2 of the groove 101 is arranged on the first dielectric layer 120. In other embodiments of the present application, as shown in the figure, the groove 101 arranged on the first dielectric layer 120 can penetrate the first dielectric layer 120. In this case, the nanowire 20 made in the groove 101 is in contact with the substrate body 110 on the side close to the substrate 100, and at this time the groove bottom A2 of the groove 101 is the substrate body 110. Figure 15

[0116] At this time, when performing the steps of making nanowires in S101-S104 described above, the catalytic metal particles 30 heated by laser are directly in contact with the substrate body 110, thereby forming nanowires 20 that can be in contact with the substrate body 110. Therefore, the substrate body 110 needs to be made of a high-temperature-resistant material. For example, the material of the substrate body 110 can include at least one of yellow polyimide, silicon nitride or silicon oxide. Alternatively, in other embodiments of the present application, the substrate body 110 and the first dielectric layer 120 are made of the same material, and at this time the substrate body 110 and the first dielectric layer 120 can be an integral structure, and the substrate 100 is a single-layer material layer.

[0117] For convenience of description, the following is an example of a substrate 100 that can include a substrate body 110 and a first dielectric layer 120 arranged in layers, and a groove bottom A2 of the groove 101 is arranged on the first dielectric layer 120. On this basis, the method of making the electronic device 10 described above can further include, as shown in the figure, Figure 16

[0118] ​​​The material constituting the second dielectric layer 50 is an insulating, opaque material possessing optical, electrical, or spatial isolation properties. In some embodiments of this application, the second dielectric layer 50 can be used to isolate the nanowire 20 from other conductive components located on the upper surface of the second dielectric layer 50 (the surface away from the nanowire 20). In some embodiments of this application, the substrate 100 includes, for example... Figure 16 In the case of the first dielectric layer 120 shown, the second dielectric layer 50 may be made of the same material as the first dielectric layer 120.

[0119] Based on this, when the nanowire 20 is a semiconductor material, the electronic device 10 having the nanowire 20 can be a transistor. Accordingly, to fabricate this transistor, the method for fabricating the electronic device 10 may further include, for example... Figure 17 As shown, at least one gate 52 is formed on the surface of the second dielectric layer 50 away from the substrate 100. In this case, the second dielectric layer 50 located between the gate 52 and the nanowire 20 can serve as the gate insulator (GI) of the transistor.

[0120] like Figure 18 As shown, the second dielectric layer 50 can cover a portion of the nanowire 20. In this case, the method for fabricating the transistor can further include fabricating a source (s) 53 and a drain (d) 54 on both sides of the gate (g) 52. Both the source 53 and the drain 54 are in contact with the nanowire 20 in the same trench 101 to be electrically connected to the nanowire 20. In this case, the nanowire 20 can serve as the channel of the transistor, which is a top-gate transistor. For example, the material of the gate 52 of the transistor can be aluminum, and the material of the second dielectric layer 50, which serves as the gate insulating layer, can be silicon oxide after 30 nm. The materials of the source 53 and the drain 54 can be at least one of titanium (Ti) and copper (Au).

[0121] The output characteristic curve of the transistor fabricated using the nanowire 20 provided in the embodiments of this application is as follows: Figure 19A As shown. By Figure 19A It can be seen that different gate-source voltages Vgs (e.g., -4V, -2V, -3V, and 0V) result in different source-drain currents Isd. Therefore, this transistor exhibits good gate control characteristics. Furthermore, due to... Figure 19B The transfer characteristic curves shown indicate that, with a source current voltage Vds of 0.5V, the transistor's on-state current I... on =1E-8A, off-state current I off = 1E-11A. Therefore, the on-state current I of this transistor is... on With off-state current Ioff The ratio (I on / I off ) can be greater than 10 4 .

[0122] It should be noted that Figure 19A and Figure 19B are only test descriptions of an electrical property of the nanowire transistor provided by the embodiments of the present application, and constitute a limitation on the index related to the electrical property of the transistor. When the accuracy of the manufacturing process and the manufacturing method and other factors change, the output characteristic curve and the transfer characteristic curve will also change accordingly.

[0123] In addition, when two nanowires are arranged in the same trench 101, which are the first nanowire 20a and the second nanowire 20b as shown in Figure 20 , in order to reduce the influence of the parasitic capacitance formed between the first nanowire 20a and the second nanowire 20b on the performance of the transistor, the electronic device 10 can also include a spacer 60 as shown in Figure 20 . The spacer 60 is located between the first nanowire 20a and the second nanowire 20b. The dielectric constant of the spacer 60 is less than that of the second dielectric layer 50, so as to reduce the parasitic capacitance formed between the first nanowire 20a and the second nanowire 20b.

[0124] In the manufacturing process, the spacer 60 can be manufactured by a photolithography process or an inkjet printing process, etc. after the first nanowire 20a and the second nanowire 20b are formed and before the second dielectric layer 50 is formed.

[0125] Alternatively, in some other embodiments of the present application, the structure of the electronic device 10 (transistor) can be as shown in Figure 21 . One gate 52 can cover multiple nanowires 21 located in different trenches 101. In this way, the transistor can have multiple channels, which is beneficial to improve the working current of the transistor.

[0126] Alternatively, in some other embodiments of the present application, the structure of the electronic device 10 can be as shown in Figure 22As shown, when a first nanowire 20a and a second nanowire 20b are disposed within each trench 101, the electronic device 10 may include a first gate 52a and a second gate 52b disposed at intervals. The vertical projection of the first nanowire 20a onto the second dielectric layer 50 is located within the range of the vertical projection of the first gate 52a onto the second dielectric layer 50. Similarly, the vertical projection of the second nanowire 20b onto the second dielectric layer 50 is located within the range of the vertical projection of the second gate 52b onto the second dielectric layer 50. In this case, the electronic device 10 may include two transistors, one transistor comprising the first gate 52a and the first nanowire 20a, and the other transistor comprising the second gate 52b and the second nanowire 20b.

[0127] As can be seen from the above, the number of nanowires in a single transistor can be adjusted by controlling the number of nanowires covered by the vertical projection of the gate, as needed.

[0128] The above description uses the nanowire 20 as an example of a straight line. In other embodiments of this application, such as... Figure 23 As shown, the vertical projection of the trench wall A1 of the trench 101 onto the substrate 100 is a curve. In this case, the nanowires 20 extending along the trench wall 100 of the trench 101 are also curved. During the fabrication process, a curved mask can be used in the above S101 to form the curved trench 101 using a photolithography process.

[0129] In this case, during the execution of S104, the catalytic metal particles 30 melted under laser irradiation move along the curved trench wall A1 of the trench 101 and absorb the material of the amorphous precursor 40, thereby enabling the growth of amorphous precursors along the curved trench wall A1 of the trench 101 within the surface where the bottom A2 of the trench 101 is located. Figure 24 The nanowire 20 shown. Among them, Figure 24 for Figure 23 SEM image from a top-down view. (By...) Figure 24 The curved shape of the pre-set groove 101 can be clearly seen, and it can be seen that the nanowire 20 grows along the extension direction of the curved groove wall A1 of the groove 101, thereby growing nanowire 20 with the same morphology as the groove 101.

[0130] Therefore, when the substrate 100 used to support the nanowire 20 is the aforementioned flexible substrate, during the bending deformation of the substrate 100, the bent nanowire 20 can release stress through deformation as it bends with the substrate 100. Thus, when the electronic device 10 is fabricated using the aforementioned bent nanowire 20, the electronic device 10 can obtain superior bending characteristics.

[0131] It should be noted that the curved nanowire 20 grown by using the trench 101 with the above-mentioned curved morphology has a twin structure inside, instead of a complete single crystal. However, compared with the polycrystal structure nanowire, the curved nanowire 20 provided by the embodiment of the present application has a more ordered arrangement and a higher working current.

[0132] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An electronic device, characterized by comprising: The electronic device comprises: a substrate; at least one trench on the substrate; at least one nanowire; the nanowire is embedded in the trench; the trench has at least one wall, and the nanowire extends along one wall of the trench and contacts the bottom of the trench; two nanowires are embedded in each trench, and the two nanowires in the same trench extend along the opposite walls of the trench, respectively; the second dielectric layer is located on the side of the nanowire away from the substrate and covers the substrate and the nanowire; the second dielectric layer and the substrate form a containing cavity for containing the nanowire; the electronic device further comprises an isolation column arranged in the second dielectric layer; the isolation column is located between the first nanowire and the second nanowire, and the dielectric constant of the isolation column is less than that of the second dielectric layer.

2. Electronic device according to claim 1, characterized in that The material of the nanowire is a semiconductor material, the Raman half-width of the nanowire is 1-2 times the Raman half-width of a single crystal material with the same material composition as the nanowire; The peak position of the nanowire is within a range of 0 cm -1 from the peak position of a single crystal material having the same material composition as the nanowire -1 .

3. Electronic device according to claim 2, characterized in that The Raman half-peak width of the nanowire is 4.5±0.5 cm -1 -1, and the peak position of the nanowire is 520.7±1 cm -1 -1.

4. The electronic device of claim 1, wherein the substrate comprises a substrate body and a first dielectric layer arranged in layers, the trench is arranged on the first dielectric layer, and the bottom of the trench is the first dielectric layer; the nanowire contacts the first dielectric layer on the side close to the substrate body.

5. The electronic device of claim 4, wherein the material of the substrate body close to the first dielectric layer comprises at least one of polyimide or polydimethylsiloxane; the first dielectric layer comprises at least one of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer.

6. The electronic device of claim 1, wherein the substrate comprises a substrate body and a first dielectric layer arranged in layers, the trench is arranged on the first dielectric layer, and the trench penetrates the first dielectric layer; the nanowire contacts the substrate body on the side close to the substrate body.

7. Electronic device according to claim 6, characterized in that the materials of the substrate body and the first dielectric layer are the same.

8. Electronic device according to claim 7, characterized in that the material of the substrate body comprises at least one of yellow polyimide, silicon nitride, or silicon oxide.

9. Electronic device according to any of claims 4-8, characterized in that, the material of the second dielectric layer is the same as that of the first dielectric layer.

10. Electronic device according to any of claims 1-8, characterized in that The material of the nanowire is a semiconductor material, a Raman half-peak width of the nanowire is 1-2 times of a Raman half-peak width of a single crystal material with the same substance component as the nanowire; a peak position of the nanowire is within a range of 0 cm -1 -2 cm -1 from a peak position of the single crystal material with the same substance component as the nanowire; and the electronic device further comprises: at least one gate electrode is arranged on the surface of the second dielectric layer away from the substrate; a source electrode and a drain electrode are respectively arranged on the two sides of the gate electrode and contact a part of the nanowire.

11. Electronic device according to claim 10, characterized in that the at least one gate electrode comprises a first gate electrode and a second gate electrode arranged at intervals; the vertical projection of the first nanowire on the second dielectric layer is located within the vertical projection of the first gate electrode on the second dielectric layer; the vertical projection of the second nanowire on the second dielectric layer is located within the vertical projection of the second gate electrode on the second dielectric layer.

12. Electronic device according to claim 11, characterized in that the gate electrode covers multiple nanowires located in different trenches.

13. Electronic device according to any of claims 1-8, characterized in that A vertical projection of a groove wall of the trench on the substrate is a curve; the nanowire extending along the groove wall of the trench is a curve.

14. The electronic device of claim 1, wherein, A depth d of the trench satisfies: 50nm≤d≤1μm; a width w of the trench satisfies: 500nm≤w≤100μm.

15. The electronic device of claim 1, wherein, The nanowire is made of a metal material.

16. An electronic device, comprising: The electronic device is arranged on the circuit board and electrically connected with the circuit board.

17. A method of manufacturing an electronic device as claimed in any one of the claims 1-15, characterized in that The manufacturing method comprises: forming at least one trench on the substrate; forming a plurality of catalytic metal particles at one end of a groove bottom of the trench; forming an amorphous precursor on a side of the substrate with the trench, the amorphous precursor being in contact with the catalytic metal particles; irradiating the catalytic metal particles with a laser, the catalytic metal particles absorbing materials of the amorphous precursor; one of the catalytic metal particles moves along one groove wall of the trench and grows the nanowire along a moving direction of the catalytic metal particle; two nanowires in the same trench extend along two opposite groove walls of the trench, respectively; wherein an absorption rate of the catalytic metal particles to the laser is higher than an absorption rate of the substrate to the laser; manufacturing an isolation column between the two nanowires in the same trench; forming a second dielectric layer on the substrate with the nanowire, the second dielectric layer covering the substrate and the nanowire, and a containing cavity for containing the nanowire being formed between the second dielectric layer and the substrate; a dielectric constant of the isolation column is less than a dielectric constant of the second dielectric layer.

18. The manufacturing method of claim 17, wherein the forming a plurality of trenches on the substrate comprises: forming a first dielectric layer on a substrate body; forming at least one trench on the first dielectric layer, a groove bottom of the trench being the first dielectric layer; the growing the nanowire comprises: generating the nanowire at the groove bottom of the trench.

19. The method of manufacturing of claim 17, wherein, the forming a plurality of catalytic metal particles at one end of the trench comprises: applying a suspension liquid with metal oxide nanoparticles at one end of the trench; volatilizing a dispersion medium in the suspension liquid of the metal oxide nanoparticles to form a plurality of the metal oxide nanoparticles dispersed at the one end of the trench; reducing the metal oxide nanoparticles to form a plurality of the catalytic metal particles.

20. The method of manufacturing of claim 17, wherein, The wavelength of the laser ranges from 700nm to 2000nm.

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