A lateral hetero-insulating layer organic field effect transistor and a preparation method and application thereof

Abstract

The application discloses a lateral hetero-insulating layer organic field effect transistor (OFET) and a preparation method and application thereof. The preparation method of the lateral hetero-insulating layer OFET comprises the following steps: sequentially preparing an inorganic insulating layer and an organic insulating layer on a gate electrode; transferring a gold film to the organic insulating layer, and then etching by using oxygen plasma; after etching off the organic insulating layer not covered by the gold film, transferring the gold film to obtain a hetero-insulating layer of the organic insulating layer / inorganic insulating layer; preparing an organic semiconductor layer on the hetero-insulating layer, and the organic semiconductor layer continuously covers the interface of the hetero-insulating layer; and preparing source-drain electrodes on the inorganic insulating layer and the organic semiconductor layer on the organic insulating layer, so that the lateral hetero-insulating layer OFET is obtained. Compared with a conventional rectifier, the rectifier disclosed by the application has the advantages of less raw materials, good universality, no need to select a corresponding opposite type semiconductor like a PN junction rectifier, and no need to select a suitable metal material like a Schottky rectifier.

Description

TECHNICAL FIELD

[0001] The present application relates to a lateral hetero-insulating layer organic field effect transistor and its preparation method and application, and belongs to the technical field of organic field effect transistor devices. BACKGROUND

[0002] An organic field effect transistor (OFET) is composed of a gate, an insulating layer, an organic semiconductor layer and a source and drain electrode. Most of the research on organic field effect transistors focuses on the development of semiconductor materials, but as the research on organic field effect transistors continues and the understanding deepens, it is found that the insulating layer material also has a very important influence on the performance of the device. Therefore, it is very necessary to study the influence of the insulating layer on the charge transport. It is found that the charge transport of OFET mainly occurs in the first few molecular layers closest to the insulating layer, so the type of insulating layer and the properties of the insulating layer surface will have a great influence on the electrical properties of OFETs. However, in most studies of field effect devices, the insulating layer is homogeneous in the direction parallel to the semiconductor, i.e. laterally. This is because in the process of preparing a laterally hetero-insulating layer, a step with a certain height difference will inevitably be generated at the junction of the insulating layer, which makes it extremely difficult to build a semiconductor on the hetero-insulating layer and to maintain certain electrical properties of OFETs after building. In 2019, M. Iqbal Bakti Utama et al. prepared the first lateral hetero-insulating layer field effect transistor by physically transferring a monolayer of boron nitride. However, since the step at the junction of different insulating layers is only one monolayer thick, it is relatively easy to build a semiconductor material at the junction of the insulating layer. However, not all insulating layers can be transferred to a thin thickness or even a monolayer thickness by physical transfer. Based on this, we invented a method for lateral hetero-insulating layer OFETs that can be applied to different types of insulating layers and different step thicknesses, which not only maintains certain electrical properties, but also achieves certain rectification effect through this method.

[0003] Organic semiconductor rectifier (AC to DC) has important applications in filtering and signal energy conversion. There are two main methods for preparing traditional rectifier: one is to make PN junction, and to use the built-in electric field formed by the junction area of P-type semiconductor and N-type semiconductor to realize unidirectional conduction of current. The other method is to use metal electrodes with different work functions, and to use the difference in Schottky barrier height between the two electrodes and the semiconductor to realize rectification. However, the first method requires at least two kinds of semiconductor materials, and most of the organic N-type materials are not stable in air, so the service life of the rectifier built by this method is relatively short. In addition to the need for two metal materials with different work functions, the second method also requires finding suitable metal materials according to the energy level structure of different semiconductors, such as the highest occupied molecular orbital (HOMO) of P-type semiconductor and the lowest unoccupied molecular orbital (LUMO) of N-type semiconductor. Therefore, it is very meaningful to design a device that consumes fewer types of raw materials, is suitable for different semiconductor materials, and has certain rectification effect. SUMMARY

[0004] The purpose of the present application is to provide a kind of lateral hetero-insulating layer organic field effect transistor (OFETs) to realize rectification effect;Wherein one of the insulating layers in the lateral hetero-insulating layer is an inorganic insulating layer resistant to oxygen plasma etching, and the other insulating layer is an organic insulating layer that can be etched by oxygen plasma. By the method of the present application, the construction of a lateral double-interface device can be realized at a position with a step of 2nm to 500nm, and the optical microscope picture, atomic force microscope picture and output transfer curve of the prepared OFET device show that the semiconductor is not damaged, and the semiconductor itself can maintain certain electrical properties and rectification characteristics.

[0005] The present application provides a universal method for preparing different lateral double-insulating layer devices, thereby providing a device basis for the influence of insulating layer on charge transport;It also provides a new method for preparing hetero-insulating layer rectifier devices;It provides a good platform for studying the influence of insulating layer on charge transport, which has the advantages of good universality, simple operation and low cost.

[0006] The "lateral hetero-insulating layer" in the present application refers to the insulating layer in direct contact with the semiconductor layer participating in conduction in the OFETs.

[0007] The OFET described in the present application has a bottom gate top contact structure, the conductive gate is placed on the substrate or the substrate itself is the gate, and then the insulating layer, the semiconductor layer and the source-drain electrode are sequentially built.

[0008] The preparation method of the lateral hetero-insulating layer OFET provided by the present application comprises the following steps:

[0009] 1) Inorganic insulating layer and organic insulating layer are prepared on the gate in sequence;

[0010] 2) transferring the gold film onto the organic insulating layer, and then etching by oxygen plasma; after etching off the organic insulating layer not covered by the gold film, transferring the gold film to obtain a hetero-insulating layer of organic insulating layer / inorganic insulating layer;

[0011] 3) preparing an organic semiconductor layer on the hetero-insulating layer, which continuously covers the interface of the hetero-insulating layer; that is, there is an organic semiconductor on each insulating layer (organic insulating layer and inorganic insulating layer);

[0012] 4) preparing a source-drain electrode on the inorganic insulating layer and the organic semiconductor layer on the organic insulating layer to obtain a lateral hetero-insulating layer OFET.

[0013] In the preparation method, in step 1), a metal layer is prepared on the substrate as the gate electrode, or a metal with conductive ability is selected as the gate electrode and the substrate;

[0014] The substrate is a non-flexible substrate or a flexible substrate;

[0015] The non-flexible substrate is quartz, glass, doped silicon or metal aluminum, etc.

[0016] The flexible substrate is polydimethylsiloxane (PDMS), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), etc.

[0017] In the preparation method, in step 1), the material of the inorganic insulating layer can be silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5) and all materials not etched by oxygen; the thickness and surface properties of the prepared insulating layer are basically not affected by oxygen etching.

[0018] In the preparation method, in step 1), the material of the organic insulating layer is polymethyl methacrylate (PMMA), fluorine-containing polymer (CYTOP), polystyrene (PS), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyimide (PI), organosiloxane (BCB), polyvinylidene fluoride and trifluoroethylene copolymer (P(VDF-TrFE), poly-alpha-methylstyrene (PαMS), polyisobutylene (PIB), polypropylene (PP), polyvinyl chloride (PVC) or polyethylene terephthalate (PET) and other organic insulating layers that can be etched by oxygen plasma; since almost all organic insulating layers can be etched by oxygen plasma, the method is basically suitable for all organic insulating layers;

[0019] The organic insulating layer can be prepared by spin coating.

[0020] In the preparation method, in step 2), the micro-operation technique is used to transfer the gold film to the organic insulating layer;

[0021] The gold film is transferred by the physical transfer method.

[0022] In the preparation method, in step 2), the oxygen plasma etching method is used to etch the whole sample. Since the oxygen plasma can oxidize and etch the organic insulating layer, but cannot etch the metal, after etching for a certain time, the organic insulating layer under the gold film will not be etched under the protection of the gold film, and the organic insulating layer without the gold film will be etched completely. The inorganic insulating layer material will not be etched. The etching time can be adjusted to achieve the effect of etching the organic insulating layer completely.

[0023] In the preparation method, in step 3), the material of the organic semiconductor layer is an alkyl-substituted benzothiophene compound (such as 2,7-dioctyl[1]benzothiophene[3,2-b][1]benzothiophene (C8-BTBT)), an alkyl-substituted bithiophene compound (such as α,ω-dihexylbithiophene (DH6T), α,ω-difluorohexylbithiophene (DFH4T), 2,2'-3,7-di-3-hexylundecyl-2,6-dicyanomethylene-naphthacene (CMUT)), an alkyl-substituted pentathiophene compound (such as 2,7-dihexylthiophene[2',3':4,5]thiophene[3,2-b]thiophene[2',3':4,5]thiophene[2,3-d]thiophene (C6-PTA)), an alkyl-substituted pentacene compound (such as dihexyl-substituted dibenzo[d,d]thieno[3,2-b;4,5-b]thiophene (C6-DBTDT)), a perylene imide compound (such as N,N'-1H,1H-perfluorobutyldicyanoperylene imide (PDIF-CN2)), a phenyl-substituted anthracene compound (such as 2,6-diphenylanthracene (DPA), dihexyl-substituted 2,6-diphenylanthracene (C6-DPA)), and other various conjugated organic semiconductor compounds with planar structure and good solubility (such as perylene, 2-phenylanthracene, or 1,4-di-5'-hexyl-2,2'-bithiophene-5-ethynylbenzene (HTEB)).

[0024] In the preparation method, in step 3), the organic semiconductor layer is prepared by any one of the following methods:

[0025] 1) The organic semiconductor layer is built on the hetero-insulating layer by using the evaporation, spin coating or printing method;

[0026] 2) The organic semiconductor crystal perpendicular to the surface of the substrate is prepared on the substrate by using the physical vapor transport method, and then the organic semiconductor crystal is physically transferred to the hetero-insulating layer by the physical transfer method.

[0027] In the preparation method, the thickness of the organic insulating layer can be adjusted by controlling the acceleration and speed of the spin coating and the concentration of the organic insulating layer material in the solvent; the thickness of the organic insulating layer is the thickness of the finally prepared step, and the OFET device with good electrical properties can be prepared on a step of 2 nm to 500 nm (such as 50 nm to 500 nm).

[0028] In the spin coating step of the preparation method, the organic insulating layer material solution all adopts an organic solvent, most of which is toxic, so the preparation method needs to be carried out in a ventilated environment.

[0029] The lateral hetero-insulating layer OFET device prepared by the method also belongs to the protection scope of the present application, has good electrical performance, has certain rectification effect, provides a good platform for studying the effect of the insulating layer on charge transport, and lays a certain foundation for the design of future rectifier devices and complex insulating layer devices.

[0030] The present application has the following beneficial effects:

[0031] 1) The method is simple and easy to operate, does not require complex and expensive equipment, has good repeatability, and has very good universality;

[0032] 2) The required organic semiconductor material has less raw material, and saves raw materials;

[0033] 3) The experiment can control the thickness of the insulating layer by controlling the concentration of the insulating layer material in the solvent, and can select any organic insulating layer to make a device, and when studying the influence of the insulating layer on the transport mechanism, multiple insulating layers and multiple step thicknesses can be studied;

[0034] 4) Based on the flexibility of the organic single crystal, a hetero-insulating layer OFET device with a very high step thickness (500 nm) can be obtained, and the step height is much higher than the thickness of the crystal itself;

[0035] 5) The rectifier device designed by the method has the advantages of less raw materials and good universality compared with conventional rectifier devices; it does not need to select the corresponding opposite type semiconductor like a PN junction rectifier, and does not need to select a suitable metal material like a Schottky rectifier. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 The figure is a schematic diagram of the method for preparing a lateral hetero-insulating layer OFET device according to Example 1 of the present application.

[0037] Figure 2 The figure is a schematic diagram of the OFET device structure prepared in Example 1 of the present application.

[0038] Figure 3 a is an optical picture of a lateral hetero-insulating layer OFET device prepared in Example 1 of the present application, Figure 3 b is an optical picture of a lateral hetero-insulating layer OFET device prepared in Example 2 of the present application.

[0039] Figure 4 a and Figure 4 b are atomic force microscope pictures of lateral hetero-insulating layer OFET devices prepared in Examples 1 and 2 of the present application, respectively.

[0040] Figure 5 a and Figure 5 b are transfer characteristic curves of a lateral hetero-insulating layer OFET device prepared in Example 1 of the present application in different current directions, respectively, Figure 5 c and 5d are output characteristic curves in different current directions, respectively. DETAILED DESCRIPTION

[0041] The experimental methods used in the following examples are conventional methods unless otherwise specified.

[0042] The materials, reagents, etc. used in the following examples can be obtained from commercial sources unless otherwise specified.

[0043] Preparation and characterization of a 50 nm step thickness PMMA / SiO2 lateral hetero-insulating layer OFET device

[0044] A clean 300 nm SiO2silicon wafer was selected, the lower surface of which was P-type doped silicon and could conduct electricity, and the upper surface of which was 300 nm SiO2.

[0045] According to the schematic diagram shown in Figure 1 A 10 mg / mL PMMA chlorobenzene solution was spin-coated onto the silicon wafer, and annealed on a 100°C hot stage for 20 min to obtain a 50 nm thick PMMA inorganic insulating layer. A gold film was attached, and then etched using an oxygen plasma etching machine at a power of 200 W for 5 min. The gold film was then removed, and DPA crystals were transferred to the interface of the insulating layer, and a gold film was attached to the DPA on each insulating layer to prepare a hetero-insulating layer OFET device. The DPA crystals in the step were prepared on a substrate by PVT.

[0046] Figure 2 The OFET device structure prepared in this example is shown in the schematic diagram, in which the P-type doped silicon is the gate electrode, the obtained hetero-insulating layers are PMMA and SiO2, respectively, the DPA is continuously attached to the two insulating layers, and the gold film is the source electrode and the drain electrode of the OFET device.

[0047] Figure 3a is an optical microscope image of the OFET device prepared in Example 1. As can be seen from the image, the DPA crystal is covered on two different insulating layers: the green part (right side) is covered on SiO2, and the orange part (left side) is covered on PMMA.

[0048] Figure 4 a is an atomic force microscope image of the OFET device fabricated in Example 1. As can be seen from the image, the step thickness is 50 nm, and the crystal is not damaged.

[0049] Figure 5 a and b represent the output curves and transfer curves of the device prepared in different current directions in Example 1, respectively. It can be seen that DPA can maintain certain electrical performance under this device structure, and the device structure has a certain rectification effect, with a larger current in the PMMA to SiO2 current direction.

[0050] Example 2: Fabrication of a 500nm CYTOP / SiO2 lateral heterostable layer OFET device.

[0051] according to Figure 1 The steps illustrated in the diagram are as follows: a 3:1 CYTOP solution is spin-coated onto the silicon wafer in Example 1, and annealed on a hot plate at 90°C for 20 min to obtain a 500 nm thick CYTOP organic insulating layer. A gold film is then attached, followed by etching using an oxygen plasma etching machine at 200 W for 10 min, and then etching again for 10 min. The gold film is transferred out, and the DPA crystal prepared by the method in Example 1 is transferred to the interface of the insulating layer. A gold film is then attached to the DPA on each of the insulating layers to fabricate a heterogeneous insulating layer OFET device.

[0052] Figure 3 b is an optical photograph of the OFET device prepared in this embodiment. As can be seen from the figure, the DPA crystal is covered on two different insulating layers. The yellow part (right side) is covered on SiO2, and the dark yellow part (left side) is covered on CYTOP.

[0053] Figure 4 b is an atomic force microscope image of the OFET device prepared in this embodiment. As can be seen from the image, the step thickness is 500 nm and the crystal is not damaged.

[0054] The fabricated heterojunction OFET device was tested, and the direction of the test affected the magnitude of the current, thereby achieving the rectification effect of the device.

Claims

1. A method for fabricating a lateral heteroinsulating layer OFET, comprising the following steps: 1) An inorganic insulating layer and an organic insulating layer are sequentially prepared on the gate; 2) Transfer the gold film onto the organic insulating layer, and then etch it using oxygen plasma; after etching away all the organic insulating layer not covered by the gold film, transfer the gold film to obtain a heterogeneous insulating layer of organic / inorganic insulating layer; 3) An organic semiconductor layer is fabricated on the heterogeneous insulating layer, wherein the organic semiconductor layer continuously covers the junction of the heterogeneous insulating layer; 4) Source and drain electrodes are fabricated on the organic semiconductor layer on the inorganic insulating layer and the organic insulating layer to obtain a lateral heterostable layer OFET.

2. The preparation method according to claim 1, characterized in that: In step 1), a metal layer is prepared on the substrate as the gate, or a metal that is conductive is selected as the gate and the substrate; The substrate can be a non-flexible substrate or a flexible substrate; The non-flexible substrate is quartz, glass, doped silicon, or metallic aluminum; The flexible substrate is polydimethylsiloxane, polyethylene naphthalate, or polyethylene terephthalate.

3. The preparation method according to claim 1 or 2, characterized in that: In step 1), the inorganic insulating layer is made of silicon dioxide, aluminum oxide, hafnium oxide, titanium dioxide, or tantalum pentoxide.

4. The preparation method according to claim 1 or 2, characterized in that: In step 1), the organic insulating layer is made of polymethyl methacrylate, fluoropolymer, polystyrene, polyvinyl alcohol, polyvinylphenol, polyimide, organosiloxanes, vinylidene fluoride and trifluoroethylene copolymer, polyα-methylstyrene, polyisobutylene, polypropylene, polyvinyl chloride or polyethylene terephthalate. The organic insulating layer was prepared by spin coating.

5. The preparation method according to claim 1 or 2, characterized in that: In step 2), the gold film is transferred onto the organic insulating layer using micromanipulation techniques; The gold film is transferred using a physical transfer method.

6. The preparation method according to claim 1 or 2, characterized in that: In step 3), the organic semiconductor layer is made of alkyl-substituted benzothiophene compounds, alkyl-substituted bithiophene compounds, α,ω-diperfluorohexyltetrathiophene, 2,2'-3,7-di-3-hexylundecyl-2,6-dicyanomethylene-tetrathiophene, alkyl-substituted pentathiophene compounds, alkyl-substituted pentabenzene fused ring compounds, perylene imide compounds, phenyl-substituted anthracene compounds, dihexyl-substituted 2,6-diphenylbianthracene, or other conjugated organic semiconductor compounds with good planar structure and solubility.

7. The preparation method according to claim 1 or 2, characterized in that: In step 3), the organic semiconductor layer is prepared using any of the following methods: 1) The organic semiconductor layer is deposited on the heterogeneous insulating layer by means of vapor deposition, spin coating or printing; 2) An organic semiconductor crystal perpendicular to the substrate surface is prepared on the substrate using a physical vapor transport method, and then the organic semiconductor crystal is physically transferred to the heterogeneous insulating layer by a physical transfer method.

8. The preparation method according to claim 1 or 2, characterized in that: The thickness of the organic insulating layer is 2 nm to 500 nm.

9. A heterogeneous insulating layer OFET device prepared by the preparation method according to any one of claims 1-8.

10. The application of the heterogeneous insulating layer OFET device of claim 9 in rectifier devices, inverters, memory devices with specific functions, and in the study of the mechanism of the influence of the insulating layer on electrical properties.

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