A method, system, device, and storage medium for rapid debugging of FPGA prototype verification

Abstract

The present invention provides a method, system, device, and storage medium for rapid debugging of FPGA prototype verification. The method includes: adding debugging function codes that can be turned on or off through macro definitions during module design; developing general debugging modules for FPGA design software including breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enabling control, and monitoring IP; transplanting the debugging function codes to the FPGA prototype verification platform, integrating the general debugging modules into the debugging function codes, and modifying the macro definitions to implement monitoring of the AXI4 bus or the AHB bus; and using the FPGA design software to synthesize the transplanted debugging function codes to generate verification files, and downloading the verification files to the FPGA prototype verification platform for verification. The present invention improves the debugging efficiency and reduces the time cost of re-synthesizing for the signals to be captured.

Description

Technical Field

[0001] The present invention relates to the field of application specific integrated circuit (ASIC) design, and more particularly, to a method, system, device and storage medium for rapid debugging of FPGA prototype verification. Background Art

[0002] In the process of ASIC (Application Specific Integrated Circuit) design, FPGA (Field Programmable Gate Array) prototype verification is an essential link. It can not only synchronously and quickly verify the accuracy of the ASIC chip function design, but also externally connect to actual physical devices to achieve proportional performance evaluation. Moreover, it can provide a development platform for the design of the ASIC chip firmware and driver solutions earlier, shift the design node of the software solution to the left, shorten the ASIC design cycle, and accelerate the ASIC chip market time.

[0003] In the process of FPGA prototype verification, the current debugging means mainly rely on the debug tools of the FPGA itself, such as SignalTap, Chipscope or ILA (Integrated Logic Analyzer), etc. After synthesis is completed, the signals to be monitored are added to the project, and then the placement and routing are completed to generate a download file. There are also some commercial FPGA prototype verification platforms that use DTD (Deep Trace Debug) technology for debugging, but they need to rely on devices outside the FPGA for auxiliary debugging.

[0004] As the functions of ASIC design become more and more numerous and complex, and the logic scale becomes larger and larger. In the prototype verification platform using the debug tools of the FPGA itself for debugging, the time for single synthesis and implementation of ASIC design becomes longer and longer, even in days. If there is a requirement to temporarily monitor certain signals during the debugging process, it is necessary to re-synthesize and implement to add monitoring of relevant signals, and the waiting time for debugging is relatively long, and the debugging efficiency is low. Moreover, during the synthesis process of the design code in the FPGA design tool, some code is usually optimized or equivalently replaced according to the synthesis strategy. Therefore, it is often difficult to find the signals to be captured during the screening process of adding monitoring signals, which affects the integrity of the debugging information, and even makes it impossible to debug due to the lack of key signals.

[0005] Secondly, during the actual debugging process, abnormal ASIC design work is often caused by abnormal connections of hardware boards, incorrect clock configurations of prototype verification platforms, reset failures, and failed downloads of FPGA Bitstream files. These low-level problems affect the debugging and verification progress and distract the designers' debugging efforts during the functional verification process.

[0006] Finally, in ASIC design, the interconnection between modules is often implemented based on the AXI4 (Advanced eXtensible Interface) bus and the AHB (Advanced High Performance Bus). During the debugging process of FPGA prototype verification, when a problem is found in a module, it mainly relies on firmware or drivers to initiate access to the problem module through the AXI4 bus or the AHB bus, and then analyze and solve the problem. This debugging process has a high dependence on the software layer, integrates software and hardware factors, and cannot quickly locate the cause of the problem; nor can it implement fault injection testing. Summary of the Invention

[0007] In view of this, the purpose of the embodiments of the present invention is to provide a method, system, computer device, and computer-readable storage medium for rapid debugging of FPGA prototypes. The present invention can simply, conveniently, and intuitively understand whether the hardware connection, clock reset, file download, etc. are normal, reduce the coupling test requirements for the software layer, simplify the interface analysis for fault location, improve the debugging efficiency, and reduce the time cost of re-synthesizing and implementing the signals to be captured.

[0008] Based on the above purpose, on the one hand, an embodiment of the present invention provides a method for rapid debugging of FPGA prototypes, including the following steps: adding debug function codes that can be turned on or off through macro definitions during the module design process; developing a general debug module for FPGA design software including breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, enabling control of AXI4 bus and AHB bus control channels and monitoring channels, and monitoring IP; transplanting the debug function codes to the FPGA prototype verification platform, integrating the general debug module into the debug function codes, and modifying the macro definitions to implement monitoring of the AXI4 bus or the AHB bus; and using the FPGA design software to synthesize the transplanted debug function codes to generate verification files, and downloading the verification files to the FPGA prototype verification platform for verification.

[0009] In some embodiments, adding debug function code that can be turned on or off through macro definition during module design includes: adding debug bus definition code in port definition and adding debug bus assignment code at the end of the module.

[0010] In some embodiments, modifying the macro definition to implement monitoring of the AXI4 bus or the AHB bus includes: integrating a general monitoring module in the debug function code and turning on the debug module of the debug function code through macro definition; and instantiating the general monitoring module in the design top layer or internal module according to actual requirements and connecting the debug bus at the same level to the general monitoring module.

[0011] In some embodiments, the method further includes: in response to a requirement for capturing waveforms of unmonitored signals, using FPGA design software to open the routed netlist file, replacing the netlist file with probes of the signals to be monitored, re-routing, generating a second verification file, and performing verification according to the second verification file.

[0012] On the other hand, an embodiment of the present invention provides a system for rapid debugging of FPGA prototype verification, including: an adding module configured to add debug function code that can be turned on or off through macro definition during module design; a development module configured to develop a general debug module including breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enabling control, and monitoring IP based on FPGA design software; an integration module configured to transplant the debug function code to the FPGA prototype verification platform, integrate the general debug module into the debug function code, and modify the macro definition to implement monitoring of the AXI4 bus or the AHB bus; and a verification module configured to synthesize the debug function code after transplantation processing using FPGA design software to generate a verification file and download the verification file to the FPGA prototype verification platform for verification.

[0013] In some embodiments, the adding module is configured to: add debug bus definition code in port definition and add debug bus assignment code at the end of the module.

[0014] In some embodiments, the integration module is configured to: integrate a general monitoring module in the debug function code and turn on the debug module of the debug function code through macro definition; and instantiate the general monitoring module in the design top layer or internal module according to actual requirements and connect the debug bus at the same level to the general monitoring module.

[0015] In some embodiments, the system further includes a wave capture module configured to: in response to a requirement for capturing waves of unmonitored signals, open the routed netlist file using FPGA design software, replace the netlist file with probes of the signals to be monitored, re-route the signals, generate a second verification file, and perform verification based on the second verification file.

[0016] In another aspect of the embodiments of the present invention, there is also provided a computer device including: at least one processor; and a memory storing computer instructions executable on the processor, and when the instructions are executed by the processor, the steps of the above method are implemented.

[0017] In yet another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above method.

[0018] The present invention has the following beneficial technical effects: By adding debugging code to the design code and enabling it, it can be ensured that during the later debugging process, if there is a need to temporarily capture certain key signals, these signals can be quickly found, and there is no problem of being optimized out or not found, which accelerates the debugging efficiency and reduces the time cost of re-synthesizing and implementing the signals to be captured; By integrating a general monitoring module into the design code, it is possible to simply, conveniently, and intuitively understand whether the hardware connection, clock reset, file download, etc. are normal, and reduce the coupling test requirements at the software level, simplify the interface analysis for fault location, and improve the debugging and verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other embodiments based on these drawings without creative efforts.

[0020] Figure 1 It is a schematic diagram of an embodiment of the method for rapid debugging of FPGA prototype verification provided by the present invention;

[0021] Figure 2 It is a schematic diagram of the AXI4 bus master VIO interface provided by the present invention;

[0022] Figure 3 It is a schematic diagram of the AHB bus master VIO interface provided by the present invention;

[0023] Figure 4 It is a schematic diagram of an embodiment of the system for rapid debugging of FPGA prototype verification provided by the present invention;

[0024] Figure 5 Schematic diagram of the hardware structure of an embodiment of a computer device for rapid debugging of FPGA prototype verification provided by the present invention;

[0025] Figure 6 Schematic diagram of an embodiment of a computer storage medium for rapid debugging of FPGA prototype verification provided by the present invention. Detailed implementation manners

[0026] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further describes the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0027] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0028] In the first aspect of the embodiments of the present invention, an embodiment of a method for rapid debugging of FPGA prototype verification is proposed. Figure 1 Shown is a schematic diagram of an embodiment of a method for rapid debugging of FPGA prototype verification provided by the present invention. As Figure 1 shown, the embodiments of the present invention include the following steps:

[0029] S1. Add debugging function codes that can be turned on or off through macro definitions during the module design process;

[0030] S2. Develop a general debugging module for the FPGA design software, including breathing light control, AXI4 bus master (main) behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enabling control, and monitoring IP;

[0031] S3. Transplant the debugging function codes to the FPGA prototype verification platform, integrate the general debugging module into the debugging function codes, and modify the macro definitions to implement monitoring of the AXI4 bus or the AHB bus; and

[0032] S4. Use the FPGA design software to synthesize the transplanted debugging function codes to generate verification files, and download the verification files to the FPGA prototype verification platform for verification.

[0033] Add debugging function codes that can be turned on or off through macro definitions during the module design process.

[0034] In some embodiments, adding debug function code that can be turned on or off through macro definition during module design includes: adding debug bus definition code in port definition and adding debug bus assignment code at the end of the module.

[0035] After the designer designs and completes according to the module spec requirements, two parts of code need to be added to the module. One is to add debug bus definition code in port definition, and the other is to add debug bus assignment code at the end of the module. Both are controlled by `ifdef and `endif macro definitions. The macro definition names used by different modules can be the same or different. The above two parts of code are also added to the wrapper layer of this module, and both are controlled by `ifdef and `endif macro definitions.

[0036] FPGA-based software development includes a breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enable control, and a general debug module for monitoring IP.

[0037] The interface of the general debug module includes the clock, reset, and control output of the breathing light; includes the clock, reset, and main part signals of the AXI4 bus control channel, as well as the main part signals of the AXI4 bus monitoring channel; includes the clock, reset, and main part signals of the AHB bus control channel, as well as the main part signals of the AHB bus monitoring channel. Among them, the dotted-line modules of the AXI4 master model control module, AXI4 monitoring module, AHB master model control module, and AHB monitoring module are modules that can be enabled or disabled through configuration; the breathing light control module is a module that always works.

[0038] The breathing light control module mainly functions to define the breathing cycle according to the selected input clock frequency. This cycle can facilitate the visual observation of the hardware breathing light and the simulated refresh display on the monitoring software interface, and then use this breathing cycle to control the lighting and extinguishing of the breathing light. The input clock and reset need to be selected through priority analysis.

[0039] AXI4 master model control module, whose main function is to simulate the behavior of the AXI4 bus master. Through the interface interaction of VIO (Virtual Input / Output), it can manually initiate AXI4 bus master read and write access operations, and has an operation completion and operation timeout waiting processing mechanism. When the bus operation ends normally, the normal end flag can be displayed through the VIO interface; when the bus has no response for a certain period of time, the currently initiated operation request is automatically ended, and a bus access timeout alarm signal is generated, which is displayed through the VIO interface and automatically cleared when the next access request is initiated. Among them, the bit width of each signal is consistent with the AXI4 bus signal width used in the design code. The specific usage method is as follows: Before initiating a write operation access, configure the AWID, AWADDR, AWLEN, AWSIZE, AWBURST, and WDATA signals through VIO, and then click the WRITE pulse button to complete the sending of the master write operation request. Observe whether the W_DONE signal and W_TIMEOUT signal on the VIO interface are 1 to determine whether the current write operation ends normally or times out abnormally; before initiating a read operation access, configure the ARID, ARADDR, ARLEN, ARSIZE, and ARBURST signals through VIO, and then click the READ pulse button to complete the sending of the master read operation request. Observe whether the R_DONE signal and R_TIMEOUT signal on the VIO interface are 1 to determine whether the current read operation ends normally or times out abnormally. The specific VIO interface is as Figure 2 shown.

[0040] AXI4 monitoring module, whose main function is to integrate the main part of a group of AXI4 bus signals into the ILA IP of Xilinx FPGA through code instantiation. This method does not have the problem of the monitored signals being optimized or not found, and at the same time can lay a foundation for replacing the monitored signals later.

[0041] AHB master model control module, whose main function is to simulate the behavior of the AHB bus master. It realizes manual initiation of AHB bus master read and write access operations through the VIO interface interaction, and has an operation completion processing mechanism. When the bus operation ends normally, the normal end flag can be displayed through the VIO interface; when the normal end flag is not valid after a certain period of time, the result can be analyzed through the display of HRESP[1:0] on the VIO interface. The specific usage method is as follows: Before initiating a write operation access, configure the signals of HADDR[31:0], HTRANS[1:0], HSIZE[2:0], HBURST[2:0], and HWDATA[31:0] through VIO, and then click the HWRITE pulse button to complete the sending of the master write operation request. Observe whether the HW_DONE signal on the VIO interface is 1 to determine whether this write operation ends normally; before initiating a read operation access, configure the signals of HADDR[31:0], HTRANS[1:0], HSIZE[2:0], and HBURST[2:0] through VIO, and then click the HREAD pulse button to complete the sending of the master read operation request. Observe whether the HR_DONE signal on the VIO interface is 1 to determine whether this read operation ends normally. The specific VIO interface is as Figure 3 shown.

[0042] AHB monitoring module, whose main function is to integrate the main part signals of a group of AHB buses into the ILA IP of Xilinx FPGA through code instantiation. This method does not have the problem of the monitored signals being optimized or not found, and at the same time can lay a foundation for subsequent replacement of the monitored signals.

[0043] Migrate the debug function code to the FPGA prototype verification platform, integrate the general debug module into the debug function code, and modify the macro definition to monitor the AXI4 bus or AHB bus.

[0044] In some embodiments, the modification of the macro definition to monitor the AXI4 bus or AHB bus includes: integrating a general monitoring module into the debug function code, and opening the debug module of the debug function code through the macro definition; and instantiating the general monitoring module in the design top layer or internal module according to actual requirements, and connecting the debug bus at the same level to the general monitoring module.

[0045] First, open the debug mode of the design code through macro definition. Secondly, the general monitoring module can be instantiated in the top-level design or internal modules according to actual needs, and the debug bus at the same level is connected to the general monitoring module. During the instantiation of the top-level module, connect the output of the breathing light control to the LED pin in the top-level interface. Note the selection of the breathing light function clock and reset. It is recommended to use the clock generated by MMCM or PLL as the control clock for the breathing light. It is recommended to use the link up signal or reset signal generated after the system reset acts on a certain IP as the control reset for the breathing light, so that the system clock, MMCM / PLL, system reset, IP, etc. can be detected whether they are working properly. If there is no need to monitor the AXI4 bus or AHB bus at this level, and there is no need for AXI4 bus master control or AHB bus master control, the AXI4 master model control module, AXI4 monitoring module, AHB master model control module, AHB monitoring module and related interfaces in the general monitoring module can be disabled through macro definition. During the instantiation of the internal module, enable the AXI4 bus / AHB bus monitoring function or the master module control function in the general monitoring module through macro definition according to needs. The clock and reset in the breathing light function interface can select the more important clock and reset in this design level, and the output control can be left floating, and only observe the breathing light through the VIO interface.

[0046] Use the FPGA design software to synthesize the debug function code after transplantation and generate a verification file, and download the verification file to the FPGA prototype verification platform for verification. Use the FPGA design software to synthesize the design code after transplantation; use the FPGA design software for design optimization, placement, post-placement optimization, routing, and post-routing optimization. Use the FPGA design software to generate a bit file; download the bit file to the FPGA prototype verification platform, observe whether the LED on the prototype verification platform flashes at the expected frequency. If it is necessary to capture the monitored signal, set the trigger condition for debugging; if it is necessary to access a certain address using the AXI4 bus or AHB bus, call the BFM interface of the corresponding bus master to initiate the access timing.

[0047] Call Vivado software, set relevant synthesis properties and strategies according to the design code, and perform design synthesis. Call Vivado software, set relevant implementation properties and strategies according to the design code, and perform design optimization, layout, post-layout optimization, routing, and post-routing optimization. Use FPGA design software to generate a bit file; download the bit file to the FPGA prototype verification platform, and observe whether the LED of the prototype verification platform flashes at the expected frequency. If you need to capture the monitored signal, you can set the trigger condition for debugging; if you need to use the AXI4 bus or AHB bus to access a certain address, you can call the BFM interface of the corresponding bus master to initiate the access timing.

[0048] In some implementations, the method further includes: in response to a requirement to capture the unmonitored signal, using FPGA design software to open the wired netlist file, replacing the netlist file with a probe of the signal to be monitored, rewiring, generating a second verification file, and performing verification according to the second verification file. If there is a requirement to capture the unmonitored signal, the wired netlist file can be opened using FPGA design software, replaced with a probe of the signal to be monitored, rewiring, generating a bit file, and repeating the above steps.

[0049] If there is a requirement to capture the unmonitored signal, since we have already opened the debug mode, the key signals in the design code have been retained by us, so there will be no problem of missing or missing key signals. And our bit file already carries a certain number of monitoring signals. We can call Vivado software to open the netlist file after routing, find the signal to be monitored and replace it with the existing monitoring signal in ECO mode, then re-incrementally route, generate the bit file and ltx signal list file, and repeat the above steps.

[0050] By adding debugging code to the design code and enabling it, the embodiment of the present invention can ensure that in the later debugging process, if there is a need to temporarily capture certain key signals, these signals can be quickly found without the problem of being optimized out or not being found, thereby improving the debugging efficiency and reducing the time cost of re-synthesizing the signals to be captured; by integrating a general monitoring module into the design code, it is possible to simply, conveniently and intuitively understand whether the hardware connection, clock reset, file download, etc. are normal, and reduce the coupling test requirements at the software level, simplify the interface analysis of fault location, and improve the debugging verification efficiency.

[0051] It should be particularly noted that each step in each embodiment of the above-mentioned method for rapid debugging of FPGA prototype verification can be mutually crossed, replaced, added, or deleted. Therefore, these reasonable permutation and combination transformations for the method of rapid debugging of FPGA prototype verification should also fall within the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.

[0052] For the above purpose, in the second aspect of the embodiments of the present invention, a system for rapid debugging of FPGA prototype verification is proposed. As Figure 4 shown, the system 200 includes the following modules: an adding module configured to add debug function codes that can be turned on or off through macro definitions during the module design process; a development module configured to develop general debug modules for FPGA design software including breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enabling control, and monitoring IP; an integration module configured to transplant the debug function codes to the FPGA prototype verification platform, integrate the general debug modules into the debug function codes, and modify the macro definitions to implement monitoring of the AXI4 bus or the AHB bus; and a verification module configured to synthesize the debug function codes after transplantation processing using FPGA design software to generate verification files, and download the verification files to the FPGA prototype verification platform for verification.

[0053] In some embodiments, the adding module is configured to: add debug bus definition codes in the port definition and add debug bus assignment codes at the end of the module.

[0054] In some embodiments, the integration module is configured to: integrate a general monitoring module into the debug function codes and turn on the debug module of the debug function codes through macro definitions; and instantiate the general monitoring module at the design top layer or internal modules according to actual requirements and connect the debug buses at the same level to the general monitoring module.

[0055] In some embodiments, the system further includes a waveform capture module configured to: in response to a requirement for capturing waveforms of unmonitored signals, use FPGA design software to open the routed netlist file, replace the netlist file with probes of the signals to be monitored, re-route, generate a second verification file, and perform verification according to the second verification file.

[0056] For the above purposes, in the third aspect of the embodiments of the present invention, a computer device is proposed, including: at least one processor; and a memory storing computer instructions that can run on the processor, and the instructions are executed by the processor to implement the following steps: S1. Add debug function codes that can be turned on or off through macro definitions during the module design process; S2. Develop software based on FPGA design, including a general debug module for breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enabling control, and monitoring IP; S3. Transplant the debug function codes to the FPGA prototype verification platform, integrate the general debug module into the debug function codes, and modify the macro definitions to monitor the AXI4 bus or the AHB bus; and S4. Use the FPGA design software to synthesize the debug function codes after transplantation and generate verification files, and download the verification files to the FPGA prototype verification platform for verification.

[0057] In some embodiments, adding debug function codes that can be turned on or off through macro definitions during the module design process includes: adding debug bus definition codes in the port definition and adding debug bus assignment codes at the end of the module.

[0058] In some embodiments, modifying the macro definitions to monitor the AXI4 bus or the AHB bus includes: integrating a general monitoring module into the debug function codes and turning on the debug module of the debug function codes through macro definitions; and instantiating the general monitoring module in the design top layer or internal modules according to actual requirements and connecting the debug buses at the same level to the general monitoring module.

[0059] In some embodiments, the steps further include: in response to a requirement to capture waveforms of unmonitored signals, use the FPGA design software to open the routed netlist file, replace the netlist file with probes for the signals to be monitored, re-route the signals, generate a second verification file, and perform verification according to the second verification file.

[0060] As Figure 5 shown, it is a schematic diagram of the hardware structure of an embodiment of the above-mentioned computer device for rapid debugging of FPGA prototype verification provided by the present invention.

[0061] Taking the device as Figure 5 shown as an example, in this device, there is a processor 301 and a memory 302.

[0062] The processor 301 and the memory 302 can be connected through a bus or other means, Figure 5 and taking the connection through the bus as an example.

[0063] The memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for rapid debugging of FPGA prototype verification in the embodiments of the present application. The processor 301 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 302, that is, implements the method for rapid debugging of FPGA prototype verification.

[0064] The memory 302 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the method for rapid debugging of FPGA prototype verification, etc. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 302 may optionally include a memory remotely set relative to the processor 301, and these remote memories can be connected to the local module through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0065] One or more computer instructions 303 corresponding to the method for rapid debugging of FPGA prototype verification are stored in the memory 302. When executed by the processor 301, they execute the method for rapid debugging of FPGA prototype verification in any of the above method embodiments.

[0066] Any embodiment of the computer device that executes the above method for rapid debugging of FPGA prototype verification can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.

[0067] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, executes the method for rapid debugging of FPGA prototype verification.

[0068] As Figure 6 shown, it is a schematic diagram of an embodiment of the above computer storage medium for rapid debugging of FPGA prototype verification provided by the present invention. Taking the computer storage medium as shown in Figure 6 shown as an example, the computer-readable storage medium 401 stores a computer program 402 that, when executed by a processor, executes the above method.

[0069] Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program of the method for rapid debugging of FPGA prototype verification can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc. The embodiments of the above computer program can achieve the same or similar effects as those of any of the foregoing method embodiments corresponding thereto.

[0070] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein do not need to be performed in any specific order. In addition, although the elements disclosed in the embodiments of the present invention can be described or claimed in individual form, they can also be understood as plural unless explicitly limited to the singular.

[0071] It should be understood that, as used herein, unless the context clearly supports an exception, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations of one or more of the associated listed items.

[0072] The serial numbers of the disclosed embodiments of the present invention above are only for description and do not represent the superiority or inferiority of the embodiments.

[0073] Those of ordinary skill in the art can understand that all or part of the steps of the above embodiments can be completed by hardware or by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disk, etc.

[0074] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the embodiments disclosed by the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features between the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for rapid debugging of FPGA prototype verification, characterized in that, It includes the following steps: Add debug function code that can be turned on or off through macro definition during the module design process; Develop software based on FPGA design, including a general debug module for breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enable control, and monitoring IP; Port the debug function code to the FPGA prototype verification platform, integrate the general debug module into the debug function code, and modify the macro definition to monitor the AXI4 bus or AHB bus; and Use FPGA design software to synthesize the debug function code after transplantation and generate a verification file, and download the verification file to the FPGA prototype verification platform for verification; In response to the requirement of capturing waveforms of unmonitored signals, use FPGA design software to open the routed netlist file, replace the netlist file with probes for the signals to be monitored, re-route, generate a second verification file, and verify according to the second verification file.

2. The method according to claim 1, wherein The step of adding debug function code that can be turned on or off through macro definition during the module design process includes: Add debug bus definition code in the port definition and add debug bus assignment code at the end of the module.

3. The method according to claim 1, characterized in that, The step of modifying the macro definition to monitor the AXI4 bus or AHB bus includes: Integrate a general monitoring module into the debug function code and turn on the debug module of the debug function code through macro definition; and Instantiate the general monitoring module in the design top layer or internal module according to actual needs and connect the debug bus at the same level to the general monitoring module.

4. A system for rapid debugging of FPGA prototype verification, characterized in that, It includes: An adding module configured to add debug function code that can be turned on or off through macro definition during the module design process; A developing module configured to develop software based on FPGA design, including a general debug module for breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enable control, and monitoring IP; An integrating module configured to port the debug function code to the FPGA prototype verification platform, integrate the general debug module into the debug function code, and modify the macro definition to monitor the AXI4 bus or AHB bus; And A verifying module configured to use FPGA design software to synthesize the debug function code after transplantation and generate a verification file, and download the verification file to the FPGA prototype verification platform for verification; A waveform capturing module configured to: In response to the requirement of capturing waveforms of unmonitored signals, use FPGA design software to open the routed netlist file, replace the netlist file with probes for the signals to be monitored, re-route, generate a second verification file, and verify according to the second verification file.

5. The system according to claim 4, wherein The adding module is configured to: Add debug bus definition code in the port definition and add debug bus assignment code at the end of the module.

6. The system according to claim 4, wherein The integrating module is configured to: Integrate a general monitoring module into the debug function code, and open the debug module of the debug function code through macro definition; and Instantiate the general monitoring module in the top-level design or internal module according to actual requirements, and connect the debug bus at the same level to the general monitoring module.

7. A computer device, characterized in that, Comprising: At least one processor; And A memory storing computer instructions executable on the processor, and when the instructions are executed by the processor, the steps of the method according to any one of claims 1-3 are implemented.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1-3 are implemented.

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