Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source, and a first drain; a second channel, a second source, and a second drain; and a gate structure disposed above the first channel and the second channel. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystalline semiconductor layer, and the second source includes a second crystalline semiconductor layer. The first source and the second source are connected via an alloy layer made of one or more Group IV elements and one or more transition metal elements. The first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer. Embodiments of the present invention also relate to methods for manufacturing semiconductor devices.

Description

[0001] This application is a divisional application of the patent application entitled “Semiconductor device and method for manufacturing the same” filed on July 6, 2017, with patent application number 201710547154.6. Technical Field

[0002] The present invention relates to semiconductor devices, such as integrated circuits, and more particularly, to semiconductor devices having a silicide layer formed on a source / drain (S / D) structure and processes for manufacturing the same. Background Art

[0003] As the semiconductor industry has entered nanotechnology process nodes in the pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional (3D) designs such as fin field-effect transistors (Fin FETs) and the use of metal gate structures with high-k (dielectric constant) materials. The metal gate structure is generally manufactured using a gate replacement technique, and the source and drain are formed using an epitaxial growth method. Source / drain contact plugs are also formed on the source / drain, and the contact resistance of the source / drain contact plugs should be low. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor device including a field effect transistor (FET), wherein the field effect transistor includes: a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure, arranged above the first channel and the second channel, the gate structure including a gate dielectric layer and a gate electrode layer, wherein: the first source includes a first crystalline semiconductor layer and the second source includes a second crystalline semiconductor layer, the first source and the second source are connected via an alloy layer made of one or more Group IV elements and one or more transition metal elements, and the first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer.

[0005] Another embodiment of the present invention provides a semiconductor device including a fin field effect transistor (Fin FET), the fin field effect transistor including: a substrate; an insulating layer formed on the substrate; a first fin protruding from the substrate, the upper portion of the first fin protruding from the insulating layer serving as a first channel; a first source and a first drain contacting the first channel; a second fin protruding from the substrate, the upper portion of the second fin protruding from the insulating layer serving as a second channel; a second source and a second drain contacting the second channel; and a gate structure disposed above the first channel and the second channel, the gate structure including a gate dielectric layer and a gate electrode layer, wherein: the first source includes a first crystalline semiconductor layer made of a material different from that of the first channel, the second source includes a second crystalline semiconductor layer made of a material different from that of the second channel, the first source and the second source are connected via a metal alloy layer, the metal alloy layer is formed by a reaction between a metal and the first source and the second source, and the first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer.

[0006] Another embodiment of the present invention provides a method for manufacturing a semiconductor device including a field effect transistor (FET), the method including: forming a first field effect transistor structure and a second field effect transistor structure, the first field effect transistor structure having a first channel, a first source, a first drain and a common gate, and the second field effect transistor structure having a second channel, a second source, a second drain and the common gate; forming an alloy layer on the first source and the second source, wherein: the first source includes a first crystalline semiconductor layer and the second source includes a second crystalline semiconductor layer, the first source and the second source are connected through the alloy layer, the alloy layer is made of one or more Group IV elements and one or more transition metal elements, and the first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1A to 1D Illustrative cross-sectional views of various stages in the fabrication of a semiconductor device according to some embodiments of the present invention are shown.

[0009] Figures 2A to 2B shows exemplary cross-sectional views of various stages for fabricating a semiconductor device according to some embodiments of the present invention, and Figures 2C to 2DIllustrative perspective views of various stages in the fabrication of a semiconductor device according to some embodiments of the present invention are shown.

[0010] Figures 3A to 3D Illustrative perspective views of various stages in the fabrication of a semiconductor device according to some embodiments of the present invention are shown.

[0011] Figures 4A to 4C Illustrative perspective views of various stages in the fabrication of a semiconductor device according to some embodiments of the present invention are shown.

[0012] 5A to 5D illustrative perspective views of various stages for manufacturing a semiconductor device according to another embodiment of the present invention are shown.

[0013] Figures 6A to 6C illustrative perspective views of various stages for manufacturing a semiconductor device according to another embodiment of the present invention are shown.

[0014] Figure 7 is an exemplary cross-sectional view of a source / drain structure of a fin field effect transistor (Fin FET) according to some embodiments of the present invention.

[0015] Figure 8 is an exemplary cross-sectional view of a source / drain structure of a Fin FET according to some embodiments of the present invention.

[0016] Figure 9 is an exemplary cross-sectional view of a source / drain structure of a Fin FET according to some embodiments of the present invention.

[0017] Figure 10 is an exemplary cross-sectional view of a source / drain structure of a Fin FET according to some embodiments of the present invention.

[0018] Figure 11 is an exemplary cross-sectional view of a source / drain structure of a Fin FET according to some embodiments of the present invention.

[0019] Figure 12 is an exemplary cross-sectional view of a source / drain structure of a Fin FET according to some embodiments of the present invention.

[0020] Figure 13 is an exemplary cross-sectional view of a source / drain structure of a Fin FET according to some embodiments of the present invention.

[0021] Figure 14 is an exemplary cross-sectional view of a source / drain structure of a Fin FET according to some embodiments of the present invention.

[0022] 15A to 15Dillustrative cross-sectional views of various stages for fabricating a semiconductor device according to another embodiment of the present invention are shown.

[0023] 16A to 16B shows exemplary cross-sectional views of various stages for fabricating a semiconductor device according to some embodiments of the present invention, and 16C to 16D Illustrative perspective views of various stages in the fabrication of a semiconductor device according to some embodiments of the present invention are shown.

[0024] 17A to 17D illustrative perspective views of various stages for manufacturing a semiconductor device according to another embodiment of the present invention are shown.

[0025] 18A to 18C illustrative perspective views of various stages for manufacturing a semiconductor device according to another embodiment of the present invention are shown.

[0026] Figure 19 is an exemplary cross-sectional view of a source / drain structure of a gate-all-around field effect transistor (GAA FET) according to some embodiments of the present invention.

[0027] Figure 20 An exemplary cross-sectional view of a source / drain structure of a gate-all-around field effect transistor (GAA FET) according to some embodiments of the present invention is shown.

[0028] Figure 21A and Figure 21B is an exemplary cross-sectional view of a source / drain structure of a gate-all-around field effect transistor (GAA FET) according to some embodiments of the present invention. DETAILED DESCRIPTION

[0029] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact, and may also include an embodiment in which additional components may be formed between the first component and the second component so that the first component and the second component are not in direct contact. For the purposes of simplicity and clarity, various components may be arbitrarily drawn in different scales. In the accompanying drawings, some layers / components may be omitted for simplicity.

[0030] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, the term "made of" may mean "including" or "consisting of." Moreover, in subsequent manufacturing processes, there may be one or more additional operations during / between the described operations, and the order of the operations may be changed.

[0031] Figures 1A to 4C 1 shows exemplary cross-sectional views of various stages for fabricating a FinFET according to some embodiments of the present invention. Figures 1A to 4C Additional operations are provided before, during, and after the illustrated processes, and some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of the operations / processes may be interchanged.

[0032] In the manufacturing method of Fin FET, a fin structure is formed. Figure 1A As shown, a mask layer 10 is formed on a substrate 50. For example, the mask layer 10 is formed by a thermal oxidation process and / or a chemical vapor deposition (CVD) process. For example, the substrate 50 is a substrate having a thickness of about 1×10 15 cm -3 to about 1×10 16 cm -3 In other embodiments, the substrate is a p-type silicon substrate having an impurity concentration in the range of about 1×10 15 cm -3 to about 1×10 16 cm -3 n-type silicon or germanium substrate with an impurity concentration within a range.

[0033] Alternatively, substrate 50 may include another elemental semiconductor such as germanium; a compound semiconductor including IV-IV compound semiconductors such as SiC and SiGe; a III-V compound semiconductor such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Substrate 50 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0034] In some embodiments, as Figure 1AAs shown, for example, the mask layer 10 includes a pad oxide (eg, silicon oxide) layer 11 and a silicon nitride mask layer 12 .

[0035] The pad oxide layer 11 may be formed by using a thermal oxidation or CVD process. The silicon nitride mask layer 12 may be formed by physical vapor deposition (PVD) such as a sputtering method, CVD, plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure CVD (LPCVD), high density plasma CVD (HDPCVD), atomic layer deposition (ALD), and / or other processes.

[0036] In some embodiments, the thickness of the pad oxide layer 11 is in a range from about 2 nm to about 15 nm and the thickness of the silicon nitride mask layer 12 is in a range from about 2 nm to about 50 nm.

[0037] A mask pattern is further formed on the mask layer. For example, the mask pattern is a photoresist pattern formed by a photolithography operation. Figure 1B As shown, hard mask patterns of the pad oxide layer 11 and the silicon nitride mask layer 12 are formed by using the mask pattern as an etching mask.

[0038] Afterwards, if Figure 1C As shown, by using a hard mask pattern as an etching mask, a substrate 50 is patterned into a fin structure 52 for an n-type FET and a fin structure 54 for a p-type FET by trench etching using a dry etching method and / or a wet etching method. The size of the fin structure 52 for the n-type FET may be the same as or different from the size of the fin structure 54 for the p-type FET.

[0039] exist Figure 1C In FIG. 5 , two fin structures 52 and two fin structures 54 are disposed above substrate 50. However, the number of fin structures is not limited to two. The number may be as small as one or more than three. In addition, one or more dummy fin structures may be disposed adjacent to both sides of fin structure 52 and / or fin structure 54 to improve pattern fidelity during the patterning process.

[0040] Fin structures 52, 54 may be made of the same material as substrate 50 and may extend continuously from or protrude beyond substrate 50. In this embodiment, the fin structures are made of Si. The silicon layer of fin structures 52, 54 may be intrinsic or appropriately doped with n-type or p-type impurities.

[0041] In some embodiments, the width W1 of the fin structures 52, 54 is in a range from about 5 nm to about 40 nm, and in other embodiments, in a range from about 7 nm to about 12 nm. In some embodiments, the spacing S1 between the two fin structures is in a range from about 10 nm to about 40 nm. In some embodiments, the height H1 (along the Z direction) of the fin structures 52, 54 is in a range from about 100 nm to about 300 nm, and in other embodiments, in a range from about 50 nm to about 100 nm.

[0042] The lower portion of the fin structures 52 and 54 may be referred to as a well region, and the upper portion of the fin structures 52 and 54 covered by the gate electrode may be referred to as a channel or a channel region, and the upper portion of the fin structures 52 and 54 not covered by the gate electrode may be referred to as a source and a drain, or a source region and a drain region. In the present invention, "source" and "drain" may be collectively referred to as "source / drain". In some embodiments, the height of the well region is in the range of from about 60 nm to 100 nm, and the height of the channel region is in the range of from about 40 nm to 120 nm, and in other embodiments, in the range of from about 38 nm to about 60 nm.

[0043] like Figure 1D As shown, after forming the fin structures 52 and 54, a first protective layer 15 is formed to cover the fin structures 52 and 54. For example, the first protective layer 15 is made of silicon oxide, silicon nitride (SiN), or silicon oxynitride (SiON). In an embodiment, the first protective layer 15 is made of SiN. The first protective layer 15 can be formed by CVD. In some embodiments, the thickness of the first protective layer 15 is in a range from about 1 nm to about 20 nm.

[0044] like Figure 2A As shown, after forming the first protective layer 15, a second protective layer 17 is formed. For example, the second protective layer 17 is made of silicon oxide, silicon nitride (SiN), or silicon oxynitride (SiON) and is different from the first protective layer 15. In an embodiment, the second protective layer 17 is made of silicon oxide. The second protective layer 17 can be formed by CVD. In some embodiments, the thickness of the second protective layer 17 is in a range from about 1 nm to about 20 nm.

[0045] In addition, if Figure 2BAs shown, an isolation insulating layer 58 is formed in the space between the fin structures and / or in the space between a fin structure and other elements formed above the substrate 50. The isolation insulating layer 58 may also be referred to as a "shallow trench isolation (STI)" layer. The insulating material used for the isolation insulating layer 58 may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG) or low-k dielectric material. The isolation insulating layer is formed by LPCVD (low pressure chemical vapor deposition), plasma CVD or flowable CVD. In flowable CVD, a flowable dielectric material is deposited instead of silicon oxide. As the name implies, the flowable dielectric material can "flow" during deposition to fill gaps or spaces with a high aspect ratio. Typically, various chemicals are added to the silicon-containing precursor to allow the deposited film to flow. In some embodiments, nitrogen-hydrogen bonds are added. Examples of flowable dielectric precursors (particularly flowable silicon oxide precursors) include silicates, siloxanes, methylsilsesquioxane (MSQ), hydrogensilsesquioxane (HSQ), MSQ / HSQ, perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), tetraethyl orthosilicate (TEOS) or silylamines (such as trimethylsilylamine (TSA)). These flowable silicon oxide materials are formed in multiple operation processes. After the flowable film is deposited, the flowable film is cured and then annealed to remove undesirable elements to form silicon oxide. When the undesirable elements are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are performed. The flowable film is cured and annealed more than once. The flowable film can be doped with boron and / or phosphorus.

[0046] like Figure 2B As shown, the insulating layer 58 is first formed as a thick layer so that the fin structure is embedded in the thick layer, and as shown in FIG. Figure 2C As shown, the thick layer is recessed to expose the upper portions of the fin structures 52 and 54. The insulating layer 58 can be recessed using dry and / or wet etching. In some embodiments, the mask layers 11 and 12 and the first and second protective layers 15 and 17 are also removed from the exposed portions of the fin structures 52 and 54.

[0047] In some embodiments, a height H2 of the fin structure from the upper surface of isolation insulating layer 58 is in a range from about 20 nm to about 100 nm, and in other embodiments, in a range from about 30 nm to about 50 nm. After or before recessing isolation insulating layer 58, a thermal process, such as an annealing process, may be performed to improve the quality of isolation insulating layer 58. In some embodiments, the thermal process is performed using rapid thermal annealing (RTA) in an inert gas environment, such as an N2, Ar, or He environment, at a temperature in a range from about 900° C. to about 1050° C. for about 1.5 seconds to about 10 seconds.

[0048] In some embodiments, a gate replacement technique is employed. Figure 2D As shown, after forming (and recessing) the isolation insulating layer 58, a dummy gate structure including a dummy gate dielectric layer 20 and a dummy gate electrode layer 22 is formed over the fin structures 52 and 54. Figure 2D As shown, the gate structure extends in the X direction, while the fin structure extends in the Y direction.

[0049] To fabricate the dummy gate structure, a dielectric layer and a polysilicon layer are formed over the insulating layer 58 and the exposed fin structures 52 and 54, and then a patterning operation is performed to obtain a dummy gate structure comprising a dummy gate electrode layer 22 made of polysilicon and a dummy gate dielectric layer 20. In some embodiments, the polysilicon layer is patterned using a hard mask and the hard mask remains on the dummy gate electrode layer 22 as a capping insulating layer. The hard mask (capping insulating layer) comprises one or more layers of insulating material. In some embodiments, the capping insulating layer comprises a silicon nitride layer formed over the silicon oxide layer. In other embodiments, the capping insulating layer comprises a silicon oxide layer formed over the silicon nitride layer. The insulating material for the capping insulating layer can be formed by CVD, PVD, ALD, electron beam evaporation, or other suitable processes. In some embodiments, the dummy gate dielectric layer 20 may comprise one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the thickness of the dummy gate dielectric layer 20 is in the range of from about 2 nm to about 20 nm, and in other embodiments, in the range of from about 2 nm to about 10 nm. In some embodiments, the height of the dummy gate structure ranges from about 50 nm to about 400 nm, and in other embodiments, ranges from about 100 nm to about 200 nm.

[0050] If the gate-first process is adopted, the dummy gate electrode layer 22 and the dummy gate dielectric layer 20 serve as the gate electrode and the gate dielectric layer.

[0051] In addition, if Figure 3A As shown, sidewall spacers 24 are formed on opposite sidewalls of the dummy gate electrode layer 22. The sidewall spacers 24 include one or more layers of an insulating material (such as SiO2, SiN, SiON, SiOCN or SiCN) formed by CVD, PVD, ALD, electron beam evaporation or other suitable processes. Low-k dielectric materials can be used as sidewall spacers. The sidewall spacers 24 are formed by forming a blanket layer of insulating material and performing anisotropic etching. In an embodiment, the sidewall spacer layer is made of a silicon nitride-based material such as SiN, SiON, SiOCN or SiCN. In some embodiments, the thickness of the sidewall spacers 24 is in the range of from about 2 nm to about 10 nm.

[0052] Afterwards, if Figure 3BAs shown, by using, for example, anisotropic dry etching, sidewall spacers 24 formed on fin structures 52 and 54 are removed to expose the source / drain regions of fin structures 52 and 54.

[0053] As Figure 3C shown, after the source / drain regions of fin structures 52 and 54 are exposed, a source / drain epitaxial layer is formed. In some embodiments, the source / drain epitaxial layer 60 for an n-type FET includes one or more layers of semiconductor materials such as SiC, SiP, and SiCP, and this layer provides appropriate stress to the channel of the n-type FET. When SiP or SiCP is used as a multi-epitaxial layer, this layer has different P and / or C concentrations. Since fin structure 52 is crystalline Si, epitaxial layer 60 is also crystalline. In some embodiments, the source / drain epitaxial layer 62 for a p-type FET includes one or more semiconductor materials such as Ge and Si x Ge 1-x , where 0 < x < 1, and this layer provides appropriate stress to the channel of the p-type FET. When SiGe is used as a multi-epitaxial layer, this layer has different Ge concentrations. Since fin structures 52 and 54 are crystalline Si, epitaxial layers 60 and 62 are also crystalline. In certain embodiments, III-V materials that provide appropriate stress to the channel are used as source / drain epitaxial layers 60 and / or 62. In some embodiments, source / drain epitaxial layers 60 and / or 62 include multiple layers of epitaxially formed semiconductor materials.

[0054] The source / drain epitaxial layers 60 and 62 can be grown by using Si-containing gases such as SiH4, Si2H6, or SiCl2H2; Ge-containing gases such as GeH4, Ge2H6, or GeCl2H2; C-containing gases such as CH4 or C2H6; and / or dopant gases such as PH3, at a pressure of about 80 to 150 Torr and a temperature of about 400 to 800 °C. The source / drain structures for n-type FETs and the source / drain structures for p-type FETs can be formed by separate epitaxial processes.

[0055] In the present invention, as Figure 3C shown, after the source / drain epitaxial layers 60 and 62 are formed, the source / drain epitaxial layer 60 formed on fin structure 52 does not contact (i.e., is physically separated from) the source / drain epitaxial layer 60 formed on an adjacent fin structure 52. Similarly, as Figure 3C shown, the source / drain epitaxial layer 62 formed on one fin structure 54 does not contact (i.e., is physically separated from) the source / drain epitaxial layer 62 formed on an adjacent fin structure 54. In some embodiments, the spacing S2 between source / drain epitaxial layers 60 (or 62) is in the range from about 5 nm to 15 nm. Depending on the spacing S1 between the two fin structures (see Figure 1C ) Adjust the thickness of the source / drain epitaxial layers 60 and 62 to ensure the desired spacing S2.

[0056] like Figure 3D As shown, after forming the source / drain epitaxial layers 60 and 62, a dielectric cap layer 65 is formed over the source / drain epitaxial layers 60 and 62 and a first interlayer dielectric (ILD) layer 67 is formed over the dielectric cap layer 65. For example, in some embodiments, the dielectric cap layer 65 is made of SiN or SiON and has a thickness ranging from about 2 nm to about 20 nm. The first ILD layer 67 is made of a material different from the dielectric cap layer 65 and, for example, is made of one or more layers of silicon oxide, SiCN, SiOCN, or a low-k material.

[0057] After forming the ILD layer 67, a metal gate structure is formed. The dummy gate structure (dummy gate electrode layer 22 and dummy gate dielectric layer 20) is removed and replaced with a metal gate structure. In some embodiments, a first ILD layer 67 is formed over the dummy gate structure and a planarization process such as a chemical mechanical polishing (CMP) process or an etch-back process is performed to expose the upper surface of the dummy gate electrode layer 22. Thereafter, the dummy gate electrode layer 22 and the dummy gate dielectric layer 20 are removed by appropriate etching processes to form a gate opening. Figure 4A As shown, a metal gate structure including a gate dielectric layer 72 and a metal gate electrode layer 74 is formed in the gate opening.

[0058] A gate dielectric layer 72 may be formed over an interfacial layer (not shown) disposed over the channel layer of the fin structures 52 and 54. In some embodiments, the interfacial layer may include silicon oxide or germanium oxide having a thickness of 0.2 nm to 1.5 nm. In other embodiments, the thickness of the interfacial layer ranges from about 0.5 nm to about 10 nm.

[0059] The gate dielectric layer 72 includes one or more layers of a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. For example, the gate dielectric layer is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), or other suitable methods and / or combinations thereof. In some embodiments, the thickness of the gate dielectric layer is in a range from about 1 nm to about 10 nm, and in other embodiments, can be in a range from about 2 nm to about 7 nm.

[0060] A metal gate electrode layer 74 is formed over the gate dielectric layer. The metal gate electrode includes one or more layers of any suitable metal material, such as aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0061] In certain embodiments, as Figure 4A As shown, one or more work function adjustment layers 73 are interposed between the gate dielectric layer 72 and the metal gate electrode layer 74. The work function adjustment layer 73 is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For n-channel Fin FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for p-channel Fin FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer.

[0062] After depositing the appropriate materials for the metal gate structure, a planarization operation such as CMP is performed. Figure 4A As shown, the metal gate structure is recessed to form a cap space, and the cap space is filled with an insulating material 78 .

[0063] After forming the metal gate structure, the first ILD layer 67 and the dielectric cap layer 65 are removed. In some embodiments, the first ILD layer 67 and the dielectric cap layer 65 are completely removed from the area around the source / drain structure, and in other embodiments, the first ILD layer 67 and the dielectric cap layer 65 are partially removed.

[0064] like Figure 4B As shown, after at least partially removing the first ILD layer 67 , metal alloy layers 80 , 81 are formed over the source / drain epitaxial layers 60 and 62 .

[0065] Metal alloy layers 80 and 81 are alloys made of one or more Group IV elements and one or more transition metal elements. When source / drain epitaxial layers 60 and 62 are formed of silicon, metal alloy layers 80 and 81 are silicide layers. When source / drain epitaxial layers 60 and 62 are formed of germanium, metal alloy layers 80 and 81 are germanide layers. When source / drain epitaxial layers 60 and 62 are formed of SiGe, metal alloy layers 80 and 81 are silicide-germanide layers.

[0066] The transition metal includes one or more of Ti, Ta, Ni, and Co. The alloy layers 80 , 81 are one or more of TiSi, TaSi, NiSi, CoSi, TiSiGe, TaSiGe, NiSiGe, and CoSiGe.

[0067] After removing the first ILD layer 67, a transition metal is deposited on the source / drain epitaxial layers 60 and 62, for example, by CVD, ALD, or PVD. In some embodiments, during deposition, the deposited transition metal reacts with Si and / or Ge in the source / drain epitaxial layers 60 and 62, thereby forming alloy layers 80 and 81. In some embodiments, the silicide (alloy) layer can be formed by PECVD, CVD, PEALD, or ALD metal deposition at a temperature range of about 250 to about 700°C, followed by an in-situ dry etch or ex-situ wet selective etch using a Cl or F-based gas to remove the remaining metal on the spacers and isolation insulating layer. In other embodiments, the silicide (alloy) layer can be formed by PECVD, CVD, PEALD, or ALD metal deposition at a temperature range of about 350 to about 650°C. In certain embodiments, a nitridation process is then performed to passivate the silicide surface for subsequent silicide formation annealing. In other embodiments, a selective silicide deposition process by surface blocking of self-assembled molecules (SAMs) or inherently selective formation from appropriate metal and silicon precursors is implemented.Other suitable silicide formation processes may be used.

[0068] In this embodiment, before forming the alloy layer 80, the source / drain epitaxial layer 60 of one fin structure is separated from the source / drain epitaxial layer 60 of an adjacent fin structure, and the source / drain epitaxial layer 62 of one fin structure is separated from the source / drain epitaxial layer 62 of an adjacent fin structure. The alloy layers 80 and 81 are formed so that the formed alloy layer 80 connects the source / drain epitaxial layer 60 of one fin structure (52) and the source / drain epitaxial layer 60 of an adjacent fin structure (52), and the formed alloy layer 81 connects the source / drain epitaxial layer 62 of one fin structure (54) and the source / drain epitaxial layer 62 of an adjacent fin structure (54).

[0069] In some embodiments, after forming the transition metal layer on the source / drain epitaxial layers 60 and 62, an annealing operation is performed to form the alloy layer 80. The annealing operation is performed at a temperature of about 250°C to about 850°C.

[0070] like Figure 4CAs shown, after alloy layers 80 and 81 are formed, a contact etch stop layer (CESL) 150 is formed to cover alloy layers 80 and 81, and a second ILD layer 160 is formed on CESL 150. In some embodiments, CESL 150 is made of a silicon nitride-based material such as SiN and SiON and has a thickness ranging from about 2 nm to about 20 nm. Second ILD layer 160 is made of a material different from CESL 150 and, for example, is made of one or more layers of silicon oxide, SiCN, SiOCN, or a low-k material.

[0071] Then, if Figure 4C As shown, a patterning operation is performed to form contact openings over the alloy layers 80 and 81 of the source / drain structure, and the openings are filled with a conductive material to form contact plugs 200 and 201. The contact plugs 200 and 201 include a single layer or multiple layers of any suitable metal such as Co, W, Ti, Ta, Cu, Al, and / or Ni and / or nitrides of Ti or Ta.

[0072] After forming the contact plugs, CMOS processes are further performed to form various features such as one or more additional interlayer dielectric layers, contacts / vias, interconnect metal layers, and passivation layers.

[0073] Although the n-channel FET and the p-channel FET are shown adjacent to each other in the previous and subsequent embodiments, the arrangement of the n-channel FET and the p-channel FET is not limited to this arrangement.

[0074] Figures 5A to 6C FIG1 shows an exemplary cross-sectional view of various stages for manufacturing a FinFET according to another embodiment of the present invention. It should be understood that Figures 5A to 6C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged. Figures 1A to 4C The same or similar configurations, materials, processes and / or operations are described, and the detailed description may be omitted.

[0075] like Figure 5A As shown, in the formation Figure 3D After forming the structure shown in FIG, the first ILD 67 is recessed by dry and / or wet etching to expose the tops of the source / drain epitaxial layers 60 and 62.

[0076] Afterwards, if Figure 5BAs shown, the source / drain epitaxial layers 60 and 62 and the fin structure 52 are removed by dry and / or wet etching to form openings 111 and 112. The fin structure 52 is recessed to be flush with the upper surface of the isolation insulating layer 58. In some embodiments, the fin structure 52 is recessed below the upper surface of the isolation insulating layer 58. As Figure 5C shown, after the openings 111 and 112 are formed, a source / drain epitaxial layer 113 for an n-channel FET and a source / drain epitaxial layer 114 for a p-channel FET are formed.

[0077] In some embodiments, after the first ILD layer 67 is recessed, one of the n-channel FET region and the p-channel FET region is covered by a protective layer (e.g., SiN) and the operations described are performed separately for the n-channel FET region and the p-channel FET region Figure 5B and Figure 5C illustrated.

[0078] The source / drain epitaxial layer 113 for the n-channel FET includes one or more layers of Si, SiC, SiP, and SiCP, and the source / drain epitaxial layer 114 for the p-channel FET includes Ge and Si x Ge 1-x (where 0 < x < 1) of one or more layers.

[0079] Subsequently, as Figure 5D shown, an ILD layer 117 is formed above the source / drain epitaxial layers 113 and 114 and the first ILD layer 67. The ILD layer 117 is made of the same or a similar material as the first ILD layer 67.

[0080] After that, as Figure 6A shown, the same or similar operations as those Figure 4A described are performed and a metal gate structure including a gate dielectric layer 72 and a metal gate electrode 74 is formed. Further, as Figure 6B shown, the same or similar operations as those Figure 4B described are performed to form alloy layers 80 and 81 to connect two adjacent source / drain epitaxial layers. Subsequently, as Figure 6C shown, the same or similar operations as those Figure 4C described are performed to form contact plugs 200 and 201. After the contact plugs are formed, further CMOS processes are performed to form various components such as additional interlayer dielectric layers, contacts / vias, interconnect metal layers, and passivation layers.

[0081] Figures 7 to 14 is an exemplary cross-sectional view of a source / drain structure of a fin field-effect transistor (Fin FET) according to various embodiments of the present invention. In Figures 7 to 14In FIG, an n-channel FET (NFET) includes two fin structures 52 shown adjacent to each other, and a p-channel FET (PFET) includes two fin structures 54 shown adjacent to each other. However, the configuration is not limited thereto. The number of fin structures may be three or more, and one or more additional structures may be provided between the NFET and the PFET.

[0082] exist Figure 7 In an n-channel FET (NFET), a first n-type epitaxial layer 132 is formed on the fin structure 52, and a second n-type epitaxial layer 134 is formed on the first n-type epitaxial layer 132. The first n-type epitaxial layer and the second n-type epitaxial layer are crystalline semiconductor layers, such as Si, SiC, SiCP, SiP, Ge, and SiGe, having lattice constants different from each other and from the fin structure. When SiC, SiP, and / or SiCP are used, the C or P concentration of the second n-type epitaxial layer 134 is higher than the C or P concentration of the first n-type epitaxial layer 132. In some embodiments, a III-V semiconductor layer is used for at least one of the first n-type epitaxial layer and the second n-type epitaxial layer. The combination of the first n-type epitaxial layer 132 and the second n-type epitaxial layer 134 corresponds to the source / drain epitaxial layer 60. In other embodiments, only one of the first n-type epitaxial layer 132 and the second n-type epitaxial layer 134 is formed, and in some embodiments, three or more n-type epitaxial layers are formed.

[0083] In addition, an alloy layer 222 (corresponding to the alloy layer 80) such as a silicide layer is formed on the second n-type epitaxial layer 134. The alloy layer 222 is formed by a reaction between the material of the second n-type epitaxial layer 134 and the transition metal layer formed thereon. Figure 7 As shown, the second n-type epitaxial layer 134 of one of the two adjacent fin structures 52 does not contact the second n-type epitaxial layer 134 of the other adjacent fin structure 52. The alloy layer 222 fills the space between the two second n-type epitaxial layers 134 and physically and electrically connects the two second n-type epitaxial layers 134.

[0084] In some embodiments, residual transition metal 215 that has not completely reacted with the second n-type epitaxial layer 134 remains. In this case, in some embodiments, the remaining transition metal can be converted into a passivation layer by a subsequent nitridation operation using NH3 or N2+H2 plasma. The passivation layer covers the surface of the alloy layer 222 to protect the alloy layer 222 from damage caused by subsequent processes. In addition, as Figure 7 As shown, CESL 150 covers the n-type source / drain structure.

[0085] Contact plug 200 contacts alloy layer 222. In some embodiments, contact plug 200 includes barrier layer 202 made of, for example, TiN or TaN, and body layer 210 made of, for example, Co, W, Ti, Ta, Cu, Ru, Rh, Ir, Al, and / or Ni.

[0086] exist Figure 7 In the embodiment shown in FIG. 5 , the transition metal layer 225 remains at the bottom of the gap 224 formed by the alloy layer 222 and the isolation insulating layer 58. The volume of the transition metal layer 225 is small enough not to affect the electrical performance of the NFET.

[0087] In addition, Figure 7 In the present invention, there are spacer residues 110, which are not in the Figure 3B The remaining portions of sidewall spacers 24 are etched during the etching operation.

[0088] In some embodiments, the width T11 (maximum width) of the fin structure 52 surrounded by the first n-type epitaxial layer along the X direction is in a range from about 4 nm to about 10 nm. In some embodiments, the thickness T12 of the first n-type epitaxial layer 132 is in a range from about 0.5 nm to about 3 nm, and in some embodiments, the thickness T13 of the second n-type epitaxial layer 134 is in a range from about 2 nm to about 8 nm. In some embodiments, the spacing T15 between two adjacent second n-type epitaxial layers 134 is in a range from about 0.5 nm to about 20 nm. In some embodiments, Figure 3B The isolation insulating layer 58 is etched in an operation of etch 110, and the etching amount H11 is in a range from about 0.5 nm to about 20 nm. In some embodiments, the vertical thickness of the spacer residue 110 is in a range from about 0.5 nm to about 30 nm.

[0089] In some embodiments, during the formation of the alloy layer, one or more voids 143 are formed. The cross-sectional shape of the voids 143 may include a diamond, a circle, an ellipse, or an irregular shape. The shape may be symmetrical or asymmetrical. In some embodiments, the number of voids may be as small as one, and in other embodiments, more than one. The size of the multiple voids and the spacing between the voids may be substantially the same or different.

[0090] Figure 7The p-channel FET (PFET) shown in the figure has a structure that is the same as or similar to that of the n-channel FET (NFET), and the description of the common configuration may be omitted. A first p-type epitaxial layer 136 is formed on the fin structure 54, and a second p-type epitaxial layer 138 is formed on the first p-type epitaxial layer 136. The first p-type epitaxial layer and the second p-type epitaxial layer are crystalline semiconductor layers, such as Si, SiC, SiCP, SiP, Ge, and SiGe, having lattice constants different from each other and from the fin structure. When SiGe is used, the Ge concentration of the second p-type epitaxial layer 138 is higher than the Ge concentration of the first p-type epitaxial layer 136. In some embodiments, a III-V semiconductor layer is used for at least one of the first p-type epitaxial layer and the second p-type epitaxial layer. The combination of the first p-type epitaxial layer 136 and the second p-type epitaxial layer 138 corresponds to the source / drain epitaxial layer 62. In other embodiments, only one of the first p-type epitaxial layer 136 and the second p-type epitaxial layer 138 is formed, and in some embodiments, three or more p-type epitaxial layers are formed.

[0091] Furthermore, an alloy layer 220 (corresponding to the alloy layer 81) such as a silicide layer is formed on the second p-type epitaxial layer 138. The alloy layer 220 is formed by a reaction between the material of the second p-type epitaxial layer 138 and the transition metal layer formed thereon. Figure 7 As shown, the second p-type epitaxial layer 138 of one of the two adjacent fin structures 54 does not contact the second p-type epitaxial layer 138 of the other of the two adjacent fin structures 54. The alloy layer 220 fills the space between the two second p-type epitaxial layers 138 and physically and electrically connects the two second p-type epitaxial layers 138.

[0092] In some embodiments, residual transition metal 215 that has not completely reacted with the second p-type epitaxial layer 138 remains. In this case, in some embodiments, the remaining transition metal can be converted into a passivation layer by a subsequent nitridation operation using NH3 or N2+H2 plasma. The passivation layer covers the surface of the alloy layer 220 to protect the alloy layer 220 from damage caused by subsequent processes. In addition, as Figure 7 As shown, CESL 150 covers the p-type source / drain structure.

[0093] Contact plug 201 contacts alloy layer 222. In some embodiments, contact plug 201 includes barrier layer 202 made of, for example, TiN or TaN, and body layer 210 made of, for example, Co, W, Ti, Ta, Cu, Ru, Rh, Ir, Al, and / or Ni.

[0094] exist Figure 7In the embodiment shown in FIG. 5 , the transition metal layer 225 remains at the bottom of the gap 224 formed by the alloy layer 222 and the isolation insulating layer 58. The volume of the transition metal layer 225 is small enough not to affect the electrical performance of the PFET.

[0095] In addition, Figure 7 In the present invention, there are spacer residues 110, which are not in the Figure 3B The remaining portions of sidewall spacers 24 are etched during the etching operation.

[0096] In some embodiments, the width T21 (maximum width) of the fin structure 54 surrounded by the first p-type epitaxial layer along the X direction is in a range from about 4 nm to about 10 nm. In some embodiments, the thickness T22 of the first p-type epitaxial layer 136 is in a range from about 0.5 nm to about 3 nm, and in some embodiments, the thickness T23 of the second p-type epitaxial layer 138 is in a range from about 2 nm to about 8 nm. In some embodiments, the spacing T25 between two adjacent second p-type epitaxial layers 138 is in a range from about 0.5 nm to about 20 nm.

[0097] In some embodiments, during the formation of the alloy layer, one or more voids 144 are formed. The cross-sectional shape of the voids 144 may include a diamond, a circle, an ellipse, or an irregular shape. The shape may be symmetrical or asymmetrical. In some embodiments, the number of voids may be as small as one, and in other embodiments, more than one. The size of the multiple voids and the spacing between the voids may be substantially the same or different.

[0098] Figure 8 FIG is an exemplary cross-sectional view of a source / drain structure of a FinFET according to another embodiment of the present invention. In addition to the absence of the spacer residue 110 in this embodiment, Figure 8 Shown with Figure 7 Basically the same structure.

[0099] Figure 9 FIG is an exemplary cross-sectional view of a source / drain structure of a FinFET according to another embodiment of the present invention. In addition to the shape of the source / drain epitaxial layer, Figure 9 Shown with Figure 7 Basically the same structure. Figure 9 In the embodiment, the source / drain epitaxial layers (eg, 132, 134, 136, and 138) are tapered, with a bottom area larger than an upper area. The shape of the source / drain epitaxial layers may be varied depending on epitaxial growth conditions.

[0100] Figure 10FIG is an exemplary cross-sectional view of a source / drain structure of a FinFET according to another embodiment of the present invention. Except that there is no spacer residue 110 in this embodiment, Figure 10 Shown with Figure 9 Basically the same structure.

[0101] Figure 11 FIG is an exemplary cross-sectional view of a source / drain structure of a FinFET according to another embodiment of the present invention. Figure 11 In the process, no source / drain epitaxial layer is formed on the fin structure 52. Figure 3B After the structure shown in FIG, the first ILD 67 is formed without forming the source / drain epitaxial layers 60, 62. Figures 3D to 4C The same or similar operations can be obtained Figure 11 structure.

[0102] exist Figure 11 In the embodiment, the alloy layer 220 or 222 is directly wrapped around the fin structure 52 made of crystalline semiconductor. In some embodiments, the spacing T15′ and T25′ between the two fin structures covered by the alloy layer 220 or 222 is in a range from about 8 nm to about 60 nm.

[0103] Although Figure 11 Spacer residue 110 is shown in FIG, but in some embodiments, no spacer residue 110 remains.

[0104] Figures 12 to 14 is based on Figures 5A to 6C An exemplary cross-sectional view of the source / drain structure of a Fin FET according to the method shown. Figures 7 to 11 Those of the same or similar configurations, structures and / or materials, and detailed descriptions may be omitted.

[0105] In such Figure 5B After recessing source / drain epitaxial layers 60 and 62 and fin structure 52 as shown, for an n-channel FET, a first n-type epitaxial layer 131 is formed on recessed fin structure 52, and a second n-type epitaxial layer 133 is formed on first n-type epitaxial layer 131, and for a p-channel FET, a first p-type epitaxial layer 135 is formed on recessed fin structure 54, and a second p-type epitaxial layer 137 is formed on first n-type epitaxial layer 135. The combination of the first n-type epitaxial layer and the second n-type epitaxial layer corresponds to source / drain epitaxial layer 113, and the combination of the first p-type epitaxial layer and the second p-type epitaxial layer corresponds to source / drain epitaxial layer 114.

[0106] First n-type epitaxial layer 131 and second n-type epitaxial layer 133 are crystalline semiconductor layers, such as Si, SiC, SiCP, SiP, Ge, and SiGe, having lattice constants that differ from one another and from those of the fin structure. When SiC, SiP, and / or SiCP are used, the C or P concentration of second n-type epitaxial layer 133 is higher than that of first n-type epitaxial layer 131. In some embodiments, a III-V semiconductor layer is used for at least one of the first n-type epitaxial layer 131 and the second n-type epitaxial layer 133. In other embodiments, only one of the first n-type epitaxial layer 131 and the second n-type epitaxial layer 133 is formed, and in some embodiments, three or more n-type epitaxial layers are formed.

[0107] First p-type epitaxial layer 135 and second p-type epitaxial layer 137 are crystalline semiconductor layers, such as Si, SiC, SiCP, SiP, Ge, and SiGe, having lattice constants that differ from one another and from those of the fin structure. When SiGe is used, the Ge concentration in second p-type epitaxial layer 137 is higher than the Ge concentration in first p-type epitaxial layer 135. In some embodiments, a III-V semiconductor layer is used for at least one of the first p-type epitaxial layer 135 and the second p-type epitaxial layer 137. In other embodiments, only one of the first p-type epitaxial layer 135 and the second p-type epitaxial layer 137 is formed, and in some embodiments, three or more p-type epitaxial layers are formed.

[0108] Since the first n-type epitaxial layer and the second n-type epitaxial layer and the first p-type epitaxial layer and the second p-type epitaxial layer are formed on Figure 5B In the shown openings 111 and 112 , the shape of the epitaxial layer is therefore limited by the shape of the openings 111 and 112 .

[0109] In some embodiments, the thickness H14 of the first n-type epitaxial layer 131 is in a range from about 0.5 nm to about 3 nm, and in some embodiments, the thickness H15 of the second n-type epitaxial layer 133 is in a range from about 2 nm to about 100 nm. In some embodiments, the thickness H24 of the first p-type epitaxial layer 135 is in a range from about 0.5 nm to about 3 nm, and in some embodiments, the thickness H25 of the second p-type epitaxial layer 137 is in a range from about 2 nm to about 100 nm.

[0110] Figure 13 is an exemplary cross-sectional view of a source / drain structure of a FinFET according to some embodiments of the present invention. Except that there is no spacer residue 110 in this embodiment, Figure 13 Shown with Figure 12 Basically the same structure.

[0111] Figure 14is an exemplary cross-sectional view of a source / drain structure of a FinFET according to another embodiment of the present invention.

[0112] In the formation Figure 3A After the structure is formed, the fin structure 52 is recessed to the isolation insulating layer 58 or below the isolation insulating layer 58, and then an epitaxial source / drain structure is formed on the recessed fin structure 52. Subsequently, a capping layer 60 and a first ILD layer 67 are formed, and the same as Figures 4A to 4C or Figures 6A to 6C In this embodiment, since the source / drain epitaxial layer is not formed in the opening, the source / drain epitaxial layer is grown laterally to have a Figure 14 The diamond cross-sectional shape shown.

[0113] More specifically, after recessing fin structure 52, for an n-channel FET, a first n-type epitaxial layer 131 is formed on recessed fin structure 52, and a second n-type epitaxial layer 133 is formed on first n-type epitaxial layer 131, and for a p-channel FET, a first p-type epitaxial layer 135 is formed on recessed fin structure 54, and a second p-type epitaxial layer 137 is formed on first n-type epitaxial layer 135. Second n-type epitaxial layer 133 has a diamond-shaped cross-sectional profile due to the lateral growth of the epitaxial layer, and second p-type epitaxial layer 137 has a diamond-shaped cross-sectional profile due to the lateral growth of the epitaxial layer.

[0114] In some embodiments, the thickness H16 of the first n-type epitaxial layer 131 is in a range from about 0.5 nm to about 3 nm, and in some embodiments, the thickness H17 of the second n-type epitaxial layer 133 is in a range from about 2 nm to about 40 nm. In some embodiments, the thickness H26 of the first p-type epitaxial layer 135 is in a range from about 0.5 nm to about 3 nm, and in some embodiments, the thickness H27 of the second p-type epitaxial layer 137 is in a range from about 2 nm to about 40 nm.

[0115] Figures 15A to 18C FIG1 shows an exemplary cross-sectional view of various stages for manufacturing a FinFET according to another embodiment of the present invention. It should be understood that Figures 15A to 18C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged. Figures 1A to 14 The same or similar configurations, structures, materials and / or dimensions as those described above are used, and their detailed descriptions may be omitted. In the following embodiments, a gate-all-around FET is adopted.

[0116] like Figure 15AAs shown, a stacked semiconductor layer is formed above a substrate 50. The stacked semiconductor layer includes a first semiconductor layer 42 and a second semiconductor layer 44. In addition, a mask layer 10 is formed above the stacked layers.

[0117] The first semiconductor layer 42 and the second semiconductor layer 44 are made of materials having different lattice constants and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the first semiconductor layer 42 and the second semiconductor layer 44 are made of Si, Si compounds, SiGe, Ge, or Ge compounds. In an embodiment, the first semiconductor layer 42 is Si 1-x Ge x , where x is greater than about 0.3, or Ge (x = 1.0), and the second semiconductor layer 44 is Si or Si 1-y Ge y , where y is less than about 0.4, and x > y. In the present invention, the "M" compound or "M-based compound" means that the main body of the compound is M.

[0118] In another embodiment, the second semiconductor layer 44 is Si 1-y Ge y or Ge, where y is greater than about 0.3, and the first semiconductor layer 42 is Si or Si 1-x Ge x , where x is less than about 0.4, and x < y. In yet another embodiment, the first semiconductor layer 42 is made of Si 1-x Ge x , where x ranges from about 0.3 to about 0.8, and the second semiconductor layer 44 is made of Si 1-x Ge x , where x ranges from about 0.1 to about 0.4.

[0119] In Figure 15A , four layers of the first semiconductor layer 42 and four layers of the second semiconductor layer 44 are provided. However, the number of layers is not limited to four and can be as small as 1 (per layer) and in some embodiments, 2 - 10 layers of each of the first semiconductor layer and the second semiconductor layer are formed. By adjusting the number of stacked layers, the drive current of the GAA FET device can be adjusted.

[0120] A first semiconductor layer 42 and a second semiconductor layer 44 are epitaxially formed over a substrate 50. The thickness of the first semiconductor layer 42 may be equal to or greater than the thickness of the second semiconductor layer 44, and in some embodiments, is in a range from about 5 nm to about 50 nm, and in another embodiment, is in a range from about 10 nm to about 30 nm. In some embodiments, the thickness of the second semiconductor layer 44 is in a range from about 5 nm to about 30 nm, and in other embodiments, is in a range from about 10 nm to about 20 nm. The thickness of each first semiconductor layer 42 may be the same, or may be different.

[0121] In some embodiments, as Figure 15A As shown, for example, the mask layer 10 includes a pad oxide (eg, silicon oxide) layer 11 and a silicon nitride mask layer 12 .

[0122] A mask pattern is further formed on the mask layer. For example, the mask pattern is a photoresist pattern formed by a photolithography operation. Figure 15B As shown, hard mask patterns of the pad oxide layer 11 and the silicon nitride mask layer 12 are formed by using the mask pattern as an etching mask.

[0123] Afterwards, if Figure 15C As shown, by using the hard mask pattern as an etching mask, the stacked semiconductor layers 42, 44 and the substrate 50 are patterned into a fin structure 152 for n-type FET and a fin structure 154 for p-type FET by trench etching using a dry etching method and / or a wet etching method. The size of the fin structure 152 for n-type FET may be the same as or different from the size of the fin structure 154 for p-type FET.

[0124] like Figure 15D As shown, after forming the fin structures 152 and 154, similar to Figure 1D , a first protection layer 15 is formed to cover the fin structures 152 and 154 .

[0125] like Figure 16A As shown, after forming the first protective layer 15, similar to Figure 2A , forming a second protective layer 17.

[0126] In addition, if Figure 16B As shown, similar to Figure 2B An isolation insulating layer (STI) 58 is formed in spaces between the fin structures and / or in spaces between a fin structure and other elements formed over the substrate 50 .

[0127] like Figure 16C As shown, similar to Figure 2B and Figure 2C, the thick insulating layer 58 is recessed to expose the upper portions of the fin structures 152, 154. In some embodiments, the height H2' of the fin structures from the upper surface of the isolation insulating layer 58 is in the range from about 20 nm to about 100 nm, and in other embodiments, in the range from about 30 nm to about 50 nm.

[0128] As Figure 16D shown, similar to Figure 2D , after forming (and recessing) the isolation insulating layer 58, a dummy gate structure including a dummy gate dielectric layer 20 and a dummy gate electrode layer 22 is formed over the fin structures 152, 154.

[0129] In addition, as Figure 17A shown, similar to Figure 3C , sidewall spacers 24 are formed on the opposite sidewalls of the dummy gate electrode layer 22.

[0130] After that, as Figure 17B shown, the sidewall spacers 24 formed on the fin structures 152, 154 are removed by using, for example, anisotropic dry etching to expose the source / drain regions (stacked semiconductor layer portions) of the fin structures 152, 154. After the source / drain regions are exposed, the first semiconductor layer 42 is selectively removed by using a wet etchant such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. In other embodiments, the second semiconductor layer 44 is selectively removed. In certain embodiments, for n-channel FETs, the first semiconductor layer 42 is removed and for p-channel FETs, the second semiconductor layer 44 is removed. In yet another embodiment, for n-channel FETs, the second semiconductor layer 44 is removed and for p-channel FETs, the first semiconductor layer 42 is removed.

[0131] Subsequently, as Figure 17C shown, source / drain epitaxial layers 46, 48 are formed. In some embodiments, the source / drain epitaxial layer 46 for n-type FETs includes one or more layers of semiconductor materials such as SiC, SiP, and SiCP, and this layer provides appropriate stress to the channel of the n-type FET. Since the second semiconductor layer 44 is a crystalline semiconductor, the epitaxial layer 46 is also crystalline. In some embodiments, the source / drain epitaxial layer 48 for p-type FETs includes one or more semiconductor materials such as Ge and Si x Ge 1-x , where 0 < x < 1, and this layer provides appropriate stress to the channel of the p-type FET. Since the second semiconductor layer 4 is a crystalline semiconductor, the epitaxial layer 48 is also crystalline.

[0132] Source / drain epitaxial layers 46, 48 may be selectively grown on and around the second semiconductor layer 44 using a Si-containing gas, such as SiH4, Si2H6, or SiCl2H2; a Ge-containing gas, such as GeH4, Ge2H6, or GeCl2H2; a C-containing gas, such as CH4 or C2H6; and / or a dopant gas, such as PH3, at a pressure of about 80 to 150 Torr and a temperature of about 600 to 800° C. The source / drain structure for n-type FETs and the source / drain structure for p-type FETs may be formed by separate epitaxial processes.

[0133] like Figure 17D As shown, after forming the source / drain epitaxial layers 46 and 48, a dielectric cap layer 45 is formed over the source / drain epitaxial layers 46 and 48, and a first interlayer dielectric (ILD) layer 67 is formed over the dielectric cap layer 45. For example, the dielectric cap layer 45 is made of SiN or SiON and, in some embodiments, has a thickness ranging from about 2 nm to about 20 nm. The first ILD 67 is made of a material different from the dielectric cap layer 45 and, for example, is made of one or more layers of silicon oxide, SiCN, SiOCN, or a low-k material.

[0134] After forming the first ILD layer 67, a nanowire channel structure and a metal gate structure are formed. In some embodiments, the first ILD layer 67 is formed above the dummy gate structure and a planarization process such as a chemical mechanical polishing (CMP) process or an etch-back process is performed to expose the upper surface of the dummy gate electrode layer 22. The dummy gate structure (dummy gate electrode layer 22 and dummy gate dielectric layer 20) is removed by using a suitable etching operation to expose the stacked structure of the first semiconductor layer 42 and the second semiconductor layer 44. Thereafter, the first semiconductor layer 42 is selectively removed to leave the second semiconductor layer 44 as a nanowire channel. Figure 18A As shown, a metal gate structure including a gate dielectric layer 72 and a metal gate electrode layer 74 is formed to wrap around the second semiconductor layer 44. One or more layers of work function tuning metal may be formed between the gate dielectric layer 72 and the metal gate electrode layer 74.

[0135] In other embodiments, the second semiconductor layer 44 is selectively removed to leave the first semiconductor layer 42 as the nanowire channel. In some embodiments, the first semiconductor layer 42 is removed for n-channel FETs, and the second semiconductor layer 44 is removed for p-channel FETs. In yet another embodiment, the second semiconductor layer 44 is removed for n-channel FETs, and the first semiconductor layer 42 is removed for p-channel FETs.

[0136] After forming the metal gate structure, the first ILD layer 67 and the dielectric cap layer 45 are removed. In some embodiments, the first ILD layer 67 and the dielectric cap layer 45 are completely removed from the area around the source / drain structure, and in other embodiments, the first ILD layer 67 and the dielectric cap layer 45 are partially removed.

[0137] like Figure 18B As shown, after at least partially removing the first ILD layer 67, similar to Figure 4B , metal alloy layers 80 and 81 are formed over the source / drain epitaxial layers 46 and 48. The alloy layer 80 is one or more of TiSi, TaSi, NiSi, CoSi, TiSiGe, TaSiGe, NiSiGe and CoSiGe.

[0138] After removing the first ILD layer 67, a transition metal is deposited on the source / drain epitaxial layers 46 and 48, for example, by CVD, ALD, or PVD. In some embodiments, during deposition, the deposited transition metal reacts with Si and / or Ge in the source / drain epitaxial layers 46 and 48 to form alloy layers 80 and 81.

[0139] In this embodiment, before forming the alloy layers 80 and 81, the source / drain epitaxial layer 46 formed on one second semiconductor layer 44 of the first fin structure is separated from the source / drain epitaxial layer 46 formed on an adjacent second semiconductor layer 44, and the source / drain epitaxial layer 48 formed on one second semiconductor layer 44 of the second fin structure is separated from the source / drain epitaxial layer 48 formed on an adjacent second semiconductor layer 44. The alloy layers 80 and 81 are formed so that the alloy layer 80 connects the source / drain epitaxial layer 46 of one second semiconductor layer 44 and the source / drain epitaxial layer 46 of an adjacent second semiconductor layer 44, and the alloy layer 81 connects the source / drain epitaxial layer 48 of one second semiconductor layer 44 and the source / drain epitaxial layer 48 of an adjacent second semiconductor layer 44.

[0140] In some embodiments, after forming the transition metal layer on the source / drain epitaxial layers 46 and 48, an annealing operation is performed to form the alloy layers 80 and 81. The annealing operation is performed at a temperature of about 250°C to about 850°C.

[0141] like Figure 18C As shown, after forming the alloy layers 80 and 81, similar to Figure 4C A contact etch stop layer (CESL) 150 is formed to cover the alloy layers 80 and 81, and a second ILD layer 160 is formed on the CESL 150. Figure 18C As shown, similar to Figure 4CA patterning operation is performed to form contact openings above the alloy layers 80 and 81 of the source / drain structure, and the openings are filled with a conductive material to form contact plugs 200 and 201 .

[0142] After forming the contact plugs, CMOS processes are further performed to form various features such as additional interlayer dielectric layers, contacts / vias, interconnect metal layers, and passivation layers.

[0143] In some embodiments, the gate-all-around field effect transistor (GAA FET) described above is used Figures 5A to 6C Instructions for operation.

[0144] Figure 19 is an exemplary cross-sectional view (X-cut) of the source / drain structure of a GAA FET according to some embodiments of the present invention. Figure 19 In the embodiment of the present invention, an n-channel GAA FET (NFET) and a p-channel GAA FET (PFET) are shown adjacent to each other. However, the configuration is not limited thereto. The number of fin structures may be two or more, and one or more additional structures may be provided between the NFET and the PFET.

[0145] exist Figure 19 In an n-channel GAA FET (NFET), an n-type semiconductor wiring layer 332 (e.g., corresponding to the second semiconductor layer 44) is disposed above the fin structure 152, and an n-type epitaxial layer 334 (e.g., corresponding to the source / drain epitaxial layer 46) is formed to surround the n-type semiconductor wiring layer 332. The n-type semiconductor wiring layer 332 and the n-type epitaxial layer 334 are crystalline semiconductor layers, such as Si, SiC, SiCP, SiP, Ge, and SiGe, having lattice constants different from each other and from those of the fin structure. When SiC, SiP, and / or SiCP are used, the C or P concentration of the n-type epitaxial layer 334 is higher than that of the n-type semiconductor wiring layer 332. In some embodiments, a III-V semiconductor layer is used for at least one of the semiconductor wiring layer and the n-type epitaxial layer. In certain embodiments, two or more n-type epitaxial layers are formed. Furthermore, the number of n-type semiconductor wiring layers 332 is not limited thereto.

[0146] In addition, an alloy layer 322 (corresponding to the alloy layer 80) such as a silicide layer is formed around the n-type epitaxial layer 334. Figure 19 As shown, one n-type epitaxial layer 334 does not contact the adjacent n-type epitaxial layer 334. The alloy layer 322 fills the space between the two n-type epitaxial layers 334 and physically and electrically connects the two n-type epitaxial layers 334.

[0147] In some embodiments, residual transition metal 324 that has not completely reacted with n-type epitaxial layer 334 remains. In this case, in some embodiments, the remaining transition metal can be converted into a passivation layer by a subsequent nitridation operation using NH3 or N2+H2 plasma. The passivation layer covers the surface of alloy layer 322 to protect alloy layer 322 from damage caused by subsequent processes. Contact plug 200 is in contact with alloy layer 322. In some embodiments, contact plug 200 includes barrier layer 202 made of, for example, TiN or TaN and body layer 210 made of, for example, Co, W, Ti, Ta, Cu, Ru, Rh, Ir, Al and / or Ni. In some embodiments, there is a spacer residue that is not in the Figure 17B The remaining portions of sidewall spacers 24 are etched during the etching operation.

[0148] In some embodiments, the thickness T84 of the n-type semiconductor wiring layer 332 is in a range from about 5 nm to about 50 nm, and in other embodiments, in a range from about 10 nm to about 30 nm. In some embodiments, the spacing T85 between two adjacent n-type semiconductor wiring layers 332 is in a range from about 5 nm to about 50 nm, and in other embodiments, in a range from about 10 nm to about 30 nm. In some embodiments, the thickness T86 of the n-type epitaxial layer 334 is in a range from about 1 nm to about 30 nm, and in other embodiments, in a range from about 2 nm to about 7 nm. In some embodiments, the spacing T87 between adjacent n-type epitaxial layers 334 is in a range from about 1 nm to about 10 nm, and in other embodiments, in a range from about 2 nm to about 5 nm.

[0149] Figure 19 The p-channel GAA FET (NFET) shown in the figure has a structure that is the same as or similar to that of the n-channel FET (NFET), and the description of the common configuration may be omitted. A p-type semiconductor wiring layer 336 (e.g., corresponding to the second semiconductor layer 44) is provided above the fin structure 154, and a p-type epitaxial layer 338 (e.g., corresponding to the source / drain epitaxial layer 48) is formed to wrap around the p-type semiconductor wiring layer 336. The semiconductor wiring layer and the p-type epitaxial layer are crystalline semiconductor layers, such as Si, SiC, SiCP, SiP, Ge, and SiGe, having lattice constants that are different from each other and from the fin structure. When SiGe is used, the Ge concentration of the p-type epitaxial layer 338 is higher than the Ge concentration of the semiconductor wiring layer 336. In other embodiments, two or more p-type epitaxial layers are formed. In addition, the number of p-type semiconductor wiring layers 336 is not limited thereto.

[0150] In addition, an alloy layer 320 (corresponding to the alloy layer 81) such as a silicide layer is formed around the p-type epitaxial layer 338. Figure 19 As shown, the p-type epitaxial layer 338 formed on one of the two adjacent semiconductor wiring layers 336 does not contact the p-type epitaxial layer 338 of the other of the two adjacent semiconductor wiring layers 336. The alloy layer 320 fills the space between the two p-type epitaxial layers 338 and physically and electrically connects the two p-type epitaxial layers 338.

[0151] In some embodiments, the thickness T94 of the p-type semiconductor wiring layer 336 is in a range from about 5 nm to about 50 nm, and in other embodiments, in a range from about 10 nm to about 30 nm. In some embodiments, the spacing T95 between two adjacent p-type semiconductor wiring layers 336 is in a range from about 5 nm to about 50 nm, and in other embodiments, in a range from about 10 nm to about 30 nm. In some embodiments, the thickness T96 of the p-type epitaxial layer 338 is in a range from about 1 nm to about 30 nm, and in other embodiments, in a range from about 2 nm to about 7 nm. In some embodiments, the spacing T97 between adjacent p-type epitaxial layers 338 is in a range from about 1 nm to about 10 nm, and in other embodiments, in a range from about 2 nm to about 5 nm.

[0152] Figure 20 An exemplary cross-sectional view (Y-cut) of a source / drain structure of a gate-all-around field effect transistor (GAA FET) according to another embodiment of the present invention is shown. Figure 20 (B) and (C) correspond to Figure 20 In this embodiment, the n-type semiconductor wiring layer 332 and the p-type semiconductor wiring layer 336 are epitaxially formed layers different from the second semiconductor layer 44. For example, in Figure 17B During the operation, the first semiconductor layer 42 and the second semiconductor layer 44 are completely removed from the source / drain regions, and an n-type semiconductor wiring layer 332 and a p-type semiconductor wiring layer 336 are epitaxially formed on the second semiconductor layer 44 extending from the channel region. In some embodiments, the n-type semiconductor wiring layer 332 and the p-type semiconductor wiring layer 336 penetrate the spacer layer 82 by an amount T70 or T72 of about 2 nm to about 10 nm.

[0153] Figure 21A and Figure 21B : is an exemplary cross-sectional view (Y-cut) of a source / drain structure of a gate-all-around field effect transistor (GAA FET) according to another embodiment of the present invention. Figure 20, the n-type semiconductor wiring layer 332 and the p-type semiconductor wiring layer 336 are layers formed epitaxially and are different from the second semiconductor layer 44. Figure 20 Differently, the n-type semiconductor wiring layer 332 of one GAA FET is separated from the n-type semiconductor wiring layer 332 of an adjacent GAA FET and is connected via the n-type epitaxial layer 334. Similarly, the p-type semiconductor wiring layer 336 of one GAA FET is separated from the p-type semiconductor wiring layer 336 of an adjacent GAA FET and is connected via the p-type epitaxial layer 338. In this embodiment, the n-type epitaxial layers 334 are physically separated from each other and are connected via the alloy layer 322, and the p-type epitaxial layers 338 are physically separated from each other and are connected via the alloy layer 320.

[0154] exist Figure 21A In the embodiment, the n-type epitaxial layer 334 and the p-type epitaxial layer 338 have the maximum thickness at their middle portions and Figure 21B In some embodiments, the p-type epitaxial layer 338 has a minimum thickness at its middle portion. In some embodiments, the maximum thickness is in a range from about 10 nm to about 40 nm and the minimum thickness is in a range from about 0.5 nm to about 5 nm. In some embodiments, the angle TH formed by the n-type epitaxial layer or the p-type epitaxial layer and the sidewall spacer 84 is in a range from about 30° to 60°. Figure 21A In the structure shown, the contact area can be increased. Figure 21B In the structure shown, a greater tensile stress can be provided to the channel due to the larger silicide volume.

[0155] In the present invention, the source / drain epitaxial layers are separated but connected by an alloy layer (e.g., a silicide layer), and the alloy layer is wrapped around each epitaxial layer. With this structure, the variation in device performance caused by misalignment between the contact plug and the source / drain structure can be minimized.

[0156] When two epitaxial layers grown above two adjacent fin structures are merged and a metal silicide layer is then formed above the merged epitaxial layer, after forming the contact hole for the plug, metal or metal silicide is formed only within the contact hole and on top of the merged S / D epitaxial layer. The total contact area between the metal silicide and the epitaxial structure is strictly limited or very small. This means that the contact resistance to the source-drain region will be very high. In addition, the epitaxially grown source / drain structure conducts current and enables the current to spread across the entire fin. However, the epitaxially grown source / drain is not as conductive as metal materials. When the epitaxial layers are not merged and the spaces between them are filled with insulating material, similar problems as mentioned above will arise.

[0157] In contrast, in this embodiment, the space between two adjacent source / drain epitaxial layers is completely filled with metal silicide. Accordingly, the total metal silicide / epitaxial layer interface contact area can be maximized by wrapping around the silicide to reduce the overall contact resistance of the transistor; and improved process margins and improved tolerances for several key manufacturing variations are obtained.

[0158] It should be understood that not all advantages have been discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0159] According to one aspect of the present invention, a semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source electrode, and a first drain electrode; a second channel, a second source electrode, and a second drain electrode; and a gate structure disposed above the first channel and the second channel. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source electrode includes a first crystalline semiconductor layer, and the second source electrode includes a second crystalline semiconductor layer. The first source electrode and the second source electrode are connected via an alloy layer made of one or more Group IV elements and one or more transition metal elements. The first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer.

[0160] In the above semiconductor device, a space between the first crystalline semiconductor layer and the second crystalline semiconductor layer is filled with the alloy layer.

[0161] In the above semiconductor device, the first crystalline semiconductor layer is a multilayer of different crystalline semiconductor materials.

[0162] In the above semiconductor device, the field effect transistor is a fin field effect transistor, the fin field effect transistor includes a first fin and a second fin protruding from a semiconductor substrate, and the first crystalline semiconductor layer is a part of the first fin.

[0163] In the above-mentioned semiconductor device, the field effect transistor is a fin field effect transistor, the fin field effect transistor includes a first fin and a second fin protruding from the semiconductor substrate, and the first crystalline semiconductor layer is part of the first fin, and the alloy layer directly covers the first crystalline semiconductor layer.

[0164] In the above-mentioned semiconductor device, wherein: the field effect transistor is a fin field effect transistor, the fin field effect transistor includes a first fin and a second fin protruding from the semiconductor substrate, and the first crystalline semiconductor layer includes one or more layers of different crystalline semiconductor materials formed on a portion of the first fin.

[0165] In the above semiconductor device, wherein: the field effect transistor is a fin field effect transistor, the fin field effect transistor includes a first fin and a second fin protruding from the semiconductor substrate, and the first crystalline semiconductor layer includes one or more layers of different crystalline semiconductor materials formed on a part of the first fin, and the alloy layer directly covers the first crystalline semiconductor layer.

[0166] In the above semiconductor device, wherein, the first channel and the second channel are made of Si, Si x Ge 1-x or Ge, where 0 < x < 1.

[0167] In the above semiconductor device, wherein, the first channel and the second channel are made of Si, Si x Ge 1-x or Ge, where 0 < x < 1, and the first crystalline semiconductor layer includes at least one of Si, SiC, SiP, SiCP, Si x Ge 1-x and Ge, where 0 < x < 1.

[0168] In the above semiconductor device, wherein, the first channel and the second channel are made of Si, Si x Ge 1-x or Ge, where 0 < x < 1, and the first crystalline semiconductor layer includes at least one of Si, SiC, SiP, SiCP, Si x Ge 1-x and Ge, where 0 < x < 1, and the alloy layer is one or more of TiSi, TaSi, NiSi, CoSi, TiSiGe, TaSiGe, NiSiGe and CoSiGe.

[0169] In the above semiconductor device, wherein: the field effect transistor is a fin field effect transistor, the fin field effect transistor includes a first fin and a second fin protruding from the semiconductor substrate, and the first channel and the second channel, the first source and the second source, and the first drain and the second drain protrude from an insulating layer formed on the semiconductor substrate, and voids are provided between the bottom of the alloy layer and the upper surface of the insulating layer.

[0170] In the above semiconductor device, wherein: the field-effect transistor is a fin field-effect transistor, the fin field-effect transistor includes a first fin and a second fin protruding from a semiconductor substrate, and the first channel and the second channel, the first source and the second source, and the first drain and the second drain protrude from an insulating layer formed on the semiconductor substrate, and a void is provided between the bottom of the alloy layer and the upper surface of the insulating layer, wherein: a metal layer is provided on the upper surface of the insulating layer in the void, and the metal layer is made of one or more of Ti, Ta, Ni, and Co.

[0171] In the above semiconductor device, wherein the field-effect transistor further includes a source contact plug in contact with the alloy layer.

[0172] According to another aspect of the present invention, a semiconductor device includes a fin field-effect transistor (Fin FET). The Fin FET includes a substrate; an insulating layer formed on the substrate; a first fin protruding from the substrate, and an upper portion of the first fin protruding from the insulating layer serves as a first channel; a first source and a first drain in contact with the first channel; a second fin protruding from the substrate, and an upper portion of the second fin protruding from the insulating layer serves as a second channel; a second source and a second drain in contact with the second channel; and a gate structure provided above the first channel and the second channel, the gate structure including a gate dielectric layer and a gate electrode layer. The first source includes a first crystalline semiconductor layer made of a material different from that of the first channel. The second source includes a second crystalline semiconductor layer made of a material different from that of the second channel. The first source and the second source are connected by a metal alloy layer. The metal alloy layer is formed by a reaction between a metal and the first source and the second source. The first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer.

[0173] In the above semiconductor device, wherein the space between the first crystalline semiconductor layer and the second crystalline semiconductor layer is filled with the metal alloy layer.

[0174] In the above semiconductor device, wherein the first crystalline semiconductor layer and the second crystalline semiconductor layer are multi-layers of different crystalline semiconductor materials.

[0175] In the above semiconductor device, wherein the metal alloy layer directly covers the first crystalline semiconductor layer and the second crystalline semiconductor layer.

[0176] In the above semiconductor device, wherein: the first channel and the second channel are made of Si, Si x Ge 1-x or Ge, where 0 < x < 1, the first crystalline semiconductor layer includes Si, SiC, SiP, SiCP, Si x Ge 1-xand at least one of Ge, where 0 < x < 1.

[0177] In the above semiconductor device, wherein: the first channel and the second channel are made of Si, Si x Ge 1-x or Ge, where 0 < x < 1, the first crystalline semiconductor layer includes Si, SiC, SiP, SiCP, Si x Ge 1-x and at least one of Ge, where 0 < x < 1, and the metal alloy layer is one or more of TiSi, TaSi, NiSi, CoSi, TiSiGe, TaSiGe, NiSiGe, and CoSiGe.

[0178] According to another aspect of the present invention, in a method of manufacturing a semiconductor device including a field effect transistor (FET), a first FET structure and a second FET structure are formed. The first FET structure has a first channel, a first source, a first drain, and a common gate, and the second FET structure has a second channel, a second source, a second drain, and a common gate. An alloy layer is formed on the first source and the second source. The first source includes a first crystalline semiconductor layer and the second source includes a second crystalline semiconductor layer. The first source and the second source are connected through the alloy layer. The alloy layer is made of one or more Group IV elements and one or more transition metal elements. The first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer.

[0179] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced by the present inventor. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device comprising a field effect transistor (FET), wherein the field effect transistor is a fin field effect transistor, the fin field effect transistor comprising: a first channel, a first source, and a first drain; a second channel, a second source and a second drain; as well as a gate structure, disposed above the first channel and the second channel, the gate structure comprising a gate dielectric layer and a gate electrode layer; A first fin and a second fin protruding from the semiconductor substrate, wherein: The first channel and the second channel, the first source and the second source, and the first drain and the second drain protrude from an insulating layer formed on the semiconductor substrate. The first source includes a first crystalline semiconductor layer and the second source includes a second crystalline semiconductor layer, the first crystalline semiconductor layer including one or more layers of different crystalline semiconductor materials formed on a portion of the first fin, The first source electrode and the second source electrode are connected through an alloy layer made of one or more Group IV elements and one or more transition metal elements and are connected to the alloy layer, a second gap is provided between a bottom of the alloy layer and an upper surface of the insulating layer, the first source electrode and the second source electrode have an undercut, and The first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer, and The alloy layer completely covers the first crystalline semiconductor layer and the second crystalline semiconductor layer, In which, the alloy layer has a middle part located between the first crystalline semiconductor layer and the second crystalline semiconductor layer, the middle part has a first inclined bottom surface and a second inclined bottom surface respectively close to the first crystalline semiconductor layer and the second crystalline semiconductor layer, the first inclined bottom surface and the second inclined bottom surface are conformal to the bottom cuts of the first source and the second source respectively, the lowest point of the top surface of the middle part is higher than the apex of the first fin and the second fin, and one or more first gaps are formed in the middle part of the alloy layer and are closed and surrounded by the alloy layer.

2. The semiconductor device according to claim 1, wherein The cross-sectional shape of the first gap includes rhombus, circle, and ellipse.

3. The semiconductor device according to claim 1, wherein The first crystalline semiconductor layer is a multilayer of different crystalline semiconductor materials.

4. The semiconductor device according to claim 1, wherein: The field effect transistor is a fin field effect transistor, which includes a first fin and a second fin protruding from a semiconductor substrate, and The first crystalline semiconductor layer is part of the first fin.

5. The semiconductor device according to claim 4, wherein The alloy layer directly covers the first crystalline semiconductor layer.

6. The semiconductor device according to claim 1, wherein: The cross-sectional shape of the first gap is irregular.

7. The semiconductor device according to claim 6, wherein The alloy layer directly covers the first crystalline semiconductor layer.

8. The semiconductor device according to claim 1, wherein The first channel and the second channel are made of Si, Si x Ge 1-x or Ge, where 0 <x<1。 9. The semiconductor device according to claim 8, wherein The first crystalline semiconductor layer includes Si, SiC, SiP, SiCP, Si x Ge 1-x and Ge, wherein 0 <x<1。 10. The semiconductor device according to claim 9, wherein The alloy layer is one or more of TiSi, TaSi, NiSi, CoSi, TiSiGe, TaSiGe, NiSiGe and CoSiGe.

11. The semiconductor device according to claim 1 , wherein: The first and second crystalline semiconductor layers are formed of germanium, and the alloy layer is a germanide layer.

12. The semiconductor device according to claim 11, wherein: A metal layer is disposed on the upper surface of the insulating layer in the second gap, and The metal layer is made of one or more of Ti, Ta, Ni and Co, and the alloy layer contacts the metal layer.

13. The semiconductor device according to claim 1, wherein The field effect transistor further includes a source contact plug in contact with the alloy layer.

14. A semiconductor device comprising a fin field effect transistor (Fin FET), the fin field effect transistor comprising: substrate; an insulating layer formed on the substrate; a first fin protruding from the substrate, wherein an upper portion of the first fin protruding from the insulating layer serves as a first channel; a first source electrode and a first drain electrode, contacting the first channel; a second fin protruding from the substrate, wherein an upper portion of the second fin protruding from the insulating layer serves as a second channel; a second source electrode and a second drain electrode, contacting the second channel; as well as A gate structure is provided above the first channel and the second channel, the gate structure comprising a gate dielectric layer and a gate electrode layer, wherein: The first source includes a first crystalline semiconductor layer made of a material different from that of the first channel, The second source includes a second crystalline semiconductor layer made of a material different from that of the second channel, The first source electrode and the second source electrode are connected through a metal alloy layer and connected to the metal alloy layer, a second gap is formed by a bottom of the metal alloy layer and an upper surface of the insulating layer, and the first source electrode and the second source electrode have an undercut, forming the metal alloy layer by a reaction between the metal and the first source electrode and the second source electrode, and The first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer, and The metal alloy layer completely covers the first crystalline semiconductor layer and the second crystalline semiconductor layer, In which, the metal alloy layer has a middle portion located between the first crystalline semiconductor layer and the second crystalline semiconductor layer, the middle portion has a first inclined bottom surface and a second inclined bottom surface extending toward the bottom of the first fin and the second fin, respectively, the first inclined bottom surface and the second inclined bottom surface are conformal to the bottom cuts of the first source and the second source, respectively, the lowest point of the top surface of the middle portion is higher than the apex of the first fin and the second fin, one or more first gaps are formed in the middle portion of the metal alloy layer, and the first gaps are closed and surrounded by the metal alloy layer.

15. The semiconductor device according to claim 14, wherein The cross-sectional shape of the first gap includes rhombus, circle, and ellipse.

16. The semiconductor device according to claim 14, wherein The first crystalline semiconductor layer and the second crystalline semiconductor layer are multiple layers of different crystalline semiconductor materials.

17. The semiconductor device according to claim 14, wherein The metal alloy layer directly covers the first crystalline semiconductor layer and the second crystalline semiconductor layer.

18. The semiconductor device according to claim 14, wherein: The first channel and the second channel are made of Si, Si x Ge 1-x or Ge, where 0 <x<1, The first crystalline semiconductor layer includes Si, SiC, SiP, SiCP, Si x Ge 1-x and Ge, wherein 0 <x<1。 19. The semiconductor device according to claim 18, wherein The metal alloy layer is one or more of TiSi, TaSi, NiSi, CoSi, TiSiGe, TaSiGe, NiSiGe and CoSiGe.

20. A method of manufacturing a semiconductor device including a field effect transistor (FET), the method comprising: forming a first field effect transistor structure and a second field effect transistor structure, wherein the first field effect transistor structure has a first channel protruding from an insulating layer, a first source, a first drain, and a common gate, and the second field effect transistor structure has a second channel protruding from the insulating layer, a second source, a second drain, and the common gate; An alloy layer is formed on the first source electrode and the second source electrode, wherein: The first source includes a first crystalline semiconductor layer and the second source includes a second crystalline semiconductor layer, The first source electrode and the second source electrode are connected through the alloy layer and connected to the alloy layer, a second gap is formed by the bottom of the alloy layer and the upper surface of the insulating layer, and the first source electrode and the second source electrode have an undercut, The alloy layer is made of one or more Group IV elements and one or more transition metal elements, and The first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer, and The alloy layer completely covers the first crystalline semiconductor layer and the second crystalline semiconductor layer, In which, the alloy layer has a middle part located between the first crystalline semiconductor layer and the second crystalline semiconductor layer, the middle part has a first inclined bottom surface and a second inclined bottom surface respectively close to the first crystalline semiconductor layer and the second crystalline semiconductor layer, the first inclined bottom surface and the second inclined bottom surface are respectively conformal to the bottom cuts of the first source and the second source, the lowest point of the top surface of the middle part is higher than the vertices of the first fin and the second fin corresponding to the first source and the second source, one or more first gaps are formed in the middle part of the alloy layer, and the first gaps are closed and surrounded by the alloy layer.

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