Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a conductive structure material layer on the substrate; forming a mask layer on part of the conductive structure material layer; forming a repair film on the sidewall surface of the mask layer, wherein the roughness of the repair film surface is lower than that of the sidewall surface of the mask layer; etching the conductive structure material layer using the mask layer and the repair film as masks to form a plurality of conductive structures on the substrate. Thus, the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits has been continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved. As the size requirements of components become smaller and smaller, the size of the conductive structure connected to the semiconductor device is also getting smaller and smaller.

[0003] However, the performance of existing semiconductor structures still needs to be improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a conductive structure material layer on the substrate; forming a mask layer on a portion of the conductive structure material layer; forming a repair film on the side wall surface of the mask layer, wherein the roughness of the surface of the repair film is lower than the roughness of the side wall surface of the mask layer; etching the conductive structure material layer using the mask layer and the repair film as masks to form a plurality of conductive structures on the substrate.

[0006] Optionally, the method for forming the repair film includes: using an atomic layer deposition process to form an initial repair film on the surface of the mask layer and the surface of the conductive structure material layer; etching the initial repair film using an anisotropic etching process until the initial repair film on the top surface of the mask layer and the surface of the conductive structure material layer is removed to form the repair film.

[0007] Optionally, the method further includes: thinning the exposed sidewalls of the conductive structure.

[0008] Optionally, the method for thinning the exposed sidewall of the conductive structure includes: etching the sidewall surface of the conductive structure by an atomic layer etching process.

[0009] Optionally, the method further includes: after forming the conductive structure, forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is also located on the sidewall surface of the conductive structure.

[0010] Optionally, the substrate has a plurality of discrete fin structures; the method for forming the semiconductor structure also includes: before forming the conductive structure material, forming a first dielectric layer on the substrate, and forming a plurality of gate structures spanning the fin structures in the first dielectric layer, at least one of the plurality of conductive structures is located on the gate structure and connected to the gate structure.

[0011] Optionally, the substrate includes a first region and a second region, the fin structure and the gate structure are located on the first region, the first dielectric layer is located on the first region and the second region, and at least one of the plurality of conductive structures is located on the second region.

[0012] Optionally, the method further includes: in the process of forming the first dielectric layer, forming a buried power rail in the second region and in the first dielectric layer, and the conductive structure on the second region is connected to the buried power rail.

[0013] Optionally, the method for forming the conductive structure material layer includes: forming a conductive opening in the first dielectric layer, the conductive opening exposing the surface of the buried power rail; depositing the material of the conductive structure material layer on the surface of the first dielectric layer, the surface of the gate structure, and in the conductive opening, the surface of the conductive structure material layer being higher than the surface of the first dielectric layer.

[0014] Optionally, the material of the conductive structure includes molybdenum or cobalt.

[0015] Optionally, the material of the repair film includes silicon oxide, silicon nitride or titanium oxide.

[0016] Optionally, the method further includes: forming a buffer layer between the conductive structure and the substrate.

[0017] Optionally, the material of the buffer layer includes Al2O3.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a repair film is formed on the side wall surface of the mask layer, the surface roughness of the repair film is lower than the side wall roughness of the mask layer, and the mask layer and the repair film are used as masks to etch the conductive structure material layer to form a conductive structure. Therefore, the side wall roughness of the mask layer is reduced by the repair film, and the side wall roughness of the mask structure forming the conductive structure is reduced, thereby improving the morphology of the mask structure forming the conductive structure, forming a conductive structure with small side wall roughness and good morphology, so that the conductive structure has small resistance and good performance, thereby improving the performance of the semiconductor structure.

[0020] Furthermore, the material film formed by the atomic layer deposition process is dense and continuous, and has high surface smoothness and low roughness. Since the atomic layer deposition process is used to form the initial repair film, and the initial repair film is etched to form the repair film, the atomic layer deposition process can form a film layer (initial repair film) with dense and continuous material, high surface smoothness and low roughness on the side wall surface of the mask layer, so that after etching the film layer, a repair film with a surface roughness lower than the side wall roughness of the mask layer can be formed to reduce the side wall roughness of the mask structure that forms the conductive structure, thereby improving the performance of the semiconductor structure.

[0021] Furthermore, the atomic layer etching process has high etching accuracy, and the surface of the structure formed after etching is smooth and has low roughness. Since the sidewall surface of the conductive structure is etched by the atomic layer etching process to thin the exposed sidewall of the conductive structure, on the one hand, the maximum line width of the conductive structure can be accurately reduced to better reduce the pattern size and improve the integration of the semiconductor structure. On the other hand, the roughness of the sidewall of the semiconductor structure can be further reduced by the atomic layer etching process to better reduce the resistance of the conductive structure and improve the performance of the conductive structure, thereby further improving the performance of the semiconductor structure.

[0022] Furthermore, the resistivity of molybdenum and cobalt is less affected by the size of the cross-sectional area of ​​the wire, that is, when the cross-sectional area of ​​the wire is very small, the resistivity of molybdenum and cobalt is very small. Since the material of the conductive structure includes molybdenum or cobalt, the conductive structure with a small line width can also maintain a very small resistance, thereby better improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1 to 3 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0024] Figures 4 to 11 It is a structural schematic diagram of each step of a formation process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] As described in the background art, the performance of existing semiconductor structures is relatively poor.

[0026] The reasons why the performance and reliability of semiconductor structures still need to be improved are described in detail below with reference to the accompanying drawings.

[0027] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0028] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0029] Please refer to Figure 1 , providing a substrate 100 having a plurality of fin structures 101 thereon; forming a gate structure 110 across the fin structure 101 on the substrate; and forming a first dielectric layer (not shown) on the surface of the substrate 100 , the surface of the fin structure 101 and the sidewall surface of the gate structure 110 .

[0030] Please refer to Figure 2 , forming a conductive structure material layer 120 on the surface of the first dielectric layer and the surface of the gate structure 110 ; and forming a conductive structure mask layer 130 on the surface of the conductive structure material layer 120 .

[0031] Please refer to Figure 3 , using the conductive structure mask layer 130 as a mask, etching the conductive structure material layer 120 until the gate structure 110 is exposed, thereby forming a conductive structure 121 connected to the gate structure 110; and forming a second dielectric layer 140 on the sidewall surface of the conductive structure 121, the top surface of the gate structure 110, and the surface of the first dielectric layer.

[0032] In the above embodiment, in order to overcome the problem that it is difficult to fill the conductive structure material in a small-sized conductive opening in nodes of smaller and smaller size, a conductive structure material layer 120 is formed in a larger space, and the conductive structure material layer 120 is etched using the conductive structure mask layer 130 as a mask, thereby forming a conductive structure 121 with fewer internal defects in the material.

[0033] However, due to the small size of the conductive structure, the morphology of the photolithography layer formed by the photolithography process is poor, and the side wall roughness of the photolithography layer is high. Therefore, the side wall roughness of the conductive structure mask layer 130 formed according to the photolithography layer is also high, resulting in the defect of the high side wall roughness being transmitted to the conductive structure during the etching process of forming the conductive structure 121, making the side wall roughness of the conductive structure 121 high, resulting in large resistance of the conductive structure 121, and further, poor performance of the semiconductor structure.

[0034] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, by forming a repair film on the side wall surface of the mask layer, and etching the conductive structure material layer using the mask layer and the repair film as a mask, to form a plurality of conductive structures on the substrate, thereby improving the performance of the semiconductor structure.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 4 to 11 It is a structural schematic diagram of each step of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0037] Please refer to Figure 4 , providing a substrate 200.

[0038] The material of the substrate 200 includes semiconductor material.

[0039] In this embodiment, the material of the substrate 200 is silicon.

[0040] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0041] In this embodiment, the substrate 200 has a plurality of separate fin structures 201 .

[0042] In this embodiment, the substrate 200 includes a first region I and a second region II, wherein the fin structure 201 is located on the first region I.

[0043] In other embodiments, the substrate includes only the first region having the fin structure, or includes only the second region not having the fin structure.

[0044] Please continue to refer to Figure 4 , a lower first dielectric layer 211 is formed on the substrate 200 in the first region I and the second region II; and an upper first dielectric layer 212 is formed on the lower first dielectric layer 211 .

[0045] The lower first dielectric layer 211 and the upper first dielectric layer 212 constitute a first dielectric layer (not shown in the figure).

[0046] In this embodiment, the material of the first dielectric layer includes silicon oxide.

[0047] In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH and SiCN.

[0048] In this embodiment, the lower first dielectric layer 211 also covers a portion of the sidewall surface of the fin structure 201 , so that the lower first dielectric layer 211 can electrically insulate adjacent fin structures 201 and the semiconductor device from the substrate 200 .

[0049] In this embodiment, a plurality of gate structures 230 are formed in the first dielectric layer and cross the fin structure 201 .

[0050] Specifically, after the lower first dielectric layer 211 is formed, the gate structure 230 is formed on the lower first dielectric layer 211 on the first region I.

[0051] In this embodiment, the gate structure 230 is a metal gate. Specifically, the gate structure 230 includes: a gate dielectric layer (not shown); a work function layer (not shown) located on the surface of the gate dielectric layer; and a metal gate layer (not shown) located on the surface of the work function layer. The upper first dielectric layer 212 exposes the surface of the metal gate layer.

[0052] The gate dielectric layer includes a high-K dielectric material (K greater than 3.9). The high-K dielectric material includes hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0053] The material of the gate electrode layer includes metal materials, for example, one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0054] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0055] In this embodiment, the method for forming the gate structure 230 includes: forming a plurality of dummy gate structures (not shown) across the fin structure 201 on the lower first dielectric layer 211 of the first region I; after forming the dummy gate structure, forming an upper first dielectric layer 212 on the surface of the lower first dielectric layer 211 and the dummy gate structure, the upper first dielectric layer 212 exposing the surface of the dummy gate structure; after forming the upper first dielectric layer 212, removing the dummy gate structure and forming a plurality of gate openings in the upper first dielectric layer 212; and filling the gate openings with the material of the gate structure 230 to form the gate structure.

[0056] In other embodiments, the material of the gate structure includes polysilicon.

[0057] In this embodiment, before forming the upper first dielectric layer 212 , source-drain structures (not shown) are formed in the fin structure 201 on both sides of the gate structure 230 in a direction perpendicular to the extension direction of the gate structure 230 .

[0058] The method for forming the source-drain structure includes: before forming the upper first dielectric layer 212 , forming source-drain openings (not shown) in the fin structure 201 on both sides of the gate structure 230 ; and forming the source-drain structure in the source-drain openings using an epitaxial growth process.

[0059] In this embodiment, during the process of forming the first dielectric layer, a buried power rail (BPR) 220 is formed in the second region II and in the first dielectric layer.

[0060] Specifically, before forming the upper first dielectric layer 212 and the gate structure 230 , the buried power rail 220 is formed in the lower first dielectric layer 211 and in the second region II.

[0061] In this embodiment, the material of the buried power rail 220 includes ruthenium.

[0062] In this embodiment, after the buried power rail 220 is formed, a buried power rail protection structure 221 is formed on the top surface of the buried power rail 220 .

[0063] The buried power rail protection structure 221 is used, on the one hand, to protect the buried power rail 220 before the subsequent formation of the conductive structure material layer to reduce the damage to the buried power rail 220 caused by the manufacturing process; on the other hand, it provides space for the subsequent formation of a conductive structure connected to the buried power rail 220 on the second area II and performs positioning.

[0064] In this embodiment, the material of the buried power rail protection structure 221 includes silicon nitride.

[0065] Please refer to Figure 5 , a conductive structural material layer 240 is formed on the substrate 200 .

[0066] The conductive structure material layer 240 provides material for subsequently forming a conductive structure.

[0067] Specifically, in this embodiment, before forming the conductive structure material layer 240 , the buried power rail protection structure 221 is removed, and a conductive opening (not shown) is formed in the first dielectric layer on the second region II, wherein the conductive opening exposes the top surface of the buried power rail 220 .

[0068] In this embodiment, the method for forming the conductive structure material layer 240 includes: forming the material of the conductive structure material layer 240 on the surface of the first dielectric layer in the first region I, the surface of the gate structure 230, within the conductive opening, and the surface of the first dielectric layer in the second region II to form the conductive structure material layer 240.

[0069] In this embodiment, the deposition process for forming the conductive structure material layer 240 includes a chemical vapor deposition process or a metal electroplating process.

[0070] In this embodiment, the conductive structure material layer 240 is made of molybdenum.

[0071] In other embodiments, the material of the conductive structural material layer includes cobalt.

[0072] In this embodiment, before forming the conductive structure material layer 240, a buffer material layer (not shown) is formed on the surface of the first dielectric layer in the first region I, the surface of the gate structure 230, in the conductive opening, and on the surface of the first dielectric layer in the second region II.

[0073] The buffer material layer is used to provide material for the subsequent formation of a buffer layer.

[0074] In this embodiment, the material of the buffer material layer includes Al2O3.

[0075] Please refer to Figure 6 , forming a mask layer 250 on a portion of the conductive structure material layer 240 .

[0076] Specifically, in this embodiment, the mask layer 250 is formed on a portion of the gate structure 230 on the first region I and on the buried power rail 220 in the second region II. Thus, a conductive structure connected to the gate structure 230 can be formed on the first region I, and a conductive structure connected to the buried power rail 220 can be formed on the second region II.

[0077] The method for forming the mask layer 250 includes: forming a mask material layer (not shown) on the surface of the conductive structure material layer 240; forming a photoresist layer (not shown) on a portion of the surface of the mask material layer through a photolithography process; using the photoresist layer as a mask, etching the mask material layer until the conductive structure material layer is exposed to form the mask layer 250.

[0078] Since the width of the mask layer 250 is small, a photoresist layer with a small width needs to be formed, resulting in a poor morphology of the photoresist layer formed by the photolithography process and a large sidewall roughness. Therefore, the sidewall roughness of the mask layer 250 formed is large.

[0079] Next, a repair film is formed on the sidewall surface of the mask layer 250, and the roughness of the surface of the repair film is lower than the roughness of the sidewall surface of the mask layer 250. For the specific steps of forming the repair film, please refer to Figures 7 and 8 .

[0080] Please refer to Figure 7 An initial repair film 261 is formed on the surface of the mask layer 250 and the surface of the conductive structure material layer 240 by using an atomic layer deposition process.

[0081] The initial repair film 261 provides material for the subsequent formation of a repair film.

[0082] In this embodiment, the material of the initial repair film 261 includes silicon oxide, silicon nitride or titanium oxide.

[0083] Please refer to Figure 8 The initial repair film 261 is etched using an anisotropic etching process until the initial repair film 261 on the top surface of the mask layer 250 and the surface of the conductive structure material layer 240 is removed to form a repair film 260 .

[0084] The repair film 260 is located on the sidewall surface of the mask layer 250 , and the surface roughness of the repair film 260 is lower than the roughness of the sidewall surface of the mask layer 250 .

[0085] The material film formed by the atomic layer deposition process is dense and continuous, and has high surface smoothness and low roughness. Since the initial repair film 261 is formed by the atomic layer deposition process, and the initial repair film 261 is etched to form the repair film 260, the atomic layer deposition process can form a film layer (initial repair film 261) with dense and continuous materials, high surface smoothness and low roughness on the side wall surface of the mask layer 250, so that after etching the film layer, a repair film 260 with a surface roughness lower than the side wall roughness of the mask layer 250 can be formed, so as to reduce the side wall roughness of the mask structure forming the conductive structure, thereby improving the performance of the semiconductor structure.

[0086] In this embodiment, the material of the repair film 260 includes silicon oxide, silicon nitride or titanium oxide.

[0087] Please refer to Fig. 9 The conductive structure material layer 240 is etched using the mask layer 250 and the repair film 260 as masks to form a plurality of conductive structures 241 on the substrate 200 .

[0088] Since a repair film 260 is formed on the side wall surface of the mask layer 250, the surface roughness of the repair film 260 is lower than the side wall roughness of the mask layer 250, and the conductive structure material layer 240 is etched using the mask layer 250 and the repair film 260 as masks to form a conductive structure 241. Therefore, the side wall roughness of the mask layer 250 is improved by the repair film 260, and the side wall roughness of the mask structure forming the conductive structure 241 is reduced, thereby improving the morphology of the mask structure forming the conductive structure 241, forming a conductive structure 241 with small side wall roughness and good morphology, so that the conductive structure 241 has small resistance and good performance, thereby improving the performance of the semiconductor structure.

[0089] In this embodiment, at least one of the plurality of conductive structures 241 is located on the gate structure 230 and connected to the gate structure 230 .

[0090] In this embodiment, at least one of the plurality of conductive structures 241 is located on the second region II. Furthermore, the conductive structure 241 on the second region II is connected to the buried power rail 220 .

[0091] In this embodiment, the material of the conductive structure 241 includes molybdenum.

[0092] The resistivity of molybdenum is less affected by the size of the cross-sectional area of ​​the wire, that is, when the cross-sectional area of ​​the wire is very small, the resistivity of molybdenum is very small. Since the material of the conductive structure 241 includes molybdenum, the conductive structure 241 with a small line width can also maintain a very small resistance, thereby better improving the performance of the semiconductor structure.

[0093] In other embodiments, the material of the conductive structure includes cobalt.

[0094] The resistivity of cobalt is less affected by the size of the cross-sectional area of ​​the wire, that is, when the cross-sectional area of ​​the wire is very small, the resistivity of cobalt is very small. Since the material of the conductive structure includes molybdenum or cobalt, the conductive structure with a small line width can also maintain a very small resistance, thereby better improving the performance of the semiconductor structure.

[0095] In this embodiment, the process of etching the conductive structure material layer 240 includes a dry etching process or a wet etching process.

[0096] In this embodiment, during the process of etching the conductive structure material layer 240 , the buffer material layer is also etched, so that a buffer layer (not shown) is formed between the conductive structure 241 and the substrate 200 .

[0097] In this embodiment, the material of the buffer layer includes Al2O3.

[0098] Please refer to Fig.10 , the sidewalls of the exposed conductive structure 241 are thinned.

[0099] By thinning the sidewalls of the exposed conductive structure 241 , the line width of the conductive structure 241 can be reduced, thereby improving the integration of the semiconductor structure.

[0100] In this embodiment, the method for thinning the sidewall of the exposed conductive structure 241 includes: etching the sidewall surface of the conductive structure 241 by using an atomic layer etching process.

[0101] The atomic layer etching process has high etching accuracy, and the surface of the structure formed after etching is smooth and has low roughness. Since the atomic layer etching process is used to etch the side wall surface of the conductive structure 241 to thin the exposed side wall of the conductive structure 241, on the one hand, the line width of the conductive structure 241 can be accurately reduced to better reduce the graphic size and improve the integration of the semiconductor structure. On the other hand, the atomic layer etching process can further reduce the roughness of the side wall of the semiconductor structure to better reduce the conductive structure 241 and improve the performance of the conductive structure 241, thereby further improving the performance of the semiconductor structure.

[0102] In this embodiment, during the process of etching the sidewall surface of the conductive structure 241 , the repair film 260 is consumed by the etching process, and thus the repair film 260 is removed.

[0103] In this embodiment, after the sidewalls of the exposed conductive structure 241 are thinned, the mask layer 250 is removed. Thus, the mask layer 250 can protect the top surface of the conductive structure 241 during the thinning process.

[0104] Please refer to Fig.11 After forming the conductive structure 241 , an interlayer dielectric layer 270 is formed on the substrate 200 , and the interlayer dielectric layer 270 is also located on the sidewall surface of the conductive structure 241 .

[0105] In this embodiment, the process of forming the interlayer dielectric layer includes a spin coating process or a deposition process. The deposition process is, for example, a chemical vapor deposition process, a fluid chemical vapor deposition process, or a physical vapor deposition process.

[0106] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A first dielectric layer is formed on the substrate; the substrate includes a first region and a second region; The first dielectric layer is located on the first region and the second region; forming a conductive structural material layer on the substrate; forming a mask layer on a portion of the conductive structure material layer; forming a repair film on the side wall surface of the mask layer, wherein the roughness of the surface of the repair film is lower than the roughness of the side wall surface of the mask layer; The conductive structure material layer is etched using the mask layer and the repair film as masks to form a plurality of conductive structures on the substrate; at least one of the plurality of conductive structures is located on the second region; wherein, in the process of forming the first dielectric layer, an embedded power rail is formed in the second region and in the first dielectric layer, and the conductive structure on the second region is connected to the embedded power rail.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the repair film includes: using an atomic layer deposition process to form an initial repair film on the surface of the mask layer and the surface of the conductive structure material layer; etching the initial repair film using an anisotropic etching process until the initial repair film on the top surface of the mask layer and the surface of the conductive structure material layer is removed to form the repair film.

3. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: The exposed sidewalls of the conductive structure are thinned.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method for thinning the exposed sidewall of the conductive structure includes: etching the sidewall surface of the conductive structure by using an atomic layer etching process.

5. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After the conductive structure is formed, an interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer is also located on the sidewall surface of the conductive structure.

6. The method for forming a semiconductor structure according to claim 1, wherein: The substrate has a plurality of mutually discrete fin structures; the method for forming the semiconductor structure also includes: before forming the conductive structure material, forming a first dielectric layer on the substrate, and forming a plurality of gate structures across the fin structures in the first dielectric layer, at least one of the plurality of conductive structures is located on the gate structure and connected to the gate structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: The fin structure and the gate structure are located on the first region.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the conductive structure material layer includes: forming a conductive opening in the first dielectric layer, wherein the conductive opening exposes the surface of the buried power rail; depositing the material of the conductive structure material layer on the surface of the first dielectric layer, the surface of the gate structure, and in the conductive opening, wherein the surface of the conductive structure material layer is higher than the surface of the first dielectric layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the conductive structure includes molybdenum or cobalt.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the repair film includes silicon oxide, silicon nitride or titanium oxide.

11. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A buffer layer is formed between the conductive structure and the substrate.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the buffer layer includes Al2O3.

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