Chip internal power supply circuit and control method thereof

Abstract

The present invention provides an internal chip power supply circuit and a control method thereof. The internal chip power supply circuit includes: a power supply module, a decision circuit, and a logic link; the power supply module receives a first input voltage, the logic link receives a second input voltage, the decision circuit outputs a decision result, the power supply module outputs the first input voltage as the output voltage of the internal chip power supply circuit according to a first enable signal, and the logic link outputs the second input voltage or the power supply voltage as the output voltage of the internal chip power supply circuit according to a second enable signal and the decision result. By switching the output voltage of the internal chip power supply circuit, the present invention reduces the scale of the internal chip power supply circuit and reduces power consumption while ensuring the accuracy of the provided power supply.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip internal power supply circuit and a control method thereof. Background Art

[0002] Currently, there are two ways to power internal chip circuits: one uses a low-dropout linear regulator (LDO) to power the circuits; the other uses an external power supply connected to the chip via an on-chip input or output port. Because the external power supply voltage cannot exceed the withstand voltage of the chip's internal loads, the power supply range is limited and compatibility is poor. While LDOs offer high-precision power supply voltages, they require larger circuits and consume high power.

[0003] Therefore, the present invention proposes an internal chip power supply circuit and a control method thereof, which can reduce the scale of the internal chip power supply circuit while ensuring the accuracy of the provided power supply. Summary of the Invention

[0004] The present invention provides an internal power supply circuit of a chip and a control method thereof, which can reduce the scale of the internal power supply circuit of the chip and reduce power consumption while ensuring the accuracy of the provided power supply.

[0005] In a first aspect, the present invention provides an internal chip power supply circuit, comprising: a power supply module, a judgment circuit and a logic link; the power supply module receives a first input voltage, and the logic link receives a second input voltage; the power supply module is electrically connected to the logic link, and the logic link is also electrically connected to the judgment circuit, and the judgment circuit outputs a judgment result; the power supply module receives a first enable signal, and outputs the first input voltage according to the first enable signal as the output voltage of the internal chip power supply circuit; the logic link receives a second enable signal and the judgment result, and outputs the second input voltage or the power supply voltage according to the second enable signal and the judgment result as the output voltage of the internal chip power supply circuit.

[0006] Its beneficial effects are: the present invention reduces the scale of the internal power supply circuit of the chip by virtue of the internal power supply circuit of the chip including a power supply module, a judgment circuit and a logic link; the output voltage of the internal power supply circuit of the chip can be switched according to the first enable signal, the second enable signal and the judgment result to reduce power consumption.

[0007] Further optionally, the decision circuit includes: a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor and a first current source circuit; the source of the first P-type transistor receives the power supply voltage, the gate of the first P-type transistor is connected to the inverted signal of the second enable signal, the source of the second P-type transistor is connected to the source of the third P-type transistor, and the drain of the first P-type transistor is connected to the source of the second P-type transistor and the source of the third P-type transistor; the gate of the second P-type transistor is connected to the control voltage, and the drain of the second P-type transistor is connected to the first The drain of the N-type transistor; the gate of the third P-type transistor is connected to the control voltage, and the drain of the third P-type transistor is connected to the drain of the second N-type transistor; the control voltage is used to make the second P-type transistor operate in the saturation region, and the third P-type transistor operate in the linear region; the gate of the first N-type transistor receives the second enable signal, and the source of the first N-type transistor is connected to the output end of the first current source circuit; the gate of the second N-type transistor receives the second enable signal, the source of the second N-type transistor is connected to the input end of the first current source circuit, and the output end of the first current source circuit is grounded.

[0008] Still further optionally, the logical link includes: a first switch and a second switch; the first switch is electrically connected to the second switch.

[0009] Further optionally, the power supply module includes: a third N-type transistor, a fourth N-type transistor, a fourth P-type transistor, a fifth P-type transistor, a second current source circuit, a third current source circuit, a fourth current source circuit, and a third switch; the gate of the third N-type transistor is connected to the first input voltage, the drain of the third N-type transistor is connected to the power supply voltage, the source of the third N-type transistor is connected to the input end of the second current source circuit, and the output end of the second current source circuit is grounded; the input end of the third current source circuit is connected to the power supply voltage, the output end of the third current source circuit is connected to the drain of the fourth N-type transistor, the source of the fourth N-type transistor is connected to the input end of the second current source circuit, and the gate of the fourth N-type transistor is connected to the source of the fourth P-type transistor; the drain of the fourth P-type transistor is connected to the input end of the fourth current source circuit, the output end of the fourth current source circuit is grounded, the gate of the fourth P-type transistor is connected to the gate of the fifth P-type transistor, the drain of the fifth P-type transistor is grounded, the source of the fifth P-type transistor is electrically connected to the third switch, and the third switch is controlled by the first enable signal.

[0010] Further optionally, the internal power supply circuit of the chip includes: the logic link electrically connected to the drain of the third P-type transistor and the drain of the second N-type transistor; and the third switch electrically connected to the logic link.

[0011] Optionally, the first switch, the second switch and the third switch are MOS transistor switch circuits or transmission gate circuits.

[0012] In a second aspect, the present invention provides a method for controlling an internal chip power supply circuit, which is applied to the internal chip power supply circuit as described in any one of the first aspects, comprising: when the power supply module receives the first enable signal, the internal chip power supply circuit outputs the first input voltage; when the logic link receives the second enable signal and the judgment result, the internal chip power supply circuit outputs the second input voltage or the power supply voltage. The beneficial effect is that the present invention controls the internal chip power supply circuit to output the first input voltage, the second input voltage, or the power supply voltage through the first enable signal, the second enable signal, and the judgment result, thereby avoiding resource waste and reducing power consumption.

[0013] Optionally, when the power supply module receives the first enable signal, the internal power supply circuit of the chip outputs the first input voltage; when the logic link receives the second enable signal and the judgment result, the internal power supply circuit of the chip outputs the second input voltage or the power supply voltage, including: when the third switch receives the first enable signal, the third switch is closed, the first switch and the second switch are disconnected, and the internal power supply circuit of the chip outputs the first input voltage; when the first switch and the second switch receive the second enable signal and the judgment result, the third switch is disconnected, and the internal power supply circuit of the chip outputs the second input voltage or the power supply voltage.

[0014] Further optionally, when the first switch and the second switch receive the second enable signal and the judgment result, the third switch is disconnected, and the internal chip power supply circuit outputs the second input voltage or the power supply voltage, including: when the first switch and the second switch receive the second enable signal and the difference between the first current and the second current is greater than a preset threshold, the third switch is disconnected, the first switch is disconnected, the second switch is closed, and the internal chip power supply circuit outputs the second input voltage; when the first switch and the second switch receive the second enable signal and the difference between the first current and the second current is less than or equal to the preset threshold, the third switch is disconnected, the first switch is closed, the second switch is disconnected, and the internal chip power supply circuit outputs the power supply voltage; the first current is the current flowing through the second P-type transistor, and the second current is the current flowing through the third P-type transistor. The beneficial effect is that when the power supply voltage is unstable, it is easy to cause the internal chip power supply circuit to operate abnormally or generate large leakage. By disconnecting the path of the logic link that inputs the second input voltage to the chip, the internal chip power supply circuit is maintained in a low power consumption state. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of an embodiment of an internal chip power supply circuit provided by the present invention;

[0016] Figure 2 A schematic diagram of another embodiment of an internal chip power supply circuit provided by the present invention;

[0017] Figure 3 This is a flow chart of an embodiment of a method for controlling a power supply circuit inside a chip provided by the present invention. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and claims of the present application, the singular expressions "a", "the", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0019] References to "one embodiment" or "some embodiments" etc. described in this specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in one or more embodiments of the present application. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in another way. The term "connected" includes direct and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0020] In the embodiments of this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0021] The present invention provides a chip internal power supply circuit, such as Figure 1As shown, the chip comprises a power supply module 101, a logic link 102, and a decision circuit 201. The decision circuit 201 includes a control voltage input terminal 2011, which is connected to a control voltage. The power supply module 101 receives a first enable signal through a first signal input port 1012, and based on the first enable signal, uses a first input voltage as the output voltage of the chip's internal power supply circuit, and outputs the voltage through an output port 103. The first input voltage is a voltage external to the chip input to the power supply module 101 through the first input port 1011. The logic link 102 receives a second enable signal and a decision result of the decision circuit 201 through a second signal input port 1022, and based on the second enable signal and the decision result, uses a second input voltage or a power supply voltage as the output voltage of the chip's internal power supply circuit, and outputs the voltage through the output port 103. The second input voltage is a voltage external to the chip input to the logic link through the second input port 1021. The first signal input port 1012 can be a write enable signal input port, or an enable signal input port for determining the working state of the chip's internal power supply circuit; the second signal input port can be a read enable signal input port, or an enable signal input port for determining the working state of the chip's internal power supply circuit. The power supply module 101, the logic link 102, and the decision circuit 201 are all connected to a power supply to obtain the power supply voltage (Volt Current Condenser, VCC). Figure 1 The voltage sources of the power supply module and the logic link described in any embodiment of the present application may not be limited.

[0022] In this embodiment, the first input voltage, the second input voltage, or the power supply voltage is used as the output voltage of the internal chip power supply circuit, and the output voltage of the internal chip power supply circuit can be switched according to the first enable signal, the second enable signal, and the judgment result. That is, the internal chip power supply circuit can switch the output voltage according to different operating states and the judgment result of the judgment circuit. The first input voltage and the second input voltage can be the same or different; the first input voltage obtained by the power supply module each time can be the same or different; similarly, the second input voltage obtained by the logic link each time can be the same or different. The specific situation is designed according to actual needs.

[0023] Optionally, the current source circuit mentioned in this application is a current mirror circuit.

[0024] In order to describe the contents described in this patent application in more detail, Figure 2 FIG. 1 is a schematic diagram illustrating another embodiment of a chip internal power supply circuit. Figure 2 As shown, the internal power supply circuit of the chip includes: a power supply module, a logic link and a decision circuit.

[0025] The decision circuit includes: a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, a first N-type transistor N1, a second N-type transistor N2 and a first current source circuit D1; the source of the first P-type transistor P1 receives the power supply voltage VCC, and the gate of the first P-type transistor P1 receives the inverted signal Read of the second enable signal EN_N, the source of the second P-type transistor P2 is connected to the source of the third P-type transistor P3, and the drain of the first P-type transistor P1 is connected to the source of the second P-type transistor P2 and the source of the third P-type transistor P3; the gate of the second P-type transistor P2 is connected to the control voltage VREF, and the drain of the second P-type transistor P2 is connected to the drain of the first N-type transistor N1; the gate of the third P-type transistor P3 is connected to the control voltage VREF, and the drain of the third P-type transistor P3 is connected to the drain of the second N-type transistor N2; the control voltage VREF is used to make the second P-type transistor P2 operate in the saturation region and the third P-type transistor P3 operate in the linear region; the gate of the first N-type transistor N1 receives the second enable signal Read EN, the source of the first N-type transistor N1 is connected to the output end of the first current source circuit D1; the gate of the second N-type transistor N2 receives the second enable signal Read EN, the source of the second N-type transistor N2 is connected to the input end of the first current source circuit D1, and the output end of the first current source circuit D1 is grounded.

[0026] The logic link includes: a first switch S1 and a second switch S2; the first switch S1 is electrically connected to the second switch S2, and the logic link receives the power supply voltage VCC and the second input voltage Vin2.

[0027] The power supply module includes: a third N-type transistor N3, a fourth N-type transistor N4, a fourth P-type transistor P4, a fifth P-type transistor P5, a second current source circuit D2, a third current source circuit D3, a fourth current source circuit D4, and a third switch S3; the gate of the third N-type transistor N3 is connected to the first input voltage Vin1, the drain of the third N-type transistor N3 is connected to the power supply voltage VCC, the source of the third N-type transistor N3 is connected to the input end of the second current source circuit D2, and the output end of the second current source circuit D2 is grounded; the input end of the third current source circuit D3 is connected to the power supply voltage VCC, and the third current source circuit D 3 is connected to the drain of the fourth N-type transistor N4, the source of the fourth N-type transistor N4 is connected to the input of the second current source circuit D2, and the gate of the fourth N-type transistor N4 is connected to the source of the fourth P-type transistor P4; the drain of the fourth P-type transistor P4 is connected to the input of the fourth current source circuit D4, the output of the fourth current source circuit D4 is grounded, the gate of the fourth P-type transistor D4 is connected to the gate of the fifth P-type transistor P5, the drain of the fifth P-type transistor P5 is grounded, and the source of the fifth P-type transistor P5 is electrically connected to the third switch S3, and the third switch S3 is controlled by the first enable signal Prg EN.

[0028] The logic link is electrically connected to the drain of the third P-type transistor P3 and the drain of the second N-type transistor N2; the third switch S3 is electrically connected to the logic link.

[0029] The first switch S1 , the second switch S2 , and the third switch S3 are MOS transistor switch circuits or transmission gate circuits.

[0030] Figure 2 The working principle of the chip internal power supply circuit shown is:

[0031] When the third switch obtains the first enable signal, the internal power supply circuit of the chip outputs the first input voltage Vin1; when the first switch and the second switch obtain the second enable signal and the judgment result, the internal power supply circuit of the chip outputs the second input voltage Vin2 or the power supply voltage VCC.

[0032] When the power supply voltage VCC is stable, the current flowing through the first P-type transistor P1 in the decision circuit is I, the current flowing through the second P-type transistor P2 is I1, and the current flowing through the third P-type transistor P3 is I2. The current source provided to the first P-type transistor P1 comes from outside the decision circuit or from a circuit source circuit between the first P-type transistor P1 and the power supply VCC ( Figure 2(not shown). The value of I1-I2 is greater than a preset threshold. The gate of the first P-type transistor P1 is connected to the inverted signal Read EN_N of the second enable signal. The gate voltages of the second P-type transistor P2 and the third P-type transistor P3 are set to a control voltage VREF. The control voltage VREF is used to operate the second P-type transistor P2 in a saturation region and the third P-type transistor P3 in a linear region.

[0033] When the power supply voltage VCC is unstable, i.e., when it drops, the first P-type transistor P1 operates in the linear region, causing I to decrease. Consequently, the current I1 flowing through the second P-type transistor P2 decreases, and the current I2 flowing through the third P-type transistor P3 also decreases. Because the operating region of the second P-type transistor P2 gradually transitions from the saturation region to the linear region, and the third P-type transistor P3 is connected to the first current source circuit D1 via the second N-type transistor N2, the current I1 flowing through the second P-type transistor P2 decreases faster than the current I2 flowing through the third P-type transistor P3, causing the value of I1-I2 to gradually decrease. When the value of I1-I2 is less than or equal to the preset threshold, the second switch S2 opens and the first switch S1 closes, causing the internal chip power supply circuit to output the power supply voltage VCC. This operation maintains the internal chip power supply circuit in a low-power hold state, and the "read" operation resumes normally the next moment after the power supply voltage VCC stabilizes.

[0034] Based on the chip internal power supply circuit provided in the above embodiment, the embodiment of the present application also provides a control method for the chip internal power supply circuit, the process of which is as follows: Figure 3 As shown, including:

[0035] S301: When the power supply module receives the first enable signal, the internal power supply circuit of the chip outputs the first input voltage;

[0036] S302: When the logic link receives the second enable signal and the judgment result, the internal power supply circuit of the chip outputs the second input voltage or the power supply voltage.

[0037] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A chip internal power supply circuit, characterized in that: include: Power supply module, decision circuit and logic link; The power supply module receives a first input voltage, and the logic link receives a second input voltage; The power supply module is electrically connected to the logic link, and the logic link is also electrically connected to the decision circuit, and the decision circuit outputs a decision result; The power supply module receives a first enable signal and outputs the first input voltage according to the first enable signal as an output voltage of an internal power supply circuit of the chip; The logic link receives the second enable signal and the judgment result, and outputs the second input voltage or the power supply voltage according to the second enable signal and the judgment result, as the output voltage of the internal power supply circuit of the chip; Wherein, the decision circuit includes: a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor and a first current source circuit; The source of the first P-type transistor receives the power supply voltage, the gate of the first P-type transistor receives the inverted signal of the second enable signal, the source of the second P-type transistor is connected to the source of the third P-type transistor, and the drain of the first P-type transistor is connected to the source of the second P-type transistor and the source of the third P-type transistor; The gate of the second P-type transistor is connected to a control voltage, and the drain of the second P-type transistor is connected to the drain of the first N-type transistor; The gate of the third P-type transistor is connected to the control voltage, and the drain of the third P-type transistor is connected to the drain of the second N-type transistor; the control voltage is used to make the second P-type transistor operate in a saturation region and the third P-type transistor operate in a linear region; The gate of the first N-type transistor receives the second enable signal, and the source of the first N-type transistor is connected to the output end of the first current source circuit; A gate of the second N-type transistor receives the second enable signal, a source of the second N-type transistor is connected to an input end of the first current source circuit, and an output end of the first current source circuit is grounded.

2. The chip internal power supply circuit according to claim 1, characterized in that: The logical link includes: a first switch and a second switch; the first switch is electrically connected to the second switch.

3. The chip internal power supply circuit according to claim 2, characterized in that: The power supply module includes: a third N-type transistor, a fourth N-type transistor, a fourth P-type transistor, a fifth P-type transistor, a second current source circuit, a third current source circuit, a fourth current source circuit, and a third switch; The gate of the third N-type transistor is connected to the first input voltage, the drain of the third N-type transistor is connected to the power supply voltage, the source of the third N-type transistor is connected to the input end of the second current source circuit, and the output end of the second current source circuit is grounded; The input end of the third current source circuit is connected to the power supply voltage, the output end of the third current source circuit is connected to the drain of the fourth N-type transistor, the source of the fourth N-type transistor is connected to the input end of the second current source circuit, and the gate of the fourth N-type transistor is connected to the source of the fourth P-type transistor; The drain of the fourth P-type transistor is connected to the input end of the fourth current source circuit, the output end of the fourth current source circuit is grounded, the gate of the fourth P-type transistor is connected to the gate of the fifth P-type transistor, the drain of the fifth P-type transistor is grounded, the source of the fifth P-type transistor is electrically connected to the third switch, and the third switch is controlled by the first enable signal.

4. The chip internal power supply circuit according to claim 3, characterized in that: include: The logic link is electrically connected to the drain of the third P-type transistor and the drain of the second N-type transistor; The third switch is electrically connected to the logic link.

5. The chip internal power supply circuit according to claim 4, characterized in that: The first switch, the second switch and the third switch are MOS transistor switch circuits or transmission gate circuits.

6. A method for controlling a power supply circuit inside a chip, characterized in that: The chip internal power supply circuit according to any one of claims 1 to 5, comprising: When the power supply module receives the first enable signal, the internal power supply circuit of the chip outputs the first input voltage; When the logic link receives the second enable signal and the judgment result, the internal power supply circuit of the chip outputs the second input voltage or the power supply voltage.

7. The method for controlling the internal power supply circuit of a chip according to claim 6, wherein: When the power supply module receives the first enable signal, the internal power supply circuit of the chip outputs the first input voltage; When the logic link receives the second enable signal and the judgment result, the internal power supply circuit of the chip outputs the second input voltage or the power supply voltage, including: When the third switch receives the first enable signal, the third switch is closed, the first switch and the second switch are opened, and the internal power supply circuit of the chip outputs the first input voltage; When the first switch and the second switch receive the second enable signal and the judgment result, the third switch is turned off, and the internal power supply circuit of the chip outputs the second input voltage or the power supply voltage.

8. The method for controlling the internal power supply circuit of a chip according to claim 7, wherein: When the first switch and the second switch receive the second enable signal and the judgment result, the third switch is turned off, and the internal power supply circuit of the chip outputs the second input voltage or the power supply voltage, including: When the first switch and the second switch receive the second enable signal and the difference between the first current and the second current is greater than a preset threshold, the third switch is opened, the first switch is opened, the second switch is closed, and the internal power supply circuit of the chip outputs the second input voltage; When the first switch and the second switch receive the second enable signal and the difference between the first current and the second current is less than or equal to a preset threshold, the third switch is opened, the first switch is closed, the second switch is opened, and the internal power supply circuit of the chip outputs the power supply voltage; The first current is a current flowing through the second P-type transistor, and the second current is a current flowing through the third P-type transistor.

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