Light detection device

Abstract

The present invention relates to a light detection device. The light detection device may include: a unit pixel, the unit pixel includes: a first pixel, including a first photoelectric conversion element and a first transfer transistor; a second pixel, including a second photoelectric conversion element and a second transfer transistor; the first pixel and the second pixel are connected to a reset transistor and an amplifying transistor; a pixel driving control unit, including a control timing table storage unit, the control timing table storage unit stores a plurality of control timing tables; the plurality of control timing tables include: a first control timing table for exposure control of the first pixel; a second control timing table for exposure control of the second pixel; the driving control unit controls the exposure of the first pixel based on the first control timing table, and controls the exposure of the second pixel based on the second control timing table, wherein the exposure start time and the exposure end time in the exposure of the first pixel are different from the exposure start time and the exposure end time in the exposure of the second pixel.

Description

[0001] This application is a divisional application of a patent application with application number 201880016205.5, whose application date is March 30, 2018 and invention name is “Solid-state imaging device, control method of solid-state imaging device, and electronic device”. Technical Field

[0002] The present disclosure relates to a solid-state imaging device, a control method for the solid-state imaging device, and an electronic device, and in particular to a solid-state imaging device, a control method for the solid-state imaging device, and an electronic device that can appropriately expand the dynamic range to reduce motion distortion (motion artifacts) for a subject moving at high speed or a subject having a large brightness difference between light and dark. Background Art

[0003] Conventionally, for example, when the exposure time is shortened in order to expand the dynamic range of a subject moving at high speed in a vehicle-mounted camera, there are some situations in which the signal is saturated during the lighting period of the traffic signal, and during the lighting period of the traffic signal, the color of the traffic signal cannot be visually identified or the signal cannot be sampled, or both cannot be performed.

[0004] Therefore, as a technique for expanding the dynamic range, a method of performing imaging with a long exposure time and imaging with a short exposure time multiple times and generating a composite image in a subsequent circuit has been proposed (see Patent Document 1).

[0005] With such a configuration, the dynamic range can be further expanded by combining an image captured with a long exposure time and an image captured with a short exposure time.

[0006] [Citation List]

[0007] [Patent Document]

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-154982 Summary of the invention

[0009] [Problems to be Solved by the Invention]

[0010] However, in the technology described in Patent Document 1, exposure time control is performed in units of rows, so rows that capture subjects with high illumination without saturation and rows that capture subjects with low illumination with high sensitivity are arranged alternately. Therefore, there is a possibility that a high dynamic range cannot be obtained in the entire area.

[0011] Furthermore, since all short exposure times are time-shared, motion artifacts are more likely to occur in a subject with high illuminance, and there is a possibility that a subject in a non-exposure period cannot be captured.

[0012] Furthermore, there is a possibility that the amount of memory to be stored increases each time a short-second exposure image is generated within the accumulation period.

[0013] The present disclosure has been made in view of such circumstances, and in particular, can appropriately expand the dynamic range to reduce motion distortion (motion artifacts) for a subject moving at high speed or a subject having a large brightness difference between light and dark.

[0014] [Solution to the problem]

[0015] According to one aspect of the present disclosure, a solid-state imaging device is a solid-state imaging device comprising: a pixel array unit, the pixel array unit comprising a plurality of pixels; and a pixel drive control unit, the pixel drive control unit being configured to control the exposure of at least a portion of the plurality of pixels separately in units of pixels.

[0016] The pixel driving control unit may be configured to control the exposure start timing and the exposure end timing of the plurality of pixels in units of pixels.

[0017] The pixel driving control unit may be configured to control a reset timing, a readout timing, the exposure start timing, and the exposure end timing in the exposure of the plurality of pixels, respectively, in units of pixels.

[0018] The pixel driving control unit may be configured to control the number of exposure periods per exposure unit time in the exposure of the plurality of pixels in units of pixels.

[0019] When the number of exposure periods in the exposure unit time in the exposure of the plurality of pixels is controlled in units of pixels, the pixel driving control unit may control the exposure periods at equal time intervals in the exposure unit time.

[0020] In the case where the exposure period in the exposure of the plurality of pixels is a plurality of times, each time the exposure is completed, the analog-to-digital converted pixel signal output from the pixel may be shift-added to the immediately preceding pixel signal.

[0021] The pixel drive control unit may be configured to control an exposure start timing and an exposure end timing in exposure of the plurality of pixels in units of a predetermined number of pixels.

[0022] The pixel drive control can include a control timing table storage unit, which stores a plurality of control timing tables, each of which includes control information for controlling the exposure of the plurality of pixels separately in units of pixels, and the pixel drive control unit controls the exposure of the plurality of pixels separately in units of pixels based on the control information of the control timing tables.

[0023] The pixel driving control unit may be caused to switch the control timing table stored in the control timing table storage unit at predetermined time intervals.

[0024] The pixel driving control unit may be caused to switch the control timing table stored in the control timing table storage unit every a predetermined number of frames.

[0025] It may further include an operation unit configured to receive a user's operation and output the received operation signal, and may enable the pixel drive control unit to switch the control timing table stored in the control timing table storage unit according to the operation signal from the operation unit.

[0026] A control method of a solid-state imaging device according to one aspect of the present disclosure is a control method of a solid-state imaging device, the method including controlling exposure of at least a portion of a plurality of pixels of a pixel array unit including the plurality of pixels, respectively, in units of pixels.

[0027] An electronic device according to one aspect of the present disclosure is an electronic device comprising: a pixel array unit, the pixel array unit comprising a plurality of pixels; and a pixel drive control unit configured to control the exposure of at least a portion of the plurality of pixels in units of pixels.

[0028] According to one aspect of the present disclosure, a pixel array unit is included. The pixel array unit includes a plurality of pixels, and exposure of at least a portion of the plurality of pixels is controlled separately in units of pixels.

[0029] [Effects of the invention]

[0030] According to one aspect of the present disclosure, it is possible to appropriately expand the dynamic range to reduce motion distortion (motion artifact) for a subject moving at high speed or a subject having a large brightness difference between bright and dark. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a diagram showing a schematic configuration of a solid-state imaging device according to the present disclosure.

[0032] Figure 2is a block diagram showing a detailed configuration example of a pixel.

[0033] Figure 3 is a block diagram showing a detailed configuration example of a comparison circuit.

[0034] Figure 4 is a diagram showing transitions of various signals during operation of the comparison circuit.

[0035] Figure 5 A diagram for explaining the detailed structure of a pixel circuit.

[0036] Figure 6 is a timing diagram showing the operation of a pixel.

[0037] Figure 7 : is a circuit diagram showing a configuration example of a comparison circuit in the case of pixel sharing.

[0038] Figure 8 This is a first exposure control example of pixels that share a pixel.

[0039] Fig. 9 This is a first exposure control example of pixels that share a pixel.

[0040] Fig.10 This is a first exposure control example of pixels that share a pixel.

[0041] Fig.11 This is a first exposure control example of pixels that share a pixel.

[0042] Fig.12 It is used to illustrate Figure 1 Flowchart of exposure control processing of a solid-state imaging device in FIG.

[0043] Fig.13 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the solid-state imaging device of the present disclosure is applied.

[0044] Fig.14 It is a diagram showing a use example of a solid-state imaging device to which the technology of the present disclosure is applied. DETAILED DESCRIPTION

[0045] The advantageous embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that in the present specification and the accompanying drawings, components having substantially the same functional configuration are denoted by the same reference numerals to omit redundant description.

[0046] Furthermore, the description is given in the following order.

[0047] 1. Schematic Configuration Example of Solid-State Imaging Device

[0048] 2. Detailed example of pixel structure

[0049] 3. Comparison circuit configuration example

[0050] 4. Example of pixel sharing configuration

[0051] 5. Exposure control of pixels sharing pixels

[0052] 6. Exposure control processing

[0053] 7. Application examples of electronic equipment

[0054] 8. Example of using solid-state imaging device

[0055] <1. Schematic Configuration Example of Solid-State Imaging Device>

[0056] Figure 1 A schematic configuration of a solid-state imaging device according to the present disclosure is shown.

[0057] Figure 1 The solid-state imaging device 1 in the embodiment includes a pixel array unit 22 in which pixels 21 are arranged in a two-dimensional array on a semiconductor substrate 11 using, for example, silicon (Si) as a semiconductor. The pixel array unit 22 is also provided with a time code transmission unit 23 for transmitting a time code generated by a time code generation unit 26 to each pixel 21. Then, a pixel driving circuit 24, a D / A converter (DAC) 25, a time code generation unit 26, a vertical driving circuit 27, an output unit 28, and a timing generation circuit 29 are formed around the pixel array unit 22 on the semiconductor substrate 11.

[0058] Each pixel 21 arranged in a two-dimensional array is provided as follows Figure 2 The pixel circuit 41 and the ADC 42 are described. The pixel 21 generates a charge signal corresponding to the amount of light received by a light receiving element (eg, a photodiode) within the pixel, converts the charge signal into a digital pixel signal SIG, and outputs the pixel signal SIG.

[0059] The pixel driving circuit 24 drives the pixel circuit 41 in the pixel 21 ( Figure 2 ). More specifically, the pixel driving circuit 24 includes a control timing table storage unit 24a. The control timing table storage unit 24a stores a control timing table in which information defining a control timing associated with driving of each pixel circuit 41 of the plurality of pixels 21 is recorded, and an exposure start time, an exposure end time, a reset time, and a readout time within an exposure unit time which is a unit time for controlling exposure of the pixel circuit 41 are recorded.

[0060] By variously setting the exposure start time, exposure end time, reset time, and readout time in the control timing table, the length of the exposure time, the exposure period, and the number of exposure times can be set separately in units of pixels 21. For each pixel, the pixel driving circuit 24 controls the driving of the pixel circuit 41 based on the information recorded in the control timing table that specifies the control timing related to the driving of each pixel circuit 41. The pixel driving circuit 24 can switch the control timing table at predetermined intervals, or can switch the control timing table to a specified control timing table according to an operation signal from the operation unit 2 that is operated by the user and outputs an operation signal according to the operation content.

[0061] In addition, after performing a series of processes based on the information recorded in the control timing table that specifies the control timing related to the drive of each pixel circuit 41, the pixel driving circuit 24 can switch the control timing table to a different control timing table. In this case, the control timing table may also include the next control timing table to be switched and information for specifying the switching time. Using this information, the pixel driving circuit 24 can control the drive of the pixel circuit 41 while switching the control timing table.

[0062] The DAC 25 generates a reference signal (reference voltage signal) REF, which is a slope signal whose level (voltage) decreases monotonically with the lapse of time, and supplies the reference signal REF to each pixel 21. The time code generation unit 26 generates a time code used when each pixel 21 converts the analog pixel signal SIG into a digital signal (AD conversion), and supplies the time code to the corresponding time code transmission unit 23. A plurality of time code generation units 26 are provided for the pixel array unit 22, and the number of time code transmission units 23 corresponding to the time code generation units 26 is provided in the pixel array unit 22. In other words, the time code generation unit 26 and the time code transmission unit 23 for transmitting the time code generated in the time code generation unit 26 correspond one to one.

[0063] The vertical drive circuit 27 performs control so as to output the digital pixel signal SIG generated in the pixel 21 to the output unit 28 in a predetermined order based on the timing signal supplied from the timing generation circuit 29. The digital pixel signal SIG output from the pixel 21 is output from the output unit 28 to the outside of the solid-state imaging device 1. The output unit 28 performs predetermined digital signal processing such as black level correction processing and correlated double sampling (CDS) processing for correcting the black level as necessary, and then outputs the digital pixel signal SIG to the outside.

[0064] The timing generation circuit 29 includes a timing generator and the like that generates various timing signals, and supplies the generated various timing signals to the pixel driving circuit 24 , the DAC 25 , the vertical driving circuit 27 , and the like.

[0065] The solid-state imaging device 1 is constructed as described above. Figure 1 In the description, a description has been given in which all the circuits constituting the solid-state imaging device 1 are formed on one semiconductor substrate 11, but a configuration may be adopted in which the circuits constituting the solid-state imaging device 1 are divided and arranged in a plurality of semiconductor substrates 11.

[0066] <2. Detailed Configuration Example of Pixel>

[0067] Figure 2 2 is a block diagram showing a detailed configuration example of the pixel 21 .

[0068] The pixel 21 includes a pixel circuit 41 and an AD converter (ADC) 42 .

[0069] The pixel circuit 41 outputs a charge signal corresponding to the amount of received light as an analog pixel signal SIG to the ADC 42. The ADC 42 converts the analog pixel signal SIG supplied from the pixel circuit 41 into a digital signal.

[0070] The ADC 42 includes a comparison circuit 51 and a data storage unit 52 .

[0071] The comparison circuit 51 compares the reference signal REF supplied from the DAC 25 with the pixel signal SIG and outputs an output signal VCO as a comparison result signal indicating the comparison result. When the reference signal REF and the pixel signal SIG become the same (voltage), the comparison circuit 51 inverts the output signal VCO.

[0072] The comparison circuit 51 includes a differential input circuit 61, a voltage conversion circuit 62, and a positive feedback circuit (PFB) 63. Figure 3 The details are explained.

[0073] In addition to the output signal VCO being input from the comparison circuit 51 to the data storage unit 52, a WR signal indicating a write operation of a pixel signal, an RD signal indicating a read operation of a pixel signal, and a WORD signal for controlling the read timing of the pixel 21 during the read operation of the pixel signal are supplied from the vertical drive circuit 27 to the data storage unit 52. Furthermore, the time code generated by the time code generation unit 26 is supplied to the data storage unit 52 via the time code transmission unit 23.

[0074] The data storage unit 52 includes a latch control circuit 71 that controls a write operation and a read operation of a time code based on a WR signal and an RD signal, and a latch storage unit 72 that stores the time code.

[0075] The latch control circuit 71 causes the latch storage unit 72 to store the time code updated per unit time supplied from the time code transmission unit 23 during the input of the high (Hi) output signal VCO from the comparison circuit 51 in the writing operation of the time code. Then, when the reference signal REF and the pixel signal SIG become the same (voltage) and the output signal VCO supplied from the comparison circuit 51 is inverted to low (Lo), the latch control circuit 71 stops writing (updating) the supplied time code and causes the latch storage unit 72 to hold the time code last stored in the latch storage unit 72. The time code stored in the latch storage unit 72 represents the time when the pixel signal SIG and the reference signal REF become equal, and represents data indicating that the pixel signal SIG is the reference voltage at this time, that is, the digitized light amount value.

[0076] After the scanning of the reference signal REF is completed and the time code is stored in the latch storage unit 72 of all the pixels 21 within the pixel array unit 22, the operation of the pixel 21 changes from the write operation to the read operation.

[0077] In the readout operation of the time code, when the timing becomes the readout timing of the pixel 21 itself based on the WORD signal timing for controlling the readout timing, the latch control circuit 71 outputs the time code (digital pixel signal SIG) stored in the latch storage unit 72 to the time code transmission unit 23. The time code transmission unit 23 sequentially transmits the supplied time code in the column direction (vertical direction) and supplies it to the output unit 28.

[0078] Hereinafter, in order to distinguish the time code in a read operation from the time code written to the latch storage unit 72 in a write operation, the digitized pixel data representing the inverted time code when the output signal VCO read from the latch storage unit 72 is inverted in the read operation of the time code, in which the pixel signal SIG is the reference voltage at this time, is also referred to as AD converted pixel data.

[0079] <3. Example of Comparison Circuit Configuration>

[0080] Figure 3 2 is a circuit diagram showing the detailed configuration of the differential input circuit 61 , the voltage conversion circuit 62 , and the positive feedback circuit 63 constituting the comparison circuit 51 .

[0081] The differential input circuit 61 compares the pixel signal SIG output from the pixel circuit 41 within the pixel 21 with the reference signal REF output from the DAC 25 , and outputs a predetermined signal (current) when the pixel signal SIG is higher than the reference signal REF.

[0082] The differential input circuit 61 includes transistors 81 and 82 forming a differential pair, transistors 83 and 84 constituting a current mirror, transistor 85 serving as a constant current source that supplies current IB according to the input bias current Vb, and transistor 86 that outputs the output signal HVO of the differential input circuit 61.

[0083] Transistors 81, 82, and 85 are composed of negative-channel MOS (NMOS) transistors, and transistors 83, 84, and 86 are composed of positive-channel MOS (PMOS) transistors.

[0084] Between the transistors 81 and 82 forming the differential pair, the reference signal REF output from the DAC 25 is input to the gate of transistor 81, and the pixel signal SIG output from the pixel circuit 41 within the pixel 21 is input to the gate of transistor 82. The sources of transistors 81 and 82 are connected to the drain of transistor 85, and the source of transistor 85 is connected to a predetermined voltage VSS (VSS < VDD2 < VDD1).

[0085] The drain of transistor 81 is connected to the gates of transistors 83 and 84 constituting the current mirror circuit and the drain of transistor 83, and the drain of transistor 82 is connected to the drain of transistor 84 and the gate of transistor 86. The sources of transistors 83, 84, and 86 are connected to the first power supply voltage VDD1.

[0086] For example, the voltage conversion circuit 62 includes an NMOS transistor 91. The drain of transistor 91 is connected to the drain of transistor 86 of the differential input circuit 61, the source of transistor 91 is connected to a predetermined connection point within the positive feedback circuit 63, and the gate of transistor 91 is connected to the bias voltage VBIAS.

[0087] The transistors 81 to 86 constituting the differential input circuit 61 are circuits that operate at a high voltage up to the first power supply voltage VDD1, while the positive feedback circuit 63 is a circuit that operates at a second power supply voltage VDD2 lower than the first power supply voltage VDD1. The voltage conversion circuit 62 converts the output signal HVO input from the differential input circuit 61 into a low-voltage signal (conversion signal) LVI that the positive feedback circuit 63 can operate on and supplies this signal to the positive feedback circuit 63.

[0088] The bias voltage VBIAS is a voltage that is sufficient to convert the voltage so as not to damage the transistors 101 to 105 of the positive feedback circuit 63 that operate at a constant voltage. For example, the bias voltage VBIAS can be the same voltage as the second power supply voltage VDD2 of the positive feedback circuit 63 (VBIAS = VDD2).

[0089] The positive feedback circuit 63 outputs a comparison result signal that is inverted when the pixel signal SIG is higher than the reference signal REF based on the conversion signal LVI obtained by converting the output signal HVO from the differential input circuit 61 into a signal corresponding to the second power supply voltage VDD2. In addition, the positive feedback circuit 63 accelerates the transition speed when the output signal VCO output as the comparison result signal is inverted.

[0090] The positive feedback circuit 63 includes five transistors 101 to 105. Here, the transistors 101, 102 and 104 are composed of PMOS transistors, and the transistors 103 and 105 are composed of NMOS transistors.

[0091] The source of transistor 91 as the output terminal of voltage conversion circuit 62 is connected to the drains of transistors 102 and 103 and the gates of transistors 104 and 105. The sources of transistors 101 and 104 are connected to the second power supply voltage VDD2, the drain of transistor 101 is connected to the source of transistor 102, and the gate of transistor 102 is connected to the drains of transistors 104 and 105 as the output terminal of positive feedback circuit 63. The sources of transistors 103 and 105 are connected to a predetermined voltage VSS. An initialization signal INI is supplied to the gates of transistors 101 and 103.

[0092] The transistors 104 and 105 constitute an inverter circuit, and a connection point between the drains of the transistors 104 and 105 is an output terminal for outputting an output signal VCO from the comparison circuit 51 .

[0093] The operation of the comparison circuit 51 configured as described above will be described. Figure 4 1 shows the transition of each signal during the operation of the comparison circuit 51. It should be noted that Figure 4 “G86” in ref: Nbsp; represents the gate potential of transistor 86.

[0094] First, the reference signal REF is set to a voltage higher than the pixel signals SIG of all the pixels 21 , the initialization signal INI is set to Hi, and the comparison circuit 51 is initialized.

[0095] More specifically, a reference signal REF is applied to the gate of transistor 81, and a pixel signal SIG is applied to the gate of transistor 82. When the voltage of the reference signal REF is higher than the voltage of the pixel signal SIG, most of the current output from the transistor 85 used as a current source flows to the diode-connected transistor 83 via the transistor 81. The channel resistance of the transistor 84 having a gate common to the transistor 83 becomes sufficiently low and maintains the gate of the transistor 86 at a level of approximately the first power supply voltage VDD1, and turns off the transistor 86. Therefore, even if the transistor 91 of the voltage conversion circuit 62 is turned on, the positive feedback circuit 63 as a charging circuit will not charge the conversion signal LVI. On the other hand, since the Hi signal is supplied as the initialization signal INI, the transistor 103 becomes turned on, and the positive feedback circuit 63 discharges the conversion signal LVI. In addition, since the transistor 101 is turned off, the positive feedback circuit 63 will not charge the conversion signal LVI via the transistor 102. As a result, the conversion signal LVI is discharged to the level of the predetermined voltage VSS, the positive feedback circuit 63 outputs the Hi output signal VCO through the transistors 104 and 105 constituting an inverter, and the comparison circuit 51 is initialized.

[0096] After initialization, the initialization signal INI is set to Lo, and scanning of the reference signal REF starts.

[0097] In the period when the reference signal REF is higher than the pixel signal SIG, the transistor 86 is turned off and thus turned off, and the output signal VCO changes to a Hi signal, so the transistor 102 is turned off and turned off. Since the initialization signal INI is Lo, the transistor 103 is also turned off. The conversion signal LVI maintains the predetermined voltage VSS in a high impedance state and outputs a Hi output signal VCO.

[0098] When the reference signal REF becomes lower than the pixel signal SIG, the output current of the transistor 85 of the current source does not flow through the transistor 81, the gate potentials of the transistors 83 and 84 rise, and the channel resistance of the transistor 84 becomes high. Then, the current flowing through the transistor 82 causes the voltage to drop so that the gate potential of the transistor 86 is reduced, and the transistor 91 becomes conductive. The output signal HVO output from the transistor 86 is converted into a conversion signal LVI by the transistor 91 of the voltage conversion circuit 62 and supplied to the positive feedback circuit 63. The positive feedback circuit 63 as a charging circuit charges the conversion signal LVI so that the potential approaches the second power supply voltage VDD2 from the low voltage VSS.

[0099] Then, when the voltage of the conversion signal LVI exceeds the threshold voltage of the inverter composed of transistors 104 and 105, the output signal VCO becomes Lo, and the transistor 102 becomes conductive. The transistor 101 is also conductive because the Lo initialization signal INI is applied, and the positive feedback circuit 63 quickly charges the conversion signal LVI via the transistors 101 and 102 to immediately raise the potential to the second power supply voltage VDD2.

[0100] Since the bias voltage VBIAS is applied to the gate of the transistor 91 of the voltage conversion circuit 62, when the voltage of the conversion signal LVI reaches a voltage value that reduces the transistor threshold from the bias voltage VBIAS, the transistor 91 is turned off. Even if the transistor 86 remains turned on, the conversion signal LVI is no longer charged to a voltage value greater than the voltage value, and the voltage conversion circuit 62 functions as a voltage clamp circuit.

[0101] The charging of the conversion signal LVI caused by the conduction of the transistor 102 initially starts from the rise of the conversion signal LVI to the inverter threshold, and is a positive feedback operation for accelerating the movement. The transistor 85 as the current source of the differential input circuit 61 has a lot of circuits that operate in parallel at the same time in the solid-state imaging device 1, so that the current of each circuit is set to a very small current. In addition, the reference signal REF is scanned very slowly because the voltage changed in the unit time of the switching time code becomes the LSB step of the AD conversion. Therefore, the change of the gate potential of the transistor 86 is also very slow, and the change of the output current of the transistor 86 driven thereby is also very slow. However, by applying the positive feedback of the rear stage to the conversion signal LVI charged with the output current, the output signal VCO can be transformed quickly enough. Desirably, the transition time of the output signal VCO is a part of the unit time of the time code and is usually 1ns or less. The comparison circuit 51 disclosed in the present invention can achieve this output transition time by simply setting a small current of, for example, 0.1uA to the transistor 85 of the current source.

[0102] <Detailed Configuration Example of Pixel Circuit>

[0103] Reference Figure 5 The detailed configuration of the pixel circuit 41 will be described.

[0104] Figure 5 It shows Figure 3 0 is a circuit diagram of a comparison circuit 51 shown in FIG. 4 in which details of a pixel circuit 41 are added.

[0105] The pixel circuit 41 includes a photodiode (PD) 121 as a photoelectric conversion element, a discharge transistor 122 , a transfer transistor 123 , a reset transistor 124 , and a floating diffusion layer (FD) 125 .

[0106] The discharge transistor 122 is used when adjusting the exposure period. Specifically, when the discharge transistor 122 is turned on when it is desired to start the exposure period at an arbitrary time, the charge accumulated in the photodiode 121 until then is discharged, so the exposure period starts when and after the discharge transistor 122 is turned off.

[0107] The transfer transistor 123 transfers the charge generated by the photodiode 121 to the FD 125. The reset transistor 124 resets the charge stored in the FD 125. The FD 125 is connected to the gate of the transistor 82 of the differential input circuit 61. Therefore, the transistor 82 of the differential input circuit 61 also functions as an amplification transistor of the pixel circuit 41.

[0108] The source of the reset transistor 124 is connected to the gate of the transistor 82 of the differential input circuit 61 and the FD 125, and the drain of the reset transistor 124 is connected to the drain of the transistor 82. Therefore, there is no fixed reset voltage for resetting the charge of the FD 125. This is because the reset voltage for resetting the FD 125 can be arbitrarily set using the reference signal REF by controlling the circuit state of the differential input circuit 61.

[0109] <Pixel unit timing diagram>

[0110] Reference Figure 6 The timing diagram in Figure 5 The operation of the pixel 21 shown in FIG. 2 will be described.

[0111] First, at time t1, the reference signal REF is lowered from the previous standby voltage V stb The reset voltage V is set to reset the charge of the FD 125. rst , and as the reset transistor 124 is turned on, the charge of the FD 125 is reset. In addition, at time t1, the initialization signal INI supplied to the gates of the transistors 101 and 103 of the positive feedback circuit 63 is set to Hi, and the positive feedback circuit 63 is set to the initial state.

[0112] At time t2, the reference signal REF rises to a predetermined voltage V u , and comparison between the reference signal REF and the pixel signal SIG is started (scanning of the reference signal REF). At this time, the output signal VCO is Hi because the reference signal REF is greater than the pixel signal SIG.

[0113] At time t3 when the reference signal REF and the pixel signal SIG are determined to be the same, the output signal VCO is inverted (turned to Low). When the output signal VCO is inverted, as described above, the positive feedback circuit 63 accelerates the inversion of the output signal VCO. In addition, the data storage unit 52 stores time data (N bits DATA[1] to DATA[N]) of the time when the output signal VCO is inverted.

[0114] At time t4 when the signal writing period ends and which is the start time of the signal reading period, the voltage of the reference signal REF to be supplied to the gate of the transistor 81 of the comparison circuit 51 decreases to a level at which the transistor 81 is turned off (standby voltage V stb ). Thus, the current consumption of the comparison circuit 51 in the signal readout period is suppressed.

[0115] At time t5, the WORD signal for controlling the read timing becomes Hi, and an N-bit latch signal Col[n] (n=1 to N) (not shown) is output from the latch control circuit 71 of the data storage unit 52. The data acquired here is the P-phase data of the reset level when the correlated double sampling (CDS) process is performed.

[0116] At time t6, the reference signal REF rises to a predetermined voltage V u , the initialization signal INI to be supplied to the gates of the transistors 101 and 103 is set to Hi, and the positive feedback circuit 63 is set to the initial state again.

[0117] At time t7 , the transfer transistor 123 of the pixel circuit 41 is turned on by the Hi transfer signal TX, and the charge generated by the photodiode 121 is transferred to the FD 125 .

[0118] After the initialization signal INI returns to Low, the comparison between the reference signal REF and the pixel signal SIG is started (scanning of the reference signal REF). At this time, the output signal VCO is Hi because the reference signal REF is greater than the pixel signal SIG.

[0119] Then, at time t8 when the reference signal REF and the pixel signal SIG are determined to be the same, the output signal VCO is inverted (turned to Low). When the output signal VCO is inverted, the positive feedback circuit 63 accelerates the inversion of the output signal VCO. In addition, the data storage unit 52 stores time data (N bits DATA[1] to DATA[N]) of the time when the output signal VCO is inverted.

[0120] At time t9 when the signal writing period ends and which is the start time of the signal reading period, the voltage of the reference signal REF to be supplied to the gate of the transistor 81 of the comparison circuit 51 decreases to a level at which the transistor 81 is turned off (standby voltage V stb ). Thus, the current consumption of the comparison circuit 51 in the signal readout period is suppressed.

[0121] At time t10, the WORD signal for controlling the read timing becomes Hi, and an N-bit latch signal Col[n] (n=1 to N) (not shown) is output from the latch control circuit 71 of the data storage unit 52. The data acquired here is the D-phase data of the signal level when the CDS process is performed. Time t11 is in the same state as the above-mentioned time t1, and the next 1V (one vertical scanning period) is driven.

[0122] According to the driving of the pixel 21 described above, first, the P-phase data (reset level) is acquired and then read out, and then, the D-phase data (signal level) is acquired and read out.

[0123] Through the above operation, the pixel 21 of the pixel array unit 22 of the solid-state imaging device 1 can perform a global shutter operation to reset all pixels at the same time and expose all pixels at the same time. Since all pixels can be exposed and read out at the same time, a holding unit that is usually set in the pixel and holds the charge until the charge is read out is not necessary. In addition, the configuration of the pixel 21 does not require a selection transistor or the like for selecting a pixel to output the pixel signal SIG, which is necessary in a column parallel readout type solid-state imaging device.

[0124] In reference Figure 6 In the driving of the pixel 21 described above, the discharge transistor 122 is controlled to be always off. Figure 6 As shown by the dotted line in FIG. 1 , the discharge signal OFG can be set to Hi at a desired time and the discharge transistor 122 can be turned off once it is turned on to set an arbitrary exposure period.

[0125] <4. Example of pixel sharing configuration>

[0126] The above-described comparison circuit 51 is configured such that one ADC 42 is arranged within one pixel 21. However, a plurality of pixels 21 may share one ADC 42.

[0127] Figure 7 The right part of FIG. 4 shows a configuration example of the comparison circuit 51 when one ADC 42 is shared by four pixels 21 of the pixel 21A, the pixel 21B, the pixel 21C, and the pixel 21D. For example, the four pixels 21 of the pixel 21A, the pixel 21B, the pixel 21C, and the pixel 21D have the following configuration example: Figure 7The 2-pixel×2-pixel layout shown in the left portion of FIG. 4 is configured in a two-dimensional array in units of 2 pixels×2 pixels that share the ADC 42 .

[0128] exist Figure 7 In the right part of FIG. 5 , the differential input circuit 61, the voltage conversion circuit 62 and the positive feedback circuit 63 constituting the comparison circuit 51 are similar to those of FIG. Figure 3 The composition shown in .

[0129] exist Figure 7 In the right part of , four pixels 21A to 21D are provided with pixel circuits 41A to 41D, and each pixel circuit 41A to 41D is provided with a photodiode 121q, a discharge transistor 122q, and a transfer transistor 123q. On the other hand, the reset transistor 174 and the FD 175 are shared by the four pixels 21A to 21D.

[0130] More specifically, Figure 7 The left portion shows an example in which two pixels out of four pixels of pixel 21A, pixel 21B, pixel 21C and pixel 21D are arranged in a two-dimensional manner in the column direction and the row direction to constitute a unit pixel group, and an example in which a plurality of unit pixel groups are arranged in a two-dimensional manner in the column direction and the row direction to constitute a pixel array.

[0131] The unit pixel group includes pixels 21A to 21D. Then, the pixels 21A to 21D constituting the unit pixel group share one ADC 42. In other words, one ADC 42 is set in the unit pixel group, and the pixels 21A to 21D share the pixel ADC 42.

[0132] Figure 7 The right part in FIG. 4 shows an equivalent circuit diagram of a unit pixel group in which four pixels 21A to 21D share one ADC 42 .

[0133] exist Figure 7 In the equivalent circuit diagram shown on the right side of , the pixel 21A includes a pixel circuit 41A, and the pixel 21A includes an FD175, a reset transistor 174 and an ADC 42 shared by four pixels 21A to 21D constituting a unit pixel group, and the ADC42 includes a differential input circuit 61, a voltage conversion circuit 62 and a positive feedback circuit 63 constituting a comparison circuit 51.

[0134] Similarly, in Figure 7 In the equivalent circuit diagram shown on the right side of , the pixel 21B includes a pixel circuit 41B, and the pixel 21B includes an FD 175, a reset transistor 174 and an ADC 42 shared by four pixels 21A to 21D constituting a unit pixel group, and the ADC 42 includes a differential input circuit 61, a voltage conversion circuit 62 and a positive feedback circuit 63 constituting a comparison circuit 51.

[0135] Similarly, in Figure 7 In the equivalent circuit diagram shown on the right side of , the pixel 21C includes a pixel circuit 41C, and the pixel 21C includes an FD 175, a reset transistor 174 and an ADC 42 shared by four pixels 21A to 21D constituting a unit pixel group, and the ADC 42 includes a differential input circuit 61, a voltage conversion circuit 62 and a positive feedback circuit 63 constituting a comparison circuit 51.

[0136] Similarly, in Figure 7 In the equivalent circuit diagram shown on the right side of , the pixel 21D includes a pixel circuit 41D, and the pixel 21D includes an FD 175, a reset transistor 174 and an ADC 42 shared by four pixels 21A to 21D constituting a unit pixel group, and the ADC 42 includes a differential input circuit 61, a voltage conversion circuit 62 and a positive feedback circuit 63 constituting a comparison circuit 51.

[0137] It should be noted that in Figure 7 In the right part, use Figure 3 The circuit configuration is shown as the circuit configuration of the comparison circuit 51. However, another circuit configuration may be adopted.

[0138] <5. Exposure Control of Pixels Sharing Pixels>

[0139] As described above, in the solid-state imaging device 1 of the present disclosure, exposure can be controlled in units of pixels.

[0140] The pixel driving circuit 24 can control the exposure in each four pixels 21 of the shared pixel according to the control timing table pre-registered in the control timing table storage unit 24a. That is, in this case, the pixel driving circuit 24 classifies the pixels 21 configured in a two-dimensional array in the pixel array unit 22 into four types in units of 2 pixels×2 pixels, and can control the exposure of the pixels 21 by the control timing table corresponding to each of the four types of pixels 21.

[0141] Note that the number of types for classifying pixels is not limited to four, and may be another number. In addition, control regarding exposure may be performed individually for all pixels, or control regarding exposure may be performed individually for a portion of pixels.

[0142] (First Exposure Control Example)

[0143] For example, Figure 8 As shown, the exposure of the pixels 21A to 21D can be set to various timings.

[0144] Figure 8The upper part of shows the passage of time in the horizontal right direction in the order of pixels 21A to 21D, pixels 21A to 21D from the top, and shows a timing diagram in which the timing of performing reset and reading out P-phase data as shown by the black square mark, and the timing of terminating exposure and reading out D-phase data at the white square mark are shown. Hereinafter, the timing processing represented by the black square mark is simply referred to as reset processing, and the timing processing represented by the white square mark is simply referred to as readout processing.

[0145] In addition, the strip-shaped mark provided with a pattern between the black square mark and the white square mark indicates the exposure period. In addition, the marks of the exposure periods given the same color indicate that the exposure periods have the same length. Figure 8 In the lower part of FIG. 1 , the exposure period when the length in the horizontal direction is one exposure unit time is shown in the frame corresponding to the layout of the pixels 21A to 21D. Therefore, as long as the same control timing table is used continuously, the exposure is repeatedly controlled using the control mode of the exposure unit time.

[0146] In other words, Figure 8 As shown in the upper part of , in the pixel 21A, after the reset process is performed at time t1, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX at the moment immediately thereafter, and at time t8, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the readout process is performed. Therefore, in the pixel 21A, the period from the moment after the reset process is performed at time t1 to time t8 is the exposure period.

[0147] Furthermore, in the pixel 21B, exposure is not performed when the transfer transistor 123 is turned on by the transfer signal TX after the reset process is performed at time t2, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX at a timing immediately thereafter after the reset process is performed again at time t7, exposure is terminated at time t9 when the transfer transistor 123 is turned on by the transfer signal TX, and readout processing is performed. Therefore, in the pixel 21B, the period from the timing after the reset process is performed at time t7 to time t9 is the exposure period.

[0148] Furthermore, in the pixel 21C, exposure is not performed when the transfer transistor 123 is turned on by the transfer signal TX after the reset process is performed at time t3, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX at a timing immediately thereafter after the reset process is performed again at time t6, and exposure is terminated at time t10 when the transfer transistor 123 is turned on by the transfer signal TX, and a readout process is performed. Therefore, in the pixel 21C, the period from the timing after the reset process is performed at time t6 to time t10 is an exposure period.

[0149] Furthermore, in the pixel 21D, after the reset process is performed at time t4, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX at a timing immediately thereafter, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX after the readout process is performed at time t5, and the reset process is performed at time t11. Therefore, in the pixel 21D, the period from the timing after the reset process is performed at time t4 to time t5 is the exposure period.

[0150] like Figure 8 As shown in the lower part of , in pixel 21A, the entire period of one exposure unit time is the exposure period, in pixel 21B, the last approximately 1 / 3 period of one exposure unit time is the exposure period, in pixel 21C, the last approximately 2 / 3 period of one exposure unit time is the exposure period, and in pixel 21D, the first approximately 1 / 6 period of one exposure unit time is the exposure period.

[0151] The timing and length of the exposure period can be controlled separately in each of the four pixels shared by the pixel.

[0152] It should be noted that in Figure 8 The reason why the reset process and the readout process are not performed at the same time is because the ADC 42 is shared by the four pixels 21 due to pixel sharing, but the reset process and the readout process can be performed at the same time when the ADC 42 is not shared and the ADC 42 is set in each pixel.

[0153] In addition, if Figure 8 As shown, information indicating the moment of controlling the on and off of the transfer transistor 123 through the transmission signal TX is stored in the control timing table storage unit 24a for each pixel 21, and the moment includes the moment of performing the reset processing, the moment of performing the readout processing, the exposure start moment and the exposure end moment, and the pixel driving circuit 24 realizes exposure control in units of pixels 21 by controlling the operation of the pixel circuit 41 of each pixel 21 based on the information in the control timing table.

[0154] (Second Exposure Control Example)

[0155] In the above description, an example has been described in which the pixels 21A to 21D are exposed once in one exposure unit time and the timing and length of the exposure period are controlled to be different. However, the exposure number may be multiple times and the respective lengths may be made the same.

[0156] In other words, Fig. 9As shown in the upper part of , in the pixel 21A, after the reset processing is performed at time t21, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t25, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0157] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t29, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0158] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t33, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the third readout process is performed.

[0159] In addition, if Fig. 9 As shown in the upper part of , in the pixel 21B, after the reset processing is performed at time t22, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t26, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0160] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t30, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the second readout process is performed. In addition, thereafter, at time t34, the third readout process is performed.

[0161] In addition, if Fig. 9 As shown in the upper part of , in the pixel 21C, after the reset processing is performed at time t23, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t27, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0162] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t31, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0163] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t35, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the third readout process is performed.

[0164] In addition, if Fig. 9As shown in the upper part of , in the pixel 21D, after the reset processing is performed at time t24, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t28, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0165] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t32, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0166] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t36, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the third readout process is performed.

[0167] It should be noted that if Fig. 9 As shown, the exposure period from when the reset process is performed and exposure starts with the transfer transistor 123 being turned off by the transfer signal TX to when exposure is terminated with the transfer transistor 123 being turned on by the transfer signal TX and the first readout process is performed is referred to as a first exposure period.

[0168] Furthermore, the exposure period from when exposure starts as the transfer transistor 123 is turned off by the transfer signal TX after the first readout process is performed to when exposure is terminated as the transfer transistor 123 is turned on by the transfer signal TX and the second readout process is performed is referred to as a second exposure period.

[0169] Furthermore, the exposure period from when exposure starts as the transfer transistor 123 is turned off by the transfer signal TX after the second readout process is performed to when exposure is terminated as the transfer transistor 123 is turned on by the transfer signal TX and the third readout process is performed is referred to as a third exposure period.

[0170] Here, the first exposure period to the third exposure period are the same in any one of the pixels 21A to 21D.

[0171] Through the above control, it is possible to realize exposure control in which the number of exposure times of the pixels 21A to 21D is set to a plurality of times and the lengths of the pixels 21 are made the same.

[0172] (Third Exposure Control Example)

[0173] In the above description, an example has been described in which the number of exposure times of the exposure period of the pixels 21A to 21D is set to a plurality of times and the timing and length are made the same. However, the number of exposure times may be set to a plurality of times and may be made different for each pixel.

[0174] In other words, Fig.10 As shown in the upper part of , in the pixel 21A, after the reset process is performed at time t51, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t63, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the readout process is performed.

[0175] In other words, Fig.10 As shown in the lower part of , the entire single exposure unit time of the pixel 21A is the exposure period.

[0176] In addition, if Fig.10 As shown in the upper part of , in the pixel 21B, after the reset processing is performed at time t52, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t56, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0177] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t60, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0178] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t64, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the third readout process is performed.

[0179] In other words, Fig.10 As shown in the lower part of , in the pixel 21B, exposure of a period obtained by roughly equally dividing one exposure unit time into three periods is repeated three times.

[0180] In addition, if Fig.10 As shown in the upper part of , in the pixel 21C, after the reset processing is performed at time t53, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t58, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0181] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t65, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0182] In other words, Fig.10 As shown in the lower part of FIG. 21 , in the pixel 21C, exposure of a period obtained by roughly equally dividing one exposure unit time into two periods is repeated twice.

[0183] In addition, if Fig.10 As shown in the upper part of , in the pixel 21D, after the reset processing is performed at time t54, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t55, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0184] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t57, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0185] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t59, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the third readout process is performed.

[0186] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t61, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the fourth readout process is performed.

[0187] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t62, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the fifth readout process is performed.

[0188] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t66, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the sixth readout process is performed.

[0189] In other words, Fig.10 As shown in the lower part of , in the pixel 21D, exposure of a period obtained by roughly equally dividing one exposure unit time into six periods is repeated six times.

[0190] Through the above-described process, the exposure time can be realized at equal intervals by different times in the pixels 21A to 21D.

[0191] (Fourth Exposure Control Example)

[0192] In the above description, an example has been described in which the number of exposure times of the pixels 21A to 21D is set to a plurality of times and the exposure periods are controlled at equal intervals. However, the number of exposure times and timings may be made different.

[0193] In other words, Fig.11As shown in the upper part of , in the pixel 21A, after the reset process is performed at time t81, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t88, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout process is performed.

[0194] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t91, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0195] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t94, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the third readout process is performed.

[0196] In addition, if Fig.11 As shown in the upper part of , in the pixel 21B, after the reset processing is performed at time t82, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t90, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0197] Thereafter, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t92, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the second readout process is performed. Furthermore, thereafter, at time t95, the third readout process is performed.

[0198] In addition, if Fig.11 As shown in the upper part of , in the pixel 21C, after the reset processing is performed at time t83, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t86, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0199] Thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t89, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0200] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t96, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the third readout process is performed.

[0201] In addition, if Fig.11As shown in the upper part of , in the pixel 21D, after the reset processing is performed at time t84, exposure starts when the transfer transistor 123 is turned off by the transfer signal TX, and at time t85, the exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the first readout processing is performed.

[0202] Thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t87, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and a second readout process is performed.

[0203] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t93, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the third readout process is performed.

[0204] Furthermore, thereafter, exposure is started when the transfer transistor 123 is turned off by the transfer signal TX, and at time t97, exposure is terminated when the transfer transistor 123 is turned on by the transfer signal TX, and the fourth readout process is performed.

[0205] In other words, Fig.11 As shown in the lower part of , in pixels 21A to 21D, for one exposure unit time, exposure control can be achieved through different exposure times, different timings, and time periods with different lengths.

[0206] Summarizing the above-mentioned exposure control example, the following exposure control can be performed in the solid-state imaging device 1 of the present disclosure. In other words, exposure control can be implemented in which the exposure time of at least one or more pixels 21 in the plurality of photoelectric conversion units sharing the ADC 42 is different from the exposure time of other photoelectric conversion units and the exposure end timing is different. In addition, the exposure period can be switched, for example, the exposure period can be changed by 2 for each pixel. <n>Power.

[0207] For example, by setting a plurality of exposure ratios and a plurality of readout numbers in one pixel 21, a signal amount of [exposure ratio] bit×[readout number] can be obtained.

[0208] Furthermore, by setting and reading out the exposure ratio in the plurality of pixels 21A to 21D sharing the ADC 42 , the signal amount of [exposure ratio] bit×[plurality of pixels] can be obtained.

[0209] Furthermore, by applying a setting in which a plurality of exposure ratios and a plurality of readout numbers are set within a predetermined one pixel 21 and the exposure ratios are set and read out in a plurality of pixels 21 sharing the ADC 42 , the amount of processed signals can be further increased.

[0210] More specifically, for example, in a case where the signal amount of the ADC 42 of one basic pixel 21 is 14 bits and the noise amount is 3 bits, the dynamic range in each state is calculated as follows.

[0211] When one pixel 21 among the pixels 21A to 21D has an exposure ratio of 16 times and the number of readouts is 3 times and similar exposure periods are respectively given to the other three pixels 21 , SN=14 bits+4 bits×3 times×1 pixel−3 bits=23 bits=130 dB.

[0212] Furthermore, in the case where the four pixels 21 of the pixels 21A to 21D have an exposure ratio of 16 times and different exposure periods, SN=14 bits+4 bits×3 pixels−3 bits=23 bits=130 dB.

[0213] Furthermore, when four pixels of pixels 21A to 21D have an exposure ratio of 16 times and different exposure periods and read out pixel signals 4 times through their own pixels, SN=14 bits+4 bits×3 pixels+2 bits−3 bits=25 bits=150 dB.

[0214] Furthermore, since the pixel signals read out in the multiple exposures are AD-converted by the ADC 42 for each pixel, a composite image can be generated by simply performing shift addition of the conversion results, and an increase in memory can be prevented.

[0215] The shift-addition is to add pixel signals composed of binary codes by shifting them to the left (in other words, multiplying them by a power of 2). As the shift amount, a value according to a ratio (exposure ratio) of the exposure time is set.

[0216] For example, the respective exposure times of the pixels 21A to 21D are Ea, Eb, Ec, and Ed. For example, values ​​satisfying the following equations (1) to (3) are set as these exposure times.

[0217] Ec=2×Ed ......(1)

[0219] Eb=2×Ec=4×Ed ......(2)

[0221] Ea=2×Eb=8×Rd ......(3)

[0223] Therefore, in the case where the ratio of another exposure time to the minimum exposure time (exposure ratio) is set to a power of 2 (2, 4, and 8), multiplication can be performed by shift addition. For example, the pixel signal from pixel 21B is shifted to the left by one position. In addition, the pixel signal from pixel 21C is shifted to the left by two positions, and the pixel signal from pixel 21D is shifted to the left by three positions. On the other hand, the pixel signal from pixel 21A is not shifted.

[0224] It should be noted that although the exposure ratio is a power of 2, the exposure ratio may be set to a value other than a power of 2. In the case where the exposure ratio is not a power of 2, it is sufficient to multiply the exposure ratio.

[0225] As described above, since the addition process can be realized by bit shifting, an increase in memory can be prevented.

[0226] It should be noted that the signal processing related to the above-mentioned shift-addition is based on the premise that all pixel signals are unsaturated, and in the case of saturation of the pixel signal, such as the full-scale value of the pixel signal level output logic or the code corresponding to the full-scale value, it is more desirable to include processing to discard data without performing addition or shifting.

[0227] In addition, the control timing table is respectively set for the above-mentioned first to fourth exposure control examples and stored in the control timing table storage unit 24a, and the control timing table can be switched at a predetermined time interval (such as a predetermined unit number of frames), or can be switched and used by a switching operation of the operation unit 2 performed by the user.

[0228] <6. Exposure Control Processing>

[0229] Next, refer to Fig.12 The flowchart in Figure 1 The exposure control process of the solid-state imaging device 1 in FIG. Fig.12 The exposure control processing described in the flowchart in refers to processing for one pixel 21, and independent processing is performed on each of the four pixels 21.

[0230] In step S31 , the pixel driving circuit 24 reads out a predetermined control timing table from the control timing table storage unit 24 a .

[0231] In step S32 , the pixel driving circuit 24 performs a reset process on the pixel 21 based on the information of the control timing table.

[0232] In step S33 , the pixel driving circuit 24 determines whether the current time is the exposure start time based on the information in the control timing table.

[0233] In step S33 , when the current time is the exposure start time, the process proceeds to step S36 .

[0234] In step S36 , the pixel driving circuit 24 turns off the transmission transistor 123 through the transmission signal TX, so that the transmission transistor 123 is in an exposure state.

[0235] In step S37 , the pixel driving circuit 24 determines whether the current time from the timing generating circuit 29 is the exposure end time based on the information of the control timing table.

[0236] In step S37, if the current time is not the exposure end time, the process returns to step S36. In other words, until the exposure end time arrives, the processes of steps S36 and S37 are repeated, and the exposure state is continued.

[0237] In step S37 , when the current time is the exposure end time, the process proceeds to step S38 .

[0238] In step S38 , the pixel driving circuit 24 turns on the transfer transistor 123 by the transfer signal TX, and performs a readout process on the pixel 21 .

[0239] In step S39, the pixel driving circuit 24 determines whether one exposure unit time has elapsed based on the information of the control timing table. If one exposure unit time has not elapsed, the process returns to step S33.

[0240] Furthermore, in step S39 , when it is considered that one exposure unit time has elapsed, the process proceeds to step S42 .

[0241] On the other hand, in step S33 , when the current time is considered not to be the exposure start time, the process proceeds to step S40 .

[0242] In step S40, the pixel driving circuit 24 determines whether one exposure unit time has elapsed based on the information of the control timing table. If one exposure unit time has not elapsed, the process proceeds to step S34.

[0243] In step S34 , the pixel driving circuit 24 determines whether the current time is the exposure start time based on the information in the control timing table.

[0244] In step S34 , when the current time is not the exposure start time, the process returns to step S40 .

[0245] In other words, in the case where the exposure start is instructed immediately after the first reset of one exposure unit time as the process of step S32 , the process proceeds to step S36 and the exposure is started immediately.

[0246] However, for example, Figure 8 As shown at times t2 and t3 in FIG. 1 , in a case where the exposure start is not instructed immediately after the first reset, the process proceeds to step S34 or S40 , and the process in step S34 or S40 is repeated until one exposure unit time elapses.

[0247] Then, in a case where the current time is regarded as the exposure start time in step S34 before one exposure unit time has passed, the process proceeds to step S35.

[0248] In step S35 , the pixel driving circuit 24 performs a reset process on the pixel 21 based on the information of the control timing table, and the process proceeds to step S36 .

[0249] In other words, Figure 8 As shown at times t6 and t7 in FIG. 1 , even in a case where the exposure start is not instructed immediately after the first reset and thereafter, when the timing becomes the exposure start timing, for example, reset is performed again and exposure is started.

[0250] Furthermore, in step S40 , when it is considered that one exposure unit time has elapsed, the process proceeds to step S41 .

[0251] In step S41 , the pixel driving circuit 24 performs a reset process on the pixel 21 based on the information of the control timing table, and the process proceeds to step S42 .

[0252] In other words, the processing of steps S33 to S40 is repeated until one exposure unit time elapses.

[0253] Then, in a case where one exposure unit time has elapsed, or in a case where one exposure unit time has elapsed and the reset process is performed in step S41 , the process proceeds to step S42 .

[0254] In step S42 , the pixel driving circuit 24 determines whether to terminate the process, and in a case where the process is not terminated, the process proceeds to step S43 .

[0255] In step S43, the pixel driving circuit 24 determines whether the current time is the time to switch the control timing table. For example, when the operation unit 2 is operated and an operation signal for switching the control timing table to a predetermined control timing table is supplied, or when the information recorded in the previously used control timing table indicates that another predetermined control timing table is used after a predetermined time has passed, the pixel driving circuit 24 determines to switch the control timing table, and the process proceeds to step S44.

[0256] In step S44 , the pixel driving circuit 24 reads out the control timing table to be switched from the control timing table stored in the control timing table storage unit 24 a , and the process returns to step S32 , and the processes thereafter are repeated.

[0257] On the other hand, in step S43, if it is determined that the current time is not the time to switch the control timing table, the processing in step S44 is skipped. In this case, the control timing table currently being read continues to be used as it is.

[0258] In step S42, in the case of an instruction to instruct the termination of the process, the process is terminated.

[0259] Through this processing, the above-mentioned pixels 21A to 21D can be controlled individually. Therefore, a wide dynamic range can be achieved in all areas. In addition, the time division of the exposure period and the occurrence of the non-exposure period can be prevented, and a subject that emits light with high illuminance in a short time can be reliably photographed.

[0260] As a result, the dynamic range can be appropriately expanded for a subject moving at high speed or a subject having a large brightness difference between light and dark. In addition, motion distortion (motion artifacts) can be reduced.

[0261] Furthermore, since the exposure signals in a plurality of short periods are AD-converted by the ADC 42 for each pixel, a composite image can be generated by simply performing shift addition of the conversion results, and an increase in memory can be prevented.

[0262] Already based on the use Figure 6 The description of the operation of the timing chart in FIG. 1 has given an explanation of the reset process and the readout process as examples. However, a similar operation can be realized using the discharge transistor 122. By using the discharge transistor 122, the degree of freedom of exposure control can be increased.

[0263] Furthermore, the ADC 42 has been described as an example in which it is provided inside the pixel 21. However, the ADC 42 may be provided outside the pixel, or a configuration other than the ADC 42 may be employed as long as the configuration can perform AD conversion.

[0264] <7. Application examples of electronic equipment>

[0265] The above-described solid-state imaging device 1 can be applied to various electronic devices, for example, imaging devices such as digital cameras and digital video cameras, mobile phone devices having an imaging function, and other devices having an imaging function.

[0266] Fig.13 This is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

[0267] Fig.13 The illustrated imaging device 201 includes an optical system 202, a shutter device 203, a solid-state image sensor 204, a drive circuit 205, a signal processing circuit 206, a display 207, and a memory 208, and is capable of imaging still images and moving images.

[0268] The optical system 202 includes one or more lenses, and guides light (incident light) from a subject to the solid-state image sensor 204 to form an image on a light receiving surface of the solid-state image sensor 204 .

[0269] The shutter device 203 is arranged between the optical system 202 and the solid-state image sensor 204 , and controls a light irradiation period and a light shielding period of the solid-state image sensor 204 according to control of the drive circuit 205 .

[0270] The solid-state image sensor 204 is composed of a package including the above-mentioned solid-state image sensor. The solid-state image sensor 204 accumulates signal charges for a fixed period of time according to light formed on the light receiving surface via the optical system 202 and the shutter device 203. The signal charges accumulated in the solid-state image sensor 204 are transmitted according to the drive signal (timing signal) supplied from the drive circuit 205.

[0271] The driving circuit 205 outputs a driving signal for controlling a transfer operation of the solid-state image sensor 204 and a shutter operation of the shutter device 203 to drive the solid-state image sensor 204 and the shutter device 203 .

[0272] The signal processing circuit 206 performs various types of signal processing on the signal charge output from the solid-state image sensor 204. An image (image data) obtained by applying the signal processing by the signal processing circuit 206 is supplied to and displayed on the display 207, and supplied to and stored (recorded) in the memory 208.

[0273] By applying the solid-state imaging device 1 instead of the solid-state image sensor 204 in the imaging device 201 thus configured, the dynamic range can be appropriately expanded to reduce motion distortion (motion artifacts) for a subject moving at high speed or a subject having a large brightness difference between light and dark.

[0274] <8. Example of use of solid-state imaging device>

[0275] Fig.14 1 is a diagram showing a usage example of the solid-state imaging device 1 described above.

[0276] For example, as described below, the camera module described above can be used to sense various aspects of light such as visible light, infrared light, ultraviolet light, and X-rays.

[0277] - A device for taking images for viewing, such as a digital camera or a mobile device with a camera function.

[0278] -Devices used for traffic, such as on-board sensors that capture images of the front, rear, surroundings, interior, etc. of a car for safe driving such as automatic stopping, identification of the driver's status, etc., surveillance cameras for monitoring moving vehicles and roads, distance measurement sensors for measuring the distance between vehicles, etc.

[0279] - A device used in household appliances such as televisions, refrigerators and air conditioners to capture user gestures and operate the device based on the gestures.

[0280] - Devices used in medical care, such as endoscopes, devices for angiography by receiving infrared light, etc.

[0281] -Devices used for security, such as surveillance cameras for crime prevention and cameras for personal identification purposes.

[0282] - Devices for beauty care, such as skin measuring instruments for photographing the skin and microscopes for photographing the scalp, etc.

[0283] -Devices for sports, etc., such as action cameras and wearable cameras for sports purposes, etc.

[0284] -Devices used in agriculture, such as cameras for monitoring the condition of fields and crops.

[0285] It should be noted that the present disclosure may have the following configurations.

[0286] <1> A solid-state imaging device comprising:

[0287] a pixel array unit, the pixel array unit comprising a plurality of pixels; and

[0288] A pixel driving control unit is configured to control exposure of at least a portion of the plurality of pixels in units of pixels.

[0289] <2> according to <1> The solid-state imaging device, wherein

[0290] The pixel driving control unit controls exposure start timing and exposure end timing of the plurality of pixels in units of pixels.

[0291] <3> according to <2> The solid-state imaging device, wherein

[0292] The pixel drive control unit controls a reset timing, a readout timing, the exposure start timing, and the exposure end timing in the exposure of the plurality of pixels, respectively, in units of pixels.

[0293] <4> according to <3> The solid-state imaging device, wherein

[0294] The pixel driving control unit controls the number of exposure periods per exposure unit time in the exposure of the plurality of pixels in units of pixels, respectively.

[0295] <5> according to <4> The solid-state imaging device, wherein

[0296] When the number of the exposure periods in the exposure unit time in the exposure of the plurality of pixels is controlled in units of pixels, respectively, the pixel driving control unit controls the exposure periods at equal time intervals in the exposure unit time.

[0297] <6> according to <4> The solid-state imaging device, wherein

[0298] In the case where the exposure period in the exposure of the plurality of pixels is a plurality of times, each time the exposure is completed, the analog-to-digital converted pixel signal output from the pixel is shift-added to the immediately preceding pixel signal.

[0299] <7> according to <2> The solid-state imaging device, wherein

[0300] The pixel drive control unit controls an exposure start timing and an exposure end timing in exposure of the plurality of pixels in units of a predetermined number of pixels.

[0301] <8> according to <1> to <7> The solid-state imaging device described in any one of the preceding claims, wherein

[0302] The pixel driving control unit includes a control timing table storage unit, wherein the control timing table storage unit stores a plurality of control timing tables, each of which includes control information for controlling the exposure of the plurality of pixels in units of pixels, and

[0303] The pixel driving control unit controls the exposure of the plurality of pixels in units of pixels based on the control information of the control timing table.

[0304] <9> according to <8> The solid-state imaging device, wherein

[0305] The pixel driving control unit switches the control timing table stored in the control timing table storage unit at predetermined time intervals.

[0306] <10> according to <9> The solid-state imaging device, wherein

[0307] The pixel driving control unit switches the control timing table stored in the control timing table storage unit every a predetermined number of frames.

[0308] <11> according to <9> The solid-state imaging device further comprises:

[0309] An operating unit is configured to receive an operation of a user and output a received operation signal, wherein

[0310] The pixel driving control unit switches the control timing table stored in the control timing table storage unit according to the operation signal from the operation unit.

[0311] <12> A control method for a solid-state imaging device, the method comprising:

[0312] Exposure of at least a portion of the pixels in a pixel array unit including a plurality of pixels is controlled in units of pixels.

[0313] <13> An electronic device, comprising:

[0314] a pixel array unit, the pixel array unit comprising a plurality of pixels; and

[0315] A pixel driving control unit is configured to control exposure of at least a portion of the plurality of pixels in units of pixels.

[0316] Reference numerals list

[0317] 1 Solid-state imaging device

[0318] 21 pixels

[0319] 22 pixel array unit

[0320] 23 Time code transmission unit

[0321] 24 Pixel drive circuit

[0322] 24a Control timing table storage unit

[0323] 26 Time code generation unit

[0324] 28 Output Units

[0325] 41 Pixel Circuit

[0326] 42 ADC

[0327] 51 Comparison Circuit

[0328] 52 Data storage unit

[0329] 61 Differential Input Circuit

[0330] 62 Voltage conversion circuit

[0331] 63 Positive feedback circuit

[0332] 71 Latch control circuit

[0333] 72 Latch storage unit

[0334] 81~87 and 91 transistors

[0335] 101~105 and 111~113 transistors< / n>

Claims

1. A light detection device, comprising: A unit pixel, wherein the unit pixel comprises: a first pixel, the first pixel comprising a first photoelectric conversion element and a first transfer transistor; a second pixel including a second photoelectric conversion element and a second transfer transistor; The first pixel and the second pixel are connected to a reset transistor and an amplifying transistor; A pixel driving control unit, the pixel driving control unit comprising: A control timing table storage unit, wherein the control timing table storage unit stores a plurality of control timing tables; Wherein, the plurality of control timing tables include: a first control timing table for exposure control of the first pixel; a second control timing table for exposure control of the second pixel; Wherein, the drive control unit controlling the exposure of the first pixel based on the first control timing table, The exposure of the second pixel is controlled based on the second control timing table, wherein an exposure start time and an exposure end time in the exposure of the first pixel are different from an exposure start time and an exposure end time in the exposure of the second pixel.

2. The light detection device according to claim 1, wherein The pixel driving control unit controls the exposure start time and the exposure end time of the first pixel and the second pixel, respectively.

3. The light detection device according to claim 2, wherein The pixel driving control unit controls a reset timing, a readout timing, the exposure start timing, and the exposure end timing of the first pixel and the second pixel, respectively.

4. The light detection device according to claim 3, wherein The pixel driving control unit controls the number of exposure periods per exposure unit time in exposure of the first pixel and the second pixel, respectively.

5. The light detection device according to claim 4, wherein When the numbers of the exposure periods in the exposure unit time in the exposure of the first pixel and the second pixel are controlled respectively, the pixel driving control unit controls the exposure periods at equal time intervals in the exposure unit time.

6. The light detection device according to claim 4, wherein In the case where the exposure period in the exposure of the first pixel and the second pixel is a plurality of times, each time the exposure is completed, the analog-to-digital converted pixel signal output from the first pixel is shift-added to the immediately preceding pixel signal.

7. The light detection device according to claim 1, wherein The pixel driving control unit switches the first control timing table and the second control timing table at predetermined time intervals.

8. The light detection device according to claim 7, wherein The pixel driving control unit switches the first control timing table and the second control timing table every a predetermined number of frames.

9. The light detection device according to claim 8, further comprising: An operating unit is configured to receive an operation of a user and output a received operation signal, wherein The pixel driving control unit switches the first control timing table and the second control timing table according to an operation signal from the operation unit.

Images