A high-resolution DTC implementation device based on SerDes

Abstract

The present invention belongs to the field of time interval signal generation, and is specifically a high-resolution DTC implementation device based on SerDes, comprising: a clock module, a data encoding module, a SerDes sampling and transmitting module, and a gate signal decomposition module; by using the SerDes sampling and transmitting module to convert low-speed parallel data into high-speed serial data, it is convenient for data processing inside the FPGA, and the required gate signal that can be regarded as high-speed serial data is generated, and the generated time interval signal has a wide dynamic range. In addition, in the DTC implementation process of the present invention, its calibration work is simpler, the implementation difficulty is lower, and it is easy to expand.

Description

Technical Field

[0001] The invention belongs to the field of time interval signal generation, and in particular relates to a high-resolution digital-to-time converter (DTC) implementation device based on a serializer / deserializer (SerDes). Background Art

[0002] The time interval signal is also called the time signal, which indicates the relative delay between two moments. As a time interval signal generating device, DTC is widely used in time domain test systems in the fields of remote sensing positioning and electronic measurement. It is used to convert digital input into analog time and generate a time interval signal with relative delay according to time parameters.

[0003] At present, the implementation methods of DTC can be divided into two categories. One category is the implementation method using application-specific integrated circuits (ASICs). This type of implementation method has problems such as fixed hardware structure, insufficient flexibility, and high cost. The other category is the implementation method based on field programmable gate arrays (FPGAs). Among these methods, FPGA-based DTC has better flexibility and convenience, and is programmable, so it is more widely used.

[0004] There are three main implementation methods of DTC based on FPGA, namely, delay chain method, direct counting method and vernier method. Among them, the DTC implemented based on the delay chain method is relatively cumbersome to calibrate because the delay chain is sensitive to changes in temperature and voltage and has poor stability. Although the circuit structure of the DTC implemented based on the direct counting method is simple, it generates the time interval signal by directly counting the system clock cycle. To achieve a resolution of picoseconds, a system clock frequency of several gigahertz is required, which is difficult to achieve inside the FPGA, so the resolution of the DTC implemented based on the direct counting method is low. The DTC implemented based on the vernier method completes the generation of the time interval signal by counting the period difference of two clocks with similar periods. It starts counting separately when the rising edges of the two clocks coincide for the first time, and counts again when the phases coincide for the second time. The maximum width of the generated time interval signal is only the product of the count value of the slow clock when the phase coincides for the second time and the period difference of the two clocks, so the dynamic range of the DTC implemented based on the vernier method is narrow. Summary of the invention

[0005] In view of this, the present invention proposes a high-resolution DTC implementation device based on SerDes to solve the problem that it is difficult to unify the high resolution, wide dynamic range and low implementation difficulty of the current DTC.

[0006] To solve the above problems, the present invention adopts the following technical solutions:

[0007] A high-resolution DTC implementation device based on SerDes, comprising: a clock module, a data encoding module, a SerDes sampling and transmitting module and a gate signal decomposition module;

[0008] The clock module is used to provide a reference clock signal for the data encoding module and the SerDes sampling and transmitting module;

[0009] The data encoding module is used to obtain the time parameters in the application system, perform operation encoding according to the received reference clock signal and the time parameters, generate a set of parallel data, and send it to the SerDes sampling and transmitting module;

[0010] The SerDes sampling and transmitting module is used to convert the parallel data according to the received reference clock signal to obtain the gate signal and send it to the gate signal decomposition module;

[0011] The gate signal decomposition module decomposes the gate signal into a start pulse signal and an end pulse signal, thereby completing the conversion of the time parameter into a time interval signal; the start pulse signal and the end pulse signal are both step signals.

[0012] Furthermore, the clock module is mainly composed of a crystal oscillator and a phase-locked loop, and the output of the crystal oscillator is connected to the phase-locked loop; the crystal oscillator generates a clock signal with a fixed frequency, which is input into the phase-locked loop, and the phase-locked loop performs frequency multiplication or division processing to generate a reference clock signal with a different frequency.

[0013] Furthermore, the specific encoding method of the data encoding module is:

[0014] The data encoding module calculates the value of n according to the received time parameter and the sampling clock cycle according to formula (1); the data encoding module first outputs a data "0", and then outputs a data "1" every other SerDes sampling clock cycle, and counts the data "1" that has been output. When the number of output data "1" is greater than or equal to n, the output of data "1" is stopped and changed to output data "0", and a group of parallel data is output in this way;

[0015]

[0016] In formula (1), t is the time parameter input to the data encoding module, T is the SerDes sampling clock period, and f is the sampling clock frequency.

[0017] Furthermore, the SerDes sampling and transmitting module includes a transmitter and a phase-locked loop module. The phase-locked loop module is connected to the clock module to divide and multiply the received reference clock signal to obtain a working clock signal; the transmitter receives the working clock signal and converts the parallel data according to the working clock signal to obtain a gate signal; the gate signal is regarded as a serial data of "01111111...1111000".

[0018] Furthermore, the gate signal decomposition module is composed of a gate signal decomposition circuit, a start pulse signal generating circuit and an end pulse signal generating circuit; the gate signal decomposition circuit decomposes the gate signal according to the signal width of the gate signal, the start pulse signal generating circuit is used to generate a start pulse signal, and the end pulse signal generating circuit is used to generate an end pulse signal; the time interval between the start pulse signal and the end pulse signal is the signal width of the gate signal.

[0019] The present invention provides a high-resolution DTC implementation device based on SerDes, which makes full use of the SerDes resources inside the FPGA. It can use a working clock of tens of gigahertz to achieve a time resolution of picoseconds; and the clock module can provide reference clocks of different frequencies. By adjusting the frequency of the reference clock, the resolution of this DTC can be adjusted; the data input to the SerDes sampling and transmitting module by the data encoding module is low-speed parallel data that the FPGA can complete real-time processing, which ensures that the time interval signal generated by this DTC has a wide dynamic range, and the calibration work in the DTC implementation process is simple and the implementation difficulty is low. In addition, the internal resources of the FPGA are rich, which is convenient for the expansion of this DTC based on SerDes; the phase-locked loop module in the SerDes sampling and transmitting module in the FPGA has a performance higher than that of the traditional phase-locked loop, and its shift register has a unified standard delay, so the linear performance of the DTC based on SerDes is good.

[0020] Compared with the existing DTC, the system of the present invention has the advantages of higher resolution, wider dynamic range, and low implementation difficulty, and the entire calibration work is simple and has strong stability, so its application range is wider. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the structure of a DTC implementation device in the embodiment;

[0022] Figure 2 It is a flow chart of a data encoding module in a DTC implementation device of an embodiment;

[0023] Figure 3 Schematic diagram of the structure of the SerDes sampling and transmitting module in the DTC implementation device of the embodiment;

[0024] Figure 4 Schematic diagram of the process of generating a start pulse signal and an end pulse signal in a DTC implementation device of an embodiment. DETAILED DESCRIPTION

[0025] In order to make the technical solutions and advantages of the present invention easier to understand, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0026] Figure 1 This is a schematic diagram of the structure of a DTC implementation device in an embodiment. Figure 4 Schematic diagram of the complete process of generating the start pulse signal and the end pulse signal in the DTC implementation device of the embodiment. Figure 1 , Figure 4 As shown, a DTC implementation device based on SerDes provided in this embodiment includes: a clock module, a data encoding module, a SerDes sampling and transmitting module and a gate signal decomposition module. Among them, the SerDes sampling and transmitting module includes a transmitter and a phase-locked loop module.

[0027] The clock module connects the data encoding module and the phase-locked loop module in the SerDes sampling and transmitting module to provide a synchronous reference clock signal for the data encoding module and the SerDes sampling and transmitting module. The data encoding module receives the time parameters provided by the outside, performs operation encoding according to the received time parameters and the reference clock signal, generates a set of parallel data, and inputs it to the SerDes sampling and transmitting module. The SerDes sampling and transmitting module converts this set of parallel data into a gate signal that can be regarded as high-speed serial data, sends it to the gate signal decomposition module for decomposition, and outputs a start pulse signal and an end pulse signal.

[0028] Figure 2 Flow chart of the data encoding module in the DTC implementation device of the embodiment. Figure 2 As shown, when the time parameter input into the DTC implementation device is sent to the data encoding module, the data encoding module performs operation encoding based on the reference clock signal provided by the clock module and the value of n calculated by formula (1). The specific encoding process is:

[0029] First, a data "0" is output, and then a data "1" is output every SerDes preset sampling clock period T. At the same time, each time a data "1" is output, the data "1" that has been output is counted and judged. When the number of output data "1" is greater than or equal to n, the output of data "1" is stopped and changed to output data "0", and then the encoding is stopped. In this way, parallel data is output and sent to the SerDes sampling transmission module.

[0030] Figure 3 FIG. 1 is a schematic diagram of the structure of the SerDes sampling and transmitting module in the DTC implementation device of the embodiment. Figure 3 As shown in FIG. 1 , the SerDes sampling and transmitting module includes a transmitter and a phase-locked loop module. The phase-locked loop module is connected to the clock module, receives the reference clock signal and performs frequency division and multiplication processing on it to obtain a working clock signal. The transmitter is connected to the phase-locked loop module, and converts the received parallel data into a gate signal according to the working clock signal. The gate signal is a signal that suddenly changes from a low level to a high level, and then suddenly changes from a high level to a low level. In digital logic, the low level is regarded as "0" and the high level is regarded as "1", so a gate signal can be regarded as a serial data of "01111111...1111000". Therefore, the gate signal can be regarded as a group of high-speed serial data such as "01111111...1111000".

[0031] The gate signal decomposition module decomposes the received gate signal to generate a start pulse signal and an end pulse signal. This part is the prior art, so it will not be described in detail in this embodiment.

[0032] The clock operating frequency in FPGA is generally hundreds of megahertz. This implementation utilizes the function of the SerDes sampling and transmitting module to convert low-speed parallel data into high-speed serial data, which not only facilitates data processing inside the FPGA, but also completes the generation of the required gate signal that can be regarded as high-speed serial data, and the generated time interval signal has a wide dynamic range; at the same time, it also utilizes the advantage that the SerDes sampling and transmitting module can use a high-speed clock of tens of gigahertz, and its internal sampling rate can reach tens of gigahertz, and the time resolution can reach the picosecond level. In addition, the clock resources inside the FPGA are very stable, and its shift register also has a uniform standard delay, without the need for complex calibration work, which ensures the linear performance of this SerDes-based high-resolution DTC implementation device while reducing the difficulty of implementation.

[0033] Quantization systems will produce errors. In this embodiment, since the value of n calculated by formula (1) is not necessarily an integer, the number of "1"s in the encoded data generated by the data encoding module in the system is not necessarily equal to n. Therefore, the generated result has an error of ±T, and the error value will not exceed one sampling clock cycle of the SerDes.

[0034] The above embodiments are only some embodiments of the present invention, not all embodiments. Based on the described embodiments, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Claims

1. A high-resolution DTC implementation device based on SerDes, comprising: The clock module, data encoding module, SerDes sampling and transmitting module and gate signal decomposition module are characterized by: The clock module is used to provide a reference clock signal for the data encoding module and the SerDes sampling and transmitting module; The data encoding module is used to obtain the time parameters in the application system, perform operation encoding according to the received reference clock signal and the time parameters, generate a set of parallel data, and send it to the SerDes sampling and transmitting module; the specific encoding method of the data encoding module is: The data encoding module calculates the value of n according to the received time parameter and the sampling clock cycle according to formula (1); the data encoding module first outputs a data "0", and then outputs a data "1" every other SerDes sampling clock cycle, and counts the data "1" that have been output. When the number of output data "1" is greater than or equal to n, the output of data "1" is stopped and the output data is changed to "0", and a group of parallel data is output in this way; In formula (1), t is the time parameter input to the data encoding module, T is the SerDes sampling clock period, and f is the sampling clock frequency; The SerDes sampling and transmitting module is used to convert parallel data according to the received reference clock signal, that is, to convert low-speed parallel data into high-speed serial data, obtain a gate signal and send it to the gate signal decomposition module; the SerDes sampling and transmitting module includes a transmitter and a phase-locked loop module, the phase-locked loop module is connected to the clock module, and the received reference clock signal is divided and multiplied to obtain a working clock signal; the transmitter receives the working clock signal, and converts the parallel data according to the working clock signal to obtain a gate signal; the gate signal is regarded as a serial data of "01111111...1111000"; The gate signal decomposition module decomposes the gate signal into a start pulse signal and an end pulse signal, thereby completing the conversion of the time parameter into a time interval signal; the start pulse signal and the end pulse signal are both step signals; The gate signal decomposition module is composed of a gate signal decomposition circuit, a start pulse signal generating circuit and an end pulse signal generating circuit; the gate signal decomposition circuit decomposes the gate signal according to the signal width of the gate signal, the start pulse signal generating circuit is used to generate a start pulse signal, and the end pulse signal generating circuit is used to generate an end pulse signal; the time interval between the start pulse signal and the end pulse signal is the signal width of the gate signal.

2. The device for realizing high-resolution DTC based on SerDes according to claim 1, characterized in that: The clock module is mainly composed of a crystal oscillator and a phase-locked loop. The output of the crystal oscillator is connected to the phase-locked loop. The crystal oscillator generates a clock signal with a fixed frequency, which is input into the phase-locked loop and multiplied or divided by the phase-locked loop to generate a reference clock signal with different frequencies.

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