A clock data recovery circuit

Abstract

The present invention discloses a clock data recovery circuit, comprising: a control logic encoder, for converting an S signal into coordinates (si, sq, siq) according to a preset lookup table; a phase-locked loop, for generating a four-phase quadrature clock and providing it to a phase rotator; the phase rotator, for performing phase interpolation on the four-phase quadrature clock by changing the coordinates (si, sq, siq), to obtain a center sampling clock and an edge sampling clock; a data sampling circuit, for sampling the center position of data according to the center sampling clock, to obtain a first sampling result; an edge sampling circuit, for sampling the edge position of data according to the edge sampling clock, to obtain a second sampling result; a phase detector, for judging whether the center position and the edge position of the data are sampled, and generating a preset signal; a loop filter, for generating an S signal after performing a logic operation on the preset signal, and outputting the S signal to the control logic encoder; the present invention can improve the linearity of the phase rotator.

Description

Technical Field

[0001] The present invention belongs to the technical field of data communication, and in particular relates to a clock data recovery circuit. Background Art

[0002] The phase interpolation circuit is the core circuit of the CDR (Clock and Data Recovery Circuits), which affects the adjustment accuracy of the clock's sampling of the center and edge positions.

[0003] Currently, common polygonal phase rotators use different intervals and currents on each side, resulting in the same phase change on each side after interpolation, but different phase changes between each side, resulting in uneven phase changes at the corners. Therefore, the phase interval changes at the corners of the clock after phase interpolation by this polygonal phase rotator are inconsistent with the phase interval changes on the sides, resulting in low linearity. This situation is particularly obvious as the number of sides of the polygon increases.

[0004] Therefore, how to improve the phase uniformity at the vertices of the polygon has become an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a clock data recovery circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a clock data recovery circuit, comprising: a control logic encoder, a phase rotator, a phase-locked loop, a data sampling circuit, an edge sampling circuit, a phase detector and a loop filter; wherein,

[0007] The control logic encoder is used to convert the S signal generated by the loop filter into coordinates (si, sq, siq) according to a preset lookup table;

[0008] The phase-locked loop is used to generate a four-phase quadrature clock and provide the four-phase quadrature clock to the phase rotator;

[0009] The phase rotator is used to perform phase interpolation on the four-phase quadrature clock by changing the coordinates (si, sq, siq) to obtain a mutually orthogonal center sampling clock and edge sampling clocks;

[0010] The data sampling circuit is configured to sample the center position of the data according to the center sampling clock to obtain a first sampling result;

[0011] The edge sampling circuit is used to sample the edge position of the data according to the edge sampling clock to obtain a second sampling result;

[0012] The phase detector is configured to determine whether the center sampling clock and the edge sampling clock sample the center position and the edge position of the data according to the first sampling result and the second sampling result, and generate a preset signal;

[0013] The loop filter is configured to generate an S signal after performing a logic operation on the preset signal, and output the S signal to the control logic encoder.

[0014] In one embodiment of the present invention, the phase detector is specifically configured to determine, based on the first sampling result and the second sampling result, whether the phase of the center sampling clock is ahead of or behind the center position of the data; if the phase of the center sampling clock is ahead of the center position of the data, generate an Early signal; if the phase of the center sampling clock is behind the center position of the data, generate a Late signal.

[0015] In one embodiment of the present invention, the phase rotator includes: a clock control circuit and a linearity adjustment circuit, wherein the linearity adjustment circuit is coupled to the control logic encoder and the clock control circuit respectively, and the clock control circuit is coupled to the phase-locked loop and the control logic encoder respectively; wherein,

[0016] The linearity adjustment circuit is used to provide current to the clock control circuit;

[0017] The clock control circuit is used to perform phase interpolation on the four-phase quadrature clock provided by the phase-locked loop to obtain a center sampling clock and an edge sampling clock.

[0018] In one embodiment of the present invention, the linearity adjustment circuit includes: a vertex angle detection circuit and a current adjustment circuit, wherein the output end of the vertex angle detection circuit is coupled to the current adjustment circuit; wherein,

[0019] The vertex angle detection circuit is used to determine whether the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex angle, and turn on the current adjustment circuit according to the determination result;

[0020] The current adjustment circuit is used to maintain the amplitude of the current when the S signal corresponding to the coordinates (si, sq, siq) has not reached the vertex of the phase rotator, and to adjust the amplitude of the current when the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex of the phase rotator so that the phase at the vertex of the phase rotator evenly divides the adjacent phases.

[0021] In one embodiment of the present invention, the current adjustment circuit includes: a first transistor, a second transistor, a third transistor, a first current source, a second current source, and a third current source; wherein,

[0022] The output end of the vertex angle detection circuit is respectively coupled to the control end of the first transistor, the control end of the second transistor and the control end of the third transistor, the first end of the first transistor is coupled to the clock control circuit, and the second end is coupled to the first end of the first current source, the first end of the second transistor is coupled to the clock control circuit, and the second end is coupled to the first end of the second current source, the first end of the third transistor is coupled to the clock control circuit, and the second end is coupled to the first end of the third current source, and the second end of the first current source, the second end of the second current source and the second end of the third current source are all grounded.

[0023] In one embodiment of the present invention, when the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex angle of the phase rotator, the vertex angle detection circuit is specifically used to compare the amplitude of the current current with the amplitude of the first current. If the amplitude of the current current is smaller than the amplitude of the first current, a low-level signal is sent to the control end of the first transistor, a high-level signal is sent to the control end of the second transistor, and a low level is sent to the control end of the third transistor respectively; if the amplitude of the current current is greater than the amplitude of the first current, a high-level signal is sent to the control end of the first transistor, the control end of the second transistor, and the control end of the third transistor respectively.

[0024] In one embodiment of the present invention, when the S signal corresponding to the coordinates (si, sq, siq) does not reach the vertex angle of the phase rotator, the vertex angle detection circuit is specifically used to send a high-level signal to the control ends of the first transistor and the second transistor respectively, and to send a low-level signal to the control end of the third transistor.

[0025] Compared with the related art, the present invention has the following beneficial effects:

[0026] The present invention provides a clock data recovery circuit, which adjusts the phase at the top corner to evenly divide the adjacent phases, calculates the change of the current at this time relative to the original current, and then adjusts the current so that the phase change at this location is uniform, thereby improving the linearity of the phase rotator.

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of a phase rotator in the related art;

[0029] Figure 2 Schematic diagram of the change of phase change step of the phase rotator with the coordinates (si, sq, siq) in the related art;

[0030] Figure 3 This is a schematic structural diagram of a clock data recovery circuit provided by an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of a clock sampling data provided by an embodiment of the present invention;

[0032] Figure 5 1 is a structural diagram of a phase rotator provided by an embodiment of the present invention;

[0033] Figure 6 This is a structural diagram of a linearity adjustment circuit provided by an embodiment of the present invention;

[0034] Figure 7 is an equivalent circuit diagram of a current regulating circuit provided by an embodiment of the present invention;

[0035] Figure 8 is another equivalent circuit diagram of the current regulation circuit provided by an embodiment of the present invention;

[0036] Figure 9 is another equivalent circuit diagram of the current regulation circuit provided by an embodiment of the present invention;

[0037] Figure 10 Schematic diagram of the change in phase change step size of the phase rotator provided by an embodiment of the present invention as a function of coordinates (si, sq, siq);

[0038] Figure 11 This is a schematic diagram of a phase rotator provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0040] Figure 1 This is a schematic diagram of a phase rotator in the related art. Figure 2 Schematic diagram of the phase change step size of the phase rotator in the related art as the coordinates (si, sq, siq) change. Figure 1 As shown, in the related art, the octagon is divided into 4 quadrants in the form of si (7 units), sq (7 units), siq (9 units) coordinates to achieve the positioning of the S code value that divides the octagon into 64 phases. In this way, the code value of the S signal can be converted to (si, sq, siq) to perform the phase interpolation function of the phase rotator 20. Figure 2As shown, when the code value of the S signal jumps, the phase corresponding to each S will also change. The phase step of the adjacent S changes can be determined by calculation, adjusting si, sq and siq, and after restoring the clock with the correct phase through phase interpolation, the center position and edge position of the data are sampled respectively to recover the data.

[0041] In the related art, the octagonal phase rotator changes si, sq, or siq on the eight sides of the octagon, and the phase change at this time is relatively uniform. However, when S reaches the top angle, that is, the dividing point where si, sq, or siq changes, this is also the dividing point where the phase change is uneven, resulting in uneven phase change at the top angle, which makes the phase change here uneven, resulting in a decrease in the phase adjustment accuracy during interpolation of the phase rotator.

[0042] In view of this, the present invention provides a clock data recovery circuit.

[0043] Figure 3 FIG. 1 is a schematic diagram of a clock data recovery circuit provided by an embodiment of the present invention. Figure 3 As shown, an embodiment of the present invention provides a clock data recovery circuit, comprising: a control logic encoder 10, a phase rotator 20, a phase-locked loop 30, a data sampling circuit 40, an edge sampling circuit 50, a phase detector 60 and a loop filter 70; wherein,

[0044] The control logic encoder 10 is used to convert the S signal generated by the loop filter 70 into coordinates (si, sq, siq) according to a preset lookup table;

[0045] A phase-locked loop 30 is configured to generate a four-phase quadrature clock and provide the four-phase quadrature clock to the phase rotator 20;

[0046] The phase rotator 20 is used to perform phase interpolation on the four-phase quadrature clock by changing the coordinates (si, sq, siq) to obtain a mutually orthogonal center sampling clock and edge sampling clock;

[0047] The data sampling circuit 40 is configured to sample the center position of the data according to the center sampling clock to obtain a first sampling result;

[0048] The edge sampling circuit 50 is used to sample the edge position of the data according to the edge sampling clock to obtain a second sampling result;

[0049] The phase detector 60 is used to determine whether the center position and the edge position of the data are sampled according to the first sampling result and the second sampling result, and generate a preset signal;

[0050] The loop filter 70 is configured to generate an S signal after performing a logic operation on the preset signal, and output the S signal to the control logic encoder 10 .

[0051] Optionally, the phase detector 60 is specifically used to determine whether the phase of the center sampling clock is ahead of or behind the center position of the data based on the first sampling result and the second sampling result; if the phase of the center sampling clock is ahead of the center position of the data, an Early signal is generated; if the phase of the center sampling clock is behind the center position of the data, a Late signal is generated.

[0052] Since it is a high-speed circuit, it is difficult for the phase-locked loop 30 to provide a clock frequency that is the same as the data rate. Therefore, the present invention adopts a half-rate clock data recovery circuit.

[0053] In this embodiment, the clock data recovery circuit includes: a control logic encoder 10, a phase rotator 20, a phase-locked loop 30, a data sampling circuit 40, an edge sampling circuit 50, a phase detector 60 and a loop filter 70; specifically, the control logic encoder 10 is coupled to the loop filter 70 and is used to convert the S signal generated by the loop filter 70 into coordinates (si, sq, siq) according to a preset lookup table; the phase-locked loop 30 is coupled to the phase rotator 20 and is used to generate a four-phase quadrature clock and send the four-phase quadrature clock to the phase rotator 20; the phase rotator 20 is coupled to the control logic encoder 10 and the phase-locked loop 30, and the phase rotator 20 performs phase interpolation on the four-phase quadrature clock provided by the phase-locked loop 30 based on the coordinates (si, sq, siq) provided by the control logic encoder 10, thereby generating four-phase quadrature clocks CLK_OUT1, CLK_OUT2, CLK_OUT3, and CLK_OUT4, i.e., the center sampling clock C LK_OUT3, CLK_OUT4 and edge sampling clocks CLK_OUT1, CLK_OUT2; the data sampling circuit 40 is coupled to the phase rotator 20, and is used to sample the center position of the data according to the center sampling clocks CLK_OUT3, CLK_OUT4 to obtain a first sampling result; the edge sampling circuit 50 is coupled to the phase rotator 20, and is used to sample the edge position of the data according to the edge sampling clocks CLK_OUT1, CLK_OUT2 to obtain a second sampling result; the phase detector 60 is coupled to the data sampling circuit 40 and the edge sampling circuit 50, and is used to determine whether the center position and edge position of the data are sampled according to the first sampling result and the second sampling result, and generate a preset signal; the loop filter 70 is coupled to the phase detector 60, and is used to generate an S signal after performing a logical operation on the preset signal, and output the S signal to the control logic encoder 10 to implement the phase adjustment function of the phase rotator 20.

[0054] For example, the four-phase quadrature clock includes: CLK_0°, CLK_180°, CLK_90° and CLK_270°. Since the clock frequency is half of the data rate, the edge positions of CLK_0° and CLK_180° sample data, and the center positions of CLK_90° and CLK_270° sample data. For the schematic diagram of clock sampling data, please refer to Figure 4 .

[0055] Figure 5 FIG. 1 is a structural diagram of a phase rotator provided by an embodiment of the present invention. Figure 5 As shown, the phase rotator 20 includes: a clock control circuit 201 and a linearity adjustment circuit 202, the linearity adjustment circuit 202 is coupled to the control logic encoder 10 and the clock control circuit 201 respectively, and the clock control circuit 201 is coupled to the phase-locked loop 30 and the control logic encoder 10 respectively; wherein,

[0056] The linearity adjustment circuit 202 is used to provide current to the clock control circuit 201;

[0057] The clock control circuit 201 is used to perform phase interpolation on the four-phase quadrature clock provided by the phase-locked loop 30 to obtain center sampling clocks CLK_OUT3 and CLK_OUT4 and edge sampling clocks CLK_OUT1 and CLK_OUT2.

[0058] Optionally, the linearity adjustment circuit 202 includes: a vertex angle detection circuit and a current adjustment circuit, wherein the output end of the vertex angle detection circuit is coupled to the current adjustment circuit;

[0059] The vertex angle detection circuit is used to determine whether the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex angle, and turn on the current adjustment circuit according to the judgment result;

[0060] A current adjustment circuit is configured to maintain the amplitude of the current when the S signal corresponding to the coordinates (si, sq, siq) has not yet reached the top corner of the phase rotator 20, and to adjust the amplitude of the current when the S signal corresponding to the coordinates (si, sq, siq) reaches the top corner of the phase rotator 20 so that the phase at the top corner of the phase rotator 20 evenly divides the adjacent phases.

[0061] It should be understood that in the clock data recovery circuit provided by the present invention, the phase at the top corner is adjusted to evenly divide the adjacent phases, and the change in current at this time relative to the original current is calculated, and then the current is adjusted so that the phase change here is uniform, thereby improving the linearity of the phase rotator.

[0062] Figure 7 This is an equivalent circuit diagram of the current regulation circuit provided by the embodiment of the present invention. Figure 7As shown, the current adjustment circuit includes: a first transistor M1, a second transistor M2, a third transistor M3, a first current source, a second current source, and a third current source; wherein,

[0063] An output end of the vertex angle detection circuit is coupled to a control end of the first transistor M1, a control end of the second transistor M2, and a control end of the third transistor M3, respectively. A first end of the first transistor M1 is coupled to the clock control circuit 201, and a second end is coupled to a first end of the first current source. A first end of the second transistor M2 is coupled to the clock control circuit 201, and a second end is coupled to a first end of the second current source. A first end of the third transistor M3 is coupled to the clock control circuit 201, and a second end is coupled to a first end of the third current source. The second end of the first current source, the second end of the second current source, and the second end of the third current source are all grounded.

[0064] In practical applications, it can be implemented through transistor-level circuits or code. Specifically, taking the code method as an example, the vertex detection circuit is implemented through Verilog code to control the increase, maintenance or decrease of the current; for example, in S3, S 28 , S 35 , S 60 When the phase is adjusted, the current increases and the 12 , S 19 , S 44 , S 51 When the angle of the vertex is less than 0.05, the current decreases after phase adjustment. When the vertex angle is not reached, the current remains unchanged. The Verilog code for the vertex angle detection circuit is as follows:

[0065]

[0066]

[0067] When the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex of the phase rotator 20, the vertex detection circuit is specifically used to compare the amplitude of the current with the amplitude of the first current. It should be understood that when the first current amplitude is when the S signal corresponding to the coordinates (si, sq, siq) does not reach the vertex of the phase rotator 20, see Figure 9In the equivalent circuit shown, the vertex detection circuit sends a high-level signal to the control end of the first transistor, sends a high-level signal to the control end of the second transistor, and sends a low-level signal to the control end of the third transistor (sel1=1, sel2=1, sel3=0) to obtain a first current amplitude of I=I1+I2. First, all the phase clocks interpolated by the phase rotator are obtained. Since the phase at the vertex is uneven, it is necessary to obtain a new vertex phase that divides the adjacent phases at the vertex, and then determine the current current required for the phase. Then, the current current is compared with the amplitude of the first current and the switches of sel1, sel2, and sel3 are selected to obtain the required current, so that the phase here can be forced to remain uniform. For example, if when the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex of the phase rotator 20, the amplitude of the current corresponding to the new phase is less than the amplitude of the first current, then please refer to Figure 8 In the equivalent circuit shown in FIG. 1 , the vertex angle detection circuit sends a low-level signal to the control terminal of the first transistor, sends a high-level signal to the control terminal of the second transistor, and sends a low-level signal to the control terminal of the third transistor (sel1=0, sel2=1, sel3=0). The amplitude of the current is I=I2. If the amplitude of the current corresponding to the new phase is greater than the amplitude of the first current, then refer to Figure 7 In the equivalent circuit shown, the vertex detection circuit sends high-level signals to the control end of the first transistor, the control end of the second transistor, and the control end of the third transistor (sel1=1, sel2=1, sel3=1) respectively, and the amplitude of the current is I=I1+I2+I3.

[0068] As can be seen from the above process, since each phase in a cycle corresponds to a current, the first current amplitude in the present invention can be pre-set. All clock phases corresponding to the first current amplitude, the new vertex phase, the new current corresponding to the new vertex phase, and the current ΔI to be adjusted, i.e., I1 or I3, can all be pre-calculated, thereby improving the linearity of the phase rotator 20 through the linearity adjustment circuit.

[0069] Figure 10 Schematic diagram of the change of the phase change step of the phase rotator according to the embodiment of the present invention with respect to the coordinates (si, sq, siq). For example, see Figure 10 The phase of S3 is the average of the phases from S2 to S4. Phase balancing is achieved by making the phase change from S2 to S3 equal to the change from S3 to S4, and then the purpose of balancing the adjacent phases here is achieved by adjusting the current. This design method compresses the phase change step range of S, thereby improving the linearity of the phase rotator 20.

[0070] Figure 11is a schematic diagram of a phase rotator provided by an embodiment of the present invention. Figure 11 It should be noted that the code value S at the top corner of the phase rotator 20 does not change, but the phase interpolated by the S code value here is adjusted and the phase interpolated by the adjacent S code values ​​is evenly divided, thereby improving the linearity of the phase rotator 20.

[0071] It can be seen from the above embodiments that the beneficial effects of the present invention are:

[0072] The present invention provides a clock data recovery circuit, which adjusts the phase at the top corner to evenly divide the adjacent phases, calculates the change of the current at this time relative to the original current, and then adjusts the current so that the phase change at this location is uniform, thereby improving the linearity of the phase rotator.

[0073] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0074] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0075] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0076] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A clock data recovery circuit, characterized in that: include: Control logic encoder, phase rotator, phase locked loop, data sampling circuit, edge sampling circuit, phase detector and loop filter; wherein, The control logic encoder is used to convert the S signal generated by the loop filter into coordinates (si, sq, siq) according to a preset lookup table; The phase-locked loop is used to generate a four-phase quadrature clock and provide the four-phase quadrature clock to the phase rotator; The phase rotator is used to perform phase interpolation on the four-phase quadrature clock by changing the coordinates (si, sq, siq) to obtain a mutually orthogonal center sampling clock and edge sampling clocks; The data sampling circuit is configured to sample the center position of the data according to the center sampling clock to obtain a first sampling result; The edge sampling circuit is used to sample the edge position of the data according to the edge sampling clock to obtain a second sampling result; The phase detector is configured to determine whether the center position and the edge position of the data are sampled according to the first sampling result and the second sampling result, and generate a preset signal; The loop filter is configured to generate an S signal after performing a logic operation on the preset signal, and output the S signal to the control logic encoder; The phase rotator includes: a clock control circuit and a linearity adjustment circuit, wherein the linearity adjustment circuit is coupled to the control logic encoder and the clock control circuit respectively, and the clock control circuit is coupled to the phase-locked loop and the control logic encoder respectively; wherein, The linearity adjustment circuit includes: a vertex angle detection circuit and a current adjustment circuit, wherein the output end of the vertex angle detection circuit is coupled to the current adjustment circuit; The vertex angle detection circuit is used to determine whether the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex angle, and turn on the current adjustment circuit according to the determination result; The current adjustment circuit is used to maintain the amplitude of the current when the S signal corresponding to the coordinates (si, sq, siq) has not reached the vertex of the phase rotator, and to adjust the amplitude of the current when the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex of the phase rotator so that the phase at the vertex of the phase rotator evenly divides the adjacent phases.

2. The clock data recovery circuit according to claim 1, wherein: The phase detector is specifically configured to determine, based on the first sampling result and the second sampling result, whether the phase of the center sampling clock is ahead of or behind the center position of the data; if the phase of the center sampling clock is ahead of the center position of the data, generate an Early signal; if the phase of the center sampling clock is behind the center position of the data, generate a Late signal.

3. The clock data recovery circuit according to claim 1, wherein: The linearity adjustment circuit is used to provide current to the clock control circuit; The clock control circuit is used to perform phase interpolation on the four-phase quadrature clock provided by the phase-locked loop to obtain a center sampling clock and an edge sampling clock.

4. The clock data recovery circuit according to claim 1, wherein: The current adjustment circuit includes: a first transistor, a second transistor, a third transistor, a first current source, a second current source, and a third current source; wherein, The output end of the vertex angle detection circuit is respectively coupled to the control end of the first transistor, the control end of the second transistor and the control end of the third transistor, the first end of the first transistor is coupled to the clock control circuit, and the second end is coupled to the first end of the first current source, the first end of the second transistor is coupled to the clock control circuit, and the second end is coupled to the first end of the second current source, the first end of the third transistor is coupled to the clock control circuit, and the second end is coupled to the first end of the third current source, and the second end of the first current source, the second end of the second current source and the second end of the third current source are all grounded.

5. The clock data recovery circuit according to claim 4, wherein: When the S signal corresponding to the coordinates (si, sq, siq) reaches the vertex angle of the phase rotator, the vertex angle detection circuit is specifically used to compare the amplitude of the current current with the amplitude of the first current. If the amplitude of the current current is smaller than the amplitude of the first current, a low-level signal is sent to the control end of the first transistor, a high-level signal is sent to the control end of the second transistor, and a low level is sent to the control end of the third transistor respectively; if the amplitude of the current current is greater than the amplitude of the first current, a high-level signal is sent to the control end of the first transistor, the control end of the second transistor, and the control end of the third transistor respectively.

6. The clock data recovery circuit according to claim 4, wherein: When the S signal corresponding to the coordinates (si, sq, siq) does not reach the vertex angle of the phase rotator, the vertex angle detection circuit is specifically used to send a high-level signal to the control ends of the first transistor and the second transistor respectively, and send a low-level signal to the control end of the third transistor.

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