Digital-to-analog conversion circuit, debugging method, and circuit debugging system

Abstract

The application provides a digital-to-analog conversion circuit, a debugging method and a circuit debugging system. The digital-to-analog conversion circuit is used for converting input digital quantity into output analog quantity. The digital-to-analog conversion circuit comprises a conversion network, an analog switch and a summation circuit. The conversion network is a ladder network. The ladder network comprises a plurality of bit conversion units with consistent parameters. The digital-to-analog conversion circuit further comprises a first switch array. The plurality of bit conversion units with consistent parameters are cascaded with each other through the first switch array. The first switch array is used for switching the cascading sequence between the bit conversion units. The debugging method of the digital-to-analog conversion circuit is used for the digital-to-analog conversion circuit. The debugging system comprises the digital-to-analog conversion circuit, a reference power supply, a measurer and a control unit. The digital-to-analog conversion circuit, the debugging method and the circuit debugging system of the application have high conversion precision and are convenient to manufacture.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to digital-to-analog converter circuits. Background Technology

[0002] With the development of global informatization, digital-to-analog converters (DACs) have become an indispensable component in many electronic systems. A DAC is a converter that converts discrete input digital quantities (D) in both amplitude and time. in Converted into a continuous analog output U in both time and amplitude out Input digital quantity D in Includes multiple binary bits D arranged sequentially from least significant bit to most significant bit. i (where i = 0, 1, 2, ..., m) A digital-to-analog converter typically includes a reference power supply, a conversion network, and a summing circuit. The reference power supply provides a reference voltage U. ref Or a reference current. The conversion network includes multiple bit conversion units, each of which is connected to the input digital quantity D. in Each binary bit corresponds one-to-one, and the bit conversion unit converts the corresponding binary bit into a weighted analog quantity U. i , The summing circuit adds the weighted analog quantities and amplifies them to obtain the output analog quantity U. out Output analog signal , where A is the gain of the amplifier.

[0003] The accuracy of a digital-to-analog converter (DAC) is a crucial indicator of its performance. It determines the amount of distortion and noise generated during the conversion process. DACs can be categorized into traditional parameter-weighted networks and ladder networks based on their conversion networks. Typical structures of traditional parameter-weighted networks include weighted resistor networks, weighted current networks, and weighted capacitor networks. The component parameters of the conversion unit increase geometrically, resulting in an excessively wide range of parameters that makes it difficult to guarantee the accuracy of parameter ratios. Typical structures of ladder networks include R-2R ladder resistor networks and C-2C switched capacitor networks. An example of an R-2R ladder resistor network is the "R-2R ladder network" disclosed in the book "CMOS INTEGRATED ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS" (ISBN 1-4020-7500-6). C-2C switched capacitor networks are exemplified by the English paper titled "The R-2R and C-2C Ladders" published in the journal "IEEE SOLID-STATE CIRCUITS MAGAZINE," which describes "The basic C-2C ladder." In a ladder network, all the bit-switching units are identical. For instance, in a ladder resistor network, all resistors have only two component parameters: R and 2R. The resistance values ​​are relatively similar, facilitating integration.

[0004] With the development of integrated circuits, more and more digital-to-analog converters are being integrated onto system-on-a-chip (SoC), which also requires converter designs to be more streamlined to reduce costs. At the same time, it is necessary to minimize device deviations and mismatches caused by manufacturing processes.

[0005] For ladder networks, as the position of the transition bit increases, taking binary as an example, from LSB (least significant bit) to MSB (most significant bit), the precision requirement of its cascaded transition units increases by a multiple of 2, which increases the manufacturing difficulty of integrated circuits.

[0006] Chinese patent CN113131942A, entitled "A Digital-to-Analog Converter," discloses a segmented structure that combines an R-2R cascaded structure with a resistor voltage divider to improve the monotonicity of the converter in the high-bit portion (MSB). However, the accuracy requirements of the resistor string in the MSB of this structure also require sufficient margin to meet the overall conversion accuracy requirements. Therefore, the resistor area in this part needs to be designed to be large enough to meet the accuracy requirements.

[0007] Chinese patent CN110572159A, entitled "A Digital-to-Analog Converter with an R-2R Ladder Network Architecture," discloses an R-2R cascaded digital-to-analog converter. It improves the matching of each stage in the cascaded structure by adjusting the size and number of series switches. However, due to process drift, this method cannot improve the consistency of the converter's accuracy in practice.

[0008] Chinese patent CN109547026A, entitled "A Current-Driven Digital-to-Analog Converter Based on an R-2R Resistor Network," discloses a cascaded R-2R current-driven digital-to-analog converter circuit. This design neglects the matching problem between the resistors and the current drivers, which will still lead to accuracy issues in actual production.

[0009] The chip “AD7568, Octal 12-bit DAC, datasheet, Analog Devices Inc” is a typical resistor ladder digital-to-analog converter circuit. Due to the limitations of the manufacturing process (resistor matching of approximately 0.5%), its accuracy is limited to 12 bits.

[0010] US Patent Publication No. US6400300B1 describes a circuit that uses an additional auxiliary resistor string to calibrate the main resistor string to compensate for the decrease in DAC accuracy caused by resistor mismatch in the chip. This circuit is complex and requires additional power consumption. Summary of the Invention

[0011] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a digital-to-analog converter circuit that has high conversion accuracy and is easy to manufacture.

[0012] To achieve the above and other related objectives, the present invention provides a digital-to-analog converter (DAC) circuit for converting an input digital quantity into an output analog quantity. The DAC circuit includes a conversion network, analog switches, and a summing circuit. The conversion network includes multiple cascaded bit conversion units, each of which converts each binary bit of the input digital quantity into a weighted analog quantity of corresponding size. The summing circuit adds the weighted analog quantities to obtain the output analog quantity. The conversion network is a ladder network, and the ladder network includes multiple bit conversion units with identical parameters. The DAC circuit also includes a first switch array, where the multiple bit conversion units with identical parameters are cascaded through the first switch array. The first switch array is used to switch the cascading order of the bit conversion units.

[0013] In one embodiment of the present invention, the trapezoidal network includes at least one of an R-2R trapezoidal resistor network, a C-2C switched capacitor network, or an R-2R current steering network.

[0014] In one embodiment of the present invention, the digital-to-analog conversion circuit further includes a storage unit for storing sorted data, and the first switch array switches the cascade order between the bit conversion units according to the sorted data.

[0015] In one embodiment of the present invention, the first switch array includes multiple row lines, multiple column lines, and multiple numerically controlled switches. The row lines and column lines intersect each other, and the numerically controlled switches are connected at the intersections of the row lines and column lines. The numerically controlled switches connect or disconnect the intersecting row lines and column lines according to the sorting data. The bit conversion unit has input terminals, output terminals, and numerically controlled terminals. The input terminals of each bit conversion unit are connected to different column lines, and the output terminals of each bit conversion unit are connected to different row lines. The numerically controlled terminals of each bit conversion unit are grounded or connected to a reference power supply through corresponding analog switches.

[0016] In one embodiment of the present invention, the digital-to-analog converter circuit has a parallel input pin for receiving the input digital quantity. The digital-to-analog converter circuit further includes a digital sorting module coupled between the parallel input pin and the ladder network. The digital sorting module is used to: reorder each binary bit of the input digital quantity according to the sorting data to obtain a rearranged digital quantity, and input the rearranged digital quantity into the ladder network.

[0017] In one embodiment of the present invention, the digital sorting module includes a data selector and / or a data distributor.

[0018] To achieve the above and other related objectives, the present invention also provides a debugging method for a digital-to-analog converter circuit, used for debugging the aforementioned digital-to-analog converter circuit, the debugging method comprising:

[0019] Step 1: Select a bit conversion unit as the precision test unit, and set the input digital quantity so that only the weighted analog quantity output by the precision test unit is non-zero, while the weighted analog quantity output by the other bit conversion units is zero.

[0020] Step 2: Record the measured output value of the output analog quantity corresponding to the weighted analog quantity;

[0021] Step 3: Calculate the error between the measured output value and the preset value;

[0022] Step four: Repeat steps one through three to obtain the error of each bit conversion unit;

[0023] Step 5: Readjust the switching state of the first switch array according to the error of each bit conversion unit, so that each bit conversion unit reaches a new cascaded state. In the new cascaded state, the bit conversion unit with smaller error converts the higher bit of the input digital quantity.

[0024] In one embodiment of the present invention, step three specifically includes:

[0025] The difference is obtained by subtracting the measured output value from the preset value;

[0026] The error is obtained by taking the absolute value of the difference.

[0027] To achieve the above and other related objectives, the present invention also provides a debugging system, including the aforementioned digital-to-analog converter circuit, reference power supply, measuring instrument, and control unit; the reference power supply provides a reference voltage or reference current to the conversion network; the control unit is used to send a first input digital quantity to the parallel input pin, the first input digital quantity causing only one of the bit conversion units to output a non-zero weighted analog quantity, and the bit conversion unit with the non-zero weighted analog quantity output is a precision testing unit; the digital-to-analog converter circuit converts the first input digital quantity into a first measured analog quantity; the measuring instrument converts the first measured analog quantity into a first measured digital quantity; the control unit is further used to compare the first measured digital quantity with a preset value to obtain the precision data of the precision testing unit; the control unit also obtains the sorting data based on the precision data of each conversion unit.

[0028] To achieve the above and other related objectives, the present invention also provides a debugging system, including the aforementioned digital-to-analog converter circuit, reference power supply, measuring instrument, and control unit; the reference power supply provides a reference voltage or reference current to the conversion network; the control unit is used to send first sorting data to the storage unit, the first sorting data causing only one bit conversion unit to be connected in the conversion network, and the bit conversion unit connected to the conversion network is a precision testing unit; the digital-to-analog converter circuit converts the input digital quantity into a first measured analog quantity; the measuring instrument converts the first measured analog quantity into a first measured digital quantity; the control unit is further used to compare the first measured digital quantity with a preset value to obtain the precision data of the precision testing unit; the control unit also obtains the sorting data based on the precision data of each conversion unit.

[0029] As described above, the digital-to-analog converter circuit of the present invention has high conversion accuracy and is easy to manufacture. Attached Figure Description

[0030] Figure 1 The diagram shows the structural block diagram of an existing digital-to-analog converter circuit.

[0031] Figure 2 The diagram shown is a detailed circuit diagram of an existing digital-to-analog converter.

[0032] Figure 3 The diagram shown is a structural block diagram of an embodiment of the digital-to-analog converter circuit of the present invention.

[0033] Figure 4 The diagram shown is a structural block diagram of an embodiment of the debugging system of the present invention.

[0034] Figure 5 The diagram shown is a structural block diagram of another embodiment of the digital-to-analog converter circuit of the present invention. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] Figure 1 This is a schematic block diagram of an existing digital-to-analog converter circuit used to convert the input digital quantity D... in Convert to output analog quantity U out See also Figure 1 Existing digital-to-analog converter circuits include conversion networks and analog switches ( Figure 1 (Not shown in the image) and a summing circuit, the conversion network includes multiple cascaded bit conversion units, each of which converts each binary bit of the input digital quantity into a weighted analog quantity of corresponding size. The summing circuit is used to add the weighted analog quantities to obtain the output analog quantity U. out Summation circuits typically include an amplifier to amplify the output analog signal before outputting it. Existing digital-to-analog converters generally also include a reference voltage U. ref Or a reference power supply with a reference current. It should be noted that... Figure 1 This is only a simplified schematic diagram. Actual circuit structures are complex and varied. Figure 1 The direction of the arrow in the diagram may be the same as or opposite to the actual direction of the current.

[0038] Figure 2 This diagram illustrates the structure of an existing R-2R ladder network digital-to-analog converter circuit. The ladder network includes m+1 bit conversion units, each with an input terminal TI, an output terminal TO, and a control terminal TD. Ignoring manufacturing errors, each conversion unit has the same structure and parameters, including a resistor R and a resistor 2R. The first end of resistor R is connected to the input terminal TI, and the second end is connected to the output terminal TO. The first end of resistor 2R is connected to the input terminal TI, and the second end is connected to the control terminal TD. The control terminal TD is connected to an analog switch S, which selects between ground and a reference power supply. Although this structure avoids exponential growth of the parameters of each bit conversion unit through cascading, it still requires exponential growth in the accuracy of each bit conversion unit.

[0039] To further improve the conversion accuracy of digital-to-analog converters (DACs), most known improvements are limited to adding compensation components to each bit conversion unit to improve the accuracy of each unit individually, thereby increasing the overall accuracy of the DAC. These existing improvements fail to fully utilize the inconsistencies in manufacturing processes to directly improve the conversion accuracy of the DAC from the overall layout perspective.

[0040] To balance conversion accuracy and manufacturing complexity, please refer to Figures 3-5 This invention provides a digital-to-analog converter circuit for converting input digital quantity D... in Convert to output analog quantity U out A digital-to-analog converter circuit includes a conversion network and analog switches. Figure 3 (Not shown in the diagram) and a summing circuit, the conversion network includes multiple cascaded bit conversion units. Each bit conversion unit converts each binary bit of the input digital quantity into a weighted analog quantity of corresponding size. The summing circuit is used to add the weighted analog quantities to obtain the output analog quantity. The conversion network is a ladder network, which includes multiple bit conversion units with identical parameters. The digital-to-analog conversion circuit also includes a first switch array. The multiple bit conversion units with identical parameters are cascaded through the first switch array, which is used to switch the cascading order between the bit conversion units.

[0041] In the digital-to-analog converter circuit of the present invention, after being manufactured using semiconductor technology, the cascading order between the bit conversion units is not fixed; instead, each bit conversion unit is connected to a first switch array. Therefore, it is possible to change the cascading order between the bit conversion units by adjusting the first switch array before or after product production, thereby selecting a cascading order that optimizes the overall conversion accuracy and improving the digital-to-analog converter circuit without adding additional error compensation components. It should be noted that in this embodiment, the first switch array itself can employ existing technologies, such as matrix switches or programmable circuits.

[0042] As can be seen from the above principles, the solution of this invention can be achieved simply by requiring the conversion network to include multiple identical repeating units. In fact, depending on the type of components, the ladder network can have various existing alternative forms. For example, the ladder network of this invention can be one of an R-2R ladder resistor network, a C-2C switched capacitor network, or an R-2R current steering network, or any combination of two. Of course, other ladder networks besides the three structures mentioned above may also exist in the prior art, and these still fall within the scope of protection of this invention, and will not be listed here again.

[0043] refer to Figure 4 In one embodiment, the digital-to-analog converter circuit further includes a storage unit for storing sorted data. The first switch array switches the cascading order between the conversion units according to the sorted data. By setting up the storage unit, this embodiment can maintain the conversion network in an optimal cascading state when the digital-to-analog converter circuit is integrated into the same chip.

[0044] refer to Figure 5 Specifically, in one embodiment, the first switch array includes multiple row lines, multiple column lines, and multiple digitally controlled switches. The row lines and column lines intersect each other, and the digitally controlled switches are connected at the intersections of the row lines and column lines. The digitally controlled switches turn the intersecting row lines and column lines on or off according to the sorting data. The bit conversion unit has an input terminal TI, an output terminal TO, and a digitally controlled terminal TD. The input terminal of each conversion unit is connected to a different column line, and the output terminal of each conversion unit is connected to a different row line. The digitally controlled terminal of each conversion unit is grounded or connected to a reference power supply through a corresponding analog switch. It should be noted that the row lines and column lines in this embodiment are relative and are independent of their actual spatial orientation.

[0045] Specifically, the summing circuit of the digital-to-analog converter includes Figure 5In the amplifier OP, the first row line LR-1 of the first switch array is grounded through resistor 2R, and the first column line LC-1 of the first switch array is connected to the input terminal of the amplifier OP. Let the bit conversion unit with the lowest measured accuracy be the worst conversion unit. Since the input terminal TI of the worst conversion unit can be connected to any row line through each digitally controlled switch, the input terminal TI of the worst conversion unit can be connected to the first row line LR-1 by sorting data to obtain the minimum weight. Thus, under the same manufacturing error conditions, the harm of manufacturing error can be minimized. The arrangement method of the remaining bit conversion units follows the same principle and will not be elaborated further.

[0046] Since the actual spatial positions of each bit conversion unit in the conversion network are fixed after semiconductor manufacturing, the first switch array only changes the logical cascade position, not the spatial position. Therefore, the order of each binary bit of the input digital quantity needs to be adjusted accordingly during use. To save users from adjusting the sequence of input digital quantities and to make the digital-to-analog converter circuit more convenient to use, in one embodiment, the digital-to-analog converter circuit has parallel input pins (… Figure 5 (Not shown in the diagram) The parallel input pin is used to receive the input digital quantity. The digital-to-analog converter circuit also includes a digital sorting module, which is coupled between the parallel input pin and the ladder network. The digital sorting module is used to: reorder the binary bits of the input digital quantity according to the sorting data to obtain the rearranged digital quantity, and input the rearranged digital quantity into the ladder network.

[0047] Specifically, in one embodiment, the number sorting module includes a data selector and / or a data distributor. For example, the number sorting module may include multiple data selectors, with the input of each data selector connected to a parallel input pin, and the output of different data selectors connected to different bit conversion units. The connection method of the data distributor is the reverse, and will not be described again. The control signals for the data selectors and / or data distributors come from the memory unit.

[0048] The present invention also provides a debugging method for a digital-to-analog converter circuit, used for debugging the digital-to-analog converter circuit of any of the above embodiments, the debugging method comprising:

[0049] Step 1: Select a bit conversion unit as the precision test unit, and set the input digital quantity so that only the weighted analog quantity output by the precision test unit is non-zero, while the weighted analog quantity output by the other bit conversion units is zero.

[0050] Step 2: Record the measured output values ​​of the output analog quantities corresponding to the weighted analog quantities;

[0051] Step 3: Calculate the error between the measured output value and the preset value;

[0052] Step 4: Repeat steps 1 through 3 to obtain the error of each conversion unit;

[0053] Step 5: Readjust the switching state of the first switch array according to the error of each conversion unit, so that each conversion unit reaches a new cascaded state. In the new cascaded state, the bit conversion unit with smaller error corresponds to the higher bit of the input digital quantity.

[0054] Specifically, in one embodiment, step three includes: subtracting the measured output value from the preset value to obtain the difference; and taking the absolute value of the difference to obtain the error.

[0055] Specifically, in one embodiment, the preset value in step three is a theoretically calculated value under ideal conditions. In another embodiment, the preset value in step three is the root mean square (RMS) of each measured output value.

[0056] refer to Figure 4 The present invention also provides a debugging system, including a digital-to-analog converter circuit, a reference power supply, a measuring instrument, and a control unit; the reference power supply provides a reference voltage or reference current to the conversion network; the control unit is used to send a first input digital quantity to the parallel input pin, the first input digital quantity causing only one weighted analog quantity output by each bit conversion unit to be non-zero, and the bit conversion unit with a non-zero weighted analog quantity output is a precision test unit; the digital-to-analog converter circuit converts the first input digital quantity into a first measured analog quantity; the measuring instrument converts the first measured analog quantity into a first measured digital quantity; the control unit is also used to compare the first measured digital quantity with a preset value to obtain the precision data of the precision test unit; the control unit also obtains sorting data based on the precision data of each conversion unit. It should be noted that the measuring instrument and control unit in this embodiment only function during the debugging stage before chip production. After the chip's precision is debugged to the highest level, the measuring instrument and control unit are no longer needed, therefore the measuring instrument and control unit do not need to be integrated into the digital-to-analog converter.

[0057] refer to Figure 4 The present invention also provides a debugging system, including a digital-to-analog converter circuit, a reference power supply, a measuring instrument, and a control unit; the reference power supply provides a reference voltage or reference current to the conversion network; the control unit is used to send first sorting data to the storage unit, the first sorting data causing only one bit conversion unit to be connected in the conversion network, and the bit conversion unit connected to the conversion network is a precision testing unit; the digital-to-analog converter circuit converts the input digital quantity into a first measured analog quantity; the measuring instrument converts the first measured analog quantity into a first measured digital quantity; the control unit is also used to compare the first measured digital quantity with a preset value to obtain the precision data of the precision testing unit; the control unit also obtains sorting data based on the precision data of each conversion unit. It should be noted that the measuring instrument and control unit in this embodiment only function during the debugging stage before chip production. After the chip's precision is debugged to the highest level, the measuring instrument and control unit are no longer needed, therefore the measuring instrument and control unit do not need to be integrated into the digital-to-analog converter.

[0058] In one embodiment, the parallel input pin of the digital-to-analog converter circuit is a differential signal pin. Two sets of conversion networks and summing circuits are provided to convert the positive and negative signals of the differential signal into analog quantities, respectively.

[0059] Another embodiment of the present invention is as follows:

[0060] (1) Set the amplifier to measurement mode; the measurement mode can be a calibration-specific design or can be shared with the normal conversion mode;

[0061] (2) Connect the input of each bit conversion unit to the reference power supply and the output to the amplifier input terminal. Measure the amplifier output to obtain the measured output value corresponding to each accuracy test unit. M_D i , ( i=0...m M is the magnification factor;

[0062] (3) Calculate the measured output values. M_D i ( i=0...m mean mean The calculation formula is as follows:

[0063]

[0064] Calculate the absolute error of each bit conversion unit separately. DM_D i absolute error DM_D i The calculation formula is as follows:

[0065]

[0066] in, M_D i This is the measured output value corresponding to this bit conversion unit.

[0067] (4) Based on the absolute error of the bit conversion unit DM_D i , obtain sorted data { S_D 0 , S_D 1 ,... S_D m The sorted data is then saved to the storage unit. This operation can be performed during the chip system's power-on process using the measurement circuitry within the system or chip, and the results are stored. Alternatively, this operation can be performed before the chip leaves the factory using dedicated testing tools or systems to achieve the measurement function shown in the diagram.

[0068] (5) Set the amplifier to normal amplification mode;

[0069] (6) Read the sorted data stored in the storage unit, which expresses the precision of each bit conversion unit;

[0070] (7) In the switch array, according to the read sorting data, sort each bit conversion unit, and place the bit conversion unit with the best accuracy, that is, the bit conversion unit with the smallest absolute error with the root mean square, in the highest position; the bit conversion unit with the second smallest absolute error is placed in the second highest position; and so on.

[0071] (8) In the digital sorting module, the digital inputs of each bit conversion unit are also rearranged according to the sorting data read out.

[0072] This invention measures the cascaded unit converters in a digital-to-analog converter before the device leaves the factory or is used. The device errors caused by manufacturing defects are amplified and measured, then differ from the ideal results and sorted. The accuracy of each unit converter is determined, and the cascaded units are sorted according to their accuracy. The unit converter with the highest accuracy is placed at the highest position in the digital-to-analog converter, and so on. In this way, the reassembled cascaded digital-to-analog converter achieves the best accuracy. It is suitable for implementation in deep submicron integrated circuit processes and has high industrial application value.

[0073] This invention optimizes the device matching problem of traditional cascaded digital-to-analog converter circuits, especially the accuracy problem in the high-minute bit (MSB) conversion; for natural signals, most of the information is located at the center of the reference source (near the MSB), such as digital-to-analog converters used in audio processing, this invention has better small-signal characteristics.

[0074] This invention fully utilizes the advantages of small area for digital circuits and analog switches under deep submicron technology, making it easier to implement and lower in cost.

[0075] This invention achieves higher conversion accuracy without increasing the area of ​​core analog devices, even when process matching and precision are limited, through calibration and sorting methods.

[0076] The technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered to be within the scope of this specification. When technical features of different embodiments are embodied in the same drawing, it can be regarded as the drawing also disclosing examples of combinations of the various embodiments involved.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A digital-to-analog converter circuit for converting an input digital quantity into an output analog quantity, the digital-to-analog converter circuit comprising a conversion network, an analog switch, and a summing circuit, the conversion network comprising multiple cascaded bit conversion units, each bit conversion unit converting each binary bit of the input digital quantity into a weighted analog quantity of corresponding size, the summing circuit being used to add the weighted analog quantities to obtain the output analog quantity, characterized in that, The conversion network is a ladder network, which includes multiple bit conversion units with identical parameters. The digital-to-analog conversion circuit also includes a first switch array. The multiple bit conversion units with identical parameters are cascaded together through the first switch array. The first switch array is used to switch the cascade order between the bit conversion units, specifically including: Step 1, selecting a bit conversion unit as a precision test unit, setting the input digital quantity such that only the weighted analog quantity output by the precision test unit is non-zero, and the weighted analog quantity output by the other bit conversion units is zero; Step 2, recording the measured output value of the output analog quantity corresponding to the weighted analog quantity; Step 3, calculating the error of the measured output value relative to a preset value; Step 4, repeating steps 1 to 3 to obtain the error of each bit conversion unit; Step 5, readjusting the switching state of the first switch array according to the error of each bit conversion unit, so that each bit conversion unit reaches a new cascade state. In the new cascade state, the bit conversion unit with the smaller error converts the higher bits of the input digital quantity.

2. The digital-to-analog converter circuit according to claim 1, characterized in that, The trapezoidal network includes at least one of an R-2R trapezoidal resistor network, a C-2C switched capacitor network, or an R-2R current steering network.

3. The digital-to-analog converter circuit according to claim 1, characterized in that, The digital-to-analog conversion circuit further includes a storage unit for storing sorted data, and the first switch array switches the cascade order between the bit conversion units according to the sorted data.

4. The digital-to-analog converter circuit according to claim 3, characterized in that, The first switch array includes multiple row lines, multiple column lines, and multiple digitally controlled switches. The row lines and column lines intersect each other, and the digitally controlled switches are connected at the intersections of the row lines and column lines. The digitally controlled switches connect or disconnect the intersecting row lines and column lines according to the sorting data. The bit conversion unit has input terminals, output terminals, and digitally controlled terminals. The input terminals of each bit conversion unit are connected to different column lines, and the output terminals of each bit conversion unit are connected to different row lines. The digitally controlled terminals of each bit conversion unit are grounded or connected to a reference power supply through corresponding analog switches.

5. The digital-to-analog converter circuit according to claim 4, characterized in that, The digital-to-analog converter circuit has a parallel input pin for receiving the input digital quantity. The digital-to-analog converter circuit also includes a digital sorting module, which is coupled between the parallel input pin and the ladder network. The digital sorting module is used to: reorder the binary bits of the input digital quantity according to the sorting data to obtain a rearranged digital quantity, and input the rearranged digital quantity into the ladder network.

6. The digital-to-analog converter circuit according to claim 5, characterized in that, The digital sorting module includes a data selector and / or a data distributor.

7. A debugging method for a digital-to-analog converter circuit, used for debugging the digital-to-analog converter circuit as described in any one of claims 1 to 6, characterized in that, The debugging method includes: Step 1: Select a bit conversion unit as the precision test unit, and set the input digital quantity so that only the weighted analog quantity output by the precision test unit is non-zero, while the weighted analog quantity output by the other bit conversion units is zero. Step 2: Record the measured output value of the output analog quantity corresponding to the weighted analog quantity; Step 3: Calculate the error between the measured output value and the preset value; Step four: Repeat steps one through three to obtain the error of each bit conversion unit; Step 5: Readjust the switching state of the first switch array according to the error of each bit conversion unit, so that each bit conversion unit reaches a new cascaded state. In the new cascaded state, the bit conversion unit with smaller error converts the higher bit of the input digital quantity.

8. The debugging method for the digital-to-analog converter circuit according to claim 7, characterized in that, Step three specifically includes: The difference is obtained by subtracting the measured output value from the preset value; The error is obtained by taking the absolute value of the difference.

9. A debugging system, characterized in that, The digital-to-analog converter circuit of claim 5 further includes a reference power supply, a measuring device, and a control unit; the reference power supply provides a reference voltage or a reference current to the conversion network; the control unit is used to send a first input digital quantity to the parallel input pin, the first input digital quantity causing only one of the bit conversion units to output a non-zero weighted analog quantity, and the bit conversion unit with a non-zero weighted analog quantity output is a precision testing unit. The digital-to-analog converter circuit converts the first input digital quantity into a first measured analog quantity; the measuring device converts the first measured analog quantity into a first measured digital quantity; the control unit is also used to compare the first measured digital quantity with a preset value to obtain the accuracy data of the accuracy testing unit; the control unit also obtains the sorting data based on the accuracy data of each conversion unit.

10. A debugging system, characterized in that, include: A digital-to-analog converter (DAC) circuit is used to convert an input digital quantity into an output analog quantity. The DAC circuit includes a conversion network, analog switches, and a summing circuit. The conversion network includes multiple cascaded bit conversion units, each of which converts each binary bit of the input digital quantity into a weighted analog quantity of a corresponding size. The summing circuit is used to add the weighted analog quantities to obtain the output analog quantity. The conversion network is a ladder network, which includes multiple bit conversion units with identical parameters. The DAC circuit also includes a first switch array, in which the multiple bit conversion units with identical parameters are cascaded. The first switch array is used to switch the cascade order of the bit conversion units. It also includes a reference power supply, measuring instruments, and a control unit; The reference power supply provides a reference voltage or reference current to the conversion network; the control unit is used to send first sorting data to the storage unit, the first sorting data causing only one bit conversion unit to be connected in the conversion network, and the bit conversion unit connected to the conversion network is a precision testing unit; the digital-to-analog conversion circuit converts the input digital quantity into a first measured analog quantity; the measuring device converts the first measured analog quantity into a first measured digital quantity; the control unit is also used to compare the first measured digital quantity with a preset value to obtain the precision data of the precision testing unit; the control unit also obtains sorting data based on the precision data of each conversion unit, the sorting data expressing the precision of each conversion unit; specifically, in the switch array, according to the read sorting data, each bit conversion unit is sorted, the bit conversion unit with the best precision is placed in the highest position, the bit conversion unit with the second best precision is placed in the second highest position; and so on.

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