A detector photodiode node capacitance testing device and method

Abstract

The present invention discloses a detector photodiode node capacitance test device and method, belonging to the field of photodetector technology. The method comprises controlling a switch to be turned on, and charging a calibration capacitor and a pixel array photodiode node capacitance to a first voltage by an external power supply. The method also comprises controlling a switch to be turned off, and after the detector starts an exposure state, the calibration capacitor supplies power to the pixel array photodiode node capacitance by the calibration capacitor, and multiple frames of exposure cause the calibration capacitor voltage to drop to a second voltage. The method also comprises reading the detector output signal value after each frame of exposure, and measuring the voltage change of the calibration capacitor after the multiple frames of exposure are completed.

Description

Technical Field

[0001] The invention relates to a detector photodiode node capacitor array, belonging to the technical field of photoelectric detectors. Background Art

[0002] The detector is the core device of the space astronomical observation payload and plays a vital role in the space telescope system. It includes astronomical visible light detectors and astronomical infrared detectors. Astronomical detectors, such as astronomical infrared detectors, generally use source follower (SFD) injection pixel circuits. The photogenerated charge generated by the detector exposure will be stored in the equivalent photodiode node capacitance C of the FD node. FD The pixel voltage is then proportionally output to the column readout circuit through the source follower. FD It is composed of source follower gate capacitance, reset transistor source capacitance, photodiode junction capacitance and other parasitic capacitances, and its source is relatively complex, so it is difficult to obtain an accurate value in calculation. Photodiode node capacitance is one of the most important parameters of the detector, including charge-to-voltage conversion gain, quantum efficiency, full well electron number, etc., which all need to participate in the calculation. Therefore, how to measure and obtain an accurate photodiode node capacitance value is particularly important.

[0003] In traditional testing methods, such as the photon shot noise method, the experimental results will deviate from the Poisson distribution due to the existence of coupling capacitance between pixels, and the measured photodiode node capacitance parameters will be too large; 55 The isotope measurement method is difficult to apply due to the difficulty of testing and the absorption of soft X-rays by its substrate material (such as cadmium zinc telluride) in, for example, infrared detector testing. Summary of the invention

[0004] The technical problem solved by the present invention is to overcome the deficiencies of the prior art and provide a detector photodiode node capacitance testing device and method, which achieves accurate measurement of the photodiode node capacitance in a simple and easy manner.

[0005] The technical solution of the present invention is: a detector photodiode node capacitance test device, the method includes a switch, a power supply, a calibration capacitor, a drive and a signal processing circuit;

[0006] The positive electrode of the power supply is electrically connected to one end of the switch, and the other end of the switch is electrically connected to the first electrode of the calibration capacitor and the power supply end of the reset transistor of the detector pixel array;

[0007] The negative electrode of the power supply, the second electrode of the calibration capacitor, and the substrate contact of the photodiode node capacitor of the detector pixel array are electrically connected together, and finally electrically connected to the ground;

[0008] The control end of the switch, the first electrode of the calibration capacitor, the row drive circuit of the detector, and the output signal V<1…n> of the detector column readout circuit are electrically connected to the drive and signal processing circuit;

[0009] The driving and signal processing circuit is configured as follows: the control switch is turned on, and the reset transistor of the pixel array is controlled at the same time, so that the calibration capacitor and the pixel array photodiode node capacitor are charged to a first voltage by the power supply; the control switch is turned off, and the calibration capacitor supplies power to the pixel array photodiode node capacitor, and the detector is controlled to start a k-frame exposure process. During the exposure process, the reset transistor in the pixel is controlled to be repeatedly switched between the closed and open states, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor until the calibration capacitor voltage drops to the second voltage, and the exposure signal output by the detector column readout circuit is read, and the capacitance value of the photodiode node capacitor is calculated according to the output signal voltage value of each pixel of the detector pixel array after each frame of exposure and the voltage change of the calibration capacitor after the k-frame exposure is completed, where k is greater than or equal to 1.

[0010] Preferably, the specification of the calibration capacitor is selected within the range of 1uF to 10uF.

[0011] Preferably, the first voltage is a pixel reset voltage of the detector.

[0012] Preferably, the second voltage drops by 0.1V to 0.5V relative to the first voltage.

[0013] Preferably, the driving and signal processing circuit comprises a first control interface, a second control interface, a first buffer circuit, a first analog-to-digital conversion circuit, a second buffer circuit, a second analog-to-digital conversion circuit, a second control interface, and a programmable signal processor;

[0014] A first control interface, connected to the control end of the switch, for sending a switch control signal to the switch to control the on and off of the switch;

[0015] A second control interface is connected to an input end of a row driving circuit of a detector pixel array and is used to send a reset control signal and a column selection control signal to the row driving circuit;

[0016] A first analog buffer circuit is connected to the first electrode of the calibration capacitor and is used to collect the voltage of the calibration capacitor;

[0017] A first analog-to-digital conversion circuit is connected to the output end of the first analog buffer circuit, converting the voltage of the calibration capacitor into a digital signal and sending it to the programmable signal processor;

[0018] A second analog buffer circuit is connected to the V_out<1…n> terminal of the detector pixel array column readout circuit and is used to read the detector output signal value;

[0019] A second analog-to-digital conversion circuit converts the detector output signal value into a digital signal and sends it to a programmable signal processor;

[0020] The programmable signal processor generates a switch control signal in an initial state to control the switch to be in an off state. After a preset period of time, the switch control signal is changed to control the switch to be in an on state. At the same time, a reset control signal is generated to control the reset transistor of the pixel array, and the calibration capacitor and the pixel array photodiode node capacitor are charged by an external power supply. The voltage value of the calibration capacitor is detected in real time until the voltage value of the calibration capacitor reaches a first voltage. The switch control signal is changed again to control the switch to be off, and power is supplied to the pixel array photodiode node capacitor through the calibration capacitor. The column selection control signal is output to control the column selection transistor in the pixel to switch repeatedly between the off state and the on state, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor. At the same time, the voltage value of the calibration capacitor is detected until the calibration capacitor voltage drops to the second voltage. The exposure signal output by the detector column readout circuit is read in real time. The capacitance value of the photodiode node capacitor is calculated according to the output signal voltage value of each pixel of the detector pixel array after each frame of exposure and the voltage change of the calibration capacitor measured after the k frames of exposure are completed.

[0021] Preferably, the photodiode node capacitance C FD Calculated according to the following formula:

[0022]

[0023] Among them, U C1 is the first voltage, U Ck is the second voltage, frames is the number of exposure frames, U s,r,l is the output signal voltage value of the pixel in the sth frame, rth row, and lth column in the pixel array, m is the number of rows of the detector pixel array, n is the number of columns of the detector pixel array, G is the gain factor of the source follower transistor SFD, C 校准电容 is the capacitance of the calibration capacitor.

[0024] Another technical solution of the present invention is: a method for testing the node capacitance of a detector photodiode, the method comprising the following steps:

[0025] S1, control the switch to be turned on, and the calibration capacitor and the pixel array photodiode node capacitor are charged to a first voltage by an external power supply;

[0026] S2, control the switch to be disconnected, supply power to the pixel array photodiode node capacitor through the calibration capacitor, and control the detector to start the k-frame exposure process. During the exposure process, control the reset transistor in the pixel to repeatedly switch between the off and on states, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor until the calibration capacitor voltage drops to the second voltage;

[0027] S3. Calculate the capacitance value of the photodiode node capacitance according to the voltage value of the output signal of each pixel of the detector pixel array after each frame of exposure and the voltage change of the calibration capacitor measured after the k-frame exposure, where k is greater than or equal to 1.

[0028] Preferably, the photodiode node capacitance C FD Calculated according to the following formula:

[0029]

[0030] Among them, U C1 is the first voltage, U Ck is the second voltage, frames is the number of exposure frames, U s,r,l is the output signal voltage value of the pixel in the sth frame, rth row, and lth column in the pixel array, m is the number of rows of the detector pixel array, n is the number of columns of the detector pixel array, G is the gain factor of the source follower transistor SFD, C 校准电容 is the capacitance of the calibration capacitor.

[0031] Preferably, the first voltage is a pixel reset voltage of the detector.

[0032] Preferably, the second voltage drops by 0.1V to 0.5V relative to the first voltage.

[0033] The advantages of the present invention compared with the prior art are:

[0034] (1) The present invention uses a charge extraction method to directly calculate the relationship between charge, voltage, and capacitance, thereby avoiding the problem that the test results of the photon shot noise method deviate from the expected Poisson distribution due to the coupling capacitance between pixels;

[0035] (2) The present invention adopts a charge extraction method which has no requirements on the exposure amount, so there is no need to use an X-ray source as a light source, thus avoiding Fe 55 The isotope measurement method cannot be used to test infrared detectors without substrate thinning (such as cadmium zinc telluride substrate);

[0036] (3) The measuring device of the present invention is simple and easy to operate, and compared with Fe 55 There is no experimental operation risk in the isotope measurement method. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a principle block diagram of the testing method and device according to the embodiment of the present invention;

[0038] Figure 2 is a principle block diagram of a driving and signal processing circuit device according to an embodiment of the present invention;

[0039] Figure 3 Schematic diagram of charging and discharging of a calibration capacitor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The idea of ​​the present invention is to utilize the characteristics of voltage change during the process of capacitor charging and discharging, and use a calibration capacitor with a measured accurate capacitance value to supply power to the pixel array photodiode node capacitance from the calibration capacitor during the detector exposure process. After multiple frames of exposure, the calibration capacitor will produce a significant voltage drop due to continuous discharge, and this voltage drop is basically equal to the photogenerated charge generated by the detector pixel during the multi-frame exposure process. By calculating the relationship between the signal value output by the detector during the multi-frame exposure process and the voltage drop of the calibration capacitor, the average value of the detector pixel photodiode node capacitance can be obtained.

[0041] The present invention is described in detail below with reference to the accompanying drawings.

[0042] like Figure 1 The figure is a principle block diagram of the test method and device involved in the present invention, including a photodiode node capacitance test device and a detector. The photodiode node capacitance test device includes a power supply, a calibration capacitor, a switch, a drive and a signal processing circuit;

[0043] The positive terminal of the power supply is electrically connected to one end of the switch, and the other end of the switch is electrically connected to the first electrode of the calibration capacitor ( Figure 1 V_Res node in the detector pixel array), and a power supply end of a reset transistor of the detector pixel array;

[0044] The negative electrode of the power supply, the second electrode of the calibration capacitor, the substrate contact of the detector pixel array photodiode node capacitor are electrically connected together, and finally electrically connected to ground ( Figure 1 V_Sub node in the

[0045] The control end of the switch, the first electrode of the calibration capacitor, the row drive circuit of the detector, and the output signal V<1...n> of the detector column readout circuit are electrically connected to the drive and signal processing circuit; the switch can be a relay switch, a photoelectric switch or a MOS switch.

[0046] The driving and signal processing circuit is configured to: control the switch to be turned on, and control the pixel array reset transistor at the same time, so that the calibration capacitor and the pixel array photodiode node capacitor are charged to a first voltage by an external power supply; the first voltage is the pixel reset voltage of the detector, the control switch is disconnected from the power supply, and the calibration capacitor supplies power to the pixel array photodiode node capacitor, and the detector is controlled to start a k-frame exposure process. During the exposure process, the reset transistor in the pixel is controlled to switch repeatedly between the closed and open states, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor until the calibration capacitor voltage drops to the second voltage. The selection of the exposure frame number is related to the detector array scale, exposure time, and the selected calibration capacitor capacity. Generally, the calibration capacitor specification can be selected within the range of 1uF to 10uF, and the standard capacitor is such as tantalum capacitor and high-frequency ceramic capacitor; the exposure time can be selected from the value specified in the detector manual, and the exposure frame number can generally be selected between tens of frames and thousands of frames. The specific exposure frame number needs to be determined according to the calibration capacitor voltage drop during the test process. Generally, the selected exposure frame number should make the calibration capacitor voltage change within the range of 0.1V to 0.5V. The exposure signal output by the detector column readout circuit is read, and the capacitance value of the photodiode node capacitance is calculated according to the output signal voltage value of each pixel of the detector pixel array after each frame exposure and the voltage change of the calibration capacitor measured before and after k frames of exposure, where k is greater than or equal to 1. Specifically: the row drive circuit inside the detector is controlled by the driving and signal processing circuit to control the opening and closing of the reset transistor and the column selection transistor, and the detector output exposure signal is read through the column readout circuit at the same time, wherein the driving and signal processing circuit is electrically connected to the row drive circuit, and the driving and signal processing circuit is electrically connected to the column readout circuit, and wherein the reading of the detector output signal value after each frame of exposure includes analog-to-digital conversion of all exposure signal voltage amplitudes in the detector pixel array.

[0047] Controlling the row driving circuit and thus controlling the reset transistor and the column gate transistor in the pixel array to turn on and off includes:

[0048] Controlling the reset transistor to selectively and electrically connect the calibration capacitor V_res node to the FD node of the pixel array photodiode node capacitance; and

[0049] The pixel array column selection transistor is controlled to connect the pixel array photodiode node capacitance C FD The voltage is output to the column readout circuit through the source follower transistor.

[0050] Figure 1The detector shown in is an example. In this example, the detector includes a pixel array, a row driving circuit, and a column readout circuit. The pixel array is composed of pixel units of size m×n, each of which includes a reset transistor M1, a source follower transistor SFD, a column selection transistor M2, a detector photodiode PD, and a photodiode node capacitance C equivalent to the D_Sub node of the FD node FD .

[0051] The row drive circuit is provided with a timing drive signal by the drive and signal processing circuit, and outputs a pixel reset signal Reset and a pixel column selection signal SEL to the pixel array. <1> To SEL <m>The column readout circuit receives the analog voltage signal Vout of the 1st to nth columns output by the pixel array <1> ……Vout <n>, and after being reordered by the column readout circuit, the Vout<1…n> signal containing all the original analog voltage signals is output to the driving and signal processing circuit.

[0052] The drain of the column selection transistor M2 of the pixel in the pixel array is connected to the drain of the column selection transistor M2 of other pixels in the column direction (such as pixel <1,1> to pixel<m,1> The drains of the column selection transistors M2 of the m pixels are connected together), and finally connected to the input end of the column readout circuit, and the gate of the column selection transistor M2 is connected to the column selection signal SEL of the row driving circuit. <1> To SEL <m>The output end of the reset transistor M1 of all pixels in the pixel array is connected together, and the drain of the reset transistor M1 is connected together with the FD node of the photodiode PD and the gate of the source follower transistor SFD; the drain of the source follower transistor SFD is connected to the power supply VDD, and the other source is connected to the source of the column selection transistor M2.

[0053] Preferably, the calibration capacitor is a tantalum capacitor or a high-frequency ceramic capacitor, and the specification of the calibration capacitor is selected within the range of 1uF to 10uF.

[0054] Preferably, the second voltage decreases by 0.1V to 0.5V relative to the first voltage.

[0055] Figure 2 The driving and signal processing circuit shown in the figure includes a first control interface, a second control interface, a first buffer circuit, a first analog-to-digital conversion circuit, a second buffer circuit, a second analog-to-digital conversion circuit, a second control interface, and a programmable signal processor; wherein the programmable signal processor can be an FPGA, a CPU or a DSP in an actual system; the analog buffer circuit can be an op amp follower circuit with a gain of 1 in an actual system.

[0056] The first digital output interface of the programmable signal processor is connected to the input end of the first control interface, and the first control interface is connected to the control end of the switch, and is used to send a switch control signal to the switch to control the on and off of the switch;

[0057] The second digital output interface of the programmable signal processor is connected to the input end of the second control interface, and the second control interface is connected to the input end of the row driving circuit of the detector pixel array, and is used to send the reset control signal and the column selection control signal to the row driving circuit;

[0058] A first analog buffer circuit is connected to the first electrode of the calibration capacitor and is used to collect the voltage of the calibration capacitor;

[0059] The first digital input interface of the programmable signal processor is connected to the output end of the first analog-to-digital conversion circuit, and the first analog-to-digital conversion circuit is connected to the output end of the first analog buffer circuit to convert the voltage of the calibration capacitor into a digital signal and send it to the programmable signal processor;

[0060] A second analog buffer circuit is connected to the V_out<1…n> terminal of the detector pixel array column readout circuit and is used to read the detector output signal value;

[0061] The second digital input interface of the programmable signal processor is connected to the output end of the second analog-to-digital conversion circuit, and the second analog-to-digital conversion circuit converts the detector output signal value into a digital signal and sends it to the programmable signal processor;

[0062] The programmable signal processor generates a switch control signal in an initial state to control the switch to be in an off state. After a preset period of time, the switch control signal is changed to control the switch to be in an on state. At the same time, a reset control signal is generated to control the reset transistor of the pixel array, and the calibration capacitor and the pixel array photodiode node capacitor are charged by an external power supply. The voltage value of the calibration capacitor is detected in real time until the voltage value of the calibration capacitor reaches a first voltage. The switch control signal is changed again to control the switch to be off, and power is supplied to the pixel array photodiode node capacitor through the calibration capacitor. A column selection control signal is output to control the column selection transistor in the pixel to switch repeatedly between the off state and the on state, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor. At the same time, the voltage value of the calibration capacitor is detected until the calibration capacitor voltage drops to the second voltage. The exposure signal output by the detector column readout circuit is read in real time through the column readout circuit. According to the output signal voltage value of each pixel of the detector pixel array after each frame of exposure and the voltage change of the calibration capacitor measured after the k frames of exposure are completed, the capacitance value of the photodiode node capacitor is calculated.

[0063] Figure 3 The figure shows the charging and discharging schematic diagram of the calibration capacitor during the test process. The horizontal axis in the figure represents time, and the vertical axis represents the voltage of the V_Res node on the calibration capacitor. During the time period t0 to t1, the switch is in the off state, and the initial voltage of the V_Res node on the first electrode of the calibration capacitor is U C0 During the time period t1 to t2, the drive and signal processing circuit control switch is turned on at time t1, and the upper electrode V_Res node of the + polarity calibration capacitor of the external power supply is charged to the first voltage U C1 During the time period t2 to t3, the drive and signal processing circuit control switch is disconnected at time t2, and the detector pixel array is controlled to start the first frame exposure process. The pixel array draws current from the upper electrode V_Res node of the calibration capacitor, and the voltage drops to the second voltage U C2 , and read the signal value V_out<1…n> output by the readout circuit of the detector pixel array of the first frame at the same time; during the subsequent time period t3 to t4, repeat the test process during the time period t2 to t3; finally, during the period t4 to t5, start the exposure of the last k-th frame, and the voltage of the node V_Res on the upper electrode of the calibration capacitor drops to the second voltage U Ck , the test process ends at time t5.

[0064] The voltage drop of the calibration capacitor is shown in equation (1):

[0065] ΔU 校准电容 =U C1 -U Ck (1)

[0066] The change in charge on the calibration capacitor is shown in equation (2):

[0067] ΔQ 校准电容 =ΔU 校准电容 ×C 校准电容 (2)

[0068] Because the pixel array draws current from the calibration capacitor during the exposure process, the charge change on the calibration capacitor should be equal to the charge change of the pixel array photodiode node capacitance during the multi-frame exposure process, and this change can be calculated from the output signal V_out<1…n> of the detector pixel array, as shown in formula (3):

[0069]

[0070] In formula (3), ΔQ out is the total charge consumption of the photodiode node capacitance of the detector pixel array after multiple frames of exposure, U s,r,l is the output voltage signal value of the pixel in the sth frame, rth row, and lth column in the pixel array, C FD is the photodiode node capacitance to be calculated, G is the gain factor of the source follower transistor SFD, the specific value is related to the body effect, usually 0.7 to 0.8. Combining equations (1) to (3), the photodiode node capacitance can be calculated according to the following equation (4):

[0071]

[0072] Among them, U C1 is the first voltage, U Ck is the second voltage, frames is the number of exposure frames, U s,r,l is the output signal voltage value of the pixel in the sth frame, rth row, and lth column in the pixel array, m is the number of rows of the detector pixel array, n is the number of columns of the detector pixel array, G is the gain factor of the source follower transistor SFD, C 校准电容 is the capacitance of the calibration capacitor.

[0073] Therefore, the present invention also proposes a detector photodiode node capacitance testing method, the method comprising the following steps:

[0074] S1, control the switch to be turned on, and the calibration capacitor and the pixel array photodiode node capacitor are charged to a first voltage by an external power supply;

[0075] S2, control the switch to be disconnected, supply power to the pixel array photodiode node capacitor through the calibration capacitor, and control the detector to start the k-frame exposure process. During the exposure process, control the reset transistor in the pixel to repeatedly switch between the off and on states, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor until the calibration capacitor voltage drops to the second voltage;

[0076] S3. Calculate the capacitance value of the photodiode node capacitance according to the voltage value of the output signal of each pixel of the detector pixel array after each frame of exposure and the voltage change of the calibration capacitor measured after the k-frame exposure, where k is greater than or equal to 1.

[0077] The testing method of the present invention includes that before the exposure test, the driving and signal processing circuit outputs a switch electrical signal to control the switch to be turned on, and at the same time, the reset control signal controls the reset transistor inside the detector pixel to be turned on, so that the calibration capacitor and the pixel array photodiode node capacitor are charged by the external power supply; after ensuring that the calibration capacitor is charged to the first voltage, the driving and signal processing circuit controls the switch to be disconnected, and at the same time controls the detector to start the exposure process. During the exposure process, the driving and signal processing circuit will repeatedly switch the reset transistor in the pixel between the closed and open states, and the specific switching time is the exposure time of each frame. During this process, the detector pixel array photodiode node capacitor will repeatedly draw current from the calibration capacitor, thereby causing the calibration capacitor to produce a significant voltage drop. The driving and signal processing circuit can calculate the capacitance value of the photodiode node capacitor by reading the detector output signal value after each frame of exposure, combined with measuring the voltage change at both ends of the calibration capacitor.

[0078] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.< / m> < / n> < / m>

Claims

1. A detector photodiode node capacitance test device, characterized in that Includes switches, power supplies, calibration capacitors, drive and signal processing circuits; The positive electrode of the power supply is electrically connected to one end of the switch, and the other end of the switch is electrically connected to the first electrode of the calibration capacitor and the power supply end of the reset transistor of the detector pixel array; The negative electrode of the power supply, the second electrode of the calibration capacitor, and the substrate contact of the photodiode node capacitor of the detector pixel array are electrically connected together, and finally electrically connected to the ground; The control end of the switch, the first electrode of the calibration capacitor, the row drive circuit of the detector, and the output signal V<1…n> of the detector column readout circuit are electrically connected to the drive and signal processing circuit; The driving and signal processing circuit is configured as follows: the control switch is turned on, and the reset transistor of the pixel array is controlled at the same time, so that the calibration capacitor and the pixel array photodiode node capacitor are charged to a first voltage by the power supply; the control switch is turned off, and the calibration capacitor supplies power to the pixel array photodiode node capacitor, and the detector is controlled to start a k-frame exposure process. During the exposure process, the reset transistor in the pixel is controlled to be repeatedly switched between the closed and open states, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor until the calibration capacitor voltage drops to the second voltage, and the exposure signal output by the detector column readout circuit is read, and the capacitance value of the photodiode node capacitor is calculated according to the output signal voltage value of each pixel of the detector pixel array after each frame of exposure and the voltage change of the calibration capacitor after the k-frame exposure is completed, where k is greater than or equal to 1.

2. A detector photodiode node capacitance test device according to claim 1, characterized in that The specification of the calibration capacitor is selected within the range of 1uF to 10uF.

3. A detector photodiode node capacitance test device according to claim 1, characterized in that The first voltage is a pixel reset voltage of the detector.

4. A detector photodiode node capacitance test device according to claim 1, characterized in that The second voltage is 0.1V to 0.5V lower than the first voltage.

5. A detector photodiode node capacitance test device according to claim 1, characterized in that The driving and signal processing circuit includes a first control interface, a second control interface, a first analog buffer circuit, a first analog-to-digital conversion circuit, a second analog buffer circuit, a second analog-to-digital conversion circuit, a second control interface, and a programmable signal processor; A first control interface, connected to the control end of the switch, for sending a switch control signal to the switch to control the on and off of the switch; A second control interface is connected to an input end of a row driving circuit of a detector pixel array and is used to send a reset control signal and a column selection control signal to the row driving circuit; A first analog buffer circuit is connected to the first electrode of the calibration capacitor and is used to collect the voltage of the calibration capacitor; A first analog-to-digital conversion circuit is connected to the output end of the first analog buffer circuit, converting the voltage of the calibration capacitor into a digital signal and sending it to the programmable signal processor; A second analog buffer circuit is connected to the V_out<1…n> terminal of the detector pixel array column readout circuit and is used to read the detector output signal value; A second analog-to-digital conversion circuit converts the detector output signal value into a digital signal and sends it to a programmable signal processor; The programmable signal processor generates a switch control signal in an initial state to control the switch to be in an off state. After a preset period of time, the switch control signal is changed to control the switch to be in an on state. At the same time, a reset control signal is generated to control the reset transistor of the pixel array, and the calibration capacitor and the pixel array photodiode node capacitor are charged by an external power supply. The voltage value of the calibration capacitor is detected in real time until the voltage value of the calibration capacitor reaches a first voltage. The switch control signal is changed again to control the switch to be off, and power is supplied to the pixel array photodiode node capacitor through the calibration capacitor. The column selection control signal is output to control the column selection transistor in the pixel to switch repeatedly between the off state and the on state, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor. At the same time, the voltage value of the calibration capacitor is detected until the calibration capacitor voltage drops to the second voltage. The exposure signal output by the detector column readout circuit is read in real time. The capacitance value of the photodiode node capacitor is calculated according to the output signal voltage value of each pixel of the detector pixel array after each frame of exposure and the voltage change of the calibration capacitor measured after the k frames of exposure are completed.

6. A detector photodiode node capacitance test device according to any one of claims 1 to 5, characterized in that The photodiode node capacitance C FD Calculated according to the following formula: Among them, U C1 is the first voltage, U Ck is the second voltage, frames is the number of exposure frames, U s,r,l is the output signal voltage value of the pixel in the sth frame, rth row, and lth column in the pixel array, m is the number of rows of the detector pixel array, n is the number of columns of the detector pixel array, G is the gain factor of the source follower transistor SFD, C 校准电容 is the capacitance of the calibration capacitor.

7. A detector photodiode node capacitance testing method based on the testing device of claim 1, characterized in that The steps include: S1, control the switch to be turned on, and the calibration capacitor and the pixel array photodiode node capacitor are charged to a first voltage by an external power supply; S2, control the switch to be disconnected, supply power to the pixel array photodiode node capacitor through the calibration capacitor, and control the detector to start the k-frame exposure process. During the exposure process, control the reset transistor in the pixel to repeatedly switch between the off and on states, so that the detector pixel array photodiode node capacitor repeatedly draws current from the calibration capacitor until the calibration capacitor voltage drops to the second voltage; S3. Calculate the capacitance value of the photodiode node capacitance according to the voltage value of the output signal of each pixel of the detector pixel array after each frame of exposure and the voltage change of the calibration capacitor measured after the k-frame exposure, where k is greater than or equal to 1.

8. A detector photodiode node capacitance testing method according to claim 7, characterized in that The photodiode node capacitance C FD Calculated according to the following formula: Among them, U C1 is the first voltage, U Ck is the second voltage, frames is the number of exposure frames, U s,r,l is the output signal voltage value of the pixel in the sth frame, rth row, and lth column in the pixel array, m is the number of rows of the detector pixel array, n is the number of columns of the detector pixel array, G is the gain factor of the source follower transistor SFD, C 校准电容 is the capacitance of the calibration capacitor.

9. A detector photodiode node capacitance testing method according to claim 8, characterized in that The first voltage is a pixel reset voltage of the detector.

10. A detector photodiode node capacitance testing method according to claim 9, characterized in that The second voltage is 0.1V to 0.5V lower than the first voltage.

Images