A video decoding chip SLT method and test device

Abstract

The present application relates to a video decoding chip SLT method and testing device, comprising the following steps: initializing a desktop tester; the desktop tester automatically sucks the chip from a tray and places it in a test socket; powering on a core test board; performing an open and short circuit test and comparing the results; performing a simulated IP test and comparing the results; performing a system application test and comparing the results; the test stand completes the test and sends a test signal to the tester; the desktop tester classifies the chip according to the signal, the testing device comprising a desktop tester and a core test board, the desktop tester being used for taking, placing and sorting the chip, the desktop tester being used for controlling the power supply of the core test board and obtaining feedback results from the core test board, the method reduces the difficulty of chip board-level testing, shortens the testing time, and by using a machine to perform data comparison, can promptly discover defects that cannot be distinguished by the human eye, reducing costs while being able to better expand production capacity.

Description

[Technical field]

[0001] The present application relates to the field of semiconductor chip testing technology, and in particular to a video decoding chip SLT method and testing device. [Background technology]

[0002] The existing SLT test of video decoding chip adopts manual judgment whether the image quality of video interface output meets the test requirements. After the human eye judges whether the screen output is qualified, the chip is taken out of the test frame and put back into the test frame according to the result. This method has the problems that the human eye can easily ignore some minor defects, the test capacity expansion is difficult and the test cost of a single chip is high. Referring to the SLT method of graphics chip based on interface data comparison published by Chinese invention patent CN114461469A, the invention combines the continuity test and board-level functional test of the graphics chip, which can complete the test of the graphics chip more comprehensively. However, the method of the invention is only applicable to the data matching of static picture output of the graphics chip. For the video decoding chip, the video data stream has a lot of content and is dynamic data, so it is difficult to match the data, and thus it cannot be applied to the test of the video decoding chip. [Summary of the invention]

[0003] In order to better test the video decoding chip, efficiently and automatically complete the continuity test, IP test and chip screening, and facilitate the expansion of chip production capacity and reduce cost investment, this application proposes the following solution:

[0004] A video decoding chip SLT method comprises the following steps:

[0005] Desktop test machine initialization;

[0006] The desktop tester automatically picks up the chip from the tray and places it into the test socket;

[0007] The core test board is powered on;

[0008] Perform open and short circuit tests and compare the results;

[0009] Conduct simulated IP tests and compare the results;

[0010] Conduct system application tests and compare results;

[0011] The test stand completes the test and sends a test signal to the test machine;

[0012] The desktop tester sorts the chips according to the signals.

[0013] In the above-mentioned video decoding chip SLT method, in the step of performing an open-short circuit test and comparing the results, the open-short circuit test includes the following steps:

[0014] Determine whether the number of IO ports is an even number. If so, divide the general IO ports into two groups of equal number, a first group and a second group, on the core test board, and connect the general IO ports of the first group and the second group one by one on the core test board;

[0015] In the first stage, the first group of general IO ports are controlled to output high level and low level respectively, and read back from the second group of general IO ports for judgment.

[0016] Control the first group of general IO ports to output high level, then read the output of the first group from the second group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip;

[0017] Control the first group of general IO ports to output low level, then read the output of the first group from the second group of general IO ports to determine whether they are all low level. If all are low level, proceed to the next step, otherwise it is determined to be a bad chip;

[0018] In the second stage, the second group of general IO ports are controlled to output high level and low level respectively, and read back from the first group of general IO ports for judgment.

[0019] Control the second group of general IO ports to output high level, then read the output of the second group from the first group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip;

[0020] Control the second group of general IO ports to output low level, then read the output of the second group from the first group of general IO ports to determine whether they are all low level. If all are low level, proceed to the next step, otherwise it is determined to be a bad chip;

[0021] Complete the open and short circuit test and proceed to the next functional test.

[0022] In the above-mentioned SLT method of a video decoding chip, if the number of IO ports is an odd number, after the general IO ports are divided into two groups of equal number, namely, the first group and the second group, on the core test board, the general IO ports of the first group and the second group are connected one by one on the core test board, and the remaining independent IO port performs the following steps:

[0023] The output of the remaining independent IO port is connected to the input of a latch chip. Any IO of the first group is connected to the output control OE terminal of the latch chip. The latch enable terminal LE of the latch chip is directly connected to the power supply, so that the latch enable is always valid. When the latch output control OE terminal is 1, the latch outputs a high impedance state and does not drive the bus. When the latch output control OE terminal is 0, the latch outputs the latched data.

[0024] In the first stage, the first group of general IO ports are controlled to output high and low levels respectively, and read back from the second group of general IO ports for judgment. After the independent IO port outputs a high level to the latch for latching, it is switched to input and the latch output is read back for judgment.

[0025] Control the first group of general IO ports to output high level, the latch output controls the OE terminal to 1, and the latch outputs high impedance; control the independent IO to output high level, and read the output of the first group from the second group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip;

[0026] Control the first group of general IO ports to output low level, the latch output controls the OE terminal to 0, the latch outputs the latched independent IO state, and then controls the independent IO to switch to input, and judges whether the independent IO state output by the latch is high level, if so, continue, otherwise it is judged as a bad chip; read the output of the first group from the second group of general IO ports, and judge whether it is low level, if all are low level, proceed to the next step, otherwise it is judged as a bad chip;

[0027] Control the independent IO to output low level, control the first group of general IO ports to output low level, the latch output controls the OE terminal to be 0, the latch outputs the latched independent IO state, and then controls the independent IO to switch to input, and judges whether it is low level, if so, proceed to the next step, otherwise it is judged as a bad chip;

[0028] In the second stage, the second group of general IO ports are controlled to output high level and low level respectively, and read back from the first group of general IO ports for judgment.

[0029] Control the second group of general IO ports to output high level, then read the output of the second group from the first group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip;

[0030] Control the second group of general IO ports to output low level, then read the output of the second group from the first group of general IO ports to determine whether they are all low level. If all are low level, proceed to the next step, otherwise it is determined to be a bad chip;

[0031] Complete the open and short circuit test and proceed to the next functional test.

[0032] In the above-mentioned video decoding chip SLT method, in the step of performing a simulated IP test and comparing the results, the simulated IP includes a USB or a DDR, the USB or the DDR is provided with a BIST mode, and the test of the simulated IP includes the following steps:

[0033] Control the chip under test to enter the corresponding BIST mode;

[0034] Given input start signal;

[0035] Determines whether the output is high level within a specific time.

[0036] In the SLT method for a video decoding chip as described above, in the step of performing analog IP testing and comparing the results, the analog IP includes an ADC, and the ADC requires an external video decoding chip to control the output DAC analog signal, and the quality of the ADC function is determined by comparing the digital output of the chip under test.

[0037] In the above-mentioned video decoding chip SLT method, in the step of performing system application test and comparing the results, the system application test includes the following steps:

[0038] The external decoding control chip controls the chip under test to enter the functional test mode;

[0039] After the chip under test starts the application from the flash and reads the multimedia data from the USB flash drive or SD card, it completes the audio and video decoding and image display processing internally and then outputs it to the HDMI interface;

[0040] The HDMI interface starts to output dynamic multimedia audio and video data;

[0041] The external decoding control chip receives multimedia audio and video data from the HDMI input port and starts decoding and then stores it in the memory;

[0042] The chip under test starts to read data from the USB flash drive and sends a start command to the external decoding control chip through the serial port. The decoding control chip reads the same multimedia data from the USB flash drive and stores it in the memory after decoding.

[0043] The main control video decoding chip starts comparing the local U disk decoded data with the multimedia data decoded by the HDMI input port;

[0044] Complete data comparison and determine the quality of the chip under test.

[0045] The video decoding chip SLT method described above specifically includes the following operations in the step of comparing the local U disk decoded data started by the master video decoding chip with the multimedia data decoded by the HDMI input port:

[0046] Locate the I-frame data after HDMI decoding;

[0047] Take the first I frame of the video data decoded from the USB flash drive and compare it with the I frame decoded from the HDMI. If the comparison fails, find the next I frame for comparison; if it fails, continue to find the next I frame for comparison until the comparison succeeds or exceeds the set number of comparisons; if the comparison succeeds, go to the next step; if the comparison exceeds the set number of comparisons, it is judged to be a failure;

[0048] The next P frame data and I frame data are compared. If the comparison fails, it is judged as a bad film. If the comparison succeeds, the comparison continues until the preset number of I frame comparisons reaches the target value.

[0049] The present application discloses a video decoder chip SLT testing device, including a desktop tester and a core test board. The desktop tester is used to take, place and sort chips, and the desktop tester is used to control the power supply of the core test board and obtain feedback results of the core test board to implement a video decoder chip SLT method as described above.

[0050] In a video decoding chip SLT testing device as described above, the core test board includes a test main control chip and a test socket for the chip to be tested, the test main control chip is used to control the chip to be tested to complete the test, the test main control chip is used to control the start and stop of the power supply of the chip to be tested, and the test socket for the chip to be tested is used to clamp the chip to be tested.

[0051] The present application also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a test main control chip, the video decoding chip SLT method as described above is implemented.

[0052] Compared with the prior art, this application has the following advantages:

[0053] The video decoding chip SLT method of the present application improves the original graphics chip SLT method so that the video decoding chip can automatically perform SLT testing. After performing IP testing and system-level application testing, the results are automatically compared without manual comparison, which reduces the difficulty of chip board-level testing and shortens the testing time. By using a machine to compare data, defects that cannot be distinguished by the human eye can be discovered in a timely manner, thereby reducing costs and expanding production capacity to a better extent.

Brief Description of the Drawings

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments are briefly introduced below.

[0055] Figure 1 It is a flowchart of the overall testing method of this application;

[0056] Figure 2 This is the open and short circuit test flow chart when the number of IO ports is an even number;

[0057] Figure 3 This is the open and short circuit test flow chart when the number of IO ports is an odd number;

[0058] Figure 4 It is a simulation IP test flow chart;

[0059] Figure 5 It is a system application test flow chart;

[0060] Figure 6 It is a flowchart of comparison of decoded multimedia data;

[0061] Figure 7 It is the framework diagram of the test plan;

[0062] Figure 8 This is the test framework diagram for odd-numbered IO ports. [Specific implementation method]

[0063] like Figure 1 As shown, this embodiment proposes a video decoding chip SLT method, comprising the following steps:

[0064] S1. Desktop test machine initialization;

[0065] S2, the desktop tester automatically picks up the chip from the tray and puts it into the test socket;

[0066] S3, the core test board is powered on;

[0067] S4. Perform open and short circuit tests and compare the results;

[0068] S5. Perform simulated IP test and compare the results;

[0069] S6. Conduct system application tests and compare results;

[0070] S7, the test stand completes the test and sends a test signal to the test machine;

[0071] S8, desktop tester classifies chips according to signals.

[0072] This embodiment improves the original SLT method of the graphics chip so that the video decoding chip can automatically perform SLT testing, and then automatically compares the results after performing IP testing and system-level application testing without manual comparison, thereby reducing the difficulty of chip board-level testing and shortening the testing time. In addition, by using a machine to compare data, defects that cannot be distinguished by the human eye can be discovered in a timely manner, thereby reducing costs and expanding production capacity to a good extent.

[0073] Preferably, if Figure 2 As shown, in the step of performing an open-short circuit test and comparing the results, the open-short circuit test includes the following steps:

[0074] S411, determining whether the number of IO ports is an even number, if so, dividing the general IO ports into two groups of equal number, a first group and a second group, on the core test board, and connecting the general IO ports of the first group and the second group one by one on the core test board;

[0075] In the first stage, the first group of general IO ports are controlled to output high level and low level respectively, and read back from the second group of general IO ports for judgment.

[0076] S412, control the first group of general IO ports to output high level, then read the output of the first group from the second group of general IO ports, and determine whether all are high level, if all are high level, proceed to the next step, otherwise it is determined to be a bad chip;

[0077] S413, control the first group of general IO ports to output low level, then read the output of the first group from the second group of general IO ports, and determine whether all are low level, if all are low level, proceed to the next step, otherwise it is determined to be a bad chip;

[0078] In the second stage, the second group of general IO ports are controlled to output high level and low level respectively, and read back from the first group of general IO ports for judgment.

[0079] S414, control the second group of general IO ports to output high level, then read the output of the second group from the first group of general IO ports, and determine whether all are high level, if all are high level, proceed to the next step, otherwise it is determined to be a bad chip;

[0080] S415, control the second group of general IO ports to output low level, then read the output of the second group from the first group of general IO ports, and determine whether all are low level, if all are low level, proceed to the next step, otherwise it is determined to be a bad chip;

[0081] S416, complete the open and short circuit test and proceed to the next functional test.

[0082] This embodiment can ensure that each IO port on the chip is a normal and available IO port by performing an open-short circuit test on the chip, thus laying a foundation for subsequent testing and use.

[0083] Preferably, if Figure 3 and Figure 8 As shown, if the number of IO ports is an odd number, the general IO ports are divided into two groups of equal number, the first group and the second group, on the core test board, and the general IO ports of the first group and the second group are connected one by one on the core test board, and the remaining independent IO port performs the following steps:

[0084] S421, the output of the remaining independent IO port is connected to the input of a latch chip, any IO of the first group is connected to the output control OE terminal of the latch chip, and the latch enable terminal LE of the latch chip is directly connected to the power supply, so that the latch enable is always valid. When the latch output control OE terminal is 1, the latch outputs a high impedance state and does not drive the bus. When the latch output control OE terminal is 0, the latch outputs the latched data.

[0085] In the first stage, the first group of general IO ports are controlled to output high and low levels respectively, and read back from the second group of general IO ports for judgment. After the independent IO port outputs a high level to the latch and then switches to input, the latch output is read back for judgment. The specific steps are as follows:

[0086] S422, control the first group of general IO ports to output high level, the latch output controls the OE terminal to be 1, and the latch outputs high impedance; control the independent IO to output high level, and read the output of the first group from the second group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip;

[0087] S423, control the first group of general IO ports to output a low level, the latch output controls the OE terminal to be 0, the latch outputs the latched independent IO state, and then controls the independent IO to switch to input, and determines whether the independent IO state output by the latch is a high level, if so, continue, otherwise it is determined to be a bad chip; read the output of the first group from the second group of general IO ports, and determine whether it is a low level, if all are low levels, proceed to the next step, otherwise it is determined to be a bad chip;

[0088] S424, control the independent IO to output low level, control the first group of general IO ports to output low level, the latch output controls the OE terminal to be 0, the latch outputs the latched independent IO state, which is low level, then control the independent IO to switch to input, and determine whether it is low level, if so, proceed to the next step, otherwise it is determined to be a bad chip;

[0089] In the second stage, the second group of general IO ports are controlled to output high level and low level respectively, and read back from the first group of general IO ports for judgment.

[0090] S425, control the second group of general IO ports to output high level, then read the output of the second group from the first group of general IO ports, and determine whether all are high level, if all are high level, proceed to the next step, otherwise it is determined to be a bad chip;

[0091] S426, control the second group of general IO ports to output low level, then read the output of the second group from the first group of general IO ports, and determine whether all are low level, if all are low level, proceed to the next step, otherwise it is determined to be a bad chip;

[0092] S427, complete the open and short circuit test and proceed to the next functional test.

[0093] This embodiment also takes into account the situation that when there is an odd number of IO ports, pairing and grouping cannot be achieved. By performing separate tests on independent IO ports, it is ensured that the open and short circuit tests can be fully covered without missing any IO ports, thereby ensuring the quality of the test.

[0094] Preferably, if Figure 4 As shown, in the step of performing a simulated IP test and comparing the results, the simulated IP includes a USB or a DDR, the USB or the DDR is provided with a BIST mode, and the test of the simulated IP includes the following steps:

[0095] S51, control the chip under test to enter the corresponding BIST mode;

[0096] S52, given input start signal;

[0097] S53. Determine whether the output is at a high level within a specific time.

[0098] This embodiment uses the BIST mode commonly used in the art to test the two analog IPs, USB and DDR, and can test the prepared results better and more stably, thereby ensuring the stability of the chip and the correctness of the test.

[0099] Preferably, in the step of performing analog IP testing and comparing results, the analog IP includes an ADC, and the ADC requires an external video decoding chip to control the output of a DAC analog signal, and the quality of the ADC function is determined by comparing the digital output of the chip under test.

[0100] This embodiment also takes into account the ADC interface in the analog IP, and performs corresponding test and comparison on the ADC through the control of an external video decoding chip, which can better and more stably test the prepared results and ensure the stability of the chip and the correctness of the test.

[0101] Preferably, if Figure 5 As shown, in the step of performing a system application test and comparing the results, the system application test includes the following steps:

[0102] S61, the external decoding control chip controls the chip under test to enter the functional test mode;

[0103] S62, after the chip under test starts the application from the flash and reads the multimedia data from the USB flash drive or SD card, it completes the audio and video decoding and image display processing internally and then outputs it to the HDMI interface;

[0104] S63, HDMI interface starts to output dynamic multimedia audio and video data;

[0105] S64, the external decoding control chip receives multimedia audio and video data from the HDMI input port, starts decoding, and then stores the data into the memory;

[0106] S65, the chip under test starts to read data from the U disk, and at the same time sends a start command to the external decoding control chip through the serial port. The decoding control chip simultaneously reads the same multimedia data from the U disk, completes decoding, and stores it in the memory;

[0107] S66, the main control video decoding chip starts comparing the local U disk decoded data with the multimedia data decoded by the HDMI input port;

[0108] S67, complete data comparison and determine whether the chip to be tested is good or bad.

[0109] This embodiment can ensure that the chip can be used normally and reduce failures during use by testing the system application, so as to ensure the stability of the chip and the correctness of the test when there are no problems with the IO port and the analog IP.

[0110] Preferably, if Figure 6 As shown, in the step of comparing the local U disk decoding data started by the main control video decoding chip with the multimedia data decoded by the HDMI input port, the following operations are specifically included:

[0111] S661, locate the I frame data after HDMI decoding;

[0112] S662, compare the first I frame of the video data decoded from the USB flash drive with the I frame decoded from the HDMI, and if the comparison fails, find the next I frame for comparison; if it fails, continue to find the next I frame for comparison until the comparison is successful or the set number of comparisons is exceeded; if the comparison is successful, proceed to the next step, and if the number of comparisons exceeds the set number, it is determined that the comparison has failed;

[0113] S663, compare the next P frame data and I frame data. If the comparison fails, it is determined to be a bad film. If the comparison succeeds, continue to compare until the preset number of I frame comparisons reaches the target value.

[0114] This embodiment can clearly display the HDMI decoding comparison process by performing specific operations on step S66 alone, so that the accuracy of this step is higher, and the prepared results can be tested better and more stably, thereby ensuring the stability of the chip and the correctness of the test.

[0115] The present embodiment discloses a video decoder chip SLT testing device, including a desktop tester and a core test board. The desktop tester is used to take, place and sort chips, and the desktop tester is used to control the power supply of the core test board and obtain feedback results of the core test board to implement a video decoder chip SLT method as described above.

[0116] like Figure 7 As shown, this embodiment discloses a device for the chip SLT test method, so that we can easily and quickly implement the chip SLT method on the device. At the same time, by combining a desktop tester, there is no need to use expensive ATE automated testing equipment, which greatly reduces the cost of testing.

[0117] Preferably, if Figure 7 As shown, the core test board includes a test main control chip and a test socket for the chip to be tested. The test main control chip is used to control the chip to be tested to complete the test, the test main control chip is used to control the start and stop of the power supply of the chip to be tested, and the test socket for the chip to be tested is used to clamp the chip to be tested.

[0118] The core test board in this embodiment is divided into two parts, which can conveniently and quickly clamp the chip, making it stable during the test process, and can control the power supply to ensure that the chip is controllable during the test process. Then, the test socket of the chip to be tested is used, so that the chip can be easily taken and placed during the test process.

[0119] This embodiment also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a test main control chip, the video decoding chip SLT method as described above is implemented.

[0120] In order to better store the relevant control programs, this embodiment also discloses a computer-readable storage medium, which is very convenient when the programs need to be executed and stored.

[0121] The above is an implementation method provided in combination with specific content, and it is not considered that the specific implementation of this application is limited to these descriptions. Any similarity or similarity with the method, structure, etc. of this application, or any technical deduction or replacement made on the premise of the concept of this application, shall be deemed to be within the scope of protection of this application.

Claims

1. A video decoding chip SLT method, characterized in that: The steps include: Desktop test machine initialization; The desktop tester automatically picks up the chip from the tray and places it into the test socket; The core test board is powered on; Perform open and short circuit tests and compare the results; Conduct simulated IP tests and compare the results; Conduct system application tests and compare results; The test stand completes the test and sends a test signal to the test machine; The desktop tester classifies the chips according to the signals; In the step of performing an open-short circuit test and comparing the results, the open-short circuit test includes the following steps: Determine whether the number of IO ports is an even number. If so, divide the general IO ports into two groups of equal number, a first group and a second group, on the core test board, and connect the general IO ports of the first group and the second group one by one on the core test board; In the first stage, the first group of general IO ports are controlled to output high and low levels respectively, and read back from the second group of general IO ports for judgment; Control the first group of general IO ports to output high level, then read the output of the first group from the second group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip; Control the first group of general IO ports to output low level, then read the output of the first group from the second group of general IO ports to determine whether they are all low level. If all are low level, proceed to the next step, otherwise it is determined to be a bad chip; In the second stage, the second group of general IO ports are controlled to output high level and low level respectively, and read back from the first group of general IO ports for judgment; Control the second group of general IO ports to output high level, then read the output of the second group from the first group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip; Control the second group of general IO ports to output low level, then read the output of the second group from the first group of general IO ports to determine whether they are all low level. If all are low level, proceed to the next step, otherwise it is determined to be a bad chip; If the number of IO ports is an odd number, divide the general IO ports into two groups of equal number, the first group and the second group, on the core test board, and connect the general IO ports of the first group and the second group one by one on the core test board. The remaining independent IO port performs the following steps: The output of the remaining independent IO port is connected to the input of a latch chip. Any IO of the first group is connected to the output control OE terminal of the latch chip. The latch enable terminal LE of the latch chip is directly connected to the power supply, so that the latch enable is always valid. When the latch output control OE terminal is 1, the latch outputs a high impedance state and does not drive the bus. When the latch output control OE terminal is 0, the latch outputs the latched data. In the first stage, the first group of general IO ports are controlled to output high and low levels respectively, and read back from the second group of general IO ports for judgment. The independent IO port outputs a high level to the latch and then switches to input to read the latch output back for judgment. The specific steps are as follows: Control the first group of general IO ports to output high level, the latch output controls the OE terminal to 1, and the latch outputs high impedance; control the independent IO to output high level, and read the output of the first group from the second group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip; Control the first group of general IO ports to output low level, the latch output controls the OE terminal to 0, the latch outputs the latched independent IO state, and then controls the independent IO to switch to input, and judges whether the independent IO state output by the latch is high level, if so, continue, otherwise it is judged as a bad chip; read the output of the first group from the second group of general IO ports, and judge whether it is low level, if all are low level, proceed to the next step, otherwise it is judged as a bad chip; Control the independent IO to output low level, control the first group of general IO ports to output low level, the latch output controls the OE terminal to be 0, the latch outputs the latched independent IO state, and then controls the independent IO to switch to input, and judges whether it is low level, if so, proceed to the next step, otherwise it is judged as a bad chip; In the second stage, the second group of general IO ports are controlled to output high level and low level respectively, and read back from the first group of general IO ports for judgment; Control the second group of general IO ports to output high level, then read the output of the second group from the first group of general IO ports to determine whether they are all high level. If all are high level, proceed to the next step, otherwise it is determined to be a bad chip; Control the second group of general IO ports to output low level, then read the output of the second group from the first group of general IO ports to determine whether they are all low level. If all are low level, proceed to the next step, otherwise it is determined to be a bad chip; Complete the open and short circuit test and proceed to the next functional test.

2. A video decoding chip SLT method according to claim 1, characterized in that: In the step of performing a simulated IP test and comparing the results, the simulated IP includes a USB or a DDR, the USB or the DDR is provided with a BIST mode, and the test of the simulated IP includes the following steps: Control the chip under test to enter the corresponding BIST mode; Given input start signal; Determines whether the output is high level within a specific time.

3. A video decoding chip SLT method according to claim 1, characterized in that: In the step of performing analog IP testing and comparing the results, the analog IP includes an ADC, and the ADC requires an external video decoding chip to control the output DAC analog signal. The quality of the ADC function is determined by comparing the digital output of the chip under test.

4. A video decoding chip SLT test device, characterized in that: It includes a desktop test machine and a core test board, wherein the desktop test machine is used to take, place and sort chips, and the desktop test machine is used to control the power supply of the core test board and obtain feedback results of the core test board to implement a video decoding chip SLT method as described in any one of claims 1-3.

5. A video decoding chip SLT testing device according to claim 4, characterized in that: The core test board includes a test main control chip and a test socket for the chip to be tested. The test main control chip is used to control the chip to be tested to complete the test. The test main control chip is used to control the start and stop of the power supply of the chip to be tested. The test socket for the chip to be tested is used to clamp the chip to be tested.

6. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the test main control chip, a video decoding chip SLT method as described in any one of claims 1-3 is implemented.

Images