A Linear Regulator without External Capacitors and Enhanced Transient Response
By introducing buffers and second-stage error amplifiers into off-chip capacitor linear regulators, the problem of insufficient transient response in traditional regulators when load changes is solved, enabling faster capacitance charging and discharging and higher Gain bandwidth improves the transient performance of the regulator.
Patent Information
- Application Number
- CN202211548928.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-05
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2042-12-05
AI Technical Summary
The traditional off-chip capacitor linear regulator will generate a large overshoot voltage when the load changes, affecting chip performance, and insufficient transient response, resulting in MOS tube breakdown.
The introduction of a new structure of buffer and a second-stage error amplifier between the first-stage error amplifier and the power tube will increase the loop gain bandwidth and increase the charging and discharging speed of the gate capacitance of the power tube, and achieve in-phase position through the RC high-pass filter Signal transmission reduces impedance and improves transient performance.
It significantly improves the transient response performance of the linear regulator, shortens the transient response time, increases the gain bandwidth, reduces the overshoot voltage amplitude at the output, and improves the rapid response ability to load changes.
Smart Images
Figure CN115729301B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of switch power supply management in analog integrated circuits, and specifically provides a linear voltage regulator with enhanced transient response and no external capacitor. Background Art
[0002] In recent years, with the continuous development of consumer electronic products, such as smart phones and tablet computers have become indispensable tools for people; these electronic products require a stable working power supply, such as mobile phones need a power supply with low noise and low ripple, and using a low dropout linear regulator (LDO) for power supply is a good choice. Figure 1 The figure shows a traditional linear regulator (LDO) without external capacitor, including: reference module, error amplifier module, power tube (M P ), voltage negative feedback branch (resistance R f1 , R f2 )、Frequency compensation module (C m );Among them, the power tube M P With resistor R f1 , R f2 In series, the resistor R f1 With R f2 The feedback voltage signal is generated between the positive input and the positive input of the error amplifier. The single-ended output of the error amplifier is connected to the power tube M. P The gate of the power tube M forms a closed loop; the frequency compensation module is usually used to adjust the stability of the loop. P The function is to maintain a stable output voltage by adjusting its own output current when the load current or input voltage changes. When the load current or input voltage changes, the output voltage passes through the resistor R f1 With resistor R f2 The feedback voltage signal is transmitted to the positive input terminal of the error amplifier through the voltage division, and then amplified by the error amplifier and transmitted to the power tube M. P The gate of the power tube M P The output current produces an opposite change, thus stabilizing the output voltage.
[0003] For the above-mentioned traditional off-chip capacitor-free linear regulator (LDO), when the load changes, since there is no large load capacitor CL to adjust the load current, a relatively large overshoot voltage will be generated at the output end of the LDO. The process of the overshoot voltage recovering to the normal voltage through the negative feedback system is the transient response process. A long-term large overshoot voltage will cause the MOS tube to break down, thereby affecting the chip performance. Therefore, it is necessary to enhance the transient response process of the LDO. Summary of the invention
[0004] The present invention aims at the problem of large signal fluctuation when switching the working state of LDO in the prior art, and provides a linear regulator without external capacitor with enhanced transient response. The present invention introduces a buffer with a new structure and a second-stage error amplifier between the first-stage error amplifier and the power tube, which can increase the loop gain bandwidth of the structure and improve the charging and discharging speed of the second-stage error amplifier to the gate capacitance of the power tube, and finally improves the transient performance of the linear regulator (LDO) from the aspects of bandwidth and speed.
[0005] To achieve the above object, the technical solution adopted by the present invention is:
[0006] A transient response enhanced non-external capacitor linear regulator is characterized by comprising: a reference module, a first-stage error amplifier, a buffer, a second-stage error amplifier, a power tube, a feedback branch and a frequency compensation module; wherein the reference module outputs a reference voltage Vref to the negative input terminal of the first-stage error amplifier, the output of the first-stage error amplifier is sequentially input to the gate of the power tube after passing through the buffer and the second-stage error amplifier, the feedback branch is connected between the drain of the power tube and the positive input terminal of the first-stage error amplifier, and the frequency compensation module is connected between the gate of the power tube and the common gate terminal of the second current mirror in the first-stage error amplifier.
[0007] Furthermore, the buffer is composed of a PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 , resistor R C With capacitor C C The second stage error amplifier is composed of a PMOS tube M 19 With NMOS tube M 20 Composition: PMOS tube M 16 The gate of the PMOS tube M is connected to the output of the first stage error amplifier. 17 The gate and drain are short-circuited and connected to the PMOS tube M 16 The drain of NMOS tube M 18 The drain connection of PMOS tube M 16 With PMOS tube M 17 The source of the PMOS tube M is connected to the power supply VDD. 18 The gate of the PMOS tube M is connected to the bias voltage. 18 The source of the NMOS tube M is grounded; the capacitor Cc is connected across 17 The gate of NMOS tube M 20 Between the gates, the resistor R C Connected across NMOS tube M 18 The gate of NMOS tube M 20 Between the gates of the PMOS tube M 19The source of the NMOS tube M is connected to the power supply VDD. 20 The source of the PMOS tube M is grounded. 19 The drain of NMOS tube M 20 The drain is short-circuited and output to the gate of the power tube.
[0008] Furthermore, the frequency compensation module is composed of a capacitor C M With resistor R M Series composition.
[0009] Furthermore, the feedback branch is composed of a resistor R f1 With resistor R f2 Composition, resistance R f1 One end is connected to the drain of the power tube and the other end is connected to the resistor R f2 to ground, resistor R f1 With resistor R f2 The feedback voltage signal is generated between the two and input to the positive input terminal of the first-stage error amplifier.
[0010] Based on the above technical solution, the beneficial effects of the present invention are:
[0011] The present invention proposes a low voltage difference output transient response enhanced non-chip capacitor linear regulator (LDO), a buffer with a new structure and a second-stage error amplifier are introduced between the first-stage error amplifier and the power tube, the buffer with the new structure can realize the same-phase signal transmission, the feedback signal amplified by the first-stage error amplifier is transmitted through the buffer (including RC high-pass filter: resistor R C With capacitor C C ) can increase the charging and discharging speed of the second-stage error amplifier to the gate capacitance of the power tube; and the buffer located between the two-stage error amplifier can also reduce the output capacitance of the first-stage error amplifier and the input impedance of the second-stage error amplifier, and move the secondary pole located at the input end of the second-stage error amplifier to a higher frequency position, thereby greatly increasing the gain bandwidth of the LDO loop; ultimately, the transient performance of the linear regulator (LDO) is improved in terms of speed and bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 Schematic diagram of the structure of a traditional linear regulator (LDO).
[0013] Figure 2 The schematic diagram is a structural diagram of a linear regulator (LDO) without external capacitors and with enhanced transient response in the present invention.
[0014] Figure 3 The schematic diagram of the circuit principle of the transient response enhanced non-external capacitor linear regulator (LDO) in the present invention.
[0015] Figure 4The diagram is a schematic diagram of voltage changes at each node when the output of the transient response enhanced non-external capacitor linear regulator of the present invention switches from light load to heavy load.
[0016] Figure 5 The diagram is a schematic diagram of voltage changes at each node when the output of the transient response enhanced non-external capacitor linear regulator of the present invention switches from heavy load to light load.
[0017] Figure 6 The transient response curve of the output voltage of the linear regulator without external capacitor and with enhanced transient response according to the embodiment of the present invention as the load is switched.
[0018] Figure 7 The transient response curve is a comparison of the output voltage of the linear regulator without external capacitor and with enhanced transient response according to the embodiment of the present invention as the load is switched.
[0019] Figure 8 The figure is an amplitude-frequency characteristic curve of the transient response enhanced non-external capacitor linear regulator under different loads in an embodiment of the present invention.
[0020] Fig. 9 The phase-frequency characteristic curves of the transient response enhanced non-external capacitor linear regulator under different loads in the embodiment of the present invention. DETAILED DESCRIPTION
[0021] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.
[0022] This embodiment provides a linear regulator without external capacitors with enhanced transient response, and its structure is as follows: Figure 2 As shown, the specific circuit is as follows Figure 3 As shown; it mainly includes: a reference module, a first-stage error amplifier, a buffer, a second-stage error amplifier, a power tube, a feedback branch and a frequency compensation module; wherein the reference module outputs a reference voltage Vref to the negative input terminal of the first-stage error amplifier, the output of the first-stage error amplifier is sequentially input to the gate of the power tube after passing through the buffer and the second-stage error amplifier, the feedback branch is connected between the drain of the power tube and the positive input terminal of the first-stage error amplifier, and the frequency compensation module is connected between the gate of the power tube and the common gate terminal of the second active current mirror in the first-stage error amplifier.
[0023] Furthermore, the power tube adopts a PMOS tube M P , PMOS tube M P The source is connected to the power supply VDD.
[0024] Furthermore, the first-stage error amplifier is composed of MOS tubes M1 to M 15Composition: PMOS tube M1 is a tail current source, its source is connected to the power supply VDD, the gate is connected to the bias voltage VB1, and the drain is connected to the source of PMOS tube M2, PMOS tube M3, PMOS tube M4, and PMOS tube M5; PMOS tube M2 and PMOS tube M3 serve as the negative input terminal of the error amplifier, and the gates of both are connected to the feedback branch; the gates of PMOS tube M4 and PMOS tube M5 serve as the positive terminal of the error amplifier, and the gates of both are connected to the reference voltage Vref; the drain of PMOS tube M2 is connected to the drain of NMOS tube M8 The gate of NMOS tube M8 is short-circuited with the gate of NMOS tube M9 and connected to the drain of NMOS tube M6 and the drain of NMOS tube M4. The gate of NMOS tube M6 is short-circuited with the gate of NMOS tube M7 and a bias voltage VB2 is applied. The source of NMOS tube M6 is connected to the drain of NMOS tube M9. NMOS tubes M6, M8 and M9 form a first active current mirror, which copies the current signal generated by PMOS tube M4 to the branch where NMOS tube M8 is located. The drain of NMOS tube M8 is connected to the drain of NMOS tube M4. 14 The source of the PMOS tube M5 is connected to the drain of the NMOS tube M 11 The drain stage of NMOS tube M 11 The gate of NMOS tube M 10 The gate of the NMOS tube M7 is short-circuited (common gate end) and connected to the drain of the NMOS tube M7 and the drain of the PMOS tube M3. The source of the NMOS tube M7 is connected to the NMOS tube M 10 The drain of NMOS tube M7, NMOS tube M 10 、NMOS tube M 11 The second active current mirror is formed to copy the current signal generated by the PMOS tube M3 to the NMOS tube M 11 The branch where it is located, NMOS tube M 11 The drain of NMOS tube M 15 The source connection of NMOS tube M 14 The gate of NMOS tube M 15 The gate of NMOS tube M is short-circuited. 14 The drain of the PMOS tube M 12 The gate and drain of NMOS tube M 15 The drain of the PMOS tube M 13 The drain of PMOS tube M 12 The gate of the PMOS tube M 13 The gate of the PMOS tube M is short-circuited. 12 With PMOS tube M 13 The source of the PMOS tube M is connected to the power supply VDD; 12 With PMOS tube M 13 The third active current mirror is formed, so that the error amplifier is composed of PMOS tube M13 The drain single-ended output to the PMOS tube M 16 The gate of the buffer is the input end of the buffer; NMOS tube M8, NMOS tube M9, NMOS tube M 10 、NMOS tube M 11 It should be noted that the first-stage error amplifier adopts the existing technology to realize the error amplification function.
[0025] Furthermore, the buffer is composed of a MOS tube M 16 ~M 18 And the resistor R C , capacitor C C The second stage error amplifier is composed of a PMOS tube M 19 With NMOS tube M 20 Composition: PMOS tube M 16 The gate of the PMOS tube M is connected to the output of the first stage error amplifier. 17 The gate and drain are short-circuited and connected to the PMOS tube M 16 The drain of NMOS tube M 18 The drain connection of PMOS tube M 16 With PMOS tube M 17 The source of the PMOS tube M is connected to the power supply VDD. 18 The gate of the PMOS tube M is connected to the bias voltage VB3. 18 The source of the NMOS tube M is grounded; the capacitor Cc is connected across 17 The gate of NMOS tube M 20 Between the gates, the resistor R C Connected across NMOS tube M 18 The gate of NMOS tube M 20 Between the gates of the PMOS tube M 19 The source of the NMOS tube M is connected to the power supply VDD. 20 The source of the PMOS tube M is grounded. 19 The drain of NMOS tube M 20 The drain of the PMOS tube M is short-circuited and output to the PMOS tube M P The gate of the power tube.
[0026] Furthermore, the frequency compensation module is composed of a capacitor C M With resistor R M Composition, capacitor C M With resistor R M After connecting in series, it is connected across the PMOS tube M P The gate of the first stage error amplifier is connected to the common gate terminal of the second active current mirror (NMOS tube M 11 The gate of NMOS tube M 10 of the gate).
[0027] Furthermore, the feedback branch is composed of a resistor R f1 With resistor R f2 Composition, resistance R f1 One end is connected to PMOS tube M P The drain of the other end is connected to the resistor R f2 to ground, resistor R f1 With resistor R f2 The feedback voltage signal is generated between the two and input to the positive input terminal of the first-stage error amplifier.
[0028] In terms of working principle, the working process of the above-mentioned transient response enhanced non-external capacitor linear regulator includes the following stages:
[0029] like Figure 4 As shown in Figure 1, when the output of the LDO switches from a light load to a heavy load, the output voltage will decrease, resulting in an undershoot; this voltage change is transmitted to the positive input of the error amplifier through the feedback network, then amplified by the error amplifier, and then transmitted to the PMOS tube M. 16 The gate of PMOS tube M 16 The gate voltage decreases, and the PMOS tube M 16 The source voltage of NMOS tube M increases; at this time, 19 The gate voltage of the NMOS tube M increases, and the 19 The current of PMOS tube M will decrease instantly; 16 The source of NMOS tube M is coupled through capacitor Cc 20 The gate of NMOS tube M 20 The gate voltage of NMOS tube M increases. 20 The current of NMOS tube M increases instantly, so 20 With NMOS tube M 19 The current difference will draw current from the gate capacitance of the power tube, which can effectively improve the second stage of the error amplifier on the power tube M. P The discharge speed of the gate capacitor increases the conversion rate of the signal, that is, the transient response is enhanced;
[0030] like Figure 5 As shown in Figure 1, when the output of the LDO switches from heavy load to light load, the output voltage will increase, resulting in overshoot; this voltage change is transmitted to the negative input terminal of the error amplifier through the feedback network, then amplified by the error amplifier, and then transmitted to the PMOS tube M. 16 The gate of PMOS tube M 16 The gate voltage increases, and the PMOS tube M 16 The source voltage of NMOS tube M is reduced. 19 The gate voltage of the NMOS tube M is reduced, and the 19 The current of PMOS tube M will increase instantly;16 The source of NMOS tube M is coupled through capacitor Cc 20 The gate of NMOS tube M 20 The gate voltage of NMOS tube M is reduced. 20 The current of NMOS tube M decreases instantly, so 19 With NMOS tube M 20 The current difference will charge the gate capacitance of the power tube, which can effectively improve the second-stage error amplifier to the power tube M. P The gate capacitance is charged faster, which enhances the transient response.
[0031] The output voltage of the linear regulator without external capacitor with enhanced transient response in this embodiment changes with load switching as shown in FIG. Figure 6 , 7 As shown in the figure, it can be seen that when the output of the LDO switches from a light load (I=200uA) to a heavy load (I=10mA) within 1us, the undershoot voltage amplitude generated at the output end is 0.053V, and the transient response time is 1.34us; while the undershoot voltage amplitude generated by the traditional LDO structure is 0.22V, and the transient response time is 1.91us; when the output of the LDO switches from a heavy load (I=10mA) to a light load (I=200uA) within 1us, the overshoot voltage amplitude generated at the output end is 0.051V, and the transient response time is 0.50us; while the undershoot voltage amplitude generated by the traditional LDO structure is 0.30V, and the transient response time is 1.41us; it can be seen that the present invention has good transient response performance compared with the traditional structure.
[0032] The amplitude-frequency characteristic curves of the transient response enhanced non-external capacitor linear regulator under different loads in this embodiment are as follows: Figure 8 , 9 As shown in the figure, it can be seen that when the load is 10mA, the closed-loop gain of the present invention is 82.47dB, the gain bandwidth is 53.58MHz, and the phase margin is 45.8deg; when the load is 1mA, the closed-loop gain of the present invention is 85.92dB, the gain bandwidth is 10.44MHz, and the phase margin is 67.7deg; when the load is 200uA, the closed-loop gain of the present invention is 85.92dB, the gain bandwidth is 4.20MHz, and the phase margin is 45.2deg.
[0033] In summary, the present invention provides a low dropout linear regulator (LDO) with fast transient response capability, which achieves fast transient response when the output load jumps and meets higher precision indicators.
[0034] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.
Claims
1. A linear regulator with enhanced transient response and no external capacitor, characterized in that: include: The reference module, the first-stage error amplifier, the buffer, the second-stage error amplifier, the power tube, the feedback branch and the frequency compensation module are composed; wherein the reference module outputs the reference voltage Vref to the negative input terminal of the first-stage error amplifier, the output of the first-stage error amplifier is sequentially input to the gate of the power tube after passing through the buffer and the second-stage error amplifier, the feedback branch is connected between the drain of the power tube and the positive input terminal of the first-stage error amplifier, and the frequency compensation module is connected between the gate of the power tube and the common gate terminal of the second current mirror in the first-stage error amplifier; The buffer is composed of a PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 , resistor R C With capacitor C C The second stage error amplifier is composed of a PMOS tube M 19 With NMOS tube M 20 Composition: PMOS tube M 16 The gate of the PMOS tube M is connected to the output of the first stage error amplifier. 17 The gate and drain are short-circuited and connected to the PMOS tube M 16 The drain of NMOS tube M 18 The drain connection of PMOS tube M 16 With PMOS tube M 17 The source of the PMOS tube M is connected to the power supply VDD. 18 The gate of the PMOS tube M is connected to the bias voltage. 18 The source of the NMOS tube M is grounded; the capacitor Cc is connected across 17 The gate of NMOS tube M 20 Between the gates, the resistor R C Connected across NMOS tube M 18 The gate of NMOS tube M 20 Between the gates of the PMOS tube M 19 The source of the NMOS tube M is connected to the power supply VDD. 20 The source of the PMOS tube M is grounded. 19 The drain of NMOS tube M 20 The drain is short-circuited and output to the gate of the power tube.
2. The linear regulator with enhanced transient response and no external capacitor according to claim 1, characterized in that: The frequency compensation module consists of a capacitor C M With resistor R M Series composition.
3. The linear regulator with enhanced transient response and no external capacitor according to claim 1, characterized in that: The feedback branch is connected by a resistor R f1 With resistor R f2 Composition, resistance R f1 One end is connected to the drain of the power tube and the other end is connected to the resistor R f2 to ground, resistor R f1 With resistor R f2 The feedback voltage signal is generated between the two and input to the positive input terminal of the first-stage error amplifier.