A method for integrating asymmetric stress-distributed vertical channel nanowire transistors

By employing an integration method with asymmetric stress distribution in vertical channel nanowire transistors, and utilizing lattice fitting and epitaxial processes, the problem of stress modulation that cannot be applied to existing vertical channel nanowire/nanosheet devices has been solved, achieving complementary on-state current and enhanced drive current in N/P type devices.

CN115763378BActive Publication Date: 2025-10-28PEKING UNIV +1
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Patent Information

Application Number
CN202211323483.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-10-27
Publication Date
2025-10-28
Estimated Expiration
2042-10-27

AI Technical Summary

Technical Problem

During the integration process, existing vertical channel nanowire/nanosheet devices cannot effectively apply and control stress through conventional stress engineering, resulting in the inability of N/P type devices to complement each other's on-state currents, making it difficult to meet the requirements of CMOS circuits.

Method used

By epitaxially forming materials with different lattice constants on a substrate, and combining lattice matching and epitaxial processes, asymmetric stress distribution can be achieved. The specific steps include forming the lattice constant difference between the bottom and top source/drain materials, using lattice mismatch to generate uniaxial stress in the vertical direction, and combining anisotropic etching and dielectric deposition to form the device structure.

Benefits of technology

It achieves complementary on-state currents of N/P type devices, improves the driving current and subthreshold characteristics of the devices, and enables flexible control of stress distribution during integration, adapting to the integration of multiple materials in the devices.

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Abstract

This invention discloses an integration method for asymmetric stress-distributed vertical-channel nanowire transistors, belonging to the field of very large-scale integrated circuit manufacturing technology. This invention designs the source / drain materials and channel materials separately, effectively applying uniaxial stress in the channel. By adjusting the magnitude and distribution of this stress, complementary drive currents are achieved for N / P type devices. Simultaneously, this invention effectively improves the hole mobility and on-state current of P-type MOSFETs. The vertical nanowire devices can achieve discrete source / drain fabrication in the manufacturing process, providing greater flexibility for adjusting device characteristics.
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