Communication method of serial bus, data signal sampling circuit of serial bus, and sampling method

Abstract

The application provides a serial bus communication method, a serial bus data signal sampling circuit and a sampling method. The serial bus communication method comprises the following steps: a host device sends an initial data signal and an initial sampling clock signal; when the host device sends the initial data signal, if the value sent in the current data sampling period is different from the value sent in the last data sampling period, the initial sampling clock signal is turned off in one data sampling period. The sampling circuit comprises a flip-flop, a first rising edge detection circuit, a first falling edge detection circuit, a first delay circuit, a second delay circuit, an OR gate, which receives the first delay clock signal and the second delay clock signal, and receives the reference sampling clock signal and performs an OR operation. The sampling method samples the data signal by using the above-mentioned sampling circuit. The application can improve the data transmission efficiency of the serial bus.

Description

Technical Field

[0001] This invention relates to the technical field of data communication and sampling, and more specifically, to a serial bus communication method, a serial bus data signal sampling circuit, and a sampling method implemented using such a circuit. Background Technology

[0002] Printing devices such as inkjet printers and laser printers typically have multiple printing consumable containers. For example, an inkjet printer contains multiple ink cartridges of different colors, and each cartridge has a cartridge chip. The control circuit of the inkjet printer needs to communicate with each cartridge chip to control the operation of each cartridge.

[0003] Most existing printers use the SPI bus for data transmission. Because the SPI bus is a serial communication bus, its communication protocol is simple, it has fewer signal lines, and its communication speed is relatively fast, making it widely used in current printers. Typically, an SPI bus includes data signal lines and clock signal lines. The number of data signal lines can be one or two, and the master and slave devices transmit data through these data signal lines. In addition, the master device sends a clock signal through the clock signal line, and each slave device receives the clock signal and uses it as a synchronization reference to sample the data signals.

[0004] like Figure 1 As shown, in the existing SPI communication protocol (taking CPOL=0, CPHA=0 configuration as an example), data is typically sampled at the rising edge of the clock signal SCK and transmitted at the falling edge of the clock signal SCK. Typically, both the master and slave devices have clock triggers. The data signal on the data signal line is obtained from the data input terminal of the trigger, and the clock signal terminal of the trigger receives the clock signal SCK, sampling the data signal once at each rising edge of the clock signal SCK.

[0005] However, the communication speed of existing SPI buses is often limited. The main limitation is that when the data signal changes, it needs to meet the requirements of setup and hold time. The setup time is the shortest time that the signal at the data input terminal of the flip-flop must remain stable before the rising edge of the clock signal, i.e., before the data sampling time. For example... Figure 1 Label 31 represents a setup time interval, which is the time interval between the data signal change and the next rising edge of the clock signal. Hold time refers to the shortest time after the rising edge of the clock signal, i.e., after the data sampling time, the signal at the data input of the flip-flop must remain stable. For example... Figure 1Label 32 represents a hold time interval, which is the time interval between the data signal change and the rising edge of the previous clock signal. If the clock signal frequency is too high, it can easily lead to insufficient setup and hold times, resulting in setup and hold time violations. To ensure that setup and hold times do not violate these rules, the existing solution is to reduce the clock signal frequency, which leads to low communication efficiency of the SPI bus. Summary of the Invention

[0006] The first objective of this invention is to provide a serial bus communication method that improves data communication efficiency.

[0007] The second objective of this invention is to provide a serial bus data signal sampling circuit that effectively avoids setup time and hold time violations and improves communication efficiency.

[0008] A third objective of this invention is to provide a data signal sampling method that utilizes the aforementioned serial bus data signal sampling circuit.

[0009] To achieve the first objective mentioned above, the serial bus communication method provided by the present invention includes: the master device sending an initial data signal and an initial sampling clock signal; when the master device sends the initial data signal, if the value sent in the current data sampling period is different from the value sent in the previous data sampling period, the initial sampling clock signal is turned off within one data sampling period.

[0010] As can be seen from the above scheme, when the data sent in the current data sampling period is different from the data sent in the previous data sampling period, turning off the initial sampling clock signal can sample the data on the data signal line once when the level of the data signal line changes, thereby avoiding the problems of setup time and hold time violations. This can increase the frequency of the clock signal and thus improve the efficiency of data transmission.

[0011] A preferred approach is to turn off the initial sampling clock signal during the current data sampling period if the value sent in the current data sampling period is different from the value sent in the previous data sampling period.

[0012] Therefore, by turning off the initial sampling clock signal during the current data sampling period, we can avoid sampling the data signal twice in the same data sampling period, thus ensuring the accuracy of the sampling results.

[0013] A further approach is to keep the clock signal line at a fixed level during the period when the initial sampling clock signal is turned off.

[0014] As can be seen, no rising or falling edge is generated during the initial sampling clock signal shutdown, so no data is sampled, thus avoiding data sampling errors.

[0015] A further approach is to increase the clock frequency of the initial sampling clock signal if the value sent in the current data sampling period is equal to the value sent in the previous two data sampling periods.

[0016] Therefore, increasing the clock frequency of the initial sampling clock signal can further improve the efficiency of data transmission.

[0017] To achieve the second objective mentioned above, the serial bus data signal sampling circuit provided by the present invention includes a flip-flop, the data input terminal of which receives an initial data signal; it also includes: a first rising edge detection circuit for detecting the rising edge signal of the initial data signal; a first falling edge detection circuit for detecting the falling edge signal of the initial data signal; a first delay circuit for receiving the signal output by the first rising edge detection circuit and outputting a first delayed clock signal after a preset delay time after receiving the signal output by the first rising edge detection circuit; a second delay circuit for receiving the signal output by the first falling edge detection circuit and outputting a second delayed clock signal after a preset delay time after receiving the signal output by the first falling edge detection circuit; and an OR gate for receiving the first delayed clock signal and the second delayed clock signal, and receiving a reference sampling clock signal, ORing the first delayed clock signal, the second delayed clock signal, and the reference sampling clock signal, and outputting a target sampling clock signal to the flip-flop; wherein the preset delay time is less than one clock cycle of the reference sampling clock signal.

[0018] As can be seen from the above scheme, after the rising and falling edges of the initial data signal arrive, a first delayed clock signal and a second delayed clock signal are formed after a certain delay. The data signal is sampled at the rising edge of the pulses of the first and second delayed clock signals. Since the initial data signal undergoes level changes at the rising and falling edges, and the initial data signal typically maintains its level for a period of time after the level change, sampling the initial data signal after a very short time delay following the detection of the rising and falling edges ensures that the initial data signal level remains stable during the sampling period, avoiding setup and hold time violations. Based on this, the frequency of the clock signal can be increased, thereby improving the data transmission rate.

[0019] A preferred embodiment further includes a second rising edge detection circuit and a second falling edge detection circuit; the second rising edge detection circuit receives the rising edge signal of the initial sampling clock signal and outputs a first detection signal when it receives the rising edge signal of the initial sampling clock signal; the second falling edge detection circuit receives the falling edge signal of the initial sampling clock signal and outputs a second detection signal when it receives the falling edge signal of the initial sampling clock signal; the reference sampling clock signal received by the OR gate includes the first detection signal and the second detection signal.

[0020] Therefore, by detecting the rising and falling edges of the initial sampling clock signal and sampling data at the rising and falling edges of the initial sampling clock signal, the efficiency of data sampling can be further improved. The data signal line can use half a clock cycle as the data transmission period, which further improves the data transmission efficiency.

[0021] A further approach is to preset the delay time to be less than half a clock cycle of the initial sampling clock signal.

[0022] It is evident that setting a shorter preset delay time can prevent inaccurate data sampling caused by an excessively long preset time.

[0023] A further approach is to connect a shift register to the output of the flip-flop, which receives the target sampling clock signal.

[0024] As can be seen, the shift register can receive the data output by the flip-flop, thus realizing the function of data storage. Moreover, the shift register also uses the target sampling clock signal as its working clock signal, which can ensure that every bit of data output by the flip-flop can be correctly received by the shift register.

[0025] A further approach is that the first delayed clock signal is a pulse signal, and the high-level duration of the pulse signal is less than half a clock cycle of the initial sampling clock signal; and / or the second delayed clock signal is a pulse signal, and the high-level duration of the pulse signal is less than half a clock cycle of the initial sampling clock signal.

[0026] It can be seen that the high-level time of the pulse signals of the first and second delayed clock signals is not long, which can avoid inaccurate data sampling due to excessively long high-level duration.

[0027] An alternative approach is that the first detection signal is a pulse signal, and the high-level duration of the pulse signal is less than half a clock cycle of the initial sampling clock signal; and / or the second detection signal is a pulse signal, and the high-level duration of the pulse signal is less than half a clock cycle of the initial sampling clock signal.

[0028] It can be seen that the high-level time of the pulse signals of the first detection signal and the second detection signal is not long, which can avoid the data sampling being inaccurate due to the high-level duration being too long.

[0029] To achieve the third objective mentioned above, the serial bus data signal sampling method provided by the present invention includes: applying a first rising edge detection circuit to detect the rising edge signal of the initial data signal and outputting it to a first delay circuit; the first delay circuit receiving the signal output by the first rising edge detection circuit and outputting a first delayed clock signal after a preset delay time after receiving the signal output by the first rising edge detection circuit; applying a first falling edge detection circuit to detect the falling edge signal of the initial data signal and outputting it to a second delay circuit; the second delay circuit receiving the signal output by the first falling edge detection circuit and outputting a second delayed clock signal after a preset delay time after receiving the signal output by the first falling edge detection circuit; ORing the first delayed clock signal, the second delayed clock signal, and a reference sampling clock signal to output a target sampling clock signal to a flip-flop; wherein the preset delay time is less than one clock cycle of the reference sampling clock signal; and the flip-flop receiving the initial data signal and sampling the initial data signal using the target sampling clock signal.

[0030] As can be seen from the above scheme, after the rising and falling edges of the initial data signal arrive, a first delayed clock signal and a second delayed clock signal are formed after a certain delay. The data signal is sampled at the rising edge of the pulses of the first and second delayed clock signals. Since the initial data signal undergoes level changes at the rising and falling edges, and the initial data signal usually remains stable for a period of time after the level change, sampling the initial data signal after a very short time delay after detecting the rising and falling edges can ensure that the initial data signal level remains stable during the sampling period, avoiding setup and hold time violations.

[0031] A preferred embodiment of the method further includes using a second rising edge detection circuit to receive the rising edge signal of the initial sampling clock signal and outputting a first detection signal when the rising edge signal of the initial sampling clock signal is received; using a second falling edge detection circuit to receive the falling edge signal of the initial sampling clock signal and outputting a second detection signal when the falling edge signal of the initial sampling clock signal is received; and ORing the first delayed clock signal, the second delayed clock signal, and the reference sampling clock signal to output a target sampling clock signal to the flip-flop includes: ORing the first delayed clock signal, the second delayed clock signal, the first detection signal, and the second detection signal to output a target sampling clock signal to the flip-flop.

[0032] A further approach is to turn off the initial sampling clock signal within one data sampling period when the value of the current period of the initial data signal is not equal to the value of the previous period.

[0033] It is evident that turning off the initial sampling clock signal after the level of the initial data signal changes can prevent frequent sampling of the data signal due to changes in the initial sampling clock signal, thus ensuring the accuracy of sampling.

[0034] A further approach is to keep the clock signal line level unchanged during the period when the initial sampling clock signal is turned off.

[0035] Therefore, protecting the stability of the clock signal line level during the initial sampling clock signal shutdown can prevent the sampling of data signals from being affected by changes in the clock signal line level, thus ensuring the accuracy of data sampling. Attached Figure Description

[0036] Figure 1 This is a waveform diagram of the data signal and clock signal during the data signal sampling process of the existing SPI bus.

[0037] Figure 2 This is a structural block diagram of the first embodiment of the serial bus data signal sampling circuit of the present invention.

[0038] Figure 3 This is a waveform diagram of the data signal and each clock signal in the first embodiment of the serial bus communication method of the present invention.

[0039] Figure 4 This is a structural block diagram of the second embodiment of the serial bus data signal sampling circuit of the present invention.

[0040] Figure 5 This is a waveform diagram of the data signal and each clock signal in the second embodiment of the serial bus communication method of the present invention.

[0041] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0042] The serial bus communication method and data signal sampling circuit of the present invention can be applied to printing devices such as inkjet printers and laser printers, and can also be applied to communication systems of other master-slave devices. The serial bus data signal sampling method of the present invention is implemented using the aforementioned serial bus data signal sampling circuit.

[0043] First embodiment:

[0044] This embodiment references and improves upon the existing SPI bus communication method. Specifically, a serial bus is established between the master and slave devices. The serial bus includes clock signal lines and data signal lines. The master device sends a clock signal to the clock signal line, and the slave device maintains synchronous communication with the master device through this clock signal. During data sampling, the slave device samples the signal on the data signal line at the rising edge of each clock cycle.

[0045] In this embodiment, the master device improves the clock signal transmission method and the slave device improves the data sampling method. Furthermore, the slave device includes a data signal sampling circuit. See [link / reference] Figure 2 The serial bus data signal sampling circuit in this embodiment includes a flip-flop 16 and a shift register 17, both of which can be implemented using D flip-flops. The data input terminal of the flip-flop 16 acquires the initial data signal; specifically, the data input terminal of the flip-flop 16 is connected to the data signal line of the serial bus. The output terminal of the flip-flop 16 is connected to the data input terminal of the shift register 17, and the shift register 17 stores the data output by the flip-flop 16.

[0046] This embodiment also includes a first rising edge detection circuit 11, a first delay circuit 12, a first falling edge detection circuit 13, and a second delay circuit 14. The first rising edge detection circuit 11 and the first falling edge detection circuit 13 can both be implemented using known level edge detection circuits. The first delay circuit 12 and the second delay circuit 14 can both be implemented using an even number of NOT gates. Their function is to delay the input signal.

[0047] The first rising edge detection circuit 11 is used to detect the rising edge of the initial data signal, and the first falling edge detection circuit 13 is used to detect the falling edge of the initial data signal. Therefore, both the first rising edge detection circuit 11 and the first falling edge detection circuit 13 are connected to the data signal line of the serial bus. When the first rising edge detection circuit 11 detects the rising edge of the initial data signal, it outputs a pulse signal. Preferably, the high-level duration of the pulse signal is very short, for example, less than one cycle of the initial sampling clock signal, and further, less than half a cycle of the initial sampling clock signal. The initial sampling clock signal is the clock signal sent by the master device to the clock signal line of the serial bus, and this clock signal is the synchronization signal for communication between the master device and the slave device. When the first falling edge detection circuit 13 detects the falling edge of the initial data signal, it also outputs a pulse signal. Similarly, the high-level duration of this pulse signal is also very short.

[0048] The first delay circuit 12 receives the signal output by the first rising edge detection circuit 11 and delays the signal output by the first rising edge detection circuit 11. Preferably, the delay time can be preset, for example, by setting the number of NOT gates to set the length of the delay time. Furthermore, the preset delay time is very short, which can be several nanoseconds or even less than one nanosecond. Since the period of the initial sampling clock signal is usually much greater than ten nanoseconds, that is, the preset delay time is much less than half a period of the initial sampling clock signal, the first delayed clock signal clk0 obtained by the first delay circuit 12 has a very short delay compared to the initial sampling clock signal and will not affect data transmission.

[0049] The second delay circuit 14 receives the signal output by the first falling edge detection circuit 13 and delays the signal output by the first falling edge detection circuit 13. Preferably, the delay time of the signal by the second delay circuit 14 is the same as the delay time of the signal by the first delay circuit 12, which is much smaller than half a cycle of the initial sampling clock signal. The first delayed clock signal clk0 output by the first delay circuit 12 and the second delayed clock signal clk1 output by the second delay circuit 14 are output to OR gate 15.

[0050] In addition to receiving the first delayed clock signal clk0 and the second delayed clock signal clk1, OR gate 15 also receives the initial sampling clock signal. It performs an OR operation on the first delayed clock signal clk0, the second delayed clock signal clk1, and the initial sampling clock signal to form a target sampling clock signal. This target sampling clock signal is output to the clock signal terminals of flip-flop 16 and shift register 17. Both flip-flop 16 and shift register 17 use the target sampling clock signal as their operating clock signal. In this embodiment, the initial sampling clock signal is also the reference sampling clock signal; that is, OR gate 15 performs an OR operation on the first delayed clock signal clk0, the second delayed clock signal clk1, and the reference sampling clock signal.

[0051] It should be noted that there can be multiple shift registers 17, which are cascaded sequentially, meaning the data output of the previous stage shift register is connected to the data input of the next stage shift register. Furthermore, the clock signal terminals of all multiple shift registers receive the target sampling clock signal, and all use the target sampling clock signal as their operating clock signal.

[0052] See Figure 3When trigger 16 samples the initial data signal, it samples the initial data signal once at each rising edge of the initial sampling clock signal, and also samples the initial data signal once at a predetermined time after each rising edge and falling edge of the initial data signal. That is, the initial data information is also sampled once at the rising edge of the pulse signal of the first delay clock signal clk0 and the second delay clock signal clk1.

[0053] However, if the level of the initial data signal changes within one cycle of the initial sampling clock signal (i.e., a rising or falling edge is generated), because sampling will occur once within that cycle due to the triggering of the pulse signals of the first and second delayed clock signals, the initial data signal will be sampled twice within one cycle of the initial sampling clock signal, resulting in two sampled values. In reality, the data transmitting device only transmits one bit of data, but if two samples are performed, two sampled values ​​will be generated, resulting in two bits of data, which will lead to a sampling error.

[0054] To avoid this problem, this embodiment employs a novel serial bus communication method, where the master device performs special processing on the initial sampling clock signal. Specifically, when the master device sends the initial data signal through the serial bus data signal line, if it detects a change in the level of the initial data signal—that is, the value of the current data sampling period of the initial data signal is different from the value of the previous data sampling period—the initial sampling clock signal is turned off during the current data sampling period. In this embodiment, since data sampling is performed on the rising edge of the initial sampling clock signal, one data sampling period is one period of the initial sampling clock signal, i.e., the duration of one high level and one low level. Turning off the initial sampling clock signal means stopping the transmission of clock signals to the serial bus clock signal line. During the period when the initial sampling clock signal is turned off, the clock signal line remains at a fixed level value, for example, a low level signal.

[0055] In this way, during the initial sampling clock cycle in which the level of the initial data signal changes, the serial bus clock signal remains at a low level, meaning that the initial sampling clock signal will not generate a rising edge during this data sampling cycle. Since either the first delayed clock signal clk0 or the second delayed clock signal clk1 generates a pulse signal during this data sampling cycle, trigger 16 is triggered and samples the initial data signal once. Therefore, during the initial sampling clock cycle in which the level of the initial data signal changes, the pulse signal generated by the first delayed clock signal clk0 or the second delayed clock signal clk1 replaces the rising edge of the initial sampling clock signal as the reference for data sampling. This ensures that the initial data signal is sampled only once during the initial sampling clock cycle in which the level of the initial data signal changes, instead of twice, thus ensuring the accuracy of the sampled data.

[0056] The sampling result of the initial data signal by trigger 16 is as follows: Figure 3 As shown, from Figure 3 As can be seen, this embodiment can accurately sample the initial data signal. Furthermore, since the first delayed clock signal clk0 and the second delayed clock signal clk1 are formed very shortly after the rising and falling edges of the initial data signal, respectively, and because the initial data signal maintains a stable level for a period after the rising and falling edges, it can be ensured that the initial data signal can be accurately sampled promptly after a level change, without worrying about setup or hold time violations caused by an immediate level change after sampling.

[0057] Furthermore, for example Figure 3 Reference numeral 41 indicates the setup time interval of the initial data signal relative to the initial clock signal, and reference numeral 42 indicates the hold time interval of the initial data signal relative to the initial clock signal; both are equal to one cycle of the initial clock signal. In contrast, the setup and hold time intervals of existing SPI buses are both half a cycle of the initial clock signal. Therefore, the serial bus in this embodiment has longer setup and hold time intervals. Based on this, the frequency of the initial sampling clock signal can be increased, thereby improving the data transmission rate.

[0058] In addition, to further improve data transmission efficiency, if the value sent by the master device in the current data sampling period is equal to the value sent in the previous two data sampling periods, that is, the value sent in three consecutive data sampling periods remains unchanged, then the clock frequency of the initial sampling clock signal is increased. Figure 3As shown, during clock cycles 45 and 46, since the data transmitted is the same as that of the previous two clock cycles, the frequency of clock cycles 45 and 46 is increased, meaning that the duration of clock cycles 45 and 46 is shorter than the duration of the next clock cycle.

[0059] Second embodiment:

[0060] This embodiment also references and improves upon the existing SPI bus communication method. Similar to the first embodiment, a serial bus is provided between the master and slave devices. The serial bus includes clock signal lines and data signal lines. The master device sends a clock signal to the clock signal lines, and the slave device maintains synchronous communication with the master device through this clock signal. Unlike the first embodiment, during data sampling, the slave device samples the data signal lines at both the rising and falling edges of each clock cycle.

[0061] See Figure 4 The serial bus data signal sampling circuit in this embodiment includes a flip-flop 26 and a shift register 27. Of course, there can be multiple shift registers, cascaded sequentially, meaning the data output of the previous stage shift register is connected to the data input of the next stage shift register. Preferably, both the flip-flop 26 and the shift register 27 can be implemented using D flip-flops. Furthermore, the data input of the flip-flop 26 acquires the initial data signal, and its data output is connected to the data input of the shift register 27.

[0062] This embodiment also includes a first rising edge detection circuit 21, a first delay circuit 22, a first falling edge detection circuit 23, and a second delay circuit 24. The first rising edge detection circuit 21 detects the rising edge of the initial data signal, and the first falling edge detection circuit 23 detects the falling edge of the initial data signal. When the first rising edge detection circuit 21 detects the rising edge of the initial data signal, it outputs a pulse signal. Preferably, the high-level duration of the pulse signal is very short, less than half a cycle of the initial sampling clock signal. When the first falling edge detection circuit 23 detects the falling edge of the initial data signal, it also outputs a pulse signal; similarly, the high-level duration of this pulse signal is also very short.

[0063] The first delay circuit 22 receives the signal output by the first rising edge detection circuit 21 and delays the signal output by the first rising edge detection circuit 21, for example, by several nanoseconds. The second delay circuit 24 receives the signal output by the first falling edge detection circuit 23 and delays the signal output by the first falling edge detection circuit 23. The first delayed clock signal clk0 output by the first delay circuit 22 and the second delayed clock signal clk1 output by the second delay circuit 24 are output to OR gate 25.

[0064] Unlike the first embodiment, this embodiment also includes a second rising edge detection circuit 28 and a second falling edge detection circuit 29. The second rising edge detection circuit 28 receives the initial sampling clock signal and outputs a pulse signal at the rising edge of the initial sampling clock signal to form a first detection signal clk2, i.e., outputting a high-level pulse. The high-level duration of this pulse is very short, for example, only a few nanoseconds, much shorter than half a cycle of the initial sampling clock signal. Similarly, the second falling edge detection circuit 29 receives the initial sampling clock signal and outputs a pulse signal at the falling edge of the initial sampling clock signal to form a second detection signal clk3, and the high-level duration of this pulse is also very short. Both the first detection signal clk2 and the second detection signal clk3 are output to an OR gate 25.

[0065] OR gate 25 performs a phase OR operation on the first delayed clock signal clk0, the second delayed clock signal clk1, the first detection signal clk2, and the second detection signal clk3 to form a target sampling clock signal. This target sampling clock signal is output to the clock signal terminal of flip-flop 26 and the clock signal terminal of shift register 27. Both flip-flop 26 and shift register 27 use the target sampling clock signal as their operating clock signal. Therefore, in this embodiment, the first detection signal clk2 and the second detection signal clk3 constitute the reference sampling clock signal.

[0066] See Figure 5 When trigger 26 samples the initial data signal, it samples the initial data signal once at each rising and falling edge of the initial sampling clock signal, and also samples the initial data signal once after a predetermined time following each rising and falling edge. That is, the initial data information is also sampled once at the rising edge of the pulse signals of the first delayed clock signal clk0 and the second delayed clock signal clk1. Therefore, compared with the first embodiment, this embodiment uses a double-edge sampling method, that is, sampling is performed on both the rising and falling edges of the initial sampling clock signal. Thus, the master device can send two bits of data within one clock cycle of each initial sampling clock signal, thereby improving data transmission efficiency.

[0067] Since this embodiment performs two data samples within one clock cycle of an initial sampling clock signal, the data sampling period of this embodiment is half a clock cycle of the initial sampling clock signal, that is, the duration of the high or low level.

[0068] To avoid sampling the initial data signal twice within a single data sampling period, the master device needs to perform special processing on the initial sampling clock signal. Specifically, when the master device sends the initial data signal through the serial bus data signal line, if it detects a change in the level of the initial data signal—that is, the value of the initial data signal in the current data sampling period is different from the value in the previous data sampling period—the initial sampling clock signal is turned off within the current data sampling period. Since this embodiment samples data on both the rising and falling edges of the clock signal, one data sampling period is actually half a clock cycle of the initial sampling clock signal.

[0069] During the period when the initial sampling clock signal is turned off, the level of the clock signal line remains constant, but the level value may be high or low. The level value of the clock signal line is the level of the clock signal line at the time of turn-off.

[0070] In this way, the serial bus clock signal will not change during a data sampling period in which the level of the initial data signal changes. That is, the initial sampling clock signal will not generate a rising edge or a falling edge during this data sampling period. This ensures that the initial data signal is sampled only once during a data sampling period in which the level of the initial data signal changes, instead of being sampled twice, thereby ensuring the accuracy of the sampled data.

[0071] The sampling result of the initial data signal by trigger 26 is as follows: Figure 5 As shown, this embodiment can accurately sample the initial data signal. Compared to the first embodiment, this embodiment has a higher data sampling rate.

[0072] Similar to the first embodiment, the serial bus in this embodiment has a longer setup and hold time interval than the existing SPI bus. Based on this, the frequency of the initial sampling clock signal can be increased, thereby improving the data transmission rate.

[0073] Of course, this embodiment can also increase the clock frequency of the initial sampling clock signal when the value sent in the current data sampling period is equal to the values ​​sent in the previous two data sampling periods. This is the same as the processing method in the first embodiment, and will not be described again.

[0074] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. Communication methods for serial buses, including: The master device sends the initial data signal and the initial sampling clock signal; Its features are: When the master device sends the initial data signal, a first rising edge detection circuit is used to detect the rising edge signal of the initial data signal and a first delay circuit is used to delay it before outputting a first delayed clock signal. A first falling edge detection circuit is used to detect the falling edge signal of the initial data signal and a second delay circuit is used to delay it before outputting a second delayed clock signal. When a change in the level of the initial data signal is detected, the initial sampling clock signal is turned off during the current data sampling period. During the period when the initial sampling clock signal is turned off, the clock signal line remains at a fixed level value. The rising edge of the initial sampling clock signal is replaced by a pulse signal generated by the first delayed clock signal or the second delayed clock signal as the reference for data sampling, so as to ensure that the initial data signal is sampled only once within one initial sampling clock period when the level of the initial data signal changes.

2. The serial bus communication method according to claim 1, characterized in that: If the value sent in the current data sampling period is equal to the value sent in the previous two data sampling periods, the clock frequency of the initial sampling clock signal is increased.

3. A serial bus data signal sampling circuit, including: A trigger, wherein the data input terminal of the trigger receives an initial data signal; The sampling circuit is characterized by further comprising: A first rising edge detection circuit is used to detect the rising edge signal of the initial data signal; A first falling edge detection circuit is used to detect the falling edge signal of the initial data signal; The first delay circuit receives the signal output by the first rising edge detection circuit, and outputs the first delayed clock signal after a preset delay time after receiving the signal output by the first rising edge detection circuit. The second delay circuit receives the signal output by the first falling edge detection circuit, and outputs the second delayed clock signal after a preset delay time after receiving the signal output by the first falling edge detection circuit. The second rising edge detection circuit is used to receive the rising edge signal of the initial sampling clock signal and output the first detection signal when the rising edge signal of the initial sampling clock signal is received. The second falling edge detection circuit is used to receive the falling edge signal of the initial sampling clock signal and output a second detection signal when the falling edge signal of the initial sampling clock signal is received. The OR gate receives the first delayed clock signal, the second delayed clock signal, the first detection signal, and the second detection signal, and outputs the target sampling clock signal to the clock signal terminal of the flip-flop after ORing the first delayed clock signal, the second delayed clock signal, the first detection signal, and the second detection signal. The preset delay time is less than half a clock cycle of the initial sampling clock signal.

4. The serial bus data signal sampling circuit according to claim 3, characterized in that: The output of the flip-flop is connected to a shift register, which receives the target sampling clock signal.

5. A method for sampling a data signal of a serial bus, applied to the data signal sampling circuit of claim 3, characterized in that, The method includes: The first rising edge detection circuit detects the rising edge signal of the initial data signal and outputs it to the first delay circuit. The first delay circuit receives the signal output by the first rising edge detection circuit and outputs the first delayed clock signal after a preset delay time after receiving the signal output by the first rising edge detection circuit. The first falling edge detection circuit detects the falling edge signal of the initial data signal and outputs it to the second delay circuit. The second delay circuit receives the signal output by the first falling edge detection circuit and outputs the second delayed clock signal after a preset delay time after receiving the signal output by the first falling edge detection circuit. The second rising edge detection circuit receives the rising edge signal of the initial sampling clock signal and outputs the first detection signal when the rising edge signal of the initial sampling clock signal is received. The second falling edge detection circuit receives the falling edge signal of the initial sampling clock signal and outputs the second detection signal when the falling edge signal of the initial sampling clock signal is received; The first delayed clock signal, the second delayed clock signal, and the first detection signal and the second detection signal are ORed together to output the target sampling clock signal to the trigger; Wherein, the preset delay time is less than half a clock cycle of the initial sampling clock signal; The trigger receives the initial data signal and samples the initial data signal using the target sampling clock signal.

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