A method of hybrid programming and related products

Abstract

The present disclosure provides a hybrid programming method and related products, which can be implemented as a compilation device that can be included in a combined processing device that can also include a general-purpose interconnect interface and other processing devices. The computing processing device interacts with the other processing devices to collectively complete a user-specified computing operation. The combined processing device can also include a storage device connected to the computing processing device and the other processing devices, respectively, for storing data of the computing processing device and the other processing devices.

Description

Technical Field

[0001] This disclosure relates to the field of computers, and more specifically, to the field of hybrid programming of computers. Background Technology

[0002] With the popularization of artificial intelligence algorithms and applications, an increasing number of types of neural networks and hardware devices have emerged. Exemplary neural networks include ResNet, GoogleNet, ReNeXt, SENet, etc., while exemplary hardware devices (such as processors) include GPUs, TPUs, etc. In this context, neural network operators must be matched with specific hardware architectures and diverse neural networks, which places special demands on operator writing.

[0003] Operators can be written using appropriate languages. For example, users can use Python primitives to adapt to specific hardware. This approach requires adherence to software conventions, involves a large workload, and is highly complex. Alternatively, operators can be automatically generated. This method produces simpler operators but is only suitable for simple operators and cannot be applied to complex operators and application scenarios. Another approach is to use the Python interface and extended languages ​​such as C++ and CUDA C to write corresponding operators. This method is relatively flexible but also highly complex. These methods work independently of each other.

[0004] Furthermore, operators generated by traditional methods are independent of each other, cannot be selected as needed, and cannot combine the advantages of multiple methods in the writing of complex operators. Summary of the Invention

[0005] One objective of this disclosure is to overcome the shortcomings of existing technologies that cannot be programmed according to specific operator requirements.

[0006] According to one aspect of this disclosure, a method for hybrid programming of neural network operators is provided, comprising: generating a hybrid programming source program to meet the needs of different neural network operators, wherein the hybrid programming source program includes multiple programs created using different programming interfaces; and compiling the hybrid programming source program to generate target code for the neural network operators.

[0007] According to a second aspect of this disclosure, an electronic device is provided, comprising: one or more processors; and a memory storing computer-executable instructions that, when executed by the one or more processors, cause the electronic device to perform the method described above.

[0008] According to a third aspect of this disclosure, a computer-readable storage medium is provided, including computer-executable instructions that, when executed by one or more processors, perform the method described above.

[0009] The technical solution disclosed herein can integrate the advantages of multiple methods in operator writing, thereby improving operator development efficiency. Furthermore, this disclosure provides multiple operator formats to facilitate user use and verification. Attached Figure Description

[0010] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0011] Figure 1 A flowchart of a method for hybrid programming of neural network operators according to one embodiment of the present disclosure is shown;

[0012] Figure 2 A flowchart is shown illustrating the compilation of the hybrid programming source program to generate target code for a neural network operator according to one embodiment of the present disclosure;

[0013] Figure 3 A schematic diagram is shown illustrating the compilation of the hybrid programming source program to generate target code for a neural network operator according to one embodiment of the present disclosure;

[0014] Figure 4 A flowchart illustrating the determination of a tensor computation primitive Python interface and a TensorOP Python interface as non-AI high-level language embedded interfaces according to one embodiment of this disclosure is shown.

[0015] Figure 5 This diagram illustrates how the source program is compiled based on different interface types.

[0016] Figure 6 A combined processing apparatus is shown; and

[0017] Figure 7 An exemplary board is shown. Detailed Implementation

[0018] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0019] It should be understood that the terms "first," "second," "third," and "fourth," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0020] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0021] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0022] To more clearly describe the technical solution of this disclosure, the characteristics of the various programming interfaces involved in this disclosure are first introduced.

[0023] This disclosure includes a programming framework based on the Python language and a programming framework based on a high-level artificial intelligence language. The high-level artificial intelligence language is an extension of the C language and can be based on a specific instruction set architecture (ISA), such as CUDAC. The two different programming frameworks can be nested together; for example, a program obtained from the high-level artificial intelligence language-based programming framework can be embedded within a Python programming framework.

[0024] The Python-based programming framework can include different levels of programming interfaces, including but not limited to operator interfaces for computation. For big data such as neural networks, these programming interfaces can perform operations and processing on tensors. For example, in this disclosure, the Python-based programming framework can include tensor operator interfaces, tensor computation primitive interfaces, and embedded interfaces from other languages ​​(including but not limited to embedded interfaces from high-level artificial intelligence languages).

[0025] TensorOp (Tensor Operator Interface): This interface provides an expression for tensor computations and operations. Using the corresponding Python interface for TensorOp, operators can be concatenated without needing to concern oneself with hardware details. Ideally, the TensorOp interface should be able to write operators, such as various activation functions, so users only need to write the computations described by the interface. The advantage is the simplicity of the computations described by the user, without needing to worry about the hardware. The disadvantage is that the provided interface requires specific support in the compilation framework, and its breadth is limited.

[0026] The Tensor Compute Primitive (TCP) Python interface uses Python computation primitives to write operators. Compared to TensorOp, which describes computation at a high level, TCP requires an understanding of the hardware architecture and needs to specify how tensors are moved at the storage level, how they are processed in chunks on the chip, and the parallel processing methods used. This interface offers greater operability and a wider range of capabilities, handling operator requirements that TensorOp cannot support.

[0027] High-level AI language embedded interfaces: These are used to write neural network operators using C-like high-level languages ​​(such as CUDAC) with embedded Python interfaces. This is a lower-level approach that provides more complete programming instructions, allowing for manual writing and tuning of operators. This method can be used to support operator development when the functionality or performance of TensorOp and TCP is insufficient.

[0028] Figure 1 A flowchart of a method for hybrid programming of neural network operators according to one embodiment of the present disclosure is shown. The method includes: in operation S110, obtaining a hybrid programming source program to meet the needs of different neural network operators, wherein the hybrid programming source program includes multiple programs created using different programming interfaces; and in operation S120, compiling the hybrid programming source program to generate target code for the neural network operators.

[0029] According to one embodiment of this disclosure, in the operator development process, one of a variety of programming interfaces can be selected for individual programming, or a variety of programming interfaces can be mixed for hybrid programming, and a unified compilation optimization module can be used to generate operators in various formats to improve the efficiency of operator development.

[0030] Hybrid programming can be used based on the requirements of operators. For example, for simple operators, operators can be generated automatically, such as by using encapsulated Python operator interfaces, like the tensor operator interface mentioned above. Users can also use Python primitives to adapt to specific hardware and follow corresponding software conventions, such as by using the tensor computation primitive interface mentioned above to generate operators. Users can also flexibly use C++, CUDA, etc. for extensions, such as by using the high-level artificial intelligence programming language interface mentioned above to generate operators.

[0031] In this embodiment, the Python programming language framework can obtain hybrid programming source programs formed using different programming interfaces through a unified Python interface. The hybrid programming source programs are then parsed and compiled to obtain the target code corresponding to the respective neural network operators. This target code includes, but is not limited to, C-like source files, binary library files, and runnable module files. In this embodiment, the compiled hybrid programming source programs can generate target files for neural network operators in different formats, thereby meeting the needs of different scenarios and improving the efficiency of operator development.

[0032] Figure 2 A flowchart illustrating the compilation of the hybrid programming source program to generate a neural network operator according to one embodiment of the present disclosure is shown. Figure 3 A schematic diagram is shown illustrating the compilation of the hybrid programming source program to generate a neural network operator according to one embodiment of the present disclosure. Figure 2 As shown, compiling the hybrid programming source program to generate a neural network operator may include: in operation S210, parsing the hybrid programming source program to determine the type of application programming interface; in operation S220, generating a low-level intermediate representation based on the determined type of application programming interface; and in operation S230, generating the target code of the neural network operator based on the low-level intermediate representation.

[0033] like Figure 3As shown, once a hybrid programming source program is formed, it can be parsed using a Python interface parsing unit to analyze the interface type used in the programming. Once the specific interface type (e.g., a Python interface or an embedded interface in a high-level AI language) is determined, the source program can be converted into a low-level intermediate representation (IR) based on the determined interface type, and then specific operators can be generated based on the corresponding IR.

[0034] According to one embodiment of this disclosure, a hybrid programming source program can be formed using at least two of the TCP Python interface, the TensorOP Python interface, and the AI ​​high-level language embedded interface.

[0035] For example, in hybrid programming, interfaces can be defined using TCP Python.

[0036] @tensor_op.decorate_tcp_OP

[0037] Def exp()

[0038] @tensor_op.decorate_tcp_OP

[0039] Def relu()

[0040] The `exp` function can be defined using the command `def exp()`, while the `relu` function can be defined using `def relu()`.

[0041] For example, in hybrid programming, the `add_vec` function can be defined using embedded interfaces in high-level AI languages ​​(such as BANG C). For instance, it can be defined as:

[0042]

[0043] Specifically, the instructions for BANG C can be written using bang_code="...".

[0044] For example, in mixed programming, computation can be described using TCP, TensorOp, and BANG C together. Below is an example of a computation description, where the comments indicate the components of the operators: exp and relu come from the TCP interface shown above, add_vec comes from the interface defined in BANG C shown above, and the rest are TensorOp interfaces.

[0045]

[0046]

[0047] According to one embodiment of this disclosure, parsing the hybrid programming source program to determine the type of application programming interface may include: determining an AI high-level language embedded interface and determining the TCP Python interface and TensorOP Python interface as non-AI high-level language embedded interfaces.

[0048] In this disclosed scheme, the compilation process for the TCP Python interface and TensorOP differs from that for the compilation process of the AI ​​high-level language embedded interface. Therefore, during compilation, it is necessary to first identify the AI ​​high-level language embedded interface and the Python interface in the mixed programming, such as the TCP Python interface and the TensorOP Python interface. Optionally, the distinction of the AI ​​high-level language embedded interface can be direct; for example, it can be directly identified by obtaining the definition of the program in the Python programming framework based on the AI ​​high-level language. This definition includes, but is not limited to, the declaration of the corresponding operator, such as the program statement "def add_vec()" above.

[0049] According to one embodiment of this disclosure, determining the TCPPython interface and the TensorOP Python interface as embedded interfaces of a non-artificial intelligence high-level language may include: determining the TCPPython interface and the TensorOP Python interface by explicitly specifying the TCPPython interface and the TensorOP Python interface when creating a hybrid programming source program.

[0050] For example, the TCP interface can be explicitly specified by describing tensor_op.decorate_tcp_op, and the operations on tensor data can be specified in detail, such as exp(tensor_in), tcp_bp = tcp.TCP(), etc.

[0051] For example, the Tensor OP interface can be explicitly specified by describing instructions such as tensor_in = tensor_op.tensor(shape, dtype = dtype, name = "input"), and various tensor operations can be described, such as out1 = tensor_op.log(out), etc.

[0052] In this embodiment of the disclosure, the user can explicitly specify the type of the Python interface during programming, and the programming framework can determine the type of the Python interface in the hybrid programming source program based on this explicit specification. For example, the programming Python interface parsing unit in the programming framework can identify whether the Python interface type in the hybrid programming source program is TCP or Tensor OP based on the interface type specification in the hybrid programming source program. For example, the function of Python decorators is to help users explicitly specify, and decorators are, for example, the Python statements added before the def statements when describing Python, as mentioned above. The @tensor_op.decorate_tcp_op statement explicitly specifies TCP. The tensor_op.decorate_bang_op statement explicitly specifies BANG C. The purpose of this is to allow a certain interface to be used in hybrid programming. Combined with the specific use cases of TCP, TensorOp, and BANG C mixed together, it is possible to explicitly specify whether certain interfaces come from TCP, TensorOp, or BANG C.

[0053] Figure 4 A flowchart illustrating the determination of the TCP Python interface and the TensorOP Python interface as embedded interfaces for non-AI high-level languages ​​according to one embodiment of this disclosure is shown. In embodiments of this disclosure, the compilation framework automatically recognizes and uses the TCP Python interface and the TensorOP Python interface without requiring explicit user specification.

[0054] like Figure 4 As shown, determining the TCP Python interface and TensorOP Python interface as embedded interfaces of non-AI high-level languages ​​may include: in operation S410, searching for the TensorOP Python interface; if no TensorOP Python interface is found, proceeding to operation S420, searching for the TCP Python interface; if a TCP Python interface is found, proceeding to operation S430, determining whether the found TCP Python interface conforms to hardware constraints; if the found TCP Python interface does not conform to hardware constraints, proceeding to operation S440, issuing a notification message requiring the rewriting of the TCP Python interface; further, in operation S450, if no TCP Python interface is found, a notification requiring the program to be written using the embedded interface of an AI high-level language can be issued. Optionally, if no TCP Python interface is found, a request can also be issued to write the program using the TCP Python interface.

[0055] For example, automatic identification of the TCP Python interface can be achieved through the following operations:

[0056]

[0057]

[0058] The above describes the process of automatically selecting and using interfaces within the compilation framework. For ease of understanding, Chinese explanations are used instead of source code.

[0059] As shown above, the first step is to locate the TensorOP interface. This TensorOP interface does not require knowledge of hardware details; various operators can be written using the TensorOp interface. Users only need to write the computations described by the interface.

[0060] If a TensorOP interface is found, it can be used normally. If no TensorOP interface is found, the search continues for a TCP interface. If a TCP interface is found, it is necessary to determine whether the TCP interface conforms to the hardware constraints. If a TCP interface that conforms to the hardware constraints is found, it is used. If the found TCP interface does not conform to the hardware constraints, a prompt message can be given, requiring the user to write the TCP interface.

[0061] Furthermore, if neither the TensorOP interface nor the TCP interface is found, or even if the TCP interface is found but does not conform to the hardware specifications, a further prompt message can be given, requiring the user to write an embedded interface in a high-level artificial intelligence language.

[0062] Figure 5 This diagram illustrates how the source code is compiled based on different interface types.

[0063] The Python interface parsing unit obtains the mixed-programming source code, then parses it to analyze the interface types used in the programming. Once the specific interface types are determined, compilation can proceed according to the corresponding interface types. For example... Figure 5As shown, according to one embodiment of this disclosure, if the type of the application programming interface is an embedded interface of an artificial intelligence high-level language, then generating a low-level intermediate representation based on the determined type of the application programming interface includes: forming a syntax tree based on the embedded interface of the artificial intelligence high-level language; and generating a low-level intermediate representation based on the syntax tree. In this disclosure, the operators of the embedded interface of the artificial intelligence high-level language are transformed into extern_ops on the low-level intermediate representation during the parsing descent process. This extern_op is ultimately compiled using a compiler, which is used to translate programs written in the artificial intelligence high-level language.

[0064] According to one embodiment of this disclosure, if the type of the application programming interface is a TCP Python interface or a TensorOP Python interface, then generating a low-level intermediate representation based on the determined type of the application programming interface includes: generating a high-level intermediate representation based on a program created through the TCP Python interface or the TensorOP Python interface; and generating a low-level intermediate representation based on the high-level intermediate representation.

[0065] High-level intermediate representations can be, for example, graph intermediate representations (GIRs). These can be computational graph intermediate representations obtained after parsing by a deep learning framework, or computational graph intermediate representations such as NNVM or Relay from a neural network compilation framework. These are merely illustrative examples and are not intended to limit the scope of this application. Low-level intermediate representations can be, for example, tensor intermediate representations (TIRs). TIRs are designed to meet the needs of machine learning and can represent scalar, vector, matrix, and tensor operations. Therefore, in addition to conventional scalar operations (such as arithmetic operations, logical operations, comparison operations, memory operations, function calls, and conditional operations), TIRs can also provide descriptions of vectors, matrices, and tensors.

[0066] According to one embodiment of this disclosure, an operator (OP) connector is inserted between the high-level intermediate representation and the low-level intermediate representation to connect different operator interfaces at compile time. The operator connector is equivalent to an identifier for the tensor address at the IR level. At the Python level, the high-level and low-level interfaces are connected via tensors; at the IR level, these special tensors (such as the tensors used in TCP) are marked as OP connectors; and during the code generation phase, they generate storage blocks on global memory, and the corresponding addresses are used as tensor handles, which are shared by the code generated by different levels of IR.

[0067] This disclosure also provides an electronic device, including: one or more processors; and a memory storing computer-executable instructions that, when executed by the one or more processors, cause the electronic device to perform the method described above.

[0068] This disclosure also provides a computer-readable storage medium including computer-executable instructions that, when executed by one or more processors, perform the method described above.

[0069] The technical solution disclosed herein can provide a unified Python interface to facilitate the generation of operators through compilation optimization; through hybrid programming, the advantages of multiple methods can be integrated in operator writing, improving operator development efficiency; in addition, it facilitates user use and verification for multiple operator formats.

[0070] The methods and devices described above can also be implemented as a compilation device, which can constitute a combined processing device.

[0071] Figure 6 A combined processing apparatus 600 is shown, comprising the aforementioned compiler 602, general interconnect interface 604, and other processing apparatus 606. The compiler according to this disclosure interacts with the other processing apparatus to jointly perform user-specified operations. Figure 6 This is a schematic diagram of the combined processing device.

[0072] This compiler can be implemented in various ways, such as software or hardware, and it can run on any one or more general-purpose / special-purpose processors, such as CPU, graphics processing unit (GPU), and neural network processor.

[0073] Other processing devices include one or more processor types such as central processing unit (CPU), graphics processing unit (GPU), and neural network processor. There is no limit to the number of processors included in other processing devices. These other processing devices serve as interfaces between the machine learning computing device and external data and control, including data transfer and basic control such as starting and stopping the machine learning computing device. Other processing devices can also collaborate with the machine learning computing device to complete computational tasks.

[0074] A general interconnect interface is used to transfer data and control instructions between a compiler (including, for example, a machine learning computing unit) and other processing units. The compiler obtains the required input data from other processing units and writes it to on-chip storage; it can obtain control instructions from other processing units and write them to on-chip control buffers; it can also read data from the compiler's storage modules and transmit it to other processing units.

[0075] Optionally, the structure may further include a storage device 608, which is connected to both the compiler and the other processing devices. The storage device is used to store data in the compiler and the other processing devices, and is particularly suitable for data that cannot be fully stored in the internal storage of the compiler or other processing devices, requiring computation.

[0076] This combined processing device can serve as a System-on-a-Chip (SoC) for devices such as mobile phones, robots, drones, and video surveillance equipment, effectively reducing the core area of ​​the control unit, increasing processing speed, and lowering overall power consumption. In this case, the universal interconnect interface of the combined processing device connects to certain components of the device, such as cameras, monitors, mice, keyboards, network cards, and Wi-Fi interfaces.

[0077] In some embodiments, this disclosure also discloses a chip that includes the above-described compilation or combination processing apparatus.

[0078] In some embodiments, this disclosure also discloses a circuit board that includes the aforementioned chip. See also Figure 7 The present invention provides an exemplary board, which, in addition to the chip 702, may also include other supporting components, including but not limited to: a storage device 704, an interface device 706, and a controller 708.

[0079] The storage device is connected to the chip within the chip package structure via a bus for storing data. The storage device may include multiple sets of storage cells 710. Each set of storage cells is connected to the chip via a bus. It is understood that each set of storage cells may be DDR SDRAM (Double Data Rate SDRAM).

[0080] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include four groups of storage cells. Each group of storage cells may include multiple DDR4 chips. In one embodiment, the chip may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification. In one embodiment, each group of storage cells includes multiple Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) units connected in parallel. DDR can transmit data twice per clock cycle. A controller for controlling DDR is provided in the chip for controlling data transmission and data storage in each storage cell.

[0081] The interface device is electrically connected to the chip within the chip package structure. The interface device is used to enable data transmission between the chip and an external device 712 (e.g., a server or computer). For example, in one embodiment, the interface device can be a standard PCIe interface. For instance, data to be processed is transferred from the server to the chip via a standard PCIe interface, realizing data transfer. In another embodiment, the interface device can also be other interfaces; this disclosure does not limit the specific form of these other interfaces, as long as the interface unit can perform the switching function. Furthermore, the calculation results of the chip are still transmitted back to the external device (e.g., the server) by the interface device.

[0082] The controller is electrically connected to the chip. The controller monitors the state of the chip. Specifically, the chip and the controller can be electrically connected via an SPI interface. The controller may include a microcontroller (MCU). The chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, capable of driving multiple loads. Therefore, the chip can operate in different states, such as high load and low load. The controller can regulate the operating states of multiple processing chips, multiple processing cores, and / or multiple processing circuits within the chip.

[0083] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this disclosure. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0084] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0085] In the embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, optical, acoustic, magnetic, or other forms.

[0086] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0087] Furthermore, the functional units in the various embodiments disclosed herein can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software program module.

[0088] If the integrated unit is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, when the technical solution disclosed herein can be embodied in the form of a software product, the computer software product is stored in a storage device and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage device includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0089] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A method of hybrid programming, comprising: acquiring a hybrid programming source program to meet a demand for different neural network operators, wherein the hybrid programming source program includes a plurality of programs created using different programming interfaces; parsing the hybrid programming source program to determine a type of application programming interface, wherein the plurality of application programming interfaces includes a Python interface and an artificial intelligence high-level language embedded interface; the plurality of application programming interfaces includes at least two of a tensor computation primitive Python interface, a tensor operator Python interface, and the artificial intelligence high-level language embedded interface, and parsing the hybrid programming source program to determine the type of application programming interface includes determining the artificial intelligence high-level language embedded interface and determining the tensor computation primitive Python interface and the tensor operator Python interface as non-artificial intelligence high-level language embedded interfaces, wherein the artificial intelligence high-level language embedded interface is used to write a neural network operator using a class C high-level language embedded Python interface; generating a low-level intermediate representation according to the determined type of application programming interface; generating target code of a neural network operator according to the low-level intermediate representation.

2. The method of claim 1, wherein, determining the tensor computation primitive Python interface and the tensor operator Python interface as non-artificial intelligence high-level language embedded interfaces includes: determining the tensor computation primitive Python interface and the tensor operator Python interface by explicitly specifying the tensor computation primitive Python interface and the tensor operator Python interface when creating the hybrid programming source program.

3. The method of claim 1, wherein, determining the tensor computation primitive Python interface and the tensor operator Python interface as non-artificial intelligence high-level language embedded interfaces includes: searching for a tensor operator Python interface; if the tensor operator Python interface is not searched for, searching for a tensor computation primitive Python interface; if the tensor computation primitive Python interface is searched for, determining whether the searched tensor computation primitive Python interface complies with hardware constraints; if the searched tensor computation primitive Python interface does not comply with the hardware constraints, giving a notification message requiring the tensor computation primitive Python interface to be rewritten; if the tensor computation primitive Python interface is not searched for, giving a message to write using the artificial intelligence high-level language embedded interface.

4. The method of any of claims 1-3, wherein, if the type of application programming interface is the artificial intelligence high-level language embedded interface, then generating the low-level intermediate representation according to the determined type of application programming interface includes: forming a syntax tree according to the artificial intelligence high-level language embedded interface; generating the low-level intermediate representation according to the syntax tree.

5. The method of any one of claims 1-3, wherein, if the type of application programming interface is the tensor computation primitive Python interface or the tensor operator Python interface, then generating the low-level intermediate representation according to the determined type of application programming interface includes: generating a high-level intermediate representation from a program created through a Python interface of a tensor computation primitive or a Python interface of a tensor operator; and generating a low-level intermediate representation from the high-level intermediate representation.

6. The method of claim 5, wherein, An OP connector is inserted between the high-level intermediate representation and the low-level intermediate representation for connecting different interfaces at compile time.

7. An electronic device, comprising: one or more processors; and a memory having computer-executable instructions stored therein that, when executed by the one or more processors, cause the electronic device to perform the method of any of claims 1-6.

8. A computer-readable storage medium comprising computer-executable instructions that, when executed by one or more processors, perform the method of any of claims 1-6.

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