Current signal sampling method, sampling circuit and switching power supply

Abstract

The embodiment of the application discloses a current signal sampling method, a sampling circuit and a switching power supply. In the embodiment, a control unit of the sampling circuit charges a charging capacitor within a turn-off delay time corresponding to a switching tube to obtain a compensation signal, so that the first sampling signal is compensated according to the compensation signal. Thus, the embodiment accurately obtains the compensation signal by charging the charging capacitor within the turn-off delay time by the current in the integrated circuit, reduces the circuit cost, facilitates the circuit integration, and reduces the circuit volume.

Description

Technical Field

[0001] This invention relates to the field of electronic power technology, and more specifically, to a signal sampling method, a sampling circuit, and a switching power supply. Background Technology

[0002] In switching power supplies, it is necessary to sample the peak value of the current signal, such as... Figure 1 As shown, when the control signal DRV of the switching transistor decreases at time t0, the sampled signal Vcs will have undershoot noise. At this time, the switching transistor does not immediately turn off, so the current signal Ippk continues to rise for a period of time until the switching transistor is completely turned off. Therefore, the peak current of the sampled current signal will be smaller than the actual peak current, resulting in a certain sampling error. Figure 1 As shown, the actual peak current signal Iac is higher than the sampled peak current Ippk. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a current signal sampling method, a sampling circuit, and a switching power supply to accurately acquire current sampling signals.

[0004] In a first aspect, embodiments of the present invention provide a current signal sampling method applied to a switching power supply, characterized in that the method includes:

[0005] Acquire the first sampled signal of the current flowing through the inductor;

[0006] In the switching power supply, a compensation signal with the same rising slope as the first sampling signal is obtained during the turn-off delay time of the power transistor, and the compensation signal is superimposed on the first sampling signal to generate a second sampling signal.

[0007] Preferably, the compensation signal begins to increase linearly when a control signal controlling the power transistor to turn off is detected, and stops increasing linearly when a zero-crossing point is detected where the current flowing through the inductor changes from positive to negative.

[0008] Preferably, during the turn-off delay time, a charging capacitor is charged using a charging current generated by a current source to generate the compensation signal on the charging capacitor.

[0009] Preferably, the charging current is determined based on the bus voltage of the switching power supply.

[0010] Preferably, the charging current is generated by acquiring the electrical signal of the auxiliary winding coupled to the primary winding, and the charging of the charging capacitor stops when the electrical signal at both ends of the auxiliary winding changes from negative to positive and crosses zero.

[0011] Preferably, it further includes: a voltage divider circuit coupled in parallel across the auxiliary winding, wherein the voltage divider circuit includes an upper resistor and a lower resistor connected in series; and

[0012] The charging current generated by the current source is inversely proportional to the resistance of the upper resistor and directly proportional to the bus voltage of the switching power supply and the turns ratio of the auxiliary winding to the primary winding.

[0013] Preferably, the resistance value of the upper resistor is configured to control the charging current to charge the charging capacitor, so that the rising slope of the compensation signal is the same as the rising slope of the first sampling signal.

[0014] Preferably, at the end of the turn-off delay time, the peak value of the second sampling signal is acquired to generate a peak current sampling signal.

[0015] Preferably, the first sampling signal is stored in the charging capacitor during the power transistor's on-time, and the voltage across the charging capacitor is used as the second sampling signal at the end of the off-time delay.

[0016] Preferably, during the power transistor's conduction period, the first sampling signal is stored in the first capacitor and the charging capacitor. During the turn-off delay time, the charging capacitor is charged using the charging current to superimpose the compensation signal onto the first sampling signal, thereby generating the second sampling signal across the charging capacitor.

[0017] In a second aspect, a current signal sampling circuit is provided for use in a switching power supply, characterized in that the current signal sampling circuit includes: a first sampling circuit configured to acquire a first sampling signal of the current flowing through an inductor; and

[0018] The second sampling circuit is configured to acquire a compensation signal with the same rising slope as the first sampling signal during the turn-off delay time of the power transistor in the switching power supply, and to superimpose the compensation signal on the first sampling signal to generate the second sampling signal.

[0019] Preferably, the compensation signal begins to increase linearly when a control signal controlling the power transistor to turn off is detected, and stops increasing linearly when a zero-crossing point is detected where the current flowing through the inductor changes from positive to negative.

[0020] Preferably, the second sampling circuit includes:

[0021] A current source is configured to generate a charging current; and

[0022] Charging capacitor,

[0023] The charging current charges the charging capacitor during the turn-off delay time to generate the compensation signal on the charging capacitor.

[0024] Preferably, the charging current is determined based on the bus voltage of the switching power supply.

[0025] Preferably, the charging current is generated by acquiring the electrical signal of the auxiliary winding coupled to the primary winding, and the charging of the charging capacitor stops when the electrical signal at both ends of the auxiliary winding changes from negative to positive and crosses zero.

[0026] Preferably, a voltage divider circuit is connected in parallel across the two ends of the auxiliary winding, wherein the voltage divider circuit includes an upper resistor and a lower resistor connected in series;

[0027] The charging current generated by the current source is inversely proportional to the resistance of the upper resistor and directly proportional to the bus voltage of the switching power supply and the turns ratio of the auxiliary winding to the primary winding.

[0028] Preferably, the resistance value of the upper resistor is configured to control the charging current to charge the capacitor, such that the rising slope of the compensation signal is the same as the rising slope of the first sampling signal.

[0029] Preferably, at the end of the turn-off delay time, the peak value of the second sampling signal is acquired to generate a peak current sampling signal.

[0030] Preferably, the first sampling signal is stored in the charging capacitor during the power transistor's on-time, and the voltage across the charging capacitor is used as the second sampling signal at the end of the off-time delay.

[0031] Preferably, the second sampling circuit includes:

[0032] First capacitor.

[0033] During the power transistor's conduction period, the first sampling signal is stored in the first capacitor and the charging capacitor. At the end of the turn-off delay time, the voltage across the charging capacitor is used as the second sampling signal.

[0034] Preferably, the second sampling circuit further includes:

[0035] A first amplifier, with its first input terminal and second input terminal respectively coupled to the first capacitor and the charging capacitor, and its output terminal coupled to the charging capacitor, is configured to control the amplification of the first sampled signal by a predetermined factor.

[0036] Preferably, the second sampling circuit further includes:

[0037] A first resistor is coupled to the output and second input terminals of the first amplifier; and

[0038] The second resistor is connected in series between the first resistor and the ground terminal;

[0039] The resistance ratio of the first resistor and the second resistor is a first predetermined value.

[0040] Thirdly, a switching power supply is provided, characterized in that the switching power supply comprises:

[0041] A transformer includes a primary winding, a secondary winding, and an auxiliary winding;

[0042] A switching transistor is configured to switch states under control of a switching control signal to maintain the output stability of the switching power supply; and

[0043] The aforementioned current signal sampling circuit.

[0044] This invention discloses a sampling circuit, an integrated circuit, and a switching power supply. In this embodiment, the control unit of the sampling circuit charges a charging capacitor during the turn-off delay time of the corresponding switching transistor. The compensation signal is determined based on the voltage of the charged capacitor after charging is complete, and then the sampling signal is compensated based on the compensation signal. Therefore, this embodiment accurately obtains the compensation signal by charging the charging capacitor with the current inside the integrated circuit during the turn-off delay time, reducing circuit cost, facilitating circuit integration, and decreasing circuit size. Attached Figure Description

[0045] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0046] Figure 1 This is a waveform diagram of the electrical signal sampling process in the prior art;

[0047] Figure 2 This is a schematic diagram of a switching power supply based on related technologies;

[0048] Figure 3 This is a schematic diagram of a switching power supply according to an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of a current signal sampling circuit according to an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the working waveform of the current signal sampling circuit according to an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of another current signal sampling circuit according to an embodiment of the present invention;

[0052] Figure 7 This is a parameter diagram of an embodiment of the present invention. Detailed Implementation

[0053] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0054] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0055] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0056] Unless the context explicitly requires it, words such as "including" or "contains" in the instruction manual should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0057] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0058] Figure 2 This is a schematic diagram of a switching power supply based on related technologies. Taking a switching power supply as an example... Figure 2 As shown, in the prior art, a switching power supply includes a rectifier circuit BD, a transformer T, a switching transistor M, and a sampling resistor R. CS The external resistor R4, drive resistor R3, integrated circuit 21, and voltage divider circuit 22 are determined. The voltage divider circuit 22 includes resistors R1 and R2, and the transformer T includes a primary winding P, a secondary winding S, and an auxiliary winding A. The input AC voltage Vac is rectified by the rectifier circuit BD to output the bus voltage Vbus.

[0059] like Figure 2As shown, the voltage signal VNa of the auxiliary winding A is divided by the voltage divider circuit 22 and transmitted to the ZCS terminal of the integrated circuit 21. The ZCS terminal can be used for current and current zero-crossing detection. The integrated circuit 21 generates a control signal DRV for the switching transistor M based on the voltage signal VNa of the auxiliary winding A, thereby controlling the on-time and switching frequency of the switching transistor M and thus controlling the constant voltage output of the switching power supply. When the switching transistor M is on, current flows through it. The integrated circuit 21 acquires the voltage across the sampling resistor Rcs just before the switching transistor M is turned off to obtain the sampling voltage Vcs, which characterizes the peak current flowing through the switching transistor M. In the actual circuit, because the switching transistor M has a turn-off delay, the sampling action of the sampling resistor Rcs is delayed relative to the actual turn-off time of the switching transistor M, thus resulting in a certain sampling error.

[0060] In related technologies, an external resistor R4 is used to compensate for sampling errors in order to accurately obtain the sampling voltage Vcs. For example... Figure 2 As shown, integrated circuit 21 includes a current mirror 221, a voltage clamp 221a, and a voltage source VCC to provide voltages for the input and output paths of the current mirror 221. The output current of the current mirror 221 is transmitted to resistor R4 via sampling pin CS. The input-to-output ratio of the current mirror is 10:1.

[0061] like Figure 2 As shown, during the process of switching the control signal DRV to low level and turning off the control switch M, the sampling error is ΔVcspk_s&h:

[0062]

[0063] Where Vbus is the bus voltage, Lp is the inductance of the primary winding P of transformer T, and Tdelay is the turn-off delay time of the switching transistor.

[0064] The sampling compensation ΔVcspk_comp is:

[0065]

[0066] Where Vbus is the bus voltage, Na is the number of turns in the auxiliary winding A of transformer T, and Np is the number of turns in the primary winding P of transformer. The sampling compensation ΔVcspk_comp is made equal to the sampling error ΔVcspk_s&h to achieve sampling compensation, which is equivalent to obtaining:

[0067]

[0068]

[0069] As shown in formula (3), in the prior art, if the current Iout_ocp (the desired overcurrent protection point) in the switching power supply increases with the rise of the AC input voltage Vac, an external resistor R4 needs to be added for further compensation. Furthermore, the turn-off delay of the Cool-MOS transistor is much longer than that of the GaN-MOS transistor, therefore, more compensation is required, i.e., the resistance value of the external resistor R4 needs to be further increased. Clearly, the current method of adding an external resistor for sampling compensation is not convenient for circuit integration. At the same time, since the sampling pin CS of a packaged chip containing both a controller and a MOS transistor cannot be connected in series with a resistor, thus… Figure 2 The compensation method of the sampling circuit shown cannot be applied to packaged chips. Therefore, this embodiment provides a sampling circuit to perform accurate sampling compensation without adding external resistors, which facilitates circuit integration and is applicable to sampling of chips in various packages.

[0070] Figure 3 This is a schematic diagram of a switching power supply according to an embodiment of the present invention. (As shown...) Figure 3 As shown, the switching power supply 3 in this embodiment includes a rectifier circuit BD1, a transformer T1, an auxiliary winding A1, a power transistor M1, and a current signal sampling circuit. Specifically, the current signal sampling circuit includes a first sampling circuit 31, a second sampling circuit 32, and a voltage divider circuit 33. The transformer T1 includes a primary winding P1, a secondary winding S1, and an auxiliary winding A1. The input AC voltage Vac1 is rectified by the rectifier circuit BD1 to output a bus voltage Vbus1. The power transistor M1 is configured to switch its state under the control of the switching control signal DRV to maintain the output stability of the switching power supply 3. The voltage divider circuit 33 is connected in parallel across the two ends of the auxiliary winding A1 and is configured to collect the electrical signal of the auxiliary winding A1. Here, the electrical signal of the auxiliary winding A1 can be its voltage signal or the current signal flowing through the auxiliary winding A1. The voltage divider circuit 33 includes an upper resistor R5 and a lower resistor R6 connected in series. The first sampling circuit 31 includes a sampling resistor Rcs1.

[0071] The first sampling circuit 31 is configured to acquire a first sampling signal Vcs1 that represents the current flowing through the inductor. The second sampling circuit 32 is configured to acquire a compensation signal with the same rising slope as the first sampling signal Vcs1 during the turn-off delay time of the power transistor M1 in the switching power supply 3, and to superimpose the compensation signal onto the first sampling signal Vcs1 to generate a second sampling signal Vcs1', thereby achieving accurate sampling of the current signal.

[0072] The current signal sampling circuit has both positive and negative voltage detection functions. Specifically, when the secondary winding S is freewheeling, the voltage signal across the auxiliary winding A1 is a positive voltage, Va_P = (Na1 / Ns1)*Vo. Na1 is the number of turns in the auxiliary winding A1, Ns1 is the number of turns in the secondary winding S1, and Vo is the output voltage of the switching power supply. Therefore, the second sampling circuit 32 can obtain the output voltage Vo of the switching power supply based on the voltage signal Va_P from the auxiliary winding. Optionally, the second sampling circuit 32 can amplify the error based on the output voltage Vo and a preset reference voltage to determine the turn-on time and switching frequency of the power transistor M1, thereby achieving constant voltage output from the switching power supply. When the power transistor M1 is turned on, the second sampling circuit 32 obtains the sampling voltage Vcs1, which characterizes the peak current flowing through the power transistor M1, by acquiring the voltage signal across the sampling resistor Rcs1 just before the power transistor M1 is turned off. In actual circuits, due to the turn-off delay of power transistor M1, the sampling action on sampling resistor Rcs1 is delayed relative to the actual turn-off time of power transistor M1. This results in inaccurate sampling of the peak current information of power transistor M1. The current sampling error is:

[0073]

[0074] Where Lp1 is the inductance of the primary winding P1 of transformer T1, and t is the turn-off delay time of power transistor M1.

[0075] During the conduction of power transistor M1, the voltage signal of auxiliary winding A1 is a negative voltage, Va_N = (Na1 / Np1)*Vbus1. Na1 is the number of turns of auxiliary winding A1, Np1 is the number of turns of secondary winding P1, and Vbus1 is the bus voltage of the switching power supply. Therefore, the second sampling circuit 32 can obtain the output voltage Vbus1 of the switching power supply based on the voltage signal Va_N across the auxiliary winding. In other words, when power transistor M1 is on, the negative current generated by the pull-up resistor R5 at the ZCS terminal of the second sampling circuit 32 reflects the bus voltage Vbus. Therefore, in this embodiment, the charging capacitor can be charged using this negative current within the second sampling circuit 32. The voltage of the charging capacitor obviously represents the actual current; therefore, in this embodiment, the voltage of the energy storage capacitor is used as a compensation signal to compensate for the current sampling error ΔVcs1. Thus, this embodiment achieves accurate sampling error compensation without using an external large resistor, facilitating circuit integration and reducing circuit cost.

[0076] In this embodiment, the compensation signal begins to increase linearly when a control signal is detected that controls the power transistor M1 to turn off, and stops increasing linearly when a zero-crossing point is detected where the current flowing through the inductor changes from positive to negative.

[0077] Preferably, the second sampling circuit includes a current source 321, a control unit 322, and a charging capacitor 323. The current source 321 is configured to generate a charging current. The control unit 322 is configured to control the charging capacitor 323 to charge during the turn-off delay time of the power transistor M1, acquire the charged capacitor voltage to obtain a compensation signal, and compensate the acquired first sampling signal Vcs1 to improve the accuracy of peak current sampling.

[0078] The charging current is determined based on the bus voltage bus1 of the switching power supply. More specifically, the charging current generated by the current source 321 is inversely proportional to the resistance of the upper resistor in the voltage divider circuit 33, and directly proportional to the bus voltage bus1 of the switching power supply 3, as well as the turns ratio of the auxiliary winding A1 to the primary winding P1. Furthermore, the charging current is generated by acquiring the electrical signal of the auxiliary winding A1, and charging of the charging capacitor 323 stops when the electrical signal across the auxiliary winding A1 changes from negative to positive and crosses zero.

[0079] In one optional implementation, the detection circuit in the current source 321 detects the electrical signal of the auxiliary winding A1 and performs zero-crossing detection on the electrical signal of the auxiliary winding A1. For example... Figure 3 As shown, the voltage signal Va of the auxiliary winding A1 is divided by the voltage divider circuit 33 and transmitted to the ZCS terminal of the second sampling circuit 32. The ZCS terminal can be used for current zero-crossing detection. Optionally, since the voltage signal of the auxiliary winding A1 of the transformer T1 is negative during the conduction time of the power transistor M1 and positive during the turn-off time of the switching transistor, the turn-off delay time of the power transistor M1 can be determined by detecting the electrical signal of the auxiliary winding. In this embodiment, the second sampling circuit 32 can perform zero-crossing detection through the ZCS terminal of the current source 321 to determine the actual turn-off time of the switching transistor. Further, the current source 321 is configured to detect the zero-crossing point of the electrical signal of the auxiliary winding A1 through the ZCS terminal, switch the charging control signal to a low level, and the second sampling circuit 32 is configured to stop charging the charging capacitor 323 in response to the charging control signal switching to a low level. It should be understood that this embodiment does not limit the turn-off delay time and the manner of turn-off time of the switching transistor. Optionally, in this embodiment, the current source 321 is configured to determine the charging current of the charging capacitor 323 based on the electrical signal of the auxiliary winding A1. That is, the current source 321 performs a mirror conversion on the current signal acquired at the ZCS terminal to determine the charging current of the charging capacitor 323 during the turn-off delay time.

[0080] Optionally, the rising slope of the compensation signal is configured to be the same as the rising slope of the first sampling signal Vcs1, so as to compensate the sampling signal with the compensation signal. Further optionally, the upper resistor R5 in the voltage divider circuit 33 is set so that the rising slope of the compensation signal is the same as the rising slope of the sampling signal.

[0081] Optionally, this embodiment uses charging capacitor 323 as an example for illustration. It should be understood that this embodiment does not limit the type of charging capacitor 323. In an optional implementation, at least one charging capacitor includes a first charging capacitor, configured to be controlled to charge during the turn-off delay time of power transistor M1 to obtain a compensation signal.

[0082] In one optional implementation, the control unit 322 includes a first switch coupled to the first charging capacitor. The first switch is configured to be controlled to turn on during the turn-off delay time of the power transistor M1 to control the charging of the first charging capacitor, thereby acquiring a compensation signal. Optionally, the second sampling circuit 32 switches the corresponding charging control signal to a high level at the falling edge of the control signal DRV of the power transistor M1 to control the first switch to turn on, and detects a zero-crossing signal at the ZCS terminal, i.e., the electrical signal of the auxiliary winding switches from negative to positive. At the moment when the power transistor M1 is completely turned off, the second sampling circuit 32 switches the corresponding charging control signal to a low level to control the first switch to turn off. Thus, the second sampling circuit 32 can control the first switch to turn on during the turn-off delay time of the power transistor M1, thereby controlling the charging of the first charging capacitor. Optionally, the charging current of the charging capacitor is determined based on the bus voltage. Since the electrical signal of the auxiliary winding A1 can characterize the bus voltage Vbus1 during the conduction of the power transistor M1, and the bus voltage Vbus1 can characterize the bus current, the current source 321 in the second sampling circuit 32 can determine the charging current of the first charging capacitor based on the acquired electrical signal of the auxiliary winding, so that the voltage of the first charging capacitor after charging can characterize the actual current signal.

[0083] In one optional implementation, at least one charging capacitor includes a first charging capacitor and a second charging capacitor. The control unit 322 also includes a second switch and a third switch. The second switch is coupled between the sampling signal acquisition terminal and the second charging capacitor, and the third switch is coupled between the first and second charging capacitors. The second and third switches are configured to be turned on by a sampling control signal and turned off by the falling edge of the control signal of the power transistor M1, thereby controlling the charging of the first and second charging capacitors to acquire the sampling signal. That is, before the falling edge of the control signal DRV of the power transistor M1, the second and third switches are turned on to acquire the first sampling signal Vcs1. At the delayed turn-off moment of the power transistor M1, the original sampling signal contains undershoot noise. Therefore, this embodiment controls the first switch to turn on and charges the first charging capacitor using a charging current determined based on the electrical signal of the auxiliary winding to acquire a compensation signal. Thus, this embodiment can acquire the current sampling signal of the power transistor M1 more accurately.

[0084] In one alternative implementation, the control unit 322 further includes a first amplifier. The input of the first amplifier is coupled to a first charging capacitor and a second charging capacitor, respectively, and the output is coupled to a third switch, which is configured to control the amplification of the sampled signal by a predetermined factor or to control the compensation signal method by a predetermined factor, so as to compensate the sampled signal according to the compensation signal.

[0085] In one alternative implementation, the control unit 322 further includes a first resistor and a second resistor connected in series between the first switch and the ground terminal. The resistance ratio of the first resistor and the second resistor is a first predetermined value.

[0086] In one alternative implementation, the first input terminal of the first amplifier is connected to the second charging capacitor, and the second input terminal is connected to the common terminal of the first resistor and the second resistor to control the amplification of the sampling signal or compensation signal by a predetermined factor, thereby further facilitating the compensation of the sampling signal according to the compensation signal.

[0087] In this embodiment of the invention, the control unit of the sampling circuit charges the charging capacitor within the turn-off delay time of the corresponding switching transistor, determines the compensation signal based on the voltage of the charging capacitor after charging, and then compensates the sampling signal based on the compensation signal. Therefore, this embodiment accurately obtains the compensation signal for the turn-off delay time of the switching transistor by charging the charging capacitor internally within the integrated circuit, eliminating the need for external large resistors, facilitating circuit integration, and reducing circuit size and cost. Furthermore, the sampling circuit of this embodiment can be applied to encapsulated chips to achieve sampling compensation for encapsulated chips.

[0088] Figure 4 This is a schematic diagram of a sampling circuit according to an embodiment of the present invention. Optionally, this embodiment uses a charging capacitor as the capacitor element, and the first sampling signal is amplified by a predetermined factor as an example for description. Figure 4 As shown, the second sampling circuit 32 of this embodiment illustrates the specific structure and connection method of the control unit 322 and the charging capacitor 323.

[0089] The second sampling circuit 32 in this embodiment includes a current source 321, a charging capacitor 323 composed of a first capacitor C1 and a second capacitor C2, and a control unit 322. The control unit 322 includes a first switch S1, a second switch S2, a third switch S3, an amplifier Am1, a first resistor R7, and a second resistor R8. The series path formed by resistors R7 and R8, and the first capacitor C1, are connected in parallel between the output terminal of the current source 321 and the ground terminal. The first switch S1 is connected between the output terminal of the current source 321 and the first capacitor C1. The second switch S2 is connected between the sampling pin CS of the second sampling circuit 32 and the second capacitor C2. The second capacitor C2 is connected between the second switch S2 and the positive input terminal of the amplifier Am1. The third switch S3 is connected between the output terminal of the amplifier Am1 and the common terminal a. The common terminal a is the common terminal of the first switch S1, the first capacitor C1, and the resistor R7.

[0090] Specifically, the first capacitor C1 stores the first sampling signal Vcs1 in the charging capacitor during the conduction period of the power transistor M1. At the end of the turn-off delay, the voltage across the charging capacitor is used as the second sampling signal Vcs1'. The amplifier Am1, the first resistor R7, and the second resistor R8 are configured to control the amplification of the first sampling signal Vcs1 by a predetermined factor. The resistance ratio of the first resistor R7 and the second resistor R8 is a first predetermined value.

[0091] like Figure 4 As shown, during the conduction time Ton of power transistor M1, i.e., the time when control signal DRV is high, the second switch S2 and the third switch S3 are kept on, and the first switch S1 is kept off, so that the first sampling signal Vcs1 is sampled into the first capacitor C1 and the second capacitor C2 to obtain the first sampling signal Vcs1 in real time. Optionally, in this embodiment, the ratio of resistors R7 and R8 is set to 2:1, so that the signal sampled by the first capacitor C1 is 3*Vcs1 based on amplifier Am1, that is, the control sampling signal Vcs is increased to 3 times the original value. It should be understood that this embodiment does not limit the ratio of resistors R7 and R8, which can be set according to the actual application scenario.

[0092] When the control signal DRV of power transistor M1 goes low (i.e., the turn-off moment), the second switch S2 and the third switch S3 are turned off, and the first switch S1 is turned on. Since the second switch S2 and the third switch S3 are already off, therefore... Figure 1 The undershoot noise generated by the sampled signal at time t0 will no longer affect the result of the sampled signal holding, that is, it will not affect the voltage value of the first capacitor C1.

[0093] After the first switch S1 is turned on, the current I1 generated at the ZCS terminal is mirrored as current I2 after passing through current source 321, so as to continue charging the first capacitor C1 through the first switch S1 until the ZCS terminal detects the current zero crossing point, that is, the power transistor M1 is completely turned off, controlling the first switch S1 to turn off and stop charging the first capacitor C1. At this time, the first switch S1, the second switch S2 and the third switch S3 are all in the off state, and the voltage on the first capacitor C1 no longer rises. The voltage on the first capacitor C1 is extracted to obtain the compensation signal. After compensation based on the compensation signal to obtain an accurate sampling signal, after subsequent processing, such as amplification processing, Tdis / T module processing, etc., the primary side feedback current Iout_psr can be obtained. The switching power supply can be further adjusted according to the primary side feedback current Iout_psr. This embodiment will not describe the subsequent processing in detail here.

[0094] Among them, the input current I1 in the current source 321 is I1 = Vbus1 / Np1*Na1*1 / R5 (4).

[0095] The output current in current source 321 is I2 = I1 / k (5).

[0096] Where k is the ratio of the input current to the output current of the current source 321, which can be set according to the specific application scenario.

[0097] The charge (i.e., compensation signal) of the first capacitor C1 during the turn-off delay time is ΔVc1=I2 / C1*t (6).

[0098] Where t is the turn-off delay time of power transistor M1.

[0099] The error of the sampled signal obtained by the first capacitor C1 is:

[0100] 3*ΔVcs1=3*Vbus1 / Lp1*Rcs1*t (7)

[0101] The sampling error is compensated based on the compensation signal, then:

[0102] ΔVc1=3*ΔVcs1

[0103] That is, I2 / C1=3*Vbus1 / Np1*Rcs1 (8)

[0104] According to formulas (4)-(8), we can obtain:

[0105] R5=Lp1 / (3*k*Rcs1*C1*Npa) (9)

[0106] Where Lp1 is the inductance of the primary winding P1 of transformer T1, and Npa is the turns ratio of the primary winding P1 to the auxiliary winding A1 of transformer T1.

[0107] Therefore, in this embodiment, the value of resistor R5 used when sampling the electrical signal of the auxiliary winding can be calculated using formula (9) so that the rising slope of the compensation signal is the same as or approximately the same as the rising slope of the first sampling signal Vcs1. However, since there is a certain deviation between the actual value and the theoretical value in the actual operation of the circuit, after calculating the value of resistor R5, it is usually necessary to perform a test to further fine-tune the value of resistor R5, so that the rising slope of the compensation signal is the same as the rising slope of the first sampling signal Vcs1, thereby further improving the sampling accuracy.

[0108] Figure 5 This is a schematic diagram of the operating waveform of the sampling circuit in an embodiment of the present invention. Figure 5 As shown, at time t1, the power transistor M1 is turned on under control, and the current I_ZCS detected at the ZCS terminal drops to a negative current. At this time, the second switch S2 and the third switch S3 are turned on under control, and the first sampling signal Vcs1 is obtained through the first capacitor C1 and the second capacitor C2. At time t2, the control signal of power transistor M1 goes low, meaning power transistor M1 is controlled to start the turn-off operation. At this time, the first sampling signal Vcs1 shows decreasing noise, the sampling control signal TS1 switches to high, the first switch S1 is turned on by the sampling control signal TS1, and the second switch S2 and the third switch S3 are turned off. The charging current I2 starts charging the first capacitor C1 until time t3, when the zero-crossing point of the current I_ZCS is detected at the ZCS terminal. At this time, power transistor M1 has been completely turned off, the sampling control signal TS1 switches to low, the first switch S1 is turned off by the control signal TS1, and the first capacitor C1 stops charging. The voltage on the first capacitor C1 at this time can be compensated to accurately represent the actual sampling signal, i.e., the second sampling signal Vcs1'. Therefore, in this embodiment, the first capacitor C1 can continue to be charged through the current at the ZCS terminal during the turn-off delay time of the switch transistor to compensate for the sampling error, without the need for an additional external large resistor, saving costs and facilitating circuit integration.

[0109] In this embodiment of the invention, the control unit of the current signal sampling circuit charges the charging capacitor during the turn-off delay time of the corresponding switch, determines the compensation signal based on the voltage of the charged capacitor after charging, and then compensates the sampled signal based on the compensation signal. Therefore, this embodiment accurately obtains the compensation signal by charging the charging capacitor with the current inside the integrated circuit during the turn-off delay time, reducing circuit cost, facilitating circuit integration, and reducing circuit size.

[0110] Figure 6 This is a schematic diagram of another sampling circuit according to an embodiment of the present invention. (As shown...) Figure 6 As shown, Figure 6 A circuit diagram is provided for a sampling method that does not amplify the first sampled signal Vcs1, that is, relative to... Figure 4 The sampling circuit shown, Figure 6 The inverting input of amplifier Am2 is directly connected to the first capacitor C1. This allows for sampling error compensation while further reducing circuit cost and saving space. It should be understood that its principle is similar to... Figures 4-5 The corresponding implementation methods are similar and will not be described in detail here.

[0111] It should be noted that, in this embodiment, as Figure 4 The first sampled signal Vcs1 is amplified by a predetermined factor, or as follows: Figure 6 It is not necessary to amplify the first sampling signal Vcs1. The purpose of amplifying the first sampling signal Vcs1 by a predetermined factor is only to further improve the accuracy of current sampling.

[0112] In this embodiment of the invention, the control unit of the sampling circuit charges the charging capacitor during the turn-off delay time of the corresponding switch, determines the compensation signal based on the voltage of the charged capacitor after charging, and then compensates the sampling signal based on the compensation signal. Therefore, this embodiment accurately obtains the compensation signal by charging the charging capacitor with the current inside the integrated circuit during the turn-off delay time, reducing circuit cost, facilitating circuit integration, and reducing circuit size.

[0113] Figure 7 This is a parameter diagram of an embodiment of the present invention. Based on any of the above embodiments, taking a specific charger as an example, according to the calculation formula of R5 in formula (9): R5=Lp1 / (3*k*Rcs1*C1*Npa), the results of taking the maximum and minimum values ​​of each parameter are calculated, such as Figure 7 As shown. Where Nps is the turns ratio of the primary and secondary windings of the transformer, and Iout_ocp is the desired overcurrent protection point. ΔVcs1 is the rise amplitude of the sampled signal Vcs within the turn-off delay time t, in mV. ΔVc1 is the rise amplitude of the first capacitor C1 in this embodiment within the turn-off delay time t, in mV; this voltage has been amplified by 3 times.

[0114] When the pull-up resistor R5 in the voltage divider circuit reaches its maximum value of 198 kΩ:

[0115] And when the bus voltage Vbus1 equals 80V, ΔVcs1=4mV (not amplified by 3 times), ΔVc1=12mV (amplified by 3 times), the sampling error matches the compensation voltage;

[0116] When Vbus1 = 380V, ΔVcs1 = 19mV (without 3x amplification) and ΔVc1 = 58mV (with 3x amplification). The sampling error is close to the compensation voltage, and they are basically matched.

[0117] When the pull-up resistor R5 of ZCS is taken as the minimum of 37 kΩ:

[0118] When Vbus1 = 80V, ΔVcs1 = 16mV (without 3x amplification) and ΔVc1 = 47mV (with 3x amplification). The sampling error is close to the compensation voltage, and they are basically matched.

[0119] When Vbus1 = 380V, ΔVcs1 = 74mV (without 3x amplification) and ΔVc1 = 222mV (with 3x amplification), the sampling error matches the compensation voltage;

[0120] Therefore, regardless of the transformer inductance, turns ratio, or the value of the sampling resistor Rcs1, the sampling error of Vcs1 can be compensated simply by calculating the resistance value of resistor R5 according to formula (9). Furthermore, after calculating the resistance value of the pull-up resistor R5, the resistance value of the pull-up resistor R5 can be finely adjusted through testing to more accurately compensate for the sampling error of the first sampling signal Vcs1.

[0121] In this embodiment of the invention, the control unit of the sampling circuit charges the charging capacitor during the turn-off delay time of the corresponding switch, determines the compensation signal based on the voltage of the charged capacitor after charging, and then compensates the sampling signal based on the compensation signal. Therefore, this embodiment accurately obtains the compensation signal by charging the charging capacitor with the current inside the integrated circuit during the turn-off delay time, reducing circuit cost, facilitating circuit integration, and reducing circuit size.

Claims

1. A current signal sampling method, applied to a switching power supply, characterized in that, The method includes: Acquire the first sampled signal of the current flowing through the inductor; In the switching power supply, a compensation signal with the same rising slope as the first sampling signal is obtained during the turn-off delay time of the power transistor, and the compensation signal is superimposed on the first sampling signal to generate a second sampling signal; During the turn-off delay time, a charging capacitor is charged using a charging current generated by a current source to generate the compensation signal on the charging capacitor.

2. The current signal sampling method according to claim 1, characterized in that, The compensation signal begins to increase linearly when a control signal controlling the power transistor to turn off is detected, and stops increasing linearly when a zero-crossing point is detected where the current flowing through the inductor changes from positive to negative.

3. The current signal sampling method according to claim 1, characterized in that, The charging current is determined based on the bus voltage of the switching power supply.

4. The current signal sampling method according to claim 1, characterized in that, The charging current is generated by acquiring the electrical signal of the auxiliary winding coupled to the primary winding, and the charging of the charging capacitor stops when the electrical signal at both ends of the auxiliary winding changes from negative to positive and crosses zero.

5. The current signal sampling method according to claim 4, characterized in that, Also includes: A voltage divider circuit is connected in parallel across the two ends of the auxiliary winding, wherein the voltage divider circuit includes an upper resistor and a lower resistor connected in series. as well as The charging current generated by the current source is inversely proportional to the resistance of the upper resistor and directly proportional to the bus voltage of the switching power supply and the turns ratio of the auxiliary winding to the primary winding.

6. The current signal sampling method according to claim 5, characterized in that, The resistance value of the upper resistor is configured to control the charging current to charge the charging capacitor, so that the rising slope of the compensation signal is the same as the rising slope of the first sampling signal.

7. The current signal sampling method according to claim 1, characterized in that, At the end of the shutdown delay time, the peak value of the second sampling signal is acquired to generate a peak current sampling signal.

8. The current signal sampling method according to claim 1, characterized in that, The first sampling signal is stored in the charging capacitor during the power transistor's on-time, and the voltage across the charging capacitor is used as the second sampling signal at the end of the off-time delay.

9. The current signal sampling method according to claim 1, characterized in that, During the power transistor's conduction period, the first sampling signal is stored in the first capacitor and the charging capacitor. During the turn-off delay time, the charging capacitor is charged using the charging current to superimpose the compensation signal onto the first sampling signal, thereby generating the second sampling signal across the charging capacitor.

10. A current signal sampling circuit, applied to a switching power supply, characterized in that, The current signal sampling circuit includes: The first sampling circuit is configured to acquire a first sample signal of the current flowing through the inductor; and The second sampling circuit is configured to acquire a compensation signal with the same rising slope as the first sampling signal during the turn-off delay time of the power transistor in the switching power supply, and to superimpose the compensation signal on the first sampling signal to generate the second sampling signal. The second sampling circuit includes: A current source is configured to generate a charging current; and A charging capacitor is charged by the charging current during the turn-off delay time to generate the compensation signal on the charging capacitor.

11. The current signal sampling circuit according to claim 10, characterized in that, The compensation signal begins to increase linearly when a control signal controlling the power transistor to turn off is detected, and stops increasing linearly when a zero-crossing point is detected where the current flowing through the inductor changes from positive to negative.

12. The current signal sampling circuit according to claim 10, characterized in that, The charging current is determined based on the bus voltage of the switching power supply.

13. The current signal sampling circuit according to claim 10, characterized in that, The charging current is generated by acquiring the electrical signal of the auxiliary winding coupled to the primary winding, and the charging of the charging capacitor stops when the electrical signal at both ends of the auxiliary winding changes from negative to positive and crosses zero.

14. The current signal sampling circuit according to claim 13, characterized in that, A voltage divider circuit is connected in parallel across the two ends of the auxiliary winding, wherein the voltage divider circuit includes an upper resistor and a lower resistor connected in series. The charging current generated by the current source is inversely proportional to the resistance of the upper resistor and directly proportional to the bus voltage of the switching power supply and the turns ratio of the auxiliary winding to the primary winding.

15. The current signal sampling circuit according to claim 14, characterized in that, The resistance value of the upper resistor is configured to control the charging current to charge the capacitor, so that the rising slope of the compensation signal is the same as the rising slope of the first sampling signal.

16. The current signal sampling circuit according to claim 10, characterized in that, At the end of the shutdown delay time, the peak value of the second sampling signal is acquired to generate a peak current sampling signal.

17. The current signal sampling circuit according to claim 10, characterized in that, The first sampling signal is stored in the charging capacitor during the power transistor's on-time, and the voltage across the charging capacitor is used as the second sampling signal at the end of the off-time delay.

18. The current signal sampling circuit according to claim 10, characterized in that, The second sampling circuit includes: First capacitor. During the power transistor's on-time, the first sampling signal is stored in the first capacitor and the charging capacitor. At the end of the off-time delay, the voltage across the charging capacitor is used as the second sampling signal.

19. The current signal sampling circuit according to claim 18, characterized in that, The second sampling circuit also includes: A first amplifier, with its first input terminal and second input terminal respectively coupled to the first capacitor and the charging capacitor, and its output terminal coupled to the charging capacitor, is configured to control the amplification of the first sampled signal by a predetermined factor.

20. The current signal sampling circuit according to claim 19, characterized in that, The second sampling circuit also includes: A first resistor is coupled to the output and second input terminals of the first amplifier; and The second resistor is connected in series between the first resistor and the ground terminal; The resistance ratio of the first resistor and the second resistor is a first predetermined value.

21. A switching power supply, characterized in that, The switching power supply includes: A transformer includes a primary winding, a secondary winding, and an auxiliary winding; A switching transistor is configured to switch states under control of a switching control signal to maintain the output stability of the switching power supply; and The current signal sampling circuit as described in any one of claims 10-20.

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