A shen wei intelligent acceleration card system based on chiplet technology

Abstract

The application relates to a Shenwei intelligent acceleration card system based on a Chiplet technology, a Chiplet architecture chip taking a Shenwei processor and a domestic FPGA as cores, being capable of supporting mainstream AI algorithm models and accelerating an inference process through cooperation of the powerful double-precision floating point and integer calculation power of the Shenwei processor, the powerful parallel computing capacity of the FPGA and the high-flexibility low-latency performance of the Chiplet architecture, and being applicable to domestic computers, servers, intelligent products and the like. The devices used in the application are all domestic, and have a higher self-controllable level; the Chiplet architecture designed with a PCIe interconnection bus as a core has the advantages of high transmission bandwidth, high calculation efficiency and easy realization of an inter-chip interconnection protocol; the Chiplet research and development idea based on the domestic general-purpose processor and the FPGA can be expanded according to application requirements to face different application fields.

Description

Technical Field

[0001] This invention relates to the field of intelligent acceleration, and more particularly to a Shenwei intelligent acceleration card system based on Chiplet technology. Background Technology

[0002] Chiplet technology combines small chips with different functions and process nodes using advanced packaging technology to form complex and heterogeneous integrated chips. It can overcome the bottleneck of single-chip photolithography area, overcome design cycle constraints, reduce design costs and complexity, and has already shown unique advantages in high-performance CPUs, FPGAs and other fields.

[0003] With the development of new-generation information technologies such as big data, cloud computing, artificial intelligence, and 5G communication, and the ever-increasing speed of data growth, the demand for AI acceleration has reached an unprecedented level. On this basis, the heterogeneous computing architecture intelligent acceleration card of Chiplet technology has emerged. Based on the performance of multi-core processors and the parallel processing capabilities of FPGAs, it has advantages such as high computing power, high reliability, short R&D time, and fast data processing speed. It can be adapted to different algorithm models and applied to different AI intelligent acceleration scenarios.

[0004] Existing computing acceleration technologies need to balance computing performance and security risks, and hardware design compatibility is a pressing issue and challenge. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a Shenwei intelligent accelerator card system based on Chiplet technology. The Chiplet architecture chip in this accelerator card system is based on a Shenwei processor and a domestically developed FPGA. The Chiplet architecture chip is formed by the Shenwei WX3231 processor and the domestically developed FPGA JFM7VX690T80 chip interconnected internally via PCIe, LPC, and GPIO signals. It supports cache coherency and a self-developed inter-chip interconnection protocol, while also providing external PCIe, SPI, UART, IIC, DDR4, DDR3, JTAG, and GPIO signal interfaces. Meanwhile, one set of PCIe X4 signals from the Shenwei WX3231 processor within the Chiplet architecture chip is led out to connect to the SATA control chip, expanding to two SATA 3.0 interfaces and two mSATA interfaces for connecting the operating system disk and the data disk. One set of PCIe X4 signals of the Shenwei WX3231 processor in the Chiplet architecture chip is led out to connect to the gigabit network control chip, expanding to four gigabit Ethernet RJ45 interfaces, providing a data exchange channel between the processor and peripherals. One set of PCIe x16 signals from the Shenwei WX3231 processor within the Chiplet architecture chip is led out to the PCIe gold fingers for use as an accelerator card connection interface. It supports the PCIe 4.0 standard and features polarity inversion, channel reversal, and link auto-negotiation. The Chiplet architecture chip contains a set of PCIe X16 signals, a set of LPC bus signals, and GPIO interconnected with the JFM7VX690T80 of the Shenwei WX3231 processor. Communication and data transmission are performed based on the PCIe bus protocol, as well as low-speed signal communication and data transmission based on the LPC bus protocol. Except for the interconnection portion with the processor, the JFM7VX690T80 chip in the Chiplet architecture chip has its HR and HP banks exposed to GPIO interfaces for FPGA system configuration and status control, and is fully compatible with the FPGA's IO pin functions.

[0006] In one embodiment of the present invention, the CPLD chip, SATA control chip, network control chip, DDR4 chip, DDR3 chip, RS232 transceiver chip, Flash chip, and RTC chip are all directly connected to the Chiplet architecture chip. The CPLD chip and RTC chip are connected to the Chiplet architecture chip through IIC, and are used to control the power-on, reset, status monitoring and RTC functions of the local system.

[0007] In one embodiment of the present invention, DDR4 and DDR3 chips are included. Both DDR4 and DDR3 chips are connected to the Chiplet architecture chip by labeling. The DDR4 chip is used for memory storage of the Shenwei WX3231 processor in the Chiplet architecture chip, and the DDR3 chip is used for memory storage of the JFM7VX690T80 chip.

[0008] In one embodiment of the present invention, the RS232 transceiver chip is connected to the UART interface of the Chiplet architecture chip and has one DB9 interface for serial output for software system debugging.

[0009] In one embodiment of the present invention, the Flash chip is connected to the SPI interface of the Chiplet architecture chip and is used to store the system's hardware configuration and parameter settings as well as the system's self-booting.

[0010] In one embodiment of the present invention, the JTAG interface, the Chiplet architecture chip integrates two sets of JTAG interfaces compatible with IEEE1149.1, respectively using the internal Shenwei WX3231 processor and the domestic FPGA JFM7VX690T80 chip.

[0011] In one embodiment of the present invention, a power supply module is also included, which consists of DC-DC power conversion chips JPM4630A, JPM4644, JPM4600HV, LDO power chip JS74401, and DDR VTT terminating voltage regulator chip SGM2054. The 12V DC voltage is converted into the core power, I / O power, peripheral power, and memory power required by the system through the above power supply module.

[0012] In one embodiment of the present invention, a clock module is also included, which mainly consists of an active crystal oscillator and a clock generator. The active crystal oscillator provides the main clock required for system startup, and the clock generator is mainly used for reference clocks of chips that operate based on PCIe signals, as well as PCIe gold fingers and peripherals.

[0013] In one embodiment of the present invention, the Chiplet architecture chip consists of a Shenwei WX3231 processor and a Fudan Micro JFM7VX690T80, the CPLD chip is an Anlu EF2L45BG256B, the SATA control chip is a JS88SE9215 from the 58th Research Institute, the network control chip is a Netcom WX1860AL4, the DDR4 chip is a Changxin CXDQ3A8AM, the DDR3 chip is an HXB15H4G800AF, the RS232 transceiver chip is a SIT3232E, the Flash chip is a Fudan Micro FM25W128, the RTC chip is an AiP8563, the power supply module mainly consists of a 58th Research Institute JPM4630A, JPM4644, and JS74401, and the clock module mainly consists of a Yangxing active crystal oscillator YSO230LR and a 58th Research Institute clock generator J9FG0841.

[0014] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The accelerator card system of the present invention uses the Shenwei WX3231 processor and Fudan Micro JFM7VX690T80 as the core of the Chiplet architecture chip, and the design is completely independent and controllable; the Chiplet technology based on advanced packaging is expected to break Moore's Law, and the heterogeneous architecture of CPU and FPGA is more suitable for intelligent acceleration scenarios; the PCIE-based bus design has the advantages of low transmission latency, high speed and high computing efficiency of each module, and the bus interconnection protocol is suitable for secondary development; the power-on sequence of the local system controlled by CPLD is more stable; the surface-mount memory chips are more reliable than the later reinforcement of memory modules, and achieve the advantages of reduced size, improved stability and service life. Attached Figure Description

[0015] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0016] Figure 1This is a structural diagram of the Chiplet architecture chip of the present invention; Figure 2 This is a schematic diagram of the overall structural framework of the present invention. Detailed Implementation

[0017] like Figure 1 and Figure 2 As shown, this embodiment provides a Shenwei intelligent accelerator card system based on Chiplet technology, specifically including a Chiplet architecture chip, a CPLD chip, a SATA control chip, a network control chip, DDR4 chips, DDR3 chips, an RS232 transceiver chip, a Flash chip, an RTC chip, a JTAG interface, an RJ45 interface, a DB9 interface, a SATA interface, an mSATA interface, a GPIO interface, a power module, and a clock module.

[0018] Specifically, the Chiplet architecture chip integrates the Shenwei WX3231 processor and the domestically produced FPGA JFM7VX690T80 chip, interconnected internally via PCIe, LPC, and GPIO signals, while externally expanding to include PCIe, SPI, UART, IIC, DDR4, DDR3, JTAG, and GPIO signal interfaces to achieve performance applications and expansion. The WX3231 processor is a domestically produced high-performance multi-core processor based on the SW64 architecture, integrating 8 DDR4 memory controller interfaces, 4 PCIe 4.0 standard I / O interfaces with 40 lanes each, and 1 set of standard LPC interfaces. It primarily provides high-performance PCIe 4.0 signal interfaces and DDR4 interfaces. This processor boasts a double-precision floating-point performance of up to 1280 GFlops and an integer performance of up to 880 GFlops, with a maximum clock speed of 2.4 GHz. With its powerful computing capabilities, it is primarily targeted at high-performance computing and high-end server applications. The JFM7VX690T80 is a high-performance, high-capacity SRAM-based FPGA product. It includes LUT6-based CLB logic resources, multi-level standard I / O interface resources, clock management unit, etc., and mainly provides multi-functional reusable GPIO interfaces to implement FPGA functions.

[0019] Specifically, the CPLD chip, SATA control chip, network control chip, DDR4 chips, DDR3 chips, RS232 transceiver chip, Flash chip, and RTC chip are all directly connected to the Chiplet architecture chip. The CPLD chip is an Anlu EF2L45BG256B, which controls the system's power and timing via IIC. The Flash chip is an FM25W128, which loads the boot program via the SPI data bus after the system is powered on, ultimately completing the board boot. The RTC chip is an AiP8563, which implements the RTC function via IIC. The DDR4 chips are Changxin CXDQ3A8AM, used for memory storage of the Shenwei WX3231, and the DDR3 chips are HXB15H4G800AF, used for memory storage of the JFM7VX690T80 chip. The RS232 transceiver chip is a SIT3232E, connected via a UART interface and with one DB9 interface for serial information printing output.

[0020] Specifically, one set of PCIe X4 signals on the outside of the Chiplet architecture chip is connected to the SATA controller chip JS88SE9215, expanding to two SATA 3.0 interfaces and two mSATA interfaces for connecting the operating system disk and the data disk.

[0021] Specifically, one set of PCIe X4 signals on the outside of the Chiplet architecture chip is connected to the Gigabit network controller chip WX1860AL4, which expands to four Gigabit Ethernet RJ45 interfaces, providing a data exchange channel between the processor and peripherals.

[0022] Specifically, one set of PCIe X16 signals on the outside of the Chiplet architecture chip is led out to connect to the standard PCIe gold fingers, providing an external connection interface for the accelerator card and supporting the PCIe 4.0 standard.

[0023] Specifically, the GPIO interfaces brought out from the outside of the Chiplet architecture chip can all reuse the functions of the JFM7VX690T80 chip.

[0024] This embodiment does not use a chiplet and PCIe switch structure, which simplifies the design of the hardware platform and makes full use of the PCIe expansion resources of the Shenwei processor.

[0025] Specifically, the power module of the Shenwei Smart Accelerator Card System based on Chiplet technology mainly consists of DC-DC power conversion chips JPM4630A, JPM4644, JPM4600HV, LDO power chip JS74401, and DDR VTT linear termination regulator chip SGM2054. The 12V DC voltage is used to generate the core voltage and I / O voltage of the Chiplet architecture chip through the power conversion chips JPM4630A and JPM4644. The 5V voltage is output by the power conversion chip JPM4600HV to supply the auxiliary voltage of the power chip JS74401 to generate the FPGA. The VVT ​​power supply voltage of the DDR chip is provided by the SGM2054 chip.

[0026] Specifically, the clock module in the Shenwei Smart Acceleration Card system based on Chiplet technology mainly consists of an active crystal oscillator YSO230LR and a clock generator J9FG0841. The active crystal oscillator provides the main clock for system startup, and the clock generator provides the reference clock for each PCIe device and conversion chip.

[0027] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A Shenwei intelligent accelerator card system based on Chiplet technology, wherein the Chiplet architecture chip in the accelerator card system is based on a Shenwei processor and a domestically produced FPGA, characterized in that, include: A printed circuit board on which a Chiplet architecture chip, serving as the core of the system, is mounted; The Chiplet architecture chip uses advanced packaging technology to heterogeneously integrate the Shenwei processor and the domestic FPGA chip in a single package, and supports inter-chip cache coherence protocol. The chips are interconnected via high-speed PCIe, LPC and GPIO signals, while also providing external signal interfaces for PCIe, SPI, UART, IIC, DDR4, DDR3, JTAG and GPIO. Meanwhile, one set of PCIe X4 signals from the Shenwei processor within the Chiplet architecture chip is led out to connect to the SATA control chip, expanding to two SATA 3.0 interfaces and two mSATA interfaces for connecting the operating system disk and the data disk; One set of PCIe X4 signals of the Shenwei processor in the Chiplet architecture chip is led out to connect to the gigabit network control chip, expanding to 4 gigabit Ethernet interfaces, providing a data exchange channel between the processor and peripherals; One set of PCIe X16 signals of the Shenwei processor inside the Chiplet architecture chip is led out to the PCIe gold finger for external connection interface of the accelerator card. The HR and HP Bank of the FPGA chip within the Chiplet architecture chip expose GPIO interfaces for dynamic configuration and control of the system.

2. The accelerator card system according to claim 1, characterized in that: The IIC signal in the Chiplet architecture chip connects the CPLD chip and the RTC clock chip, and is used for local system shutdown, reset functions and to implement RTC functions.

3. The accelerator card system according to claim 1, characterized in that: DDR4 and DDR3 memory chips are connected to the Chiplet architecture chip using a label method. The two memory channels of the DDR4 interface are connected to two sets of DDR4 memory chips respectively, and one memory channel of the DDR3 interface is connected to the DDR3 memory chip.

4. The accelerator card system according to claim 1, characterized in that: The UART signal in the Chiplet architecture chip is connected to the RS232 transceiver, and one DB9 interface is brought out for serial output and software system debugging.

5. The accelerator card system according to claim 1, characterized in that: The SPI signal in the Chiplet architecture chip is connected to the Flash chip to store the system's hardware configuration and parameter settings, as well as the system's self-booting process.

6. The accelerator card system according to claim 1, characterized in that: The accelerator card system also includes a power module, which includes a DC-DC power conversion chip, an LDO power chip, and a DDR VTT terminal voltage regulator chip. The DC-DC power conversion chip and the LDO power chip are used to convert the external power supply into the operating voltage of each power domain required by the intelligent accelerator card system, ensuring the stability of the system power supply.

7. The accelerator card system according to claim 1, characterized in that: The accelerator card system also includes a clock module, comprising a clock generator, a crystal oscillator, and a real-time clock chip, used to generate various clocks required for system operation.

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