A cryptographic algorithm debugging data hierarchical packet compression method for a reconfigurable cryptographic chip
By hierarchically grouping and compressing the debugging data of the reconfigurable cryptographic chip using Huffman coding, the problems of large debugging data volume and performance limitations are solved, improving the transmission performance and compression rate of debugging data, and making it suitable for various cryptographic algorithms.
Patent Information
- Application Number
- CN202211722753.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-30
- Publication Date
- 2026-03-20
- Estimated Expiration
- 2042-12-30
AI Technical Summary
During the debugging process of reconfigurable cryptographic chips, the amount of debugging data is large and the performance is limited, resulting in high debugging complexity and difficulty in meeting the requirements for efficient data transmission and accurate positioning.
The debugging data is filled or spliced using a hierarchical grouping method and compressed using Huffman coding. The hierarchical grouping includes L1, L2 and L3 levels, which correspond to different debugging data types. When the data bit width does not meet or exceeds 128 bits, appropriate adjustments are made. Finally, the data is compressed using Huffman coding.
It achieves a compression rate of over 60% for debugging data, improves the transmission performance of debugging data, reduces storage resource requirements, and is suitable for various cryptographic algorithms such as AES, DES, ZUC, SNOW3G, SM3, and MD5.
Smart Images
Figure CN116011039B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of cipher algorithm debugging data compression of reconfigurable cryptographic chips, and particularly relates to a cipher algorithm debugging data hierarchical grouping compression method for reconfigurable cryptographic chips. BACKGROUND
[0002] Cryptographic chips play a major role in the field of information security. Cryptographic chips implemented in a reconfigurable computing manner combine the advantages of high performance of GPP and high flexibility of ASIC, and are one of the ideal schemes for implementing current cryptographic algorithms. Compared with the processing of one-dimensional instruction sets and data in the GPP debugging process and the processing of limited data streams in the ASIC debugging process, the reconfigurable architecture debugging process needs to consider two-dimensional configuration changes and matching processing of data, and the debugging process is more complex, and the amount of intermediate data generated by the debugging process is larger. On the other hand, from the application demand level, the reconfigurable processor needs to meet the data transmission demand and the single-step debugging demand of accurate positioning of algorithm efficient debugging in different application scenarios, and also needs to process and locate the exception handling in the configuration dynamic switching process. In order to ensure the running stability of the reconfigurable cryptographic chip, it is particularly important to design and implement a debugger for the reconfigurable cryptographic chip in the chip development process. The high bandwidth and high performance of the reconfigurable cryptographic processor also bring the problem of large amount of algorithm calculation debugging data for the reconfigurable debugger, which is also the main challenge and key point of the design of the reconfigurable debugger. SUMMARY
[0003] The present application aims to provide a cipher algorithm debugging data hierarchical grouping compression method for reconfigurable cryptographic chips, to solve the technical problems of large amount of debugging data and limited debugging performance in the debugging design of reconfigurable cryptographic chips.
[0004] To solve the above technical problems, the specific technical solutions of the present application are as follows:
[0005] A cipher algorithm debugging data hierarchical grouping compression method for reconfigurable cryptographic chips, which groups the debugging data, then fills or splices the debugging data, and then compresses the debugging data through Huffman coding.
[0006] Further, the debugging data includes reconfigurable cryptographic algorithm configuration information and intermediate data of cryptographic algorithm operation.
[0007] The reconfigurable cryptographic algorithm configuration information is control information for controlling each operator or each module to execute the functions it possesses on the reconfigurable cryptographic chip.
[0008] The intermediate data of the cryptographic algorithm operation is input data required by each operator operation and output data generated on the reconfigurable cryptographic chip.
[0009] Further, the hierarchical grouping of the debugging data comprises the following steps: grouping the debugging data into three different levels, L1, L2 and L3, on the reconfigurable cryptographic chip; grouping the reconfigurable cryptographic algorithm configuration information in the debugging data into two levels, L1 and L2; and grouping the intermediate data of the cryptographic algorithm operation in the debugging data into L3.
[0010] Further, the debugging data of different levels is grouped into one or more groups according to the cryptographic algorithm, and each group is organized according to a certain format; the debugging data of L1 and L2 levels is grouped, and is also called configuration information table, and each group corresponds to the configuration information of different modules or operators on the cryptographic chip.
[0011] Further, the debugging data of L1 level contains the index of the debugging data grouping of L2 level.
[0012] Further, the data transmission bus width of the reconfigurable cryptographic chip is N=128 bits, and the debugging data is less than or more than N=128 bits, and is filled or spliced to N=128 bits or an integer multiple of N=128 bits.
[0013] The cryptographic algorithm debugging data hierarchical grouping compression method for the reconfigurable cryptographic chip has the following advantages: the debugging data generated by debugging the block cipher algorithm AES and DES, the stream cipher algorithm ZUC and SNOW3G, and the hash cipher algorithm SM3 and MD5 is tested, the data compression rate of the configuration information of the cryptographic algorithm is more than 60% after the hierarchical grouping compression method is used, and the intermediate data compression rate of the cryptographic algorithm is more than 53%. The transmission performance of the debugging data is effectively increased while the storage resource of the debugging data is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1 is the overall structure diagram of the reconfigurable debugging data of the present application;
[0015] Figure 2 is the hierarchical diagram of the reconfigurable debugging data of the present application;
[0016] Figure 3 is the data filling diagram of the configuration information RCU table of the present application;
[0017] Figure 4 is the data filling diagram of the configuration information BFU table, the ROUTE table and the MEM table of the present application;
[0018] Figure 5 is the data splicing diagram of the configuration information BFU table and the ROUTE table of the present application. DETAILED DESCRIPTION
[0019] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides a hierarchical grouping compression method for debugging cryptographic algorithms in reconfigurable cryptographic chips.
[0020] like Figure 1 As shown, a hierarchical grouping compression scheme for debugging data of cryptographic algorithms for reconfigurable cryptographic chips includes: hierarchically grouping the debugging data, padding or splicing the debugging data, and compressing the debugging data through Huffman coding.
[0021] The debugging data includes reconfigurable cryptographic algorithm configuration information and intermediate data from cryptographic algorithm operations. The reconfigurable cryptographic algorithm configuration information refers to the control information on the reconfigurable cryptographic chip that controls each operator or module to perform its functions. The intermediate data from cryptographic algorithm operations refers to the input data required for each operator's operation and the output data generated on the reconfigurable cryptographic chip.
[0022] On a reconfigurable cryptographic chip, debugging data is divided into multiple different levels. The debugging data at different levels corresponds to the configuration information of different operators and modules of the reconfigurable cryptographic chip or the intermediate data of cryptographic algorithm operations.
[0023] In the debugging data at different levels, the configuration information of reconfigurable cryptographic algorithms is divided into one or more groups. Each group is organized according to a certain format, i.e., a configuration information table. Each group corresponds to the configuration information of different modules or operators on the cryptographic chip.
[0024] Debug data at one level can contain indexes of debug data groups at other levels.
[0025] like Figure 2 As shown, the debugging data is divided into three levels. The first level, L1, contains the configuration information of the Reconfigurable Computing Unit (RCU) in the cryptographic chip, as well as the indexes of three configuration information groups. This level of debugging data is denoted as the RCU table. The second level, L2, contains configuration information divided into multiple groups, each containing three parts of information: the BFU table, the ROUTE table, and the MEM table. The third level, L3, contains intermediate data generated during the specific operation of the cryptographic algorithm.
[0026] The configuration information of the basic functional unit (BFU) is recorded in the BFU table; the configuration information of the two basic operators (SBOX and BENES) and the four computing resources (MEM, SREG, OFIFFO, and LFSR) is recorded in the ROUTE table; the interconnection status information of the reconstructed operators in the cryptographic chip and the memory read / write configuration information of the reconstructible array in the reconstructible cryptographic chip are recorded in the MEM table.
[0027] The three configuration information packet indexes in the first level L1 correspond to the respective groups of the second level debugging data.
[0028] The data transmission bus bit width of the reconfigurable cryptographic system is M=128bit, the debugging data bit width is less than N=128bit, is filled to N=128bit, or is filled to a length that can be evenly divided by N=128bit. The debugging data bit width is more than N=128bit, and is filled to an integer multiple of N=128bit.
[0029] For example, for the RCU table with an actual bit width of 214bit, the data bit width is filled to 256bit by adding 0 to the high bit, as shown in the following table. Figure 3 For the 52bit BFU table, the 28bit ROUTE table and the 102bit MEM table contained in the second level debugging data group, they are filled to 64bit, 32bit and 128bit respectively, as shown in the following table. Figure 4
[0030] If the debugging data is still less than N=128bit after filling, multiple filled debugging data need to be spliced to 128bit. As shown in the following table, two groups of 64bit BFU table are spliced to one group of 128bit data, and four groups of 32bit ROUTE table are spliced to one group of 128bit data. Figure 5
[0031] The filled or spliced debugging data is compressed by Huffman coding. In the implementation, the data granularity of the reconfigurable cryptographic algorithm is 32bit, the data of the operator port in the reconfigurable array and the configuration information data of the reconfigurable array are represented in hexadecimal, so when the Huffman coding is used to compress the data of the reconfigurable cryptographic algorithm, the information entropy has at most 16 kinds. As shown in the following table, the compressed debugging data encoding is stored and then transmitted to the host computer through the transmission interface for decompression and debugging. Figure 1
[0032] It can be understood that the present application is described by some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the present application. In addition, under the guidance of the present application, the features and embodiments can be modified to adapt to specific conditions and materials without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the scope of the present application.
Claims
1. A hierarchical grouping compression method for debugging cryptographic algorithms in reconfigurable cryptographic chips, characterized in that, The debug data is hierarchically grouped, then the debug data is filled or spliced, and finally compressed using Huffman coding. Debugging data includes reconfigurable cryptographic algorithm configuration information and intermediate data from cryptographic algorithm operations; The reconfigurable cryptographic algorithm configuration information is: control information on the reconfigurable cryptographic chip that controls each operator or module to perform its functions; The intermediate data for the cryptographic algorithm operation are: the input data required for each operator operation and the output data generated on the reconfigurable cryptographic chip.
2. The hierarchical grouping compression method for cryptographic algorithm debugging data for reconfigurable cryptographic chips according to claim 1, characterized in that, The specific steps for classifying and grouping debugging data include: on the reconfigurable cryptographic chip, the debugging data is divided into three different levels, namely L1, L2, and L3; the reconfigurable cryptographic algorithm configuration information in the debugging data is divided into two levels, namely L1 and L2; and the intermediate data for cryptographic algorithm operations in the debugging data is L3.
3. The hierarchical grouping compression method for cryptographic algorithm debugging data for reconfigurable cryptographic chips according to claim 2, characterized in that, The debugging data at different levels are divided into one or more groups based on the cryptographic algorithm, and each group is organized in a certain format. The debugging data groups at the L1 and L2 levels are also called configuration information tables, and each group corresponds to the configuration information of different modules or operators on the cryptographic chip.
4. The hierarchical grouping compression method for cryptographic algorithm debugging data for reconfigurable cryptographic chips according to claim 2, characterized in that, L1-level debug data contains indexes of L2-level debug data groups.
5. The hierarchical grouping compression method for cryptographic algorithm debugging data for reconfigurable cryptographic chips according to claim 1, characterized in that, The data transmission bus width of the reconfigurable cryptographic chip is N=128 bits. If the debugging data is less than N=128 bits or more than N=128 bits, it is padded or spliced to N=128 bits or an integer multiple of N=128 bits.