Verification Method, System, Device and Storage Medium for Instruction Self-Modification

Abstract

The present disclosure provides a verification method, system, device, and storage medium for self-modifying instructions. The method includes: sending a first request to a secondary cache model module of a backend model module, the first request including a fetch operation request provided by a fetch model module of a frontend model module or a write operation request provided by a first-level data cache module to be tested, and the physical address of the write operation request is used to access the instructions of the secondary cache model module; obtaining a data cache status according to the first request; obtaining a fetch status according to the data cache status, the fetch status including fetch valid or waiting in response to the fetch operation request, or fetch valid or invalid in response to the write operation request; and obtaining a verification result according to the fetch status. The present disclosure verifies whether the data written by the write operation is obtained during instruction fetching by simulating the interaction between the frontend environment and the backend environment of the processor and the first-level data cache module to be tested, and realizes the verification of the correctness of the implementation of the self-modifying instruction function.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method, system, device, and storage medium for verifying self-modifying instructions. Background Art

[0002] With the continuous development of integrated circuit process technology and computer architecture technology, the performance of processors has increased exponentially in the past few decades. Along with this, the design scale and complexity of processors have also increased rapidly. As a result, the difficulty of verification has increased sharply. Due to the very complex architecture and microarchitecture of high-performance processors, effective methods must be adopted for rapid verification to conduct sufficient verification. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for verifying self-modifying instructions, including: sending at least one first request to a secondary cache model module included in a backend model module, where a frontend model module includes an instruction fetch model module and a primary instruction cache model module, and the at least one first request includes at least one instruction fetch operation request provided by the instruction fetch model module or a write operation request provided by a primary data cache module to be tested, and a physical address of the write operation request is configured to access an instruction of the secondary cache model module; obtaining a corresponding data cache state according to each of the at least one first request; obtaining an instruction fetch state according to the data cache state, where the instruction fetch state includes instruction fetch valid or instruction fetch waiting in response to the instruction fetch operation request, or the instruction fetch state includes instruction fetch valid or instruction fetch invalid in response to the write operation request; and obtaining a verification result according to the instruction fetch state.

[0004] For example, in a verification method provided by at least one embodiment of the present disclosure, in response to the at least one first request including the at least one instruction fetch operation request, sending the at least one first request to the secondary cache model module includes: obtaining a virtual address of each of the at least one instruction fetch operation request; obtaining an address memory type and a physical address corresponding to the virtual address to send the at least one instruction fetch operation request to the secondary cache model module.

[0005] For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining a virtual address of each of the at least one instruction fetch operation request includes: constructing an address pool according to an access address of the write operation request; randomly selecting and obtaining a virtual address of each of the at least one instruction fetch operation request from the address pool.

[0006] For example, in a verification method provided by at least one embodiment of the present disclosure, in response to the at least one first request including the at least one fetch operation request, obtaining the corresponding data cache status according to each of the at least one first request includes: obtaining the data cache status based on the physical address of each of the at least one fetch operation requests, where the data cache status includes that the instruction cache is valid; or, obtaining the data cache status based on the physical address of each of the at least one fetch operation requests, where the data cache status includes that the instruction cache is invalid.

[0007] For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining the fetch status according to the data cache status includes: in response to the data cache status including that the instruction cache is valid, the fetch status is configured as fetch valid; in response to the data cache status including that the instruction cache is invalid, the secondary cache model module sends a query request to the primary data cache module to obtain the write request access status corresponding to the physical address of the fetch operation request replied by the primary data cache module, and obtaining the fetch status according to the write request access status.

[0008] For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining the fetch status according to the write request access status includes: in response to the write request access status being non-access, the fetch status is fetch valid; in response to the write request access status being to-be-accessed, the fetch status is fetch waiting.

[0009] For example, in a verification method provided by at least one embodiment of the present disclosure, in response to the write request access status being non-access, obtaining the fetch status according to the write request access status further includes: the secondary cache model module sets the fetch valid status bit.

[0010] For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining the verification result according to the fetch status includes: in response to the fetch status being configured as fetch valid, the front-end model module configures the fetch operation request corresponding to the fetch status as an instruction allowed to be submitted; in response to the fetch status being fetch waiting, the front-end model module waits to be woken up by the secondary cache model module, and the front-end model module blocks the fetch operation of the fetch operation request.

[0011] For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining a verification result according to the fetch status further includes: in response to the waiting time of the front-end model module being greater than a preset time, the front-end model module reports an error; in response to the waiting time of the front-end model module being less than the preset time and the front-end model module obtaining a fetch wake-up signal replied by the secondary cache model module, the fetch model module of the front-end model module resends a fetch operation request to the secondary cache model module according to the fetch wake-up signal.

[0012] For example, in a verification method provided by at least one embodiment of the present disclosure, in response to the at least one first request including the write operation request, sending the at least one first request to the secondary cache model module includes: the write operation request sent to the secondary cache model module includes a cacheable write operation request or a non-cacheable write operation request.

[0013] For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining a corresponding data cache status according to each of the at least one first requests includes: in response to the write operation request including the cacheable write operation request, obtaining the data cache status based on the physical address of the cacheable write operation request, where the data cache status includes a non-cache status of the back-end model module and a cached status of the back-end model module; in response to the write operation request including the non-cacheable write operation request, obtaining the data cache status based on the physical address of the non-cacheable write operation request, where the data cache status includes a non-cache status of the back-end model module.

[0014] For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining a fetch status according to the data cache status includes: in response to the data cache status including the non-cache status of the back-end model module, the secondary cache model module obtains the fetch status by sending a fetch status query request to the front-end model module; in response to the data cache status including the cached status of the back-end model module, the secondary cache model module obtains the fetch status by querying the fetch valid status bit corresponding to the physical address of the write operation request.

[0015] For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining a verification result according to the fetch status includes: in response to the fetch status being fetch valid, controlling the fetch operation request corresponding to the fetch status to be executed again; in response to the fetch status being fetch invalid, the write operation request is executed normally.

[0016] For example, a verification method provided by at least one embodiment of the present disclosure further includes: in response to each of the at least one fetch operation request having completed fetching, for each current fetch operation request among the at least one fetch operation request, checking the consistency between the data of the instruction fetched by the current fetch operation request and the real-time data stored at the physical address of the write operation request.

[0017] At least one embodiment of the present disclosure provides a verification system for verifying instruction self-modification. The verification system is configured to be operatively connected to a first-level data cache module to be tested. The verification system includes: a front-end model module, including a fetch model module and a first-level instruction cache model module, wherein the fetch model module is configured to provide at least one fetch operation request; a back-end model module, including a second-level cache model module, and the second-level cache model module is configured to obtain the at least one fetch operation request or a write operation request provided by the first-level data cache module. The physical address of the write operation request is configured to be used to access an instruction of the second-level cache model module; the second-level cache model module is configured to obtain a data cache state based on the physical address of each of the at least one first request to obtain a fetch state, and the fetch state is configured to be used to obtain a verification result, wherein the fetch state includes fetch valid or fetch waiting in response to the at least one fetch operation request, or the fetch state includes fetch valid or fetch invalid in response to the write operation request.

[0018] At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the verification method as described in any one of the above is implemented.

[0019] At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the verification method as described in any of the above examples is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a flowchart of a verification method for instruction self-modification provided by some embodiments of the present disclosure;

[0022] Figure 2Schematic diagram of a verification system provided by some embodiments of the present disclosure;

[0023] Figure 3 Provided by some embodiments of the present disclosure Figure 1 Flowchart of step S1 therein;

[0024] Figure 4 Provided by some embodiments of the present disclosure Figure 3 Flowchart of step S11 therein;

[0025] Figure 5 Provided by some embodiments of the present disclosure Figure 1 Flowchart of step S3 therein;

[0026] Figures 6 to 7 Flowcharts of a verification method when a fetch operation request is initiated in a front-end model module, respectively, provided by some embodiments of the present disclosure;

[0027] Figure 8 Flowchart of a verification method when a write operation request is initiated in a primary data cache module, provided by some embodiments of the present disclosure; and

[0028] Figure 9 Block diagram of an electronic device provided by some embodiments of the present disclosure. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the embodiments of the present disclosure.

[0031] In the embodiments of the present disclosure, the terms "first", "second" and similar terms do not denote any order, quantity or importance, but are only used to distinguish different components. Similar terms such as "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. Similarly, terms such as "comprising" or "including" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0032] In the embodiments of the present disclosure, flowcharts are used to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the steps before or after do not necessarily need to be carried out precisely in sequence. On the contrary, they can be carried out in reverse order or various steps can be processed simultaneously. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0033] The module test of the Level-1 Data Cache (LSDC) is an important aspect in the verification of high-performance processors. The verification work of the Level-1 Data Cache module is very crucial in the processor design and runs through the entire design process. Currently, the difficulty of verifying the Level-1 Data Cache module is getting higher and higher. For example, when the Level-1 Data Cache module implements more functions, the high-performance requirements of the Level-1 Data Cache module lead to more complex logic, and the higher the integration complexity of the circuit, the greater the complexity and workload of the verification work. Therefore, how to scientifically and effectively verify the Level-1 Data Cache module becomes crucial.

[0034] Self-Modifying Code (SMC) refers to code that modifies itself during program execution. For example, the uses of self-modifying code include making some important jump locations invalid or hiding some important code.

[0035] The inventors of the present disclosure found that for an instruction, it may need to be modified before execution, i.e., instruction modification. Fetching an instruction is a speculative behavior. For example, currently, an old instruction is being executed, but at this time, a very new instruction may have been fetched.

[0036] The inventors of the present disclosure also found that for instruction modification, the data of the instruction can be rewritten through a write operation to achieve instruction modification. In the case where the write operation in a normal program coincides with the subsequent instruction fetch operation, i.e., the write operation changes the stored content by writing data and this stored content is accessed by the subsequent instruction fetch operation, instruction self-modification is achieved, which is also called SMC. This feature of SMC means that the subsequent instruction fetch operation needs to fetch the modified content.

[0037] Thus, SMC is an important feature based on X86 architecture processors. It allows write operations to access the instruction storage space, enabling a program to modify itself. Depending on the data written by the write operation, the subsequent executed instructions will change. The inventors of the present disclosure also found that for SMC, in other processors such as ARM, it is implemented through a series of barrier instructions. Barrier instructions can be used to prevent out-of-order execution of the CPU. For example, a barrier instruction requires that the instructions before it be executed before the subsequent instructions are executed. That is, this solution requires additional instructions to be implemented, but this will bring a series of problems, such as more complex processor design and affected operating efficiency, etc.

[0038] In response to this, at least one embodiment of the present disclosure provides a method for verifying instruction self-modification, including: sending at least one first request to a secondary cache model module included in a backend model module, where the frontend model module includes an instruction fetch model module and a primary instruction cache model module, and the at least one first request includes at least one instruction fetch operation request provided by the instruction fetch model module or a write operation request provided by a primary data cache module to be tested, and the physical address of the write operation request is configured to access the instructions of the secondary cache model module; obtaining the corresponding data cache status according to each of the at least one first request; obtaining an instruction fetch status according to the data cache status, where the instruction fetch status includes instruction fetch valid or instruction fetch waiting in response to an instruction fetch operation request, or the instruction fetch status includes instruction fetch valid or instruction fetch invalid in response to a write operation request; and obtaining a verification result according to the instruction fetch status.

[0039] The verification method of the above embodiments of the present disclosure can accurately verify whether the data written by a write operation is obtained during instruction fetching by simulating the frontend environment and the backend environment and simulating a series of interactions with the primary data cache module to be tested regarding, for example, direct access to the instruction storage space by a write operation, and realizes the verification of instruction self-modification, that is, verifies the correctness of the implementation of the SMC function. In at least one example of the present disclosure, the method for verifying instruction self-modification is applied in the logical code design stage of a chip, which can avoid errors in subsequent production and manufacturing caused by incorrect design of the primary data cache module in the early stage, thereby reducing a large amount of time and money costs.

[0040] Figure 1 It is a flowchart of a method for verifying instruction self-modification provided by some embodiments of the present disclosure. Figure 2 It is a schematic diagram of a verification system for verifying instruction self-modification provided by some embodiments of the present disclosure.

[0041] For example, as Figure 1 shown, the method for verifying instruction self-modification provided by at least one embodiment of the present disclosure includes steps S1 to S4.

[0042] For example, as Figure 2 shown, the verification system 100 for verifying self-modifying verification instructions provided by at least one embodiment of the present disclosure is configured to be operably connected to a first-level data cache module 200 to be tested. The verification system 100 includes a front-end model module (FAKE FE) 110 and a back-end model module (FAKE BE) 120.

[0043] For example, the front-end model module 110 may also be referred to as a processor front-end model module. The front-end model module 110 is configured to simulate the front-end simulation environment of the first-level cache, such as for simulating instruction fetching, interaction simulation, and instruction submission, etc. The back-end model module 120 may also be referred to as a processor back-end model module. The back-end model module 120 is configured to simulate the back-end simulation environment of the first-level cache, such as for responsible for backfill, listening, etc.

[0044] For example, as Figure 2 shown, the front-end model module 110 includes an instruction fetching model module 111 and a first-level instruction cache model module 112. The back-end model module 120 includes a second-level cache model module 121. The instruction fetching model module 111 is configured to simulate an instruction fetching module, such as configured to simulate related behaviors such as instruction fetching. The first-level instruction cache model module 112 is configured to simulate a first-level instruction cache module. The second-level cache model module 121 is configured to simulate a second-level cache module.

[0045] It should be noted that since the front-end model module 110 is not the focus to be described in the embodiments of the present disclosure, for the clarity and conciseness of the embodiments of the present disclosure, the embodiments of the present disclosure omit the related content such as the specific composition of the front-end model module 110. Those skilled in the art can know the related content of the front-end model module 110 according to the relevant descriptions in this article and the background technology in this field. For example, the front-end model module 110 may further include a decoding module, etc., which will not be elaborated in the embodiments of the present disclosure.

[0046] The verification method provided by some embodiments of the present disclosure includes steps S1 to S4 as described below.

[0047] Step S1: Send at least one first request to the second-level cache model module 121 included in the back-end model module 120. For example, for step S1, at least one first request includes at least one instruction fetching operation request A1 provided by the instruction fetching model module 111 or a write operation request B1 provided by the first-level data cache module 200 to be tested. The physical address of the write operation request B1 is configured as an instruction for accessing the second-level cache model module 121, that is, the write operation request B1 can access the instruction storage space.

[0048] Step S2: Obtain the corresponding data cache status according to each of the at least one first request.

[0049] Step S3: Obtain the instruction fetch status according to the data cache status, where the instruction fetch status includes instruction fetch valid or instruction fetch waiting in response to the instruction fetch operation request A1, or the instruction fetch status includes instruction fetch valid or instruction fetch invalid in response to the write operation request B1.

[0050] Step S4: Obtain the verification result according to the instruction fetch status.

[0051] In some examples, in step S3, the instruction fetch valid in response to the instruction fetch operation request A1 means that there is no write operation accessing or about to access the data at the physical address corresponding to the instruction fetch, and thus the instruction can be directly fetched. The instruction fetch waiting in response to the instruction fetch operation request A1 means that there is a write operation accessing or about to access the data at the physical address corresponding to the instruction fetch. The instruction fetch valid in response to the write operation request B1 means that the instruction data at the relevant physical address has been fetched when the write operation request is written, and the instruction fetch invalid in response to the write operation request B1 means that the instruction data at the relevant physical address has not been fetched when the write operation request is written.

[0052] In the verification system 100 for verifying instruction self-modification provided in some embodiments of the present disclosure, the instruction fetch model module 111 is configured to provide at least one instruction fetch operation request A1. The secondary cache model module 121 is configured to obtain at least one first request. For example, the secondary cache model module 121 is configured to obtain the at least one instruction fetch operation request A1 or the write operation request B1 provided by the primary data cache module 200. The physical address of the write operation request B1 is configured to be used to access the instruction of the secondary cache model module 121. The secondary cache model module 121 is configured to obtain the data cache status based on the physical address of each of the at least one first requests to obtain the instruction fetch status. The instruction fetch status is configured to be used to obtain the verification result. For example, the instruction fetch status includes instruction fetch valid or instruction fetch waiting in response to at least one instruction fetch operation request A1, or the instruction fetch status includes instruction fetch valid or instruction fetch invalid in response to the write operation request B1.

[0053] The verification method or system of the embodiments of the present disclosure verifies whether the latest written data of the write operation is obtained when fetching an instruction by simulating a series of interactions between the front-end environment and the back-end model, as well as simulating and the to-be-tested primary data cache module regarding, for example, the write operation directly accessing the instruction storage space, and can verify the correctness of the SMC function implementation.

[0054] Figure 3 For some embodiments provided by the present disclosure Figure 1 The flowchart of step S1.

[0055] For example, as Figure 3 shown, in response to at least one first request including at least one instruction fetch operation request A1 provided by the instruction fetch model module 111, step S1 includes step S11 and step S12.

[0056] Step S11: Obtain the virtual address (VA) of each of at least one fetch operation request A1.

[0057] Step S12: Obtain the address memory type (Memtype) and physical address (PA) corresponding to the virtual address, so as to send at least one fetch operation request A1 to the secondary cache model module 121.

[0058] In the embodiments of the present disclosure, the virtual address is converted to obtain the physical address, which is safer and can also reduce the burden on the system. Moreover, the address memory type is obtained through the virtual address, which is convenient for verification.

[0059] Figure 4 For some embodiments of the present disclosure Figure 3 is the flowchart of step S11.

[0060] For example, as Figure 4 shown, step S11 includes step S111 and step S112.

[0061] Step S111: Construct an address pool according to the access address of the write operation request B1. For example, for step S111, the access address of the write operation request B1 includes the addresses that the write operation request B1 has accessed.

[0062] Step S112: Randomly select and obtain the virtual address of each of at least one fetch operation request A1 from the address pool.

[0063] In the embodiments of the present disclosure, the virtual address of the fetch operation request is obtained according to the address that the write operation request has accessed, which can make the address of the fetch operation request and the address of the write operation request more likely to be relevant, improve the SMC probability, and is convenient for verification.

[0064] In some examples, after the front-end model module 110 sends the fetch operation request A1 for step S1, the fetch result is first recorded as waiting for backfill.

[0065] In some examples, in response to at least one first request including at least one fetch operation request A1 provided by the fetch model module 111, step S2 includes: obtaining the data cache status based on the physical address of each fetch operation request A1, and the data cache status includes that the instruction cache is valid. The instruction cache being valid means that the instruction corresponding to the physical address exists in the primary instruction cache. For example, the instruction cache being valid means that the instruction corresponding to the physical address exists in Figure 2 the primary instruction cache model module 120.

[0066] In some examples, the secondary cache model module 121 records identification bits to identify whether the instruction or data corresponding to the physical address is in the primary instruction cache or the primary data cache. This is merely exemplary and not a limitation of the present disclosure. For example, the secondary cache model module 121 is provided with an instruction cache valid bit to identify whether the instruction corresponding to the physical address is in the primary instruction cache, so as to facilitate the acquisition or identification of the data cache state.

[0067] In other examples, in response to at least one first request including at least one fetch operation request A1 provided by the fetch model module 111, step S2 includes: obtaining the data cache state based on the physical address of each fetch operation request A1, and the data cache state includes an invalid instruction cache. An invalid instruction cache indicates that the instruction corresponding to the physical address is not in the primary instruction cache. For example, an invalid instruction cache indicates that the instruction corresponding to the physical address is not in Figure 2 the primary instruction cache model module 120.

[0068] The embodiments of the present disclosure can know whether an instruction exists in the primary instruction cache through the physical address of the fetch operation request initiated by the front-end model module. The verification method of the embodiments of the present disclosure can cover the verification scenarios of both valid instruction cache and invalid instruction cache, with relatively comprehensive verification and good universality.

[0069] In some examples, for step S3, when the above data cache state includes a valid instruction cache, the fetch state is configured to be fetch valid.

[0070] Figure 5 For some embodiments of the present disclosure Figure 1 is the flowchart of step S3.

[0071] For example, as Figure 5 shown, when the above data cache state includes an invalid instruction cache, step S3 includes step S31 and step S32.

[0072] Step S31: The secondary cache model module 121 sends a query request B2 to the primary data cache module 200 to obtain the write request access state corresponding to the physical address of the fetch operation request replied by the primary data cache module 200, that is, the primary data cache module 200 gives a corresponding reply according to whether the instruction data corresponding to the physical address needs to be used.

[0073] Step S32: Obtain the fetch state according to the write request access state.

[0074] For example, in step S31, the write request access status indicates whether the instruction data corresponding to the physical address needs to be used by the first-level data cache module, that is, whether there is a write operation request issued by the first-level data cache module accessing the instruction data corresponding to the physical address or the first-level data cache module is about to issue a write operation request to access the instruction data corresponding to the physical address.

[0075] The embodiments of the present disclosure can verify various scenarios where there is no write operation and there is an operation access when fetching an instruction according to the instruction fetch operation request initiated by the front-end model module, so as to realize the verification of whether the relevant address obtains the latest data written by the write operation when fetching an instruction.

[0076] In some examples, for step S32, when the write request access status is non-access, the fetch status is fetch valid. For example, non-access means that there is no write operation request accessing or about to access the data corresponding to the physical address. In this way, the embodiments of the present disclosure can verify whether the latest data after the write operation is fetched when there is no write operation at the corresponding address during instruction fetching, so as to verify the correctness of the SMC function implementation.

[0077] In some examples, for step S32, when the write request access status is access required, the fetch status is fetch waiting. For example, access required means that there is a write operation request accessing or about to access the data corresponding to the physical address. In this way, the verification method of the embodiments of the present disclosure covers the verification scenario of whether the fetch is successfully released after being blocked when there is a write operation at the corresponding address during instruction fetching.

[0078] In some examples, the physical address of the above write operation request B1 is configured to access the instruction of the second-level cache model module 121, that is, it means that the write operation request B1 can access the instruction storage space to rewrite the instruction data, so that the corresponding instruction can be modified. For example, rewriting the instruction data includes rewriting the operation code and / or operands of the instruction, etc. Of course, this is only exemplary and not a limitation of the present disclosure. In some examples, the physical address of the write operation request and the physical address of the instruction fetch operation request in the embodiments of the present disclosure correspond one by one, that is, they can match, so as to implement the SMC function.

[0079] In some examples, when the write request access status in step S31 is non-access and the fetch status is configured to be fetch valid, step S4 includes the following steps or processes: the front-end model module 110 configures the instruction fetch operation request A1 corresponding to the fetch status as instruction submission allowed. This enables smooth instruction fetching when there is no write operation access at the corresponding address during instruction fetching to check whether the fetched data is correct.

[0080] In some examples, when the write request access status in step S4 is non-access and the fetch status is configured to be fetch-valid, for step S4, the secondary cache model module 121 of the backend model 120 sends a fetch status reply signal A2 to the frontend model module 110, that is, the backend model 120 replies to the frontend model module 110 that the fetch is successful, so that the frontend model module 110 records the fetch result as successful according to the fetch status reply signal A2. Therefore, when the fetch is successful, the frontend model module 110 configures the corresponding fetch operation request as an instruction allowing submission, so that the instruction can be submitted smoothly, that is, the fetch is successful. The fetch status reply signal A2 can represent a signal corresponding to the fetch status being fetch-valid, and it has an address that matches the fetch operation request one by one. Since this is not the focus of the description of the embodiments of the present disclosure, it will not be elaborated here.

[0081] In some examples, when the write request access status in step S31 is non-access, step S32 further includes the following steps or processes: The secondary cache model module 121 sets the fetch-valid status bit. The fetch-valid status bit is a status bit in the secondary cache model module 121, indicating that the instruction data corresponding to the physical address has been fetched.

[0082] In this way, the embodiments of the present disclosure can know whether the instruction data at the relevant address has been fetched by setting the fetch-valid status bit, which is convenient for querying whether the SMC is dangerous when the write operation request accesses the secondary cache model module.

[0083] In some examples, for step S4, when the write request access status in step S31 is access required and the fetch status is fetch waiting, that is, at this time there is a write operation request accessing or about to access the data corresponding to the physical address, the backend model 120 does not reply to the frontend model module 110 that the fetch is successful, but makes the frontend model module 110 wait, so that the fetch is performed after the write operation request finishes writing the data.

[0084] In some examples, when the write request access status in step S31 is access required and the fetch status is fetch waiting, step S4 includes the following steps or processes: The frontend model module 110 waits to be woken up by the secondary cache model module 121, and the frontend model module 110 blocks the fetch operation of the fetch operation request A1.

[0085] In some examples, when the write request access status is to be accessed and the fetch status is fetch waiting, for step S4, the secondary cache model module 121 of the backend model 120 does not reply to the frontend model module 110 and makes the frontend model module 110 wait, that is, the frontend model module 110 waits to be woken up by the secondary cache model module 121 so that fetching can be performed after the write operation request finishes writing the data. This is merely exemplary and not a limitation of the present disclosure. For example, embodiments of the present disclosure can also achieve the fetch waiting of the frontend model module 110 through other reasonable means. For example, the secondary cache model module 121 of the backend model 120 can also send a reply signal corresponding to fetch waiting to the frontend model module 110 to make the frontend model module 110 wait. Embodiments of the present disclosure will not elaborate on this.

[0086] Thus, embodiments of the present disclosure can stop subsequent fetch operations to block fetching when the current instruction does not receive a reply of successful fetch from the secondary cache model module, facilitating the verification of the scenario of whether the blocked fetch is successfully released.

[0087] In some examples, when the write request access status is to be accessed and the fetch status is fetch waiting, for step S4, if the waiting time of the frontend model module 110 is greater than the preset time, that is, it does not receive a wake-up response for a long time, the frontend model module 110 reports an error.

[0088] In other examples, when the write request access status is to be accessed and the fetch status is fetch waiting, for step S4, if the waiting time of the frontend model module 110 is less than the preset time and the frontend model module 110 obtains the fetch wake-up signal replied by the secondary cache model module 121, that is, the backend model 120 wakes up the frontend model module 110, the fetch model module 111 of the frontend model module 110 resends a fetch operation request to the secondary cache model module 121 according to the fetch wake-up signal, that is, cancels the block after the write operation request of the primary data cache module 200 finishes writing the data.

[0089] For example, the preset time is set in advance and can be set according to experience. Embodiments of the present disclosure do not limit this, and it can be adjusted accordingly according to different situations. Details are not elaborated here.

[0090] Figures 6 to 7 Respectively, they are flowcharts of a verification method provided by some embodiments of the present disclosure when the frontend model module initiates a fetch operation request.

[0091] For example, as Figure 2 and Figure 6 shown, the verification method provided by some embodiments of the present disclosure includes steps T1 to T4.

[0092] Step T1: Send at least one fetch operation request A1 to the secondary cache model module 121.

[0093] Step T2: Based on the physical address of each of the at least one fetch operation request A1 in Step T1, obtain the corresponding data cache status, where the data cache status includes instruction cache valid.

[0094] Step T3: Configure the fetch status as fetch valid.

[0095] Step T4: The front-end model module 110 configures the fetch operation request A1 corresponding to the fetch status as instruction submission allowed.

[0096] Thus, the test scenarios covered by the verification method of the embodiments of the present disclosure include that when fetching instructions, there is no write operation at the corresponding address, and the instructions can be fetched smoothly to check whether the fetched data is correct.

[0097] For example, as Figure 2 and Figure 7 shown, the verification method provided by some embodiments of the present disclosure includes Step P1 to Step P7.

[0098] Step P1: Send at least one fetch operation request A1 to the secondary cache model module 121.

[0099] Step P2: Based on the physical address of each of the at least one fetch operation request A1 in Step P1, obtain the corresponding data cache status, where the data cache status includes instruction cache invalid.

[0100] Step P3: Configure the fetch status as fetch waiting.

[0101] Step P4: The front-end model module 110 waits to be woken up by the secondary cache model module 121, and the front-end model module 110 blocks the fetch operation of the fetch operation request A1.

[0102] Step P5: Compare and determine whether the waiting time of the front-end model module 110 is greater than the preset time: if so, that is, if the wake-up response cannot be obtained for a long time, go to Step P6; if not, that is, if the front-end model module 110 is woken up by the back-end model module 120 within the preset time, go to Step P7.

[0103] Step P6: The front-end model module 110 reports an error.

[0104] Step P7: The fetch model module 111 of the front-end model module 110 resends the fetch operation request to the secondary cache model module 121 according to the fetch wake-up signal.

[0105] Accordingly, the embodiments of the present disclosure can verify that when there is a write operation at the corresponding address during instruction fetching, subsequent fetching operations are stopped to block fetching, thereby verifying the correctness of the blocked fetching operation.

[0106] In some examples, in response to at least one first request including a write operation request B1 provided by the first-level data cache module 200, step S1 includes the following steps or processes: The write operation request B1 sent to the secondary cache model module 121 includes a cacheable write operation request or a non-cacheable write operation request. A cacheable write operation request represents a write operation that accesses the cache, and a non-cacheable write operation request represents a write operation that cannot be written to the cache but is directly written to the main memory.

[0107] In some examples, in response to the write operation request B1 including a cacheable write operation request, step S2 includes the following steps or processes: Obtain the data cache status based on the physical address of the cacheable write operation request. The data cache status includes the non-cache status of the backend model module and the cached status of the backend model module.

[0108] In other examples, in response to the write operation request B1 including a non-cacheable write operation request, step S2 includes the following steps or processes: Obtain the data cache status based on the physical address of the non-cacheable write operation request. The data cache status includes the non-cache status of the backend model module.

[0109] Accordingly, the embodiments of the present disclosure can know whether an instruction exists in the secondary cache through the physical address of the write operation request initiated by the backend model module. The verification method of the embodiments of the present disclosure can cover the verification scenarios of the non-cache status and the cached status of the backend model module, with relatively comprehensive verification and good universality.

[0110] It should be noted that the non-cache status of the backend model module means not being cached in the secondary cache model module 121 of the backend model, and the cached status of the backend model module means being cached in the secondary cache model module 121 of the backend model. It should also be noted that since the non-cacheable write operation request is a write operation that cannot be written to the cache but is directly written to the main memory, when the write operation request B1 includes a non-cacheable write operation request, the data cache status can be directly regarded as the non-cache status of the backend model module.

[0111] In some examples, when the data cache status includes the non-cache status of the backend model module, the secondary cache model module 121 sends a fetch status query request to the frontend model module 110 to obtain the fetch status, that is, to check whether the instruction data corresponding to the physical address of the write operation request B1 has been fetched.

[0112] In some other examples, when the data cache status includes the status that the backend model module has cached, the secondary cache model module 121 queries the fetch valid status bit corresponding to the physical address of the write operation request B1 to obtain the fetch status, that is, to check whether the instruction data corresponding to the physical address of the write operation request B1 has been fetched.

[0113] Embodiments of the present disclosure can verify various scenarios of whether the data at the relevant address has been fetched when writing according to the write operation request initiated by the backend model module, so as to implement the verification of the fetch status query related to SMC.

[0114] In some examples, for step S4, when the fetch status is that the fetch is valid in response to the write operation request B1, that is, it is known that the instruction data corresponding to the physical address of the write operation request B1 has been fetched, then it is necessary to reply SMC Dangerous to the primary data cache module 200, that is, report an exception. Therefore, it is necessary to control the fetch operation request corresponding to this fetch status to re-execute the fetch.

[0115] In some examples, for step S4, when the fetch status is that the fetch is invalid in response to the write operation request B1, that is, it is known that the instruction data corresponding to the physical address of the write operation request B1 has not been fetched, then it is necessary to reply that SMC is not dangerous to the primary data cache module 200. Therefore, the write operation request B1 is executed normally.

[0116] Embodiments of the present disclosure query the fetch status based on the write operation request and thereby know whether SMC is dangerous, so that the fetch can be re-executed in case of an exception, enabling the program to execute normally.

[0117] For example, SMC dangerous can be represented by SMC Danger = 1 and SMC not dangerous can be represented by SMC Danger = 0. For example, when SMC Danger = 1, it means that the instruction data at the relevant physical address has been fetched when the write operation request is written, and when SMC Danger = 0, it means that the instruction data at the relevant physical address has not been fetched when the write operation request is written. This is merely exemplary and not a limitation of the present disclosure.

[0118] In some examples, the verification method of the embodiments of the present disclosure further includes the following steps or processes: when the fetch operation request A1 has completed fetching, that is, when the instruction is committed, clear the instruction cache valid bit and / or the fetch valid status bit set by the backend model module 120 to release the storage space of the backend model module 120.

[0119] In some examples, the verification method of the embodiments of the present disclosure further includes: when each fetch operation request has completed fetching, for each current fetch operation request in at least one fetch operation request, checking the consistency between the data of the instruction fetched by the current fetch operation request A1 and the real-time data stored at the physical address of the write operation request B1, so as to verify the correctness of the fetched data.

[0120] For example, some embodiments of the present disclosure can check the consistency between the data of the instruction fetched by the current fetch operation request and the real-time data stored at the physical address of the write operation request through the data checker MPMM. This is merely exemplary and not a limitation of the present disclosure.

[0121] Thus, the embodiments of the present disclosure can test whether the first-level data cache module 200 correctly queries the fetch status of the SMC.

[0122] Figure 8 It is a flowchart of a verification method provided for some embodiments of the present disclosure when a write operation request is initiated in the first-level data cache module.

[0123] For example, as Figure 2 and Figure 8 shown, the verification method provided for some embodiments of the present disclosure includes steps Q1 to step Q9.

[0124] Step Q1: Send a write operation request B1 to the secondary cache model module 121.

[0125] Step Q2: Determine whether the write operation request B1 is a cacheable write operation request. If so, go to step Q3; if not, go to step Q5.

[0126] Step Q3: Obtain the data cache status based on the physical address of the cacheable write operation request, and continue to execute step Q4.

[0127] Step Q4: Determine whether the data cache status is a non-cache status of the backend model module. If so, go to step Q5; if not, go to step Q6.

[0128] Step Q5: The secondary cache model module 121 sends a fetch status query request to the frontend model module 110 to obtain the fetch status, and continue to execute step Q7.

[0129] Step Q6: The secondary cache model module 121 obtains the fetch status by querying the fetch valid status bit corresponding to the physical address of the write operation request B1, and continue to execute step Q7.

[0130] Step Q7: Determine whether the fetch status is fetch valid. If so, go to step Q8; if not, go to step Q9.

[0131] Step Q8: Reply to the primary data cache module 200 that SMC is dangerous, report the anomaly, and control the fetch operation request corresponding to the fetch status to be executed again.

[0132] Step Q9: Reply to the primary data cache module 200 that SMC is not dangerous, and the write operation request B1 is executed normally.

[0133] Thus, the embodiments of the present disclosure can verify various scenarios where the data at the relevant address has been fetched during the write operation, thereby realizing the verification of the fetch status query related to SMC.

[0134] It should be noted that, for the sake of clarity and conciseness of this article, the specific implementation manners and technical effects of the verification system 100 for verifying instruction self-modification can refer to the relevant descriptions of the instruction self-modification verification method provided in the above embodiments of the present disclosure, which will not be elaborated here.

[0135] It should be noted that, in the embodiments of the present disclosure, the verification system 100 may include more or fewer modules, and the connection relationships between the various modules are not limited and can be determined according to actual needs. The specific composition manners of the various modules are not limited. Each of the above modules can be configured to be software, hardware, firmware, or any combination of the above to execute specific functions. For example, these modules can correspond to dedicated integrated circuits, or pure software code, or modules combining software and hardware.

[0136] It should also be noted that although the verification system for verifying instruction self-modification is divided into modules for respectively executing corresponding processes above, however, those skilled in the art are aware that the processes executed by each module can also be executed without any specific module division in the random system or without a clear demarcation between the various modules.

[0137] Figure 9 This is a schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure. The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 9 The illustrated electronic device is only an example and should not impose any limitations on the functions and usage scopes of the embodiments of the present disclosure.

[0138] For example, as Figure 9As shown, in some examples, the electronic device 200 includes a processing device (such as a central processing unit, a graphics processing unit, etc.) 201, which can execute the verification method as described above according to a program stored in a read-only memory (ROM) 202 or a program loaded from a storage device 208 into a random access memory (RAM) 203. In the RAM 203, various programs and data required for the operation of the computer system are also stored. The processing device 201, the ROM 202, and the RAM 203 are connected to each other through a bus 204. An input / output (I / O) interface 205 is also connected to the bus 204.

[0139] For example, the following components may be connected to the I / O interface 205: an input device 206 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 207 including, such as a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 208 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 209 including a network interface card such as a LAN card, a modem, etc. The communication device 209 can allow the electronic device 200 to communicate with other devices wirelessly or wiredly to exchange data and perform communication processing via a network such as the Internet. A driver 210 is also connected to the I / O interface 205 as needed. A removable medium 211, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the driver 210 as needed so that a computer program read from it can be installed into the storage device 209 as needed. Although Figure 9 an electronic device 200 including various devices is shown, it should be understood that it is not required to implement or include all the shown devices. More or fewer devices may be alternatively implemented or included.

[0140] For example, the electronic device 200 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 209 may communicate with the network and other devices through wireless communication. The network may be, for example, the Internet, an intranet, and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication may use any one of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), WiMAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0141] For example, the electronic device may be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or may be any combination of an electronic device and hardware. The embodiments of the present disclosure are not limited thereto.

[0142] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart may be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium. The computer program includes program code for performing the method shown in the flowchart. In such an embodiment, the computer program may be downloaded and installed from the network through the communication device 209, or installed from the storage device 208, or installed from the ROM 202. When the computer program is executed by the processing device 201, the above-described verification function for derivation defined in the method of the embodiment of the present disclosure is executed.

[0143] It should be noted that the above-mentioned computer-readable medium in the present disclosure may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In an embodiment of the present disclosure, the computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, and this computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0144] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (for example, a communication network). Examples of communication networks include local area networks ("LAN"), wide area networks ("WAN"), the Internet (for example, the Internet), and end-to-end networks (for example, ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0145] The above-mentioned computer-readable medium may be included in the above-mentioned electronic device; or it may exist separately and not be assembled into the electronic device.

[0146] It should be noted that in the embodiments of the present disclosure, for the specific functions and technical effects of the electronic device 200, reference may be made to the description of the instruction self-modification verification method in the above text, and details are not described herein again.

[0147] The following points need to be noted:

[0148] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0149] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0150] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A verification method for instruction self - modification, comprising: Sending at least one first request to a secondary cache model module included in a backend model module, wherein a frontend model module includes an instruction fetch model module and a primary instruction cache model module, and the at least one first request includes at least one instruction fetch operation request provided by the instruction fetch model module or a write operation request provided by a primary data cache module to be tested, and a physical address of the write operation request is configured to be used to access an instruction of the secondary cache model module; Obtaining a corresponding data cache status according to each of the at least one first request; Obtaining an instruction fetch status according to the data cache status, wherein the instruction fetch status includes instruction fetch valid or instruction fetch waiting in response to the instruction fetch operation request, or the instruction fetch status includes instruction fetch valid or instruction fetch invalid in response to the write operation request; Obtaining a verification result according to the instruction fetch status.

2. The verification method according to claim 1, wherein In response to the at least one first request including the at least one instruction fetch operation request, sending the at least one first request to the secondary cache model module includes: Obtaining a virtual address of each of the at least one instruction fetch operation request; Obtaining an address memory type and a physical address corresponding to the virtual address to send the at least one instruction fetch operation request to the secondary cache model module.

3. The verification method according to claim 2, wherein, Obtaining a virtual address of each of the at least one instruction fetch operation request includes: Constructing an address pool according to an access address of the write operation request; Randomly selecting and obtaining a virtual address of each of the at least one instruction fetch operation request from the address pool.

4. The verification method according to any one of claims 1 to 3, wherein, In response to the at least one first request including the at least one instruction fetch operation request, obtaining a corresponding data cache status according to each of the at least one first request includes: Based on a physical address of each of the at least one instruction fetch operation request, obtaining the data cache status, and the data cache status includes instruction cache valid; or Based on a physical address of each of the at least one instruction fetch operation request, obtaining the data cache status, and the data cache status includes instruction cache invalid.

5. The verification method according to claim 4, wherein, Obtaining an instruction fetch status according to the data cache status includes: In response to the data cache status including the instruction cache valid, the instruction fetch status is configured to be instruction fetch valid; In response to the data cache status including the instruction cache invalid, the secondary cache model module sends a query request to the primary data cache module to obtain a write request access status corresponding to a physical address of the instruction fetch operation request replied by the primary data cache module, and obtaining the instruction fetch status according to the write request access status.

6. The verification method according to claim 5, wherein, Obtaining the instruction fetch status according to the write request access status includes: In response to the write request access status being non - access, the instruction fetch status is instruction fetch valid; In response to the write request access status being to - be - accessed, the instruction fetch status is instruction fetch waiting.

7. The verification method according to claim 6, wherein, In response to the write request access status being non - access, obtaining the instruction fetch status according to the write request access status further includes: The secondary cache model module sets an instruction fetch valid status bit.

8. The verification method according to claim 5 or 6, wherein, Obtaining a verification result according to the instruction fetch status includes: In response to the fetch status being configured as fetch valid, the front-end model module configures the fetch operation request corresponding to the fetch status as an instruction permission to submit. In response to the fetch status being fetch waiting, the front-end model module waits to be woken up by the secondary cache model module, and the front-end model module blocks the fetch operation of the fetch operation request.

9. The verification method according to claim 8, wherein, Obtaining the verification result according to the fetch status further includes: In response to the waiting time of the front-end model module being greater than the preset time, the front-end model module reports an error. In response to the waiting time of the front-end model module being less than the preset time and the front-end model module obtaining the fetch wake-up signal replied by the secondary cache model module, the fetch model module of the front-end model module resends the fetch operation request to the secondary cache model module according to the fetch wake-up signal.

10. The verification method according to claim 1, wherein, In response to the at least one first request including the write operation request, sending the at least one first request to the secondary cache model module includes: The write operation request sent to the secondary cache model module includes a cacheable write operation request or a non-cacheable write operation request.

11. The verification method according to claim 10, wherein, Obtaining the corresponding data cache status according to each of the at least one first request includes: In response to the write operation request including the cacheable write operation request, obtaining the data cache status based on the physical address of the cacheable write operation request, where the data cache status includes the non-cache status of the back-end model module and the cached status of the back-end model module. In response to the write operation request including the non-cacheable write operation request, obtaining the data cache status based on the physical address of the non-cacheable write operation request, where the data cache status includes the non-cache status of the back-end model module.

12. The verification method according to claim 11, wherein, Obtaining the fetch status according to the data cache status includes: In response to the data cache status including the non-cache status of the back-end model module, the secondary cache model module obtains the fetch status by sending a fetch status query request to the front-end model module. In response to the data cache status including the cached status of the back-end model module, the secondary cache model module obtains the fetch status by querying the fetch valid status bit corresponding to the physical address of the write operation request.

13. The verification method according to claim 12, wherein, Obtaining the verification result according to the fetch status includes: In response to the fetch status being fetch valid, controlling the fetch operation request corresponding to the fetch status to be re-executed. In response to the fetch status being fetch invalid, the write operation request is executed normally.

14. The verification method according to claim 1, further includes: In response to each of the at least one fetch operation requests having completed fetching, for each current fetch operation request in the at least one fetch operation requests, checking the consistency between the data of the instruction fetched by the current fetch operation request and the real-time data stored at the physical address of the write operation request.

15. A verification system for verifying instruction self-modification, the verification system being configured to work in connection with a first-level data cache module to be tested, the verification system includes: The front-end model module includes an instruction fetch model module and a first-level instruction cache model module. Among them, the instruction fetch model module is configured to provide at least one instruction fetch operation request; The back-end model module includes a second-level cache model module, and the second-level cache model module is configured to obtain the at least one instruction fetch operation request or the write operation request provided by the first-level data cache module. The physical address of the write operation request is configured to be used to access the instruction of the second-level cache model module; the second-level cache model module is configured to obtain the data cache status based on the physical address of each of the at least one first request to obtain the instruction fetch status, and the instruction fetch status is configured to be used to obtain the verification result. Among them, the instruction fetch status includes instruction fetch valid or instruction fetch waiting in response to the at least one instruction fetch operation request, or the instruction fetch status includes instruction fetch valid or instruction fetch invalid in response to the write operation request.

16. An electronic device, comprising: A processor and a memory, Among them, a computer program is stored on the memory, and when the computer program is executed by the processor, the verification method described in any one of claims 1 to 14 is implemented.

17. A computer-readable storage medium, wherein, A computer program is stored in the storage medium, and when the computer program is executed by the processor, the verification method described in any one of claims 1 to 14 is implemented.

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