A SiC MOSFET signal input end bidirectional full-port electrostatic protection module and a preparation method thereof

Abstract

The application discloses a SiC MOSFET signal input end bidirectional full-port electrostatic protection module, which comprises a SiC epitaxial region and a SiC substrate, a drain back gold, a side wall polysilicon, a side wall-free polysilicon gate, a source lead-out metal and a gate connection metal, the SiC epitaxial wafer is prepared by a standard SiC MOSFET process, and the SiC epitaxial wafer comprises a SiC substrate and a doped SiC epitaxial region above the SiC substrate, wherein the SiC epitaxial region comprises a SiC N-drift region, a SiC NSL current diffusion layer, a JFET region, a Pwell region, a Pbase region, a P++ region, an electric field advance termination N++ region, an ohmic contact injection N++ region and a gate connection injection N++ region. The application constructs a bidirectional full-port electrostatic protection device for a SiC MOSFET signal input end, and forms full-port protection for four types of electrostatic impacts, i.e., positive and negative electrostatic charges of a gate-source and positive and negative electrostatic charges of a gate-drain.

Description

TECHNICAL FIELD

[0001] The present application relates to microelectronic technology, in particular to a SiC MOSFET signal input end bidirectional full-port electrostatic protection module and a preparation method. BACKGROUND

[0002] Silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) is a unipolar device with an insulated gate structure, and it is predicted that by 2025, SiC MOSFET will be used as a main power device in more than 50% of electric vehicle power systems, vehicle chargers and DC / DC converters.

[0003] The obvious feature of SiC MOSFET in structure is that it has an insulating gate composed of oxide (usually SiO2) or high-K dielectric. The application of the insulating gate makes SiC MOSFET a common off-type voltage-controlled device, which is more convenient when used as a power switch, makes the entire power module more safe and reliable, and is more compatible with silicon-based component circuit design and thus easier to design and use. However, in addition to the above advantages, the insulating gate structure brings a serious problem, that is, the insulating gate structure is very fragile and easily damaged by various electric stresses.

[0004] With the rapid development of science and technology, the wide application of microelectronic technology and the increasingly complex electromagnetic environment, more and more attention is paid to the electromagnetic field effects of electrostatic discharge such as electromagnetic interference (EMI) and electromagnetic compatibility (EMC). Static electricity is a kind of electric energy, which exists on the surface of an object and is a phenomenon caused by the local imbalance of positive and negative charges. Static electricity is the general term for the phenomena exhibited during the generation and disappearance of electric charges. When the energy of the static electric field reaches a certain level, the phenomenon of discharge caused by the breakdown of the medium between the electrodes is called electrostatic discharge.

[0005] SiC MOSFET, like other electronic components, also faces the problem of failure under electrostatic impact. Whether using the conventional silicon oxide gate technology or the advanced high-K gate technology, the signal input end of SiC MOSFET is easily damaged by electrostatic impact and cannot be reversed. Considering that SiC MOSFET is still a high-value power device, the reinforcement of the electrostatic protection reliability of SiC MOSFET, especially the prevention of electrostatic breakdown and burning of SiC MOSFET gate dielectric, has practical application significance and economic value.

[0006] At present, the general scheme is to carry out electrostatic reinforcement by implanting TVS anti-static tube and the like at the exposed port of the SiC MOSFET module in the packaging stage. This method has two disadvantages, one is high cost, the packaging cost and the TVS anti-static tube cost are very obvious; the other disadvantage is that it cannot avoid the static damage received in the storage, transportation, assembly and the like during the long period from the scribing to the end of the packaging. SUMMARY

[0007] In view of the problems in the prior art, the present application provides a SiC MOSFET signal input end bidirectional full-port electrostatic protection module and a preparation method, which are constructed in consideration of process compatibility, development verification difficulty and production cost while preparing the SiC MOSFET, and form a full-port protection SiC MOSFET signal input end bidirectional full-port electrostatic protection module and a preparation method for four types of electrostatic impact of gate-source positive and negative electrostatic charges and gate-drain positive and negative electrostatic charges.

[0008] The object of the present application is achieved by the following technical solutions.

[0009] A SiC MOSFET signal input end bidirectional full-port electrostatic protection module, comprising a SiC epitaxial region and a SiC substrate, a drain back gold, a side wall polysilicon, a side wall-free polysilicon gate, a source lead-out metal, and a gate connection metal, the SiC epitaxial wafer is prepared by a standard SiC MOSFET process, and the SiC epitaxial wafer comprises a SiC substrate and a doped SiC epitaxial region on the SiC substrate, wherein the SiC epitaxial region comprises a SiC N-drift region, a SiC NSL current diffusion layer, a JFET region, a Pwell region, a Pbase region, a P++ region, an electric field advance termination N++ region, an ohmic contact injection N++ region, and a gate connection injection N++ region.

[0010] Pbase region P-type doped region, formed by nitrogen ion implantation; P++ region, ohmic contact implantation N++ region, source lead-out metal together form the source of the SiC MOSFET signal input end bidirectional full-port static protection module; gate connection implantation N++ region and gate connection metal together form the signal port protection pole of the SiC MOSFET signal input end bidirectional full-port static protection module, connected with the gate of the protected SiC MOSFET; side wall polysilicon only has a side wall near the gate connection implantation N++ region, used to accurately define the position of the N++ region, Pbase region and gate connection implantation N++ region; side wall-free polysilicon gate is used to accurately define the distance between the ohmic contact implantation N++ region and the gate connection implantation N++ region; terminal lead-out metal and P++ region constitute the terminal junction, and the drain back gold forms the drain of the SiC MOSFET signal input end bidirectional full-port static protection module, connected with the drain of the protected SiC MOSFET.

[0011] The SiC MOSFET main device is protected, and the source port, gate port and drain port of the SiC MOSFET main device are exposed outside,

[0012] The source lead-out metal and the terminal lead-out metal are connected to the source port, the gate connection metal is connected to the gate port, and the drain back gold is connected to the drain port.

[0013] When a positive charge static shock hits the input end, i.e. the gate port of the SiC MOSFET main device, the static protection module has a parasitic transistor between the gate port and the source port, the base region and the emitter of the parasitic transistor are connected to the source port, the collector of the parasitic transistor is connected to the gate port, and the parasitic transistor includes the gate connection implantation N++ region, the Pbase region and the ohmic contact implantation N++ region. The width of the Pbase region determines the width of the base region of the parasitic transistor, and the doping concentration of the Pbase region determines the doping concentration of the base region of the parasitic transistor.

[0014] When a negative charge static shock hits the input end, i.e. the gate port of the SiC MOSFET main device, the static protection module has a parasitic PIN diode between the gate port and the source port, the P pole and the emitter of the parasitic PIN diode are connected to the source port, and the N pole of the parasitic PIN diode is connected to the gate port. The parasitic PIN diode includes the gate connection implantation N++ region, the Pbase region and the P++ region, and the width of the Pbase region is the width of the base region of the parasitic PIN diode.

[0015] When the positive or negative electrostatic charge impacts the input end, i.e. the gate port of the SiC MOSFET main device, the electrostatic protection module has a parasitic back-to-back diode between the gate port and the drain port, the two ends N of the parasitic back-to-back diode are connected with the gate port and the drain port respectively, the parasitic back-to-back diode includes a gate connection injection N++ region, a Pbase region, a JFET region, an electric field advance termination N++ region, a SiC substrate, a SiC N-drift region and a SiC NSL current diffusion layer, when the electrostatic charge impacts the input end, the parasitic back-to-back diode discharges the electrostatic charge between the gate port and the drain port, and the parasitic back-to-back diode additionally utilizes the JFET region and the electric field advance termination N++ region to form an advance termination of the transverse electric field to the terminal.

[0016] A preparation method of a SiC MOSFET signal input end bidirectional full-port electrostatic protection module, steps comprising:

[0017] S1: cleaning the SiC epitaxial wafer, making an alignment mark on the epitaxial wafer, and using the alignment mark to align with the subsequent patterns;

[0018] S2-S5: selective doping of the SiC epitaxial wafer: ion implantation is the only way to realize selective doping of SiC at present, and can realize doping distribution of box-shaped, buried layer and abrupt junction by controlling the energy and dose of ion implantation:

[0019] S6: thermal oxidation process to grow a gate oxide layer;

[0020] S7: depositing a polysilicon gate and its patterning and etching process, to complete the first channel region definition;

[0021] S8: depositing a polysilicon gate again, generating a side wall on the side of the first polysilicon, and finally completing the definition of the channel region width between the ohmic contact injection N++ region and the gate connection injection N++ region, the width between the electric field advance termination N++ region and the gate connection injection N++ region, and the width between the electric field advance termination N++ region and the Pbase region through a patterning and etching process;

[0022] S9: Si3N4 passivation layer grown by PECVD at high temperature;

[0023] S10: ohmic contact process: N-type SiC ohmic contact is prepared by using heavily doped nitrogen ions of SiC and Ni; and P-type SiC ohmic contact is prepared by using heavily doped Al ions of SiC and Ti;

[0024] S11: front side metallization and connection according to patterns;

[0025] S12: back side metallization.

[0026] In steps S2-S5, 2 mu m thick SiO2 material is used as an ion implantation mask, high-energy high-dose ion implantation is usually carried out at high temperature, and after selective doping, high-temperature activation annealing is required at 1600 DEG C under the condition of covering carbon on the SiC surface to repair the lattice damage.

[0027] Steps S2-S5 are specifically as follows:

[0028] S2: high-energy nitrogen ion implantation is carried out at an ambient temperature of 520 DEG C, the implantation energy is 120 keV-400 keV, the implantation dose is 5E11 cm-2-7.5E13 cm-2, and after the entire selective doping, high-temperature annealing activation is carried out to finally form an NSL region;

[0029] S3: multiple Al ion implantations are carried out at an ambient temperature of 520 DEG C, the implantation energy is 35 keV-420 keV, the implantation dose is 4E11 cm-2-4E13 cm-2, and a polycrystalline silicon is deposited and patterned and etched to define the implantation region; after the entire selective doping, high-temperature annealing activation is carried out to finally form Pwell and Pbase regions;

[0030] S4: multiple Al ion implantations are carried out at an ambient temperature of 520 DEG C, the implantation energy is 30 keV-400 keV, the implantation dose is 1E14 cm-2-7.5E14 cm-2, and after the entire selective doping, high-temperature annealing activation is carried out to finally form a P++ region;

[0031] S5: multiple nitrogen ion implantations are carried out at an ambient temperature of 520 DEG C, the implantation energy is 25 keV-90 keV, the implantation dose is 2E14 cm-2-4E14 cm-2, and after the entire selective doping, high-temperature annealing activation is carried out to finally form an N++ region.

[0032] Compared with the prior art, the advantages of the present application are: 1. The SiC MOSFET signal input bidirectional full-port electrostatic protection device disclosed in the patent can reinforce the electrostatic reliability of the SiC MOSFET signal input port, avoid damage to the gate insulating medium caused by electrostatic charges including gate-source positive charge, gate-source negative charge, gate-drain positive charge and gate-drain negative charge, and achieve the effect of effectively protecting the SiC MOSFET from static electricity.

[0033] 2. The SiC MOSFET signal input end bidirectional full-port electrostatic protection device disclosed in the patent can be integrated in the SiC base wafer in the form of a protection module near the SiC MOSFET main device, and can effectively avoid electrostatic damage in the storage, transportation, assembly and other processes from the beginning of scribing to the end of packaging.

[0034] 3. The preparation method of the SiC MOSFET signal input end bidirectional full-port electrostatic protection device disclosed in the patent can be well compatible with common SiC MOSFET processes, has low development and verification difficulty, does not significantly increase production and assembly costs, and greatly improves production yield. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A schematic diagram of a SiC MOSFET protected by the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection module provided by the embodiment of the present application.

[0036] Figure 2 A schematic diagram of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection module provided by the embodiment of the present application.

[0037] Figures 3-7 A schematic diagram of the application method of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection device provided by the embodiment of the present application.

[0038] Among them, Figure 3 A schematic diagram of the connection of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection device provided by the embodiment of the present application in actual use.

[0039] Figure 4 A schematic diagram of the protection of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection device provided by the embodiment of the present application in actual use against positive charge electrostatic shock (GS-P) between the signal input end source end and its equivalent circuit.

[0040] Figure 5 A schematic diagram of the protection of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection device provided by the embodiment of the present application in actual use against negative charge electrostatic shock (GS-N) between the signal input end source end and its equivalent circuit.

[0041] Figure 6The schematic diagram of the new SiC MOSFET signal input end bidirectional full-port electrostatic protection device in actual use for protecting positive charge electrostatic impact (GD-P) between the signal input end and the drain end and the equivalent circuit thereof.

[0042] Figure 7 The schematic diagram of the new SiC MOSFET signal input end bidirectional full-port electrostatic protection device in actual use for protecting negative charge electrostatic impact (GD-N) between the signal input end and the drain end and the equivalent circuit thereof.

[0043] Figure 8 The preparation method and flowchart of the new SiC MOSFET signal input end bidirectional full-port electrostatic protection module.

[0044] Figure 9 The three-dimensional schematic diagram of the new SiC MOSFET signal input end bidirectional full-port electrostatic protection module and the SiC MOSFET protected by the embodiment of the present application.

[0045]

[0046] DETAILED DESCRIPTION

[0047] The present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0049] Please refer to Figures 1-9 The present application provides several technical solution embodiments based on the present application.

[0050] Figure 1 The schematic diagram of the SiC MOSFET protected by the new SiC MOSFET signal input end bidirectional full-port electrostatic protection module provided by the embodiment of the present application.

[0051] Figure 1The device is made by standard SiC MOSFET process on SiC epi. The SiC epi includes SiC substrate 1-01 and medium doped SiC epi region on top of it, which includes SiC N-drift region 1-02, SiC NSL current spreading layer 1-03, JFET region 1-04, Pwell region 1-05, P++ region 1-07, Ohmic contact implant N++ region 1-09. The SiC epi region together with SiC substrate 1-01, drain back metal 1-17, sidewall poly 1-11, source lead metal 1-13, poly gate up lead metal 1-15 forms the protected SiC MOSFET 3-01 / 4-01 / 5-01 / 6-01 / 7-01.

[0052] The structure is described in detail below Figure 1 , with specific structural features:

[0053] SiC substrate 1-01 is a high concentration doped region with thickness up to hundreds of microns (range from 130 microns to 300 microns due to different thinning techniques).

[0054] SiC N-drift region 1-02 is a medium concentration N-type region with thickness up to tens of microns, the specific value is determined by SiC MOSFET standard process.

[0055] SiC NSL current spreading layer 1-03 is a medium concentration N-type buried layer formed by multiple deep implantation used in SiC MOSFET standard process, which plays a role in spreading current conduction area and reducing one of the important performance parameters of power devices, on-resistance.

[0056] JFET region 1-04 is a medium concentration N-type region, the concentration can be but not limited to consistent with SiC N-drift region 1-02. When SiC MOSFET is turned on, the current in JFET region 1-04 changes from lateral to vertical, and SiC MOSFET standard process needs to adopt appropriate JFET region 1-04 concentration and width to ensure breakdown voltage and optimize on-resistance.

[0057] Pwell region 1-05 is a medium concentration P-type doped region. Considering that the mobility of impurities in SiC is very low, it is generally formed by nitrogen ion implantation. Considering the threshold drift problem of long-term robustness, in many SiC MOSFET standard processes, Pwell region 1-05 adopts layered doping with upper light and lower thick, and the Pwell region 1-05 shown in this patent only adopts one layer of doping for simplification, but it does not affect the scope of protection of the present invention.

[0058] P++ region 1-07, ohmic contact implant N++ region 1-09, source lead metal 1-13 together form the source of the protected SiC MOSFET. In order to achieve better ohmic contact effect, in addition to high concentration P++ region 1-07 doping and high concentration ohmic contact implant N++ region 1-09 doping, there is but not limited to the use of additional metallization technology such as silicon alloy.

[0059] There are sidewall polysilicon 1-11 and polysilicon gate lead metal 1-15 together form the gate of the protected SiC MOSFET. There are sidewall polysilicon 1-11 by one or more times of deposition of the sidewall to define the implant position of Pwell region 1-05 and the implant position of ohmic contact implant N++ region 1-09, so as to accurately prepare the protected SiC MOSFET device with uniform gate width. In addition to the sidewall process, there is also a method of one or more times of oxidation in other SiC MOSFET standard processes to obtain the protected SiC MOSFET device with uniform gate width, but it does not affect the scope of the present application.

[0060] Drain back metal 1-17 forms the drain of the protected SiC MOSFET, and the SiC MOSFET standard process in the embodiment adopts but is not limited to nickel or nickel-aluminum alloy to form the back metal structure located below the SiC substrate 1-01.

[0061] The innovation of the present application is not in the standard SiC MOSFET process, and the present application does not limit the standard SiC MOSFET process used by the protected SiC MOSFET, and the use of different SiC MOSFET processes does not affect the protection scope and claims of the present application.

[0062] Figure 2 The new SiC MOSFET signal input end bidirectional full port electrostatic protection module schematic diagram provided for the embodiment of the present application.

[0063] In order to embody the practicability and practical use value of the present application, and at the same time show the process compatibility and low cost advantage of the present application, Figure 2 The main part of the present application mainly relies on Figure 1 The standard SiC MOSFET structure and standard SiC MOSFET process and the realizable structure preparation.

[0064] Figure 2The module structure also relies on the SiC epitaxial wafer prepared by the standard SiC MOSFET process. The SiC epitaxial wafer includes a SiC substrate 2-01 and a medium-doped SiC epitaxial region thereon, wherein the SiC epitaxial region includes the SiC N-drift region 2-02, the SiC NSL current diffusion layer 2-03, the JFET region 2-04, the Pwell region 2-05, the Pbase region 2-06, the P++ region 2-07, the electric field termination N++ region 2-08, the ohmic contact injection N++ region 2-09, the gate connection injection N++ region 2-10, and multiple regions. The SiC epitaxial region, together with the SiC substrate 2-01, the drain back gold 2-17, the polysilicon with a side wall 2-11, the polysilicon gate without a side wall 2-12, the source lead-out metal 2-13, and the gate connection metal 1-16, constitutes the SiC MOSFET signal input end bidirectional full-port static protection module 3-02 / 4-02 / 5-02 / 6-02 / 7-02 implemented by the protection.

[0065] The following will be described in combination with Figure 2 , and the structural features will be specifically described:

[0066] The SiC substrate 2-01 is a high-concentration N-type region of an Al ion-doped region, which is thinned to a thickness of 130 microns by mechanical grinding for the purpose of optimizing the on-resistance and heat dissipation, but is not limited thereto.

[0067] The SiC N-drift region 2-02 is a medium-concentration N-type region of an Al ion-doped region, and the thickness needs to be thick enough to ensure the breakdown voltage. In this embodiment, the thickness of the SiC N-drift region 2-02 is 23 microns of a medium-concentration N-type region by using a 600V SiC MOSFET standard process.

[0068] The SiC NSL current diffusion layer 2-03 is a medium-concentration N-type buried layer formed by multiple deep implantations, which functions to diffuse the current conduction area and optimize one of the important performance parameters of the power device, i.e., the on-resistance. In this embodiment, the SiC NSL current diffusion layer 2-03 is in contact with the Pwell region 2-05, and the implantation depth is 7.5 microns, but is not limited thereto.

[0069] The JFET region 2-04 is a medium-concentration N-type region, and in this embodiment, the doping concentration is consistent with the SiC N-drift region 2-02, but is not limited thereto, and no additional nitrogen ion implantation is required in the preparation process. In the structure shown in Figure 2 , the JFET region 2-04 is different from Figure 1 , and no regular current flows therethrough, and only an appropriate JFET region 2-04 concentration and width are required to ensure the breakdown voltage, and the width precision is no longer as high as Figure 1The gate 1-11 is defined by the polysilicon gate with sidewall 2-11.

[0070] The Pwell region 2-05 is a moderately doped P-type region. Considering the low mobility of impurities in SiC, it is usually formed by multiple implantations of nitrogen ions. The depth of the Pwell region 2-05 in this embodiment is 7.5 microns. Considering the threshold shift problem of long-term robustness, the Pwell region 2-05 in many SiC MOSFET standard processes is a layered doping with a lighter upper part and a denser lower part. The Pwell region 2-05 shown in this patent is only one layer of doping for simplicity, but it does not affect the scope of protection of the invention.

[0071] The Pbase region 2-06 is a moderately doped P-type region, also formed by multiple implantations of nitrogen ions. In this invention, the Pbase region 2-06 needs to be the base region of the parasitic BJT, so its concentration is related to the minimum holding voltage of the parasitic BJT when discharging static electricity. Therefore, if the doping concentration of the Pwell region 2-05 in the SiC MOSFET standard process is too low, selectively and not necessarily, in order to get a higher holding voltage, the Pbase region 2-06 is implanted with one or more nitrogen ions on the basis of the Pwell region 2-05 to increase the doping concentration of the Pbase region 2-06.

[0072] The P++ region 2-07, the ohmic contact implanted N++ region 2-09, and the source lead metal 2-13 together form the source of the SiC MOSFET signal input bidirectional full-port static protection module. In addition to the high-concentration P++ region 2-07 doping and the high-concentration ohmic contact implanted N++ region 2-09 doping, this embodiment does not use but is not limited to using additional metallization techniques such as silicon alloy to achieve good ohmic contact effect.

[0073] The gate connection implanted N++ region 2-10 and the gate connection metal 2-16 together form the signal port protection electrode of the SiC MOSFET signal input bidirectional full-port static protection module, which is connected to the gate of the protected SiC MOSFET. In addition to the high-concentration gate connection implanted N++ region 2-10 doping, this embodiment does not use but is not limited to using additional metallization techniques such as silicon alloy to achieve good ohmic contact effect.

[0074] The polysilicon gate with sidewall 2-11 and the gate 1-11 together form the gate of the SiC MOSFET signal input bidirectional full-port static protection module. Figure 1The sidewall polysilicon 2-11 in the figure is different from the sidewall polysilicon 1-11 in the figure, and is not a symmetrical sidewall process. The sidewall polysilicon 2-11 has a sidewall only on one side close to the gate connection injection N++ area 2-10, and is used to accurately define the position of the electric field termination N++ area 2-08, the Pbase area 2-06 and the gate connection injection N++ area 2-10, and to achieve good process consistency. In addition to the sidewall process, a method of one or more times of oxidation is also used in other SiC MOSFET standard processes to obtain a gate width consistent protected SiC MOSFET device, but it does not affect the scope of the present application.

[0075] The polysilicon gate 2-12 without sidewall is also different from the sidewall polysilicon 1-11 in the figure, and is a sidewall-free process, which is used to accurately define the spacing between the ohmic contact injection N++ area 2-09 and the gate connection injection N++ area 2-10, and to achieve good process consistency. This spacing is the base width of the parasitic transistor. Figure 1

[0076] The terminal lead-out metal 2-14 and the P++ area 2-07 thereunder form a terminal junction, and the distance and shape thereof are determined by the standard SiC process. In the standard SiC process, the terminal withstand voltage is generally 70% of the longitudinal withstand voltage, and the terminal lead-out metal 2-14 is generally connected with the source. In the present application, the electric field termination N++ area 2-08 is injected and formed at the position as shown in the figure, and the electric field termination N++ area 2-08 is ingeniously used to distort the electric field in the JFET area 2-04, so that the lateral distribution of the electric field is concentrated near the electric field termination N++ area 2-08, causing the terminal to break down in advance. Figure 2

[0077] The drain back metal 2-17 forms the drain of the SiC MOSFET signal input end bidirectional full-port electrostatic protection module, and is connected with the drain of the protected SiC MOSFET. In the standard process of the SiC MOSFET of the present embodiment, nickel or nickel-aluminum alloy is used to form the back metal structure under the SiC substrate 1-01, but is not limited thereto.

[0078] The present application does not limit the standard SiC MOSFET process used by the protected electrostatic protection module 3-02 / 4-02 / 5-02 / 6-02 / 7-02, and the use of the idea and structural principle of the present application is within the protection and scope of claims of the present application. The use of different SiC MOSFET processes or non-substantial changes to the process structure does not affect the protection scope and claims of the present application.

[0079] Figure 3 The new SiC MOSFET signal input end bidirectional full-port electrostatic protection device provided for the embodiments of the present application is connected in the actual use. ​​

[0080] SiC MOSFET main device 3-01 is protected by SiC MOSFET signal input end bidirectional full port static protection module 3-02 of the application, and source port 3-03, gate port 3-04 and drain port 3-05 of SiC MOSFET main device 3-01 are exposed. The static protection module 3-02 provided by the application is connected with SiC MOSFET main device 3-01 according to Figure 3 .

[0081] Among them, the static protection module 3-02 provided by the application is connected with source port 3-03 through 2-13 and 2-14 in Figure 2 , connected with gate port 3-04 through 2-16 in Figure 2 , and connected with drain port 3-05 through 2-17 in Figure 2 . In this embodiment, the connection is completed by two layers of copper-aluminum alloy metal medium.

[0082] Static shock may occur at source port 3-03, gate port 3-04 and drain port 3-05 of SiC MOSFET main device 3-01, and there are positive and negative static charges. In order to provide complete static protection capability, the positive and negative static charge shocks of each port should be considered.

[0083] Figure 4 The new SiC MOSFET signal input end bidirectional full port static protection device provided by the embodiment of the application protects the positive charge static shock (GS-P) between the source ports of the signal input end and its equivalent circuit diagram in actual use.

[0084] When positive charge static shock 4-03 shocks the input end, i.e. gate port 4-04 of SiC MOSFET main device 4-01, based on the connection of Figure 3 , the static protection module provided by the application has a parasitic transistor 4-02 between gate port 4-04 and source port 4-05. As shown in Figure 4 , the base region and the emitter of the parasitic transistor 4-02 are connected with source port 4-03, and the collector of the parasitic transistor 4-02 is connected with gate port 4-04.

[0085] The parasitic transistor 4-02 is formed by Figure 2The width of 2-06 determines the width of the base region of the parasitic transistor 4-02, and the doping concentration of 2-06 determines the doping concentration of the base region of the parasitic transistor 4-02. Therefore, in practical applications, the width and the doping concentration of 2-06 need to be carefully adjusted so that the minimum holding voltage of the parasitic transistor 4-02 when back-punching is greater than the maximum operating voltage of the gate port 4-04. The width of 2-06 is determined by 2-12, and the doping concentration of 2-06 is determined by the nitrogen ion implantation in the process of forming 2-06. In this embodiment, the width of 2-06 is 0.5 microns, and the doping concentration of 2-06 is formed by multiple nitrogen ion implantations, with a concentration of 4.75E17 cm-3.

[0086] Figure 5 The equivalent circuit diagram of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection device provided by the embodiment of the application in actual use protects the signal input end from positive charge electrostatic impact (GD-P).

[0087] When the negative charge electrostatic impact 5-03 impacts the input end, i.e., the gate port 5-04 of the SiC MOSFET main device 5-01, based on the connection of Figure 3 , the electrostatic protection module provided by the application has a parasitic PIN diode 5-02 between the gate port 5-04 and the source port 5-05. As shown in Figure 5 , the P pole and the emitter of the parasitic PIN diode 5-02 are connected to the source port 5-03, and the N pole of the parasitic PIN diode 5-02 is connected to the gate port 5-04.

[0088] The parasitic PIN diode 5-02 is composed of Figure 2 2-10, 2-06, and 2-07 shown in the above figure, and the presence of 2-06 further reduces the on-resistance under the effect of carrier injection when discharging large electrostatic charges, which is conducive to further improving the electrostatic protection capability. The width of 2-06 is the width of the base region of the parasitic PIN diode 5-02. In this embodiment, the width of 2-06 is 0.5 microns, and the doping concentration of 2-06 is formed by multiple nitrogen ion implantations, with a concentration of 4.75E17 cm-3.

[0089] Figure 6 The equivalent circuit diagram of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection device provided by the embodiment of the application in actual use protects the signal input end from positive charge electrostatic impact (GD-P). Figure 7 The equivalent circuit diagram of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection device provided by the embodiment of the application in actual use protects the signal input end from positive charge electrostatic impact (GD-P).

[0090] When the positive charge 6-03 or the negative charge 7-03 electrostatically impacts the input end, that is, the gate port 6-04 / 7-04 of the SiC MOSFET main device 6-01 / 7-01, based on the connection, the electrostatic protection module provided by the present application has a parasitic back-to-back diode 6-02 / 7-02 between the gate port 6-04 / 7-04 and the drain port 6-03 / 7-03. Figure 3 Figure 5 As shown in FIGS. 1 and 2, the two ends N of the parasitic back-to-back diode 6-02 / 7-02 are connected with the gate port 6-04 / 7-04 and the drain port 6-03 / 7-03 respectively. Figure 6 The parasitic back-to-back diode 6-02 / 7-02 is composed of 2-10, 2-06, 2-04, 2-08, 2-03, 2-02, and 2-01 as shown in FIG. 2. Considering that the actual structure and process of the standard SiC MOSFET process will avoid the formation of a vertical transistor, and the doping concentration of 2-06 of the present application is higher than that of the Pwell region 1-05 / 2-05 of the standard process, the N-type / P-type / N-type arrangement of 2-10, 2-04, 2-03, 2-02, and 2-01 in the vertical direction will not form a vertical NPN transistor, but a parasitic back-to-back diode 6-02 / 7-02. When the electrostatic charge electrostatically impacts the input end 6-03 / 7-03, the parasitic back-to-back diode 6-02 / 7-03 inside the electrostatic protection module provided by the present application discharges the electrostatic charge between the gate port 6-04 / 7-04 and the drain port 6-03 / 7-03.

[0091] Figure 2 The parasitic back-to-back diode 6-02 / 7-02 is composed of 2-10, 2-06, 2-04, 2-08, 2-03, 2-02, and 2-01 as shown in FIG. 2. Considering that the actual structure and process of the standard SiC MOSFET process will avoid the formation of a vertical transistor, and the doping concentration of 2-06 of the present application is higher than that of the Pwell region 1-05 / 2-05 of the standard process, the N-type / P-type / N-type arrangement of 2-10, 2-04, 2-03, 2-02, and 2-01 in the vertical direction will not form a vertical NPN transistor, but a parasitic back-to-back diode 6-02 / 7-02. When the electrostatic charge electrostatically impacts the input end 6-03 / 7-03, the parasitic back-to-back diode 6-02 / 7-03 inside the electrostatic protection module provided by the present application discharges the electrostatic charge between the gate port 6-04 / 7-04 and the drain port 6-03 / 7-03.

[0092] The vertical withstand voltage of the standard SiC MOSFET process is very high, much higher than the breakdown critical voltage of the gate port insulating medium, so additional means are required to make the electrostatic protection module between the gate port 6-04 / 7-04 and the drain port 6-03 / 7-03 open earlier when electrostatic occurs. The parasitic back-to-back diode 6-02 / 7-02 inside the electrostatic protection module provided by the present application additionally utilizes 2-04 and 2-08 to terminate the lateral electric field to the terminal in advance. The terminal withstand voltage under the standard process of the SiC MOSFET is 70% of the SiC MOSFET withstand voltage, and in the present embodiment, the termination of the lateral electric field to the terminal in advance is realized by 2-04 and 2-08, so that the lateral electric field is concentrated near 2-04 and 2-08 in 2-04, and then the breakdown occurs in advance. By changing the distance from 2-08 to 2-06, the width of 2-11 is essentially changed, and the breakdown voltage, that is, the opening voltage of the parasitic back-to-back diode 6-02 / 7-02, is flexibly adjusted between 25% and 70% of the SiC MOSFET withstand voltage.​​

[0093] Based on the above principles and embodiment descriptions, the application provides perfect electrostatic protection capability, and finally achieves the effect of bidirectional full-port electrostatic protection.

[0094] Figure 8 The preparation method and flowchart of the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection module provided by the embodiment of the application. The standard SiC MOSFET relied on by the flowchart is one of the processes of a planar gate SiC MOSFET device, and the key preparation steps of the electrostatic protection module of the application in the planar gate SiC MOSFET device process are highlighted. The details of the actual design of the standard SiC process do not constitute a limitation on the scope of the patent.

[0095] S1: The SiC epitaxial wafer is cleaned, and alignment marks are made on the epitaxial wafer, and the alignment marks need to be used for alignment with the subsequent patterns.

[0096] S2-S5: The SiC epitaxial wafer is subjected to selective doping. Ion implantation is the only way to realize selective doping of SiC at present, and can realize box-shaped, buried layer and abrupt junction doping distribution by controlling the energy and dose of ion implantation.

[0097] 2 μm thick SiO2 material is used as an ion implantation mask, and high-energy high-dose ion implantation is usually carried out at high temperature. After selective doping, high-temperature activation annealing at 1600 DEG C is required under the condition of covering carbon on the surface of SiC to repair lattice damage.

[0098] S2: High-energy nitrogen ion implantation is carried out at an ambient temperature of 520 DEG C, the implantation energy is 120 keV-400 keV, the implantation dose is 5E11 cm-2-7.5E13 cm-2, and high-temperature annealing activation is carried out after the entire selective doping, finally forming an NSL region.

[0099] S3: Multiple Al ion implantations are carried out at an ambient temperature of 520 DEG C, the implantation energy is 35 keV-420 keV, the implantation dose is 4E11 cm-2-4E13 cm-2, and the implantation region is defined by depositing polysilicon and patterning etching. High-temperature annealing activation is carried out after the entire selective doping, finally forming a Pwell and Pbase region.

[0100] S4: Multiple Al ion implantations are carried out at an ambient temperature of 520 DEG C, the implantation energy is 30 keV-400 keV, the implantation dose is 1E14 cm-2-7.5E14 cm-2, and high-temperature annealing activation is carried out after the entire selective doping, finally forming a P++ region.

[0101] S5: Multiple nitrogen ion implantation at 520℃ ambient temperature, implantation energy 25keV~90keV, implantation dose 2E14cm-2~4E14cm-2, high temperature annealing activation after doping in the whole selected area, finally form N++ area.

[0102] Different from the way of making polysilicon gate first and then making channel implantation in silicon-based power MOSFET device, the implantation area and high temperature annealing process are completed first, and then the polysilicon gate is made in SiC MOSFET device. The channel width is controlled in mainstream SiC MOSFET process, which has two ways of polysilicon sidewall and polysilicon thermal growth, and the sidewall way of S6~S8 is adopted to control the channel and the definition of other structures with high pattern consistency requirement.

[0103] S6: Thermal oxidation process to grow gate oxide layer;

[0104] S7: Deposition of polysilicon gate and its patterning etching process, to complete the first channel area definition.

[0105] S8: Deposition of polysilicon gate again, to generate sidewall on the side of the first polysilicon, and finally complete the definition of the channel area width between 2-09 and 2-10, the width between 2-08 and 2-10, and the width between 2-08 and 2-06 in this embodiment through patterning etching process.

[0106] The main structure of the basic embodiment is basically completed through the above steps, and the subsequent process steps are supplemented to form a complete usable structure.

[0107] S9: Si3N4 passivation layer grown by PECVD at high temperature.

[0108] S10: Ohmic contact process. N-type SiC ohmic contact is prepared by heavily doped nitrogen ions (>5E18cm-3) and Ni; P-type SiC ohmic contact is prepared by heavily doped Al ions (>5E18cm-3) and Ti. In this embodiment, it is not limited but not excluded to form source P-type and N-type SiC ohmic contact at the same time, and heavily doped Al ions (≥1×1020cm-3) of SiC and heavily doped Al ions (3×1019cm-3) of SiC and Al / Ti are used to simplify the manufacturing process flow.

[0109] S11: Front metalization and connection according to pattern. In this embodiment, two layers but not limited to more layers of metal are used to complete the design of the invention.

[0110] S12: Back metalization, in this embodiment, but not limited to, nickel aluminum and its alloy are used to prepare back metal.

[0111] After the above steps, all the new SiC MOSFET signal input end bidirectional full-port electrostatic protection modules proposed by the application are completed. As can be seen from the reference preparation method provided in the embodiment, the application can be easily integrated with the standard SiC process, and there is no excessive additional process and cost, and the application has the advantages of easy integration, low cost and simple preparation.

[0112] Figure 9 To embody the new SiC MOSFET signal input end bidirectional full-port electrostatic protection module of the application and the three-dimensional perspective view of the SiC MOSFET protected by the embodiment of the application in practical use.

[0113] Figure 9 contains Figure 1 , Figure 2 The protected SiC MOSFET and the new SiC MOSFET signal input end bidirectional full-port electrostatic protection module provided by the embodiment of the application are labeled with the structure of Figure 1 , Figure 2 Figure 9

[0114] SiC substrate 9-01, SiC N-drift region 9-02, SiC NSL current diffusion layer 9-03, JFET region 9-04, Pwell region 9-05, P++ region 9-07, ohmic contact injection N++ region 9-09, polysilicon gate with side wall 9-11, source lead-out metal 9-13, polysilicon gate lead-out metal 9-15, terminal lead-out metal 9-14, drain back gold 9-17 jointly constitute the protected SiC MOSFET of the embodiment. As shown in Figure 9 , the protected SiC MOSFET is located on the right side of the perspective view, and the number of fingers is 6 and is not limited to more.

[0115] SiC substrate 9-01, SiC N-drift region 9-02, SiC NSL current diffusion layer 9-03, JFET region 9-04, Pwell region 9-05, Pbase region 9-06, P++ region, 9-07, electric field advance termination N++ region 9-08, ohmic contact injection N++ region 9-09, gate connection injection N++ region 9-10, polysilicon gate with side wall 9-11, polysilicon gate without side wall 9-12, source lead-out metal 9-13, terminal lead-out metal 9-14, gate connection metal 9-16, drain back gold 9-17 jointly constitute the new SiC MOSFET signal input end bidirectional full-port electrostatic protection module of the embodiment. As shown in Figure 9 ​​As shown, the novel SiC MOSFET signal input end bidirectional full-port electrostatic protection module of the embodiment is located on the left side of the perspective view, and the number of fingers is 1 and is not limited to more. It is recommended that the ratio of the number of fingers of the protected SiC MOSFET and the SiC MOSFET signal input end bidirectional full-port electrostatic protection module be between 1:5 and 1:20, and a too low finger number ratio cannot fully exert the electrostatic protection effect, and a too high finger number ratio occupies valuable chip area.

[0116] The present application is different from electrostatic protection at the package level or the PCB level, but electrostatic protection at the wafer level, not only providing electrostatic protection capability from scribing to packaging stage, but also reducing the cost of providing electrostatic protection function due to manufacturing together with SiC MOSFET;

[0117] The present application comprehensively reinforces the easily damaged gate medium, provides electrostatic charges including positive charges and negative charges, and bidirectional full-port electrostatic protection capability of full-port between gate-source port and gate-drain port.

Claims

1. A SiC MOSFET signal input bidirectional full-port electrostatic protection module, characterized in that The SiC epitaxial wafer is prepared by a standard SiC MOSFET process, and the SiC epitaxial wafer comprises a SiC substrate and a doped SiC epitaxial region on the SiC substrate, wherein the SiC epitaxial region comprises a SiC N-drift region, a SiC NSL current diffusion layer, a JFET region, a Pwell region, a Pbase region, a P++ region, an electric field termination N++ region, an ohmic contact injection N++ region and a gate connection injection N++ region.

2. The bidirectional full-port ESD protection module for SiC MOSFET signal input terminal according to claim 1, characterized in that The Pbase region, the P++ region and the ohmic contact injection N++ region jointly form a source electrode of a SiC MOSFET signal input end bidirectional full-port electrostatic protection module. The gate connection injection N++ region and the gate connection metal jointly form a signal port protection electrode of the SiC MOSFET signal input end bidirectional full-port electrostatic protection module, and are connected to a gate of a protected SiC MOSFET. The terminal lead-out metal and the P++ region constitute a terminal junction, and the drain back metal forms a drain electrode of the SiC MOSFET signal input end bidirectional full-port electrostatic protection module, and is connected to a drain electrode of the protected SiC MOSFET.

3. The SiC MOSFET signal input bidirectional full-port ESD protection module according to claim 1, characterized in that The SiC MOSFET main device is protected, and a source port, a gate port and a drain port of the SiC MOSFET main device are exposed, and the source port is connected to the source lead-out metal and the terminal lead-out metal, the gate port is connected to the gate connection metal, and the drain port is connected to the drain back metal.

4. The bidirectional full-port ESD protection module for SiC MOSFET signal input according to claim 1, characterized in that When a positive electrostatic shock hits the input end, i.e., the gate port of the SiC MOSFET main device, a parasitic transistor exists between the gate port and the source port, a base region and an emitter of the parasitic transistor are connected to the source port, a collector of the parasitic transistor is connected to the gate port, and the parasitic transistor comprises the gate connection injection N++ region, the Pbase region and the ohmic contact injection N++ region, a width of the Pbase region determines a width of the base region of the parasitic transistor, and a doping concentration of the Pbase region determines a doping concentration of the base region of the parasitic transistor.

5. The SiC MOSFET signal input bidirectional full-port ESD protection module according to claim 1, characterized in that When the negative electrostatic charge impacts the input end, i.e. the gate port of the SiC MOSFET main device, the electrostatic protection module has a parasitic PIN diode between the gate port and the source port, the P pole and the emitter of the parasitic PIN diode are connected with the source port, the N pole of the parasitic PIN diode is connected with the gate port, and the parasitic PIN diode includes a gate-connected injection N++ region, a Pbase region and a P++ region.

6. The SiC MOSFET signal input bidirectional full-port ESD protection module according to claim 1, characterized in that When the positive or negative electrostatic charge impacts the input end, i.e. the gate port of the SiC MOSFET main device, the electrostatic protection module has a parasitic back-to-back diode between the gate port and the drain port, the two N poles of the parasitic back-to-back diode are connected with the gate port and the drain port respectively, the parasitic back-to-back diode includes a gate-connected injection N++ region, a Pbase region, a JFET region, an electric field advance termination N++ region, a SiC substrate, a SiC N-drift region and a SiC NSL current diffusion layer, when the electrostatic charge impacts the input end, the parasitic back-to-back diode discharges the electrostatic charge between the gate port and the drain port, and the parasitic back-to-back diode additionally utilizes the JFET region and the electric field advance termination N++ region to form an advance termination of the lateral electric field to the terminal.

7. A method for preparing a bidirectional full-port ESD protection module for SiC MOSFET signal input, characterized by the steps of Comprise: S1: cleaning the SiC epitaxial wafer, making an alignment mark on the epitaxial wafer, and needing to use the alignment mark to align with the subsequent patterns; S2-S5: selected area doping of the SiC epitaxial wafer: ion implantation is the only way to realize SiC selected area doping at present, and can realize doping distribution of box-shaped, buried layer and abrupt junction by controlling energy and dose of ion implantation: S6: growing a gate oxide layer through a thermal oxidation process; S7: depositing a polysilicon gate and performing a patterning etching process, to complete the first channel region definition; S8: depositing a polysilicon gate again, generating a side wall on the side of the first polysilicon, and finally completing the definition of the channel region width between the ohmic contact injection N++ region and the gate-connected injection N++ region, the width between the electric field advance termination N++ region and the gate-connected injection N++ region, and the width between the electric field advance termination N++ region and the Pbase region through a patterning etching process; S9: a Si3N4 passivation layer grown by PECVD at high temperature; S10: ohmic contact process: N-type SiC ohmic contact is prepared by using heavily doped nitrogen ions of SiC and Ni; and P-type SiC ohmic contact is prepared by using heavily doped Al ions of SiC and Ti; S11: front side metallization and connection according to patterns; S12: back side metallization.

8. The method of claim 7, wherein the method further comprises: forming a gate oxide layer on the SiC MOSFET; forming a gate electrode on the gate oxide layer; and forming a gate pad on the gate electrode. In steps S2-S5, 2 mu m thickness of SiO2 material is used as an ion implantation mask, high-energy and high-dose ion implantation is usually performed at high temperature, and after selected area doping, high-temperature activation annealing at 1600 DEG C is needed to repair lattice damage under the condition of covering carbon on the surface of SiC.

9. The method of claim 7 or 8, wherein the method further comprises: forming a gate oxide layer on the surface of the SiC MOSFET; forming a gate electrode on the gate oxide layer; and forming a gate pad on the gate electrode. Steps S2-S5 are specifically: S2: at 520℃ ambient temperature, high-energy nitrogen ion implantation is carried out, implantation energy is 120keV-400keV, implantation dose is 5E11cm-2-7.5E13cm-2, high-temperature annealing activation is carried out after doping in the whole selected area, and finally the NSL area is formed; S3: at 520℃ ambient temperature, multiple Al ion implantations are carried out, implantation energy is 35keV-420keV, implantation dose is 4E11cm-2-4E13cm-2, and the implantation area is defined by depositing polysilicon and patterning etching; high-temperature annealing activation is carried out after doping in the whole selected area, and finally the Pwell and Pbase areas are formed; S4: at 520℃ ambient temperature, multiple Al ion implantations are carried out, implantation energy is 30keV-400keV, implantation dose is 1E14cm-2-7.5E14cm-2, high-temperature annealing activation is carried out after doping in the whole selected area, and finally the P++ area is formed; S5: at 520℃ ambient temperature, multiple nitrogen ion implantations are carried out, implantation energy is 25keV-90keV, implantation dose is 2E14cm-2-4E14cm-2, high-temperature annealing activation is carried out after doping in the whole selected area, and finally the N++ area is formed.

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